Resistive memory device

Abstract

A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first border transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0161668, filed on December 6, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to memory devices, and more specifically, to resistive memory devices. Background Technology

[0004] Examples of resistive memory devices include phase-change random access memory (PRAM), nanofloating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and resistive RAM (RRAM). Resistive memory devices advantageously exhibit the high speed of dynamic RAM (DRAM) and the non-volatility of flash memory.

[0005] In a resistive memory device, the resistance distribution of a memory cell corresponds to the data programmed therein. To read a memory cell, a given current or voltage can be applied to the cell, and the voltage, which depends on the resistance of the memory cell, can be read, thereby sensing the data. However, the sensing margin of a read operation can be negatively affected by parasitic capacitance components on the word lines and bit lines connected to the memory cells of the resistive memory device. Furthermore, parasitic capacitance components can cause read / write interference, such as changes to the programming state of memory cells adjacent to the memory cell being read. Summary of the Invention

[0006] According to one aspect of the present invention, a resistive memory device is provided, comprising: a first bit line group including a first edge bit line; a second bit line group including a second edge bit line; and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line when the first edge bit line is selected. The first edge bit line is configured to be closest to the second bit line group in the first bit line group, and the second edge bit line is configured to be closest to the first bit line group in the second bit line group.

[0007] According to another aspect of the present inventive concept, there is provided a resistive memory device, comprising: a first bit line group including a first edge bit line; a second bit line group including a second edge bit line; a first edge transistor configured to apply a selection voltage to the first edge bit line according to a first selection signal; a second edge transistor configured to apply a selection voltage to the second edge bit line according to a second selection signal; a third edge transistor configured to apply a non-selection voltage to the first edge bit line according to the first selection signal; and a fourth edge transistor configured to apply a non-selection voltage to the second edge bit line according to the second selection signal.

[0008] According to another aspect of the present inventive concept, there is provided a resistive memory device, comprising: a first word line group including a first edge word line; a second word line group including a second edge word line; a first boundary transistor configured to apply a non-selection voltage to the second edge word line when the first edge word line is selected; and a second boundary transistor configured to apply a non-selection voltage to the first edge word line when the second edge word line is selected. The first edge word line is disposed closest to the second word line group in the first word line group, and the second edge word line is disposed closest to the first word line group in the second word line group.

[0009] According to another aspect of the present inventive concept, there is provided an operating method of a resistive memory device including a first bit line group defined by a decoder structure. The method comprises: applying a non-selection voltage to a first edge bit line disposed at an outermost position in the first bit line group; and floating a first middle bit line included in the first bit line group.

[0010] According to another aspect of the present inventive concept, there is provided a resistive memory device, comprising: a first bit line group including a plurality of bit lines; a first edge bit line disposed at an outermost position in the first bit line group; and a first middle bit line included in the first bit line group, the first middle bit line being adjacent to the first edge bit line. A number of transistors connected to the first edge bit line is different from a number of transistors connected to the first middle bit line.

[0011] According to another aspect of the present inventive concept, there is provided a resistive memory device, comprising: a first bit line group including a plurality of bit lines; a first edge bit line disposed at an outermost position in the first bit line group; and a first middle bit line included in the first bit line group, the first middle bit line being adjacent to the first edge bit line. At least some nodes connected to the first edge bit line through transistors are different from at least some nodes connected to the first middle bit line through transistors. BRIEF DESCRIPTION OF DRAWINGS

[0012] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and by comparison with the claims, in which:

[0013] Figure 1 is a block diagram illustrating a memory system according to an embodiment;

[0014] Figure 2 is a block diagram illustrating a memory device according to an embodiment;

[0015] Figure 3A is a diagram illustrating a portion of a memory device according to an embodiment;

[0016] Figure 3B is a diagram illustrating a memory cell according to an embodiment;

[0017] Figures 4A to 4C is a diagram illustrating a memory cell according to an embodiment;

[0018] Figure 5 is a graph for reference in describing a set operation and a reset write operation performed on a variable resistor of a memory cell according to an embodiment;

[0019] Figure 6A is a graph illustrating an exemplary resistance distribution of a single-layer memory cell;

[0020] Figure 6B is a graph illustrating an exemplary resistance distribution of a multi-layer memory cell;

[0021] Figure 7 is a flowchart for reference in describing an operation of a memory device according to an embodiment;

[0022] Figure 8 is a block diagram illustrating a column decoder according to an embodiment;

[0023] Figure 9A and Figure 9B is a circuit diagram illustrating a column decoder according to an embodiment;

[0024] Figure 10 is a circuit diagram illustrating a column decoder according to an embodiment;

[0025] Figure 11 is a circuit diagram illustrating a column decoder according to an embodiment;

[0026] Figure 12 is a circuit diagram illustrating a column decoder according to an embodiment;

[0027] Figure 13 is a block diagram illustrating a memory device according to an embodiment;

[0028] Figure 14 is a circuit diagram illustrating a column decoder according to an embodiment;

[0029] Figure 15is a block diagram illustrating a memory device according to an embodiment;

[0030] Figure 16 is a circuit diagram illustrating a column decoder according to an embodiment;

[0031] Figure 17A and Figure 17B is a diagram for reference in describing a local decoder according to an embodiment; and

[0032] Figure 18 is a block diagram illustrating an example in which a memory device according to an embodiment is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 is a block diagram illustrating a memory system 10 according to an embodiment. As illustrated, the memory system 10 of the present embodiment includes a memory device 100 and a memory controller 200.

[0035] The memory controller 200 can include a processor (not shown) that controls the memory controller 200 to perform various memory operations on the memory device 100. The corresponding control platform can be implemented in software, hardware, or a combination thereof. For example, in response to a write / read request from a host HOST, the memory controller 200 can control the memory device 100 to read data stored in the memory device 100 or write data into the memory device 100. To perform these operations, the memory controller 200 can provide an address ADDR, a command CMD, and a control signal CTRL to the memory device 100 to control a program (write) operation, a read operation, and an erase operation, respectively, performed on the memory device 100. In addition, data DATA to be written and data DATA read can be transmitted and received between the memory controller 200 and the memory device 100.

[0036] The memory controller 200 can include Figure 1Other components not shown. For example, memory controller 200 may also include random access memory (RAM) that serves as the processor's working memory. As other examples, memory controller 200 may include a host interface that operates according to a pre-established host interface protocol. Examples of host interface protocols include Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnection Express (PIC-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0037] The memory controller 200 and the memory device 100 may be implemented as separate semiconductor devices. Alternatively, the memory controller 200 and the memory device 100 may be integrated into a single semiconductor device. For example, the memory controller 200 and the memory device 100 may be integrated into a single semiconductor device and may be configured as a memory card. That is, the memory controller 200 and the memory device 100 may be integrated into a single semiconductor device and may be configured as a personal computer (PC) card (e.g., PCMCIA), compressed flash memory (CF) card, smart media card (e.g., SM / SMC), memory stick, multimedia card (e.g., MMC, RS-MMC, or micro MMC), secure digital card (SD) card (e.g., SD, mini SD, or micro SD), or universal flash memory (UFS).

[0038] like Figure 1 As shown, the memory device 100 may include a memory cell array 110, a row decoder 120, and a column decoder 130. The memory cell array 110 may contain multiple resistive memory cells; therefore, the memory device 100 may be referred to as a resistive memory device. In the following text, for convenience, a resistive memory cell may be simply referred to as a memory cell.

[0039] Memory device 100 may be implemented by one or more chips and may be implemented in various module and / or package types. For example, memory device 100 may be a device implemented as a single memory chip. Alternatively, memory device 100 may be defined as a device comprising multiple memory chips, and for example, memory device 100 may be a memory module equipped with multiple memory chips. As another example, memory device 100 may be implemented in a semiconductor package containing one or more memory dies. However, the embodiments are not limited to any particular implementation.

[0040] The memory cell array 110 can include a plurality of memory cells disposed in a plurality of regions defined by the intersection of a plurality of first signal lines and a plurality of second signal lines, respectively. Accordingly, the memory device 100 can be referred to as a cross-point memory. Hereinafter, a memory cell of the plurality of memory cells to which a write operation is to be performed can be referred to as a "selected memory cell."

[0041] Each of the above-described first signal lines can be one of a bit line and a word line, and each of the above-described second signal lines can be the other of the bit line and the word line. Also, each of the plurality of memory cells can be a single layer cell (SLC) storing one bit of data, or can be a multi layer cell (MLC) storing two or more bits of data. Also, the memory cell can have a plurality of resistance distributions according to the number of bits stored in each memory cell. For example, in the case where one bit of data is written in each memory cell, the memory cell can have any one of two resistance distributions. In the case where two bits of data are written in each memory cell, the memory cell can have any one of four resistance distributions.

[0042] The memory cell array 110 can include a plurality of resistive memory cells including a variable resistor (not shown). For example, the variable resistor can include a phase change material whose resistance varies based on temperature, and the resistive memory device can be a phase change RAM (PRAM). As another example, in the case where the variable resistor includes an upper electrode, a lower electrode, and a composite metal oxide therebetween, the resistive memory device can be a resistive RAM (RRAM). As another example, in the case where the variable resistor includes an upper electrode of a magnetic material, a lower electrode of a magnetic material, and a dielectric material therebetween, the resistive memory device can be a magnetic RAM (MRAM).

[0043] The row decoder 120 can be connected to the memory cell array 110 through a plurality of word lines, and in response to a row address generated by decoding an address ADDR, the row decoder 120 can activate a selected word line of the plurality of word lines. Here, the phrase "selected word line" can mean a word line of the plurality of word lines connected to a selected memory cell.

[0044] In response to the row address, the row decoder 120 can control a voltage applied to the selected word line of the plurality of word lines, or can control a connection relationship of the selected word line. The row decoder 120 can include a plurality of transistors, and at least one transistor can be connected to each of the plurality of word lines. The selected word line can be activated for a write / read operation according to the on or off operation of each of the plurality of transistors.

[0045] The column decoder 130 can be connected to the memory cell array 110 via multiple bit lines, and in response to the column address generated by the decoded address ADDR, the column decoder 130 can activate a selected bit line among the multiple bit lines. Here, the phrase "selected bit line" can refer to the bit line among the multiple bit lines that is connected to the selected memory cell.

[0046] In response to a column address, column decoder 130 can control the voltage applied to selected bit lines among a plurality of bit lines, or it can control the connection relationship of selected bit lines. Column decoder 130 may include a plurality of transistors, and at least one transistor may be connected to each of the plurality of word lines. Selected bit lines can be activated for write / read operations based on the on or off operation of each of the plurality of transistors.

[0047] According to embodiments, as will be explained in more detail below, row decoder 120 may apply a non-selection voltage such that edge word lines arranged near selected word lines are not floated, and column decoder 130 may apply a non-selection voltage such that edge bit lines arranged near selected bit lines are not floated. The memory device 100 according to embodiments can prevent edge word lines or edge bit lines from floating, thereby eliminating coupling capacitance between selected word lines and edge word lines or between selected bit lines and edge bit lines, thus reducing interference between adjacent word lines or bit lines. According to embodiments, the non-selection voltage applied to the edge word lines or edge bit lines may vary based on their location.

[0048] Figure 2 This illustrates an embodiment. Figure 1 Block diagram of memory device 100 of memory system 10.

[0049] Reference Figure 2 The memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, a voltage generator 150, control logic 140, and a write / read circuit 160.

[0050] The memory cell array 110 can be connected to a plurality of first signal lines and a plurality of second signal lines. Furthermore, the memory cell array 110 may include a plurality of memory cells (not shown) disposed in a plurality of regions defined by the intersections of the plurality of first signal lines and the plurality of second signal lines. Hereinafter, an example will be described where the plurality of first signal lines are a plurality of word lines WL and the plurality of second signal lines are a plurality of bit lines BL.

[0051] Control logic 140 can control various elements of memory device 100, thereby performing memory operations, such as data write operations and data read operations. For example, control logic 140 can control various elements of memory controller (…). Figure 1The command CMD, the address ADDR, and the control signal CTRL received from the control logic 140 are output to the write / read circuit 160, the voltage generator 150, the row decoder 120, and the column decoder 130.

[0052] The various control signals output from the control logic 140 can be provided to the write / read circuit 160, the voltage generator 150, the row decoder 120, and the column decoder 130. In detail, the control logic 140 can provide an operation selection signal CTRL_op to the write / read circuit 160, and can provide a voltage control signal CTRL_vol to the voltage generator 150. Further, the control logic 140 can decode the address ADDR to provide a row address X_ADDR to the row decoder 120 and a column address Y_ADDR to the column decoder 130.

[0053] In an embodiment, when performing a read operation, the control logic 140 can control the word line selection operation and the bit line selection operation of the row decoder 120 and the column decoder 130 and the sensing operation of the write / read circuit 160 to read data from a selected memory cell, and can control the voltage generator 150 so that the voltage provided to the row decoder 120, the column decoder 130, and the write / read circuit 160 has a predetermined voltage level.

[0054] The voltage generator 150 can generate various voltages for performing a write operation, a read operation, and an erase operation on the memory cell array 110 according to the voltage control signal CTRL_vol. In detail, the voltage generator 150 can generate a plurality of first driving voltages V WL for driving a plurality of word lines WL and a plurality of second driving voltages V BL for driving a plurality of bit lines BL. For example, when performing a read operation, the voltage generator 150 can generate a first pre-charge voltage, a discharge voltage, and an on or off voltage corresponding to a transistor included in the row decoder 120 as the first driving voltage V WL , and can generate a second pre-charge voltage, a clamp voltage, and an on or off voltage corresponding to a transistor of the column decoder 130 as the second driving voltage V BL Further, the voltage generator 150 can generate various voltages (e.g., a set voltage or a reset write voltage, a reference voltage, etc.) provided to the write / read circuit 160.

[0055] The write / read circuit 160 can be selectively connected to the bit line BL and / or the word line WL, and can provide a write current to the selected memory cell, thereby programming data DATA to be stored into the memory cell array 110. Also, the write / read circuit 160 can be selectively connected to the bit line BL and / or the word line WL, and can read data written in the selected memory cell. For example, the write / read circuit 160 can detect a voltage from the word line WL connected to the selected memory cell, and can amplify the detected voltage to output the read data DATA.

[0056] The row decoder 120 can include a boundary transistor BT_R. The boundary transistor BT_R included in the row decoder 120 can be connected to an edge word line disposed adjacent to the selected word line WL. Based on a selection voltage applied to the selected word line WL, the boundary transistor BT_R can bias the edge word line to a non-selection voltage.

[0057] The column decoder 130 can include a boundary transistor BT_C. The boundary transistor BT_C included in the column decoder 130 can be connected to an edge bit line disposed adjacent to the selected bit line BL. Based on a selection voltage applied to the selected bit line BL, the boundary transistor BT_C can bias the edge bit line to a non-selection voltage.

[0058] The boundary transistor BT_R included in the row decoder 120 can perform substantially the same or similar operations as the boundary transistor BT_C included in the column decoder 130. Hereinafter, it can be understood that the description of the operations of the boundary transistor BT_R included in the row decoder 120 can be similarly applied to the operations of the boundary transistor BT_C included in the column decoder 130.

[0059] In a read operation performed on the memory cell array 110, a read voltage can be provided to each of the selected word line and the selected bit line, and for example, a first pre-charge voltage and a second pre-charge voltage can be applied to the selected word line and the selected bit line, respectively, such that a voltage difference between the selected word line and the selected bit line corresponds to a set value. Also, after completing a pre-charge operation of the selected word line and the selected bit line, a voltage level detected from at least one of the selected word line and the selected bit line can vary based on a programming state (e.g., a set state or a reset state) of the selected memory cell.

[0060] In an embodiment, in a case where sensing data is performed by using a voltage detected from a selected word line, a voltage level detected from the selected word line can vary based on a program state of the selected memory cell. For example, when a level of the voltage detected from the selected word line is higher than a reference level, data "0" can be sensed based on a set state of the selected memory cell, while when the level of the voltage detected from the selected word line is lower than the reference level, data "1" can be sensed based on a reset state of the selected memory cell. In another embodiment, the memory device 100 can be implemented to sense data by using a voltage detected from a selected bit line. Alternatively, the memory device 100 can be implemented such that data "1" is sensed when the selected memory cell is in a set state, and data "0" is sensed when the selected memory cell is in a reset state.

[0061] In a read operation, the plurality of word lines and the plurality of bit lines can each have one or more capacitive components (i.e., one or more parasitic capacitors can be present). For example, the plurality of word lines and the plurality of bit lines can have a capacitive component thereof, a capacitive component caused by a word line adjacent thereto, a capacitive component caused by a memory cell connected thereto, and a capacitive component caused by a peripheral circuit (e.g., a driver circuit and a sensing circuit) connected thereto. The capacitive component of each of the word lines and the bit lines can affect a sensing margin and a read / write disturbance characteristic.

[0062] For example, when a capacitance of a word line and / or a bit line is relatively high, a large amount of current can flow through a memory cell and a temperature of the memory cell can increase. As a result, a read / write disturbance can occur. Also, in a read method in which data is sensed according to a voltage level of a word line or a bit line, when a capacitance of the word line or the bit line is low, a sensing margin can decrease.

[0063] The boundary transistor BT_R and the boundary transistor BT_C can apply a non-selection voltage bias to an edge word line and / or an edge bit line disposed adjacent to the selected word line and / or the selected bit line according to a selection voltage applied to the selected word line and / or the selected bit line. Accordingly, a read / write disturbance occurring in the edge word line and / or the edge bit line can be reduced, and a sensing margin of the selected word line and / or the selected bit line can be increased.

[0064] Figure 3A FIG. 1 is a diagram illustrating a memory device according to an embodiment, and Figure 3B FIG. 2 is a diagram illustrating a memory cell according to an embodiment. Specifically, Figure 3A and Figure 3B It is shown that the resistive memory cell is an example of a PRAM memory cell. Figure 3A The memory cell array 110 shown in FIG. 1 can correspond to one cell block.

[0065] Referring to Figure 3A The memory device 100 can include a memory cell array 110, a row decoder 120, and a column decoder 130. The memory cell array 110 can be disposed adjacent to the row decoder 120 in a first direction (e.g., an X direction), and can be disposed adjacent to the column decoder 130 in a second direction (e.g., a Y direction).

[0066] The memory cell array 110 can include a two-dimensional (2D) memory cell array having a horizontal structure, and can include a plurality of word lines WL0 to WLa, a plurality of bit lines BL0 to BLb, and a plurality of memory cells MC. The memory cell array 110 can include a plurality of memory blocks. Each memory block can include a plurality of memory cells arranged in rows and columns. Here, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC can vary differently according to embodiments. However, embodiments are not limited to any particular number of word lines WL, bit lines BL, and memory cells MC. In addition, in some embodiments, the memory cell array 110 can include a three-dimensional (3D) memory cell array.

[0067] Referring to Figure 3B In embodiments, each of the plurality of memory cells MC can include a variable resistor R and a switch SW. Here, the variable resistor R can include a variable resistance material, and the switch SW can function as a selector.

[0068] In embodiments, the variable resistor R can be connected between one of the plurality of bit lines BL0 to BLb and the switch SW, and the switch SW can be connected between the variable resistor R and one of the plurality of word lines WL0 to WLa. However, the present disclosure is not limited thereto, and the switch SW can be connected between one of the plurality of bit lines BL0 to BLb and the variable resistor R, and the variable resistor R can be connected between the switch SW and one of the plurality of word lines WL0 to WLa.

[0069] The switch SW can be connected between one of the plurality of word lines WL0 to WLa and the variable resistor R, and can control the supply of current to the variable resistor R according to a voltage applied to each of the word lines and the bit lines connected thereto. The switch SW can be implemented with an ovonic threshold switch (OTS) material. However, the present embodiments are not limited thereto, and in other embodiments, the switch SW can be other switchable elements, such as a unidirectional diode, a bidirectional diode, or a transistor.

[0070] A voltage can be applied to the variable resistor R of the memory cell MC through a plurality of word lines WL0 to WLa and a plurality of bit lines BL0 to BLb, and a current can flow in the variable resistor R. For example, the variable resistor R can include a phase change material layer reversibly converted between a first state and a second state. However, the variable resistor R is not limited thereto, and can include any variable resistor whose resistance value varies based on an applied voltage. For example, in the selected memory cell MC, the resistance of the variable resistor R can be reversibly converted between a first state and a second state according to a voltage applied to the variable resistor R.

[0071] Based on the resistance change of the variable resistor R, the memory cell MC can store digital information "0" or "1", and can erase the digital information from the memory cell MC. For example, data can be written in the memory cell MC in a high resistance state "0" and a low resistance state "1". Here, a write operation from the high resistance state "0" to the low resistance state "1" can be referred to as a set operation, and a write operation from the low resistance state "1" to the high resistance state "0" can be referred to as a reset operation. However, the memory cell MC according to an embodiment is not limited to storing only binary information of the high resistance state "0" and the low resistance state "1", but can store resistance states of other types of data such as ternary data.

[0072] Any memory cell MC can be addressed by selecting a plurality of word lines WL0 to WLa and a plurality of bit lines BL0 to BLb, and a specific signal (e.g., a voltage or a current) can be applied between the plurality of word lines WL0 to WLa and the plurality of bit lines BL0 to BLb, whereby the memory cell MC can be programmed. In an embodiment, a voltage can be measured through a selected word line among the plurality of word lines WL0 to WLa, and thus information (i.e., programmed data) based on the resistance value of the variable resistor R of the selected memory cell MC can be read.

[0073] As Figure 3B illustrated, the variable resistor R can include a phase change layer 11 that is a variable resistor layer including germanium (Ge), antimony (Sb), and tellurium (Te) (GST, Ge-Sb-Te), an upper electrode 12 disposed on the phase change layer 11, and a lower electrode 13 disposed below the phase change layer 11.

[0074] The upper electrode 12 and the lower electrode 13 can include any one of various metals, metal oxides, and / or metal nitrides. As an example, the upper electrode 12 and the lower electrode 13 can include aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium oxide (TiOx), and / or aluminum oxide (AlOx). x Al y N zone or more of indium (In), gallium (Ga), germanium (Ge), arsenic (As), antimony (Sb), bismuth (Bi), tellurium (Te), selenium (Se), lead (Pb), tin (Sn), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), molybdenum (Mo), palladium (Pd), etc. In addition, the upper electrode 12 and the lower electrode 13 can include tin (Sn). In addition, the upper electrode 12 and the lower electrode 13 can include at least one of zirconium (Zr), zinc (Zn), IrO2, StZrO3, etc.

[0075] The phase change layer 11 can include a bipolar resistive memory material or a unipolar resistive memory material. The bipolar resistive memory material can be programmed to a set state or a reset state according to a polarity of a current, and can use a perovskite-based material. The unipolar resistive memory material can be programmed to a set state or a reset state according to a current having the same polarity, and can use a transition metal oxide such as NiO x or TiO x .

[0076] At least a portion 14 of the GST material of the phase change layer 11 can be programmed between an amorphous state having a relatively high resistivity and a crystalline state having a relatively low resistivity. The GST material can be programmed by heating the GST material. The magnitude and duration of the heating can be used to determine whether the GST material is programmed to the amorphous state or the crystalline state. The high resistivity and the low resistivity can be designated as programmed values "logic 0" and "logic 1", respectively. Conversely, the high resistivity and the low resistivity can be designated as programmed values "logic 1" and "logic 0", respectively. In either case, the high resistivity or the low resistivity can be sensed by measuring the resistivity of the GST material.

[0077] Figures 4A to 4C is a diagram illustrating a memory cell according to an embodiment.

[0078] Referring to Figure 4A , a memory cell MCa according to an embodiment can include a variable resistor R, a switch SW, and a heater H. Here, the variable resistor R can be referred to as a variable resistor or a variable resistive material, and the heater H can be referred to as a heating electrode or a heating electrode layer.

[0079] In an embodiment, the variable resistor R can be connected between the switch SW and the heater H, and the switch SW and the heater H can be connected to a bit line BL and a word line WL, respectively. In other words, one end of the switch SW can be connected to the bit line BL, and the other end thereof can be connected to the variable resistor R. In addition, one end of the heater H can be connected to the word line WL, and the other end thereof can be connected to the variable resistor R.

[0080] The variable resistor R can become one of a plurality of resistance states according to an electrical pulse (e.g., a programming current) applied thereto. According to embodiments, the variable resistor R can include a phase change material, where a crystalline state of the phase change material changes based on an amount of current. The phase change material can be various materials, such as GaSb, InSb, InSe, Sb2Te3, and GeTe produced by mixing two elements, GeSbTe (GST), GaSeTe, InSbTe, SnSb2Te4, and InSbGe produced by mixing three elements, and AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te produced by mixing four elements 81 Ge 15 Sb2S2.

[0081] The phase change material can have an amorphous state with a relatively high resistance and a crystalline state with a relatively low resistance. The phase of the phase change material can change through Joule heating that occurs based on an amount of current. Further, data can be written by using phase change. For example, a high resistance state or a reset state can be defined as "0" and a low resistance state or a set state can be defined as "1", and thus, data can be stored in the variable resistor R.

[0082] In another embodiment, the variable resistor R can include a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, rather than a phase change material.

[0083] The switch SW can control a current supply to the variable resistor R according to a current or a voltage applied to a connected word line WL. The switch SW can include a bidirectional threshold switch (OTS) including a chalcogenide compound. The OTS can include a material including arsenic (As), germanium (Ge), selenium (Se), tellurium (Te), silicon (Si), bismuth (Bi), sulfur (S), and antimony (Sb). In particular, the OTS can include a six-element material in which Se and S are added to a compound including Ge, Si, As, and Te.

[0084] The heater H can heat the variable resistor R when a data write operation (e.g., a reset / set operation) is being performed. The heater H can include a conductive material that generates heat sufficient to induce a phase change of the variable resistor R without reacting with the variable resistor R. For example, the heater H can include a carbon-based conductive material.

[0085] In the embodiments, the heater H may include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, carbon (C), SiC, SiCN, carbon nitride (CN), TiCN, TaCN, or refractory metals corresponding to combinations thereof, or their nitrides.

[0086] Reference Figure 4B According to an embodiment, the memory cell MCb may include a variable resistor Ra, and the variable resistor Ra may be connected between the bit line BL and the word line WL. The memory cell MCb may store data based on a programming current applied through the bit line BL. Furthermore, the data stored in the memory cell MCb may be read based on a read current applied through the word line WL.

[0087] Reference Figure 4C According to an embodiment, the memory cell MCc may include a variable resistor Rb and a bidirectional diode Db. The variable resistor Rb may include a resistive material for storing data. The bidirectional diode Db may be connected between the variable resistor Rb and the bit line BL, and the variable resistor Rb may be connected between the word line WL and the bidirectional diode Db. Leakage current flowing in an unselected resistive memory cell may be interrupted by the bidirectional diode Db.

[0088] Figure 5 This is a graph used for reference when describing the set operation and reset write operation performed on the variable resistor of the memory cell according to the embodiment.

[0089] Reference Figure 5 When a variable resistor is heated at a temperature between its crystallization temperature Tx and melting point Tm... Figure 3B When a phase change material (PCT) is heated for a certain period of time and then gradually cooled, it can transition (set) to a crystalline state. The crystalline state can be called the set state and can be a state that stores the data "0". Conversely, when a PCT is heated for a certain period of time at a temperature equal to or higher than its melting point Tm and then rapidly cooled, it can transition (reset) to an amorphous state. The amorphous state can be called the reset state and can be a state that stores the data "1". Data can be stored by supplying current to the variable resistor R and can be read by measuring the resistance value of the variable resistor R.

[0090] Figure 6A It is a graph showing an exemplary resistance distribution of a single-layer memory cell, and Figure 6B This is a graph illustrating an exemplary resistance distribution of a multilayer memory cell.

[0091] Referring to Figure 6A , the horizontal axis represents resistance, and the vertical axis represents the number of memory cells MC. For example, when the memory cells MC are single-layer cells programmed by 1 bit, the memory cells MC can have a low resistance state LRS or a high resistance state HRS.

[0092] The low resistance state LRS and the high resistance state HRS can each correspond to one of data "0" and data "1". In an embodiment, the resistance levels R can increase in the order of data "0" to data "1". That is, the low resistance state LRS can correspond to data "0", and the high resistance state HRS can correspond to data "1".

[0093] An operation of applying a programming current to the memory cell MC to change the memory cell MC from the high resistance state HRS to the low resistance state LRS can be referred to as a set operation or a set write operation. Also, an operation of applying a programming current to the memory cell MC to change the memory cell MC from the low resistance state LRS to the high resistance state HRS can be referred to as a reset operation or a reset write operation.

[0094] Referring to Figure 6B , the horizontal axis represents resistance, and the vertical axis represents the number of memory cells MC. For example, when the memory cells MC are single-layer cells programmed by 1 bit, the memory cells MC can have a low resistance state LRS or a high resistance state HRS.

[0095] Each of the first resistance state RS1 to the fourth resistance state RS4 can correspond to one of data "00", data "01", data "10", and data "11". In an embodiment, the resistance levels R can increase in the order of data "11", data "01", data "00", and data "10". That is, the first resistance state RS1 can correspond to data "11", the second resistance state RS2 can correspond to data "01", the third resistance state RS3 can correspond to data "00", and the fourth resistance state RS4 can correspond to data "10".

[0096] Figure 7 is a flowchart for reference in describing an operation of the memory device 100 according to an embodiment.

[0097] Referring to Figure 1and Figure 7 In operation S10, the memory device 100 can decode an address ADDR of the memory controller 200 to generate a column address (Y_ADDR) of the memory device 100. In operation S20, the memory device 100 can determine whether the column address Y_ADDR corresponds to a first edge bit line included in a first bit line group. Here, the bit line group can mean a plurality of bit lines connected to one local decoder, and the edge bit line can mean a bit line located at an outermost position in the bit line group. This will be described in detail below with reference to FIG. 1B. Figure 2 Figure 8

[0098] When the first edge bit line is selected, in operation S30, the memory device 100 can apply a non-selection voltage to a second edge bit line included in a second bit line group adjacent to the first bit line group. Here, the non-selection voltage can mean a voltage applied to a non-selected bit line of the bit line group, and in an embodiment, the non-selection voltage can be a ground voltage.

[0099] Figure 8 FIG. 1B is a block diagram illustrating a column decoder 130 according to an embodiment.

[0100] Referring to Figure 8 , the row decoder 130 of the present embodiment includes a first local decoder 131, a second local decoder 132, a global decoder 134, and a boundary transistor (TR) BT. The first local decoder 131 can be connected to a first bit line group BLG1 including a plurality of bit lines, and can activate the plurality of bit lines included in the first bit line group BLG1 according to a column address (Y_ADDR) of the memory device 100. The second local decoder 132 can be connected to a second bit line group BLG2 including a plurality of bit lines, and can activate the plurality of bit lines included in the second bit line group BLG2 according to the column address (Y_ADDR) of the memory device 100. Figure 2 Figure 2

[0101] The global decoder 134 can be connected to a plurality of local decoders (e.g., the first local decoder 131 and the second local decoder 132) through a global bit line group GBLB, and based on the column address Y_ADDR, the global decoder 134 can apply a selection voltage to a selected bit line corresponding to the plurality of bit lines connected to the first local decoder 131 and the second local decoder 132, and can apply a non-selection voltage to other bit lines.

[0102] ​​​​In an embodiment, the first local decoder 131 can activate the first bit line group BLG1 according to the column address Y_ADDR, and the second local decoder 132 can activate the second bit line group BLG2 according to the column address Y_ADDR. The global decoder 134 can apply a selection voltage to the first edge bit line EBL1 located at the outermost position in the first bit line group BLG1 according to the column address Y_ADDR, and can apply a non-selection voltage to the bit lines other than the first edge bit line EBL1 among the plurality of bit lines included in the first bit line group BLG1.

[0103] When the first edge bit line EBL1 is selected, the boundary transistor BT can apply a non-selection voltage Vuns to the second edge bit line EBL2 adjacent to the first bit line group BLG1. In an embodiment, the non-selection voltage Vuns can have the same voltage level as the voltage applied to the unselected bit lines of the first bit line group BLG1 (for example, a ground voltage).

[0104] In Figure 8 , an example in which the column decoder 130 includes two local decoders (for example, the first local decoder 131 and the second local decoder 132) is shown, but this is merely an embodiment, and it is obvious that the inventive concept can be applied to an embodiment in which the column decoder 130 includes three or more local decoders.

[0105] Further, in Figure 8 , the boundary transistor BT can apply a non-selection voltage Vuns to the second edge bit line EBL2 according to the selection of the first edge bit line EBL1, but the inventive concept is not limited thereto, and it can be understood that an embodiment can be applied to all such elements that apply a non-selection voltage Vuns to the second edge bit line EBL2 according to the selection of the first edge bit line EBL1.

[0106] Figure 9A and Figure 9B is a circuit diagram showing a column decoder according to an embodiment.

[0107] Referring to Figure 9A , the column decoder 130a according to an embodiment can include a first local decoder 131a, a second local decoder 132a, a global decoder 134a, a first boundary transistor BT1, and a second boundary transistor BT2. The first local decoder 131a can include a plurality of transistors ET1, ET2, DT1, and DT2, and the plurality of transistors ET1, ET2, DT1, and DT2 can be connected to first to fourth bit lines BL0 to BL3, respectively. The first to fourth bit lines BL0 to BL3 can configure the first bit line group BLG1.

[0108] One end of the first edge transistor ET1 and one end of the second edge transistor ET2 can be connected to the first bit line BL0 and the fourth bit line BL3, respectively, disposed at the outermost positions in the first bit line group BLG1. The other end of the first edge transistor ET1 and the other end of the second edge transistor ET2 can be connected to the first global bit line GBL0 and the fourth global bit line GBL3, respectively. According to an embodiment, the other end of the first edge transistor ET1 and the other end of the second edge transistor ET2 can be connected to unselected power sources, such as a ground node and a power source node, rather than global bit lines.

[0109] In addition, one end of the first decode transistor DT1 and one end of the second decode transistor DT2 can be connected to the second bit line BL1 and the third bit line BL2, respectively. The other end of the first decode transistor DT1 and the other end of the second decode transistor DT2 can be connected to the second global bit line GBL1 and the third global bit line GBL2.

[0110] Here, like the first bit line BL0 and the fourth bit line BL3, a bit line located at the outermost position in one bit line group can be referred to as an edge bit line. In addition, a transistor connected to the edge bit line and included in the first local decoder 131a and the second local decoder 132a can be referred to as an edge transistor, and a transistor other than the edge transistor among the transistors of the first local decoder 131a and the second local decoder 132a can be referred to as a decode transistor (e.g., the first decode transistor DT1 and the second decode transistor DT2).

[0111] The first bit line group selection signal Sel_BLG1 can be received by the plurality of transistors ET1, ET2, DT1, and DT2 included in the first local decoder 131a. The plurality of transistors ET1, ET2, DT1, and DT2 included in the first local decoder 131a can electrically connect or disconnect the first bit line group BLG1 to or from the first to fourth global bit lines GBL0 to GBL3 according to the first bit line group selection signal Sel_BLG1.

[0112] Like the first local decoder 131a, the second local decoder 132a can include a plurality of transistors and can electrically connect or disconnect the second bit line group BLG2 to or from the first to fourth global bit lines GBL0 to GBL3 according to the second bit line group selection signal Sel_BLG2. In an embodiment, the first bit line group selection signal Sel_BLG1 and the second bit line group selection signal Sel_BLG2 can include a column address (Y_ADDR) of the memory cell array 100. Figure 2

[0113] ​The global decoder 134a can include a plurality of transistors (e.g., complementary metal-oxide-semiconductor (CMOS) transistors) connected to the first to fourth global bit lines GBL0 to GBL3. The plurality of transistors included in the global decoder 134a can apply a selection voltage Vsel or a non-selection voltage Vuns to the first to fourth global bit lines GBL0 to GBL3, respectively, according to a plurality of global bit line selection signals Sel_GBL0 to Sel_GBL3. In an embodiment, the first to fourth global bit lines GBL0 to GBL3 can be included in a column address Y_ADDR.

[0114] One end of the first boundary transistor BT1 can be connected to a fifth bit line BL4 disposed closest to the first bit line group BLG1 among the second bit line group BLG2, and the other end of the first boundary transistor BT1 can be connected to the first global bit line GBL0. Also, a gate of the first boundary transistor BT1 can receive a first bit line group selection signal Sel_BLG1. The first boundary transistor BT1 can electrically connect or disconnect the fifth bit line BL4 to or from the first global bit line GBL0 according to the first bit line group selection signal Sel_BLG1.

[0115] One end of the second boundary transistor BT2 can be connected to a fourth bit line BL3 disposed closest to the second bit line group BLG2 among the first bit line group BLG1, and the other end of the second boundary transistor BT2 can be connected to the fourth global bit line GBL3. Also, a gate of the second boundary transistor BT2 can receive a second bit line group selection signal Sel_BLG2. The second boundary transistor BT2 can electrically connect or disconnect the fourth bit line BL3 to or from the fourth global bit line GBL3 according to the second bit line group selection signal Sel_BLG2.

[0116] In an embodiment in which the fourth bit line BL3 is selected, the first bit line group selection signal Sel_BLG1 can have an on state (e.g., a logic high level), and the second bit line group selection signal Sel_BLG2 can have an off state (e.g., a logic low level). Accordingly, the first local decoder 131a can electrically connect the first bit line group BLG1 to the first to fourth global bit lines GBL0 to GBL3, and the second local decoder 132a can electrically disconnect the second bit line group BLG2 from the first to fourth global bit lines GBL0 to GBL3.

[0117] In addition, based on the plurality of global bit line selection signals (e.g., first to fourth global bit line selection signals) Sel_GBL0 to Sel_GBL3, the global decoder 134a can apply the unselect voltage Vuns to the first to third global bit lines GBL0 to GBL2, and can apply the select voltage Vsel to the fourth global bit line GBL3 connected with the fourth bit line BL3. To this end, the first to third global bit line selection signals Sel_GBL0 to Sel_GBL2 can have an off state (e.g., a logic low level), and the fourth global bit line selection signal Sel_GBL3 can have an on state (e.g., a logic high level).

[0118] Accordingly, the unselect voltage Vuns can be applied to the first to third bit lines BL0 to BL2 connected to the first to third global bit lines GBL0 to GBL2, respectively, and the select voltage Vsel can be applied to the fourth bit line BL3 connected to the fourth global bit line GBL3.

[0119] In addition, the second bit line group BLG2 electrically disconnected by the transistor included in the second local decoder 132a can be in an electrically floating state. Based on the first bit line group selection signal Sel_BLG1, the first boundary transistor BT1 can electrically connect the first global bit line GBL0 to the fifth bit line BL4, and can apply the unselect voltage Vuns to the fifth bit line BL4 disposed closest to the first bit line group BLG1 among the second bit line group BLG2.

[0120] When the peripheral bit lines near the selected bit line are in a floating state, read disturbance can occur due to parasitic capacitance between the selected bit line and the peripheral bit lines. According to an embodiment, the first boundary transistor BT1 can apply the unselect voltage Vuns to bias the edge bit line (e.g., BL4) adjacent to the selected bit line (e.g., BL3) according to the first bit line group selection signal Sel_BLG1, thereby preventing read disturbance.

[0121] In Figure 9A In the above-described embodiment, an example in which four bit lines are included in one bit line group BLG1 or BLG2 is shown, but this is merely an embodiment, and five or more bit lines or three or less bit lines (e.g., 8, 16, 32, 64, or 128 bit lines) can be included in one bit line group.

[0122] In addition, in Figure 9AThe example shown illustrates a first boundary transistor BT1 connected to a first global bit line GBL0. However, this is merely one embodiment, and the first boundary transistor BT1 may be connected to a fourth bit line BL3 corresponding to an edge bit line, or one of the first to third global bit lines GBL0 to GBL2, instead of the fourth global bit line GBL3 connected to the fifth bit line BL4 in the second bit line group, which corresponds to the edge bit line adjacent to the first bit line group. Similarly, the second boundary transistor BT2 may be connected to one of the global bit lines GBL1 to GBL3 instead of the first global bit line GBL0.

[0123] Reference Figure 9B The multiple transistors included in the first local decoder 131b can each be a p-type metal-oxide-semiconductor (PMOS) transistor. In this case, the first boundary transistor BT1 can be configured as a PMOS transistor. Furthermore, when the multiple transistors included in the second local decoder 132b are PMOS transistors, the second boundary transistor BT2 can be configured as a PMOS transistor.

[0124] Figure 9B The column decoder 130b can execute with Figure 9A The column decoder 130a operates in the same or similar manner, but is used for items included in the column decoder. Figure 9B The control signals of various transistors in the column decoder 130b can have the same characteristics as... Figure 9A The logic levels of the column decoder 130a are opposite to the logic levels. Figure 10 This is a circuit diagram illustrating a column decoder 130c according to an embodiment. In detail, Figure 10 An embodiment is shown in which multiple boundary transistors BT1 to BT4 are connected to different global bit lines GBL0 to GBL3. (Compared to...) Figure 9A Descriptions that are identical or similar to those in the original text are omitted.

[0125] Reference Figure 10 The column decoder 130c may include a first local decoder 131c, a second local decoder 132c, a third local decoder 133c, a global decoder 134c, and multiple boundary transistors (e.g., first to fourth boundary transistors) BT1 to BT4.

[0126] One end of the first boundary transistor BT1 can be connected to the fifth bit line BL4, which is closest to the first bit line group BLG1 in the second bit line group BLG2, and the other end of the first boundary transistor BT1 can be connected to the first global bit line GBL0. The first boundary transistor BT1 can electrically connect the fifth bit line BL4 to the first global bit line GBL0 or disconnect it from the first global bit line GBL0 according to the first bit line group selection signal Sel_BLG1.

[0127] One end of a second boundary transistor BT2 can be connected to a fourth bit line BL3 in the first bit line group BLG1 disposed closest to the second bit line group BLG2, and the other end of the second boundary transistor BT2 can be connected to a second global bit line GBL1. The second boundary transistor BT2 can electrically connect or disconnect the fourth bit line BL3 to or from the second global bit line GBL1 according to a second bit line group selection signal Sel_BLG2.

[0128] One end of a third boundary transistor BT3 can be connected to a ninth bit line BL8 in the third bit line group BLG3 disposed closest to the second bit line group BLG2, and the other end of the third boundary transistor BT3 can be connected to a third global bit line GBL2. The third boundary transistor BT3 can electrically connect or disconnect the ninth bit line BL8 to or from the third global bit line GBL2 according to a second bit line group selection signal Sel_BLG2.

[0129] One end of a fourth boundary transistor BT4 can be connected to an eighth bit line BL7 in the second bit line group BLG2 disposed closest to the third bit line group BLG32, and the other end of the fourth boundary transistor BT4 can be connected to a fourth global bit line GBL3. The fourth boundary transistor BT4 can electrically connect or disconnect the eighth bit line BL7 to or from the fourth global bit line GBL3 according to a third bit line group selection signal Sel_BLG3.

[0130] According to an embodiment, the plurality of boundary transistors BT1 to BT4 can be connected to different global bit lines GBL0 to GBL3. In an embodiment, odd boundary transistors (e.g., the first boundary transistor BT1 and the third boundary transistor BT3) can be connected to odd global bit lines (e.g., the first global bit line GBL0 and the third global bit line GBL2), and even boundary transistors (e.g., the second boundary transistor BT2 and the fourth boundary transistor BT4) can be connected to even global bit lines (e.g., the second global bit line GBL1 and the fourth global bit line GBL3).

[0131] Figure 11 is a circuit diagram illustrating a column decoder 130d according to an embodiment. In detail, Figure 11 An embodiment in which the other ends of the boundary transistors BT1 and BT2 are connected to a ground terminal is illustrated. The same or similar descriptions as those of Figure 9A The same or similar descriptions as those of

[0132] Referring to Figure 11The column decoder 130d can include a first local decoder 131d, a second local decoder 132d, a global decoder 134d, and a plurality of boundary transistors (e.g., first and second boundary transistors) BT1 and BT2. One end of the first boundary transistor BT1 can be connected to the fifth bit line BL4, and the other end of the first boundary transistor BT1 can be connected to a ground node. The first boundary transistor BT1 can apply a ground voltage GND to the fifth bit line BL4 according to a first bit line group selection signal Sel_BLG1. One end of the second boundary transistor BT2 can be connected to the fourth bit line BL3, and the other end of the second boundary transistor BT2 can be connected to the ground node. The second boundary transistor BT2 can apply the ground voltage GND to the fourth bit line BL3 according to a second bit line group selection signal Sel_BLG2.

[0133] According to an embodiment, the other ends of the first and second boundary transistors BT1 and BT2 can be connected to the ground node, and thus, the ground voltage GND can be applied to bias the edge bit line (e.g., BL4) adjacent to the selected bit line (e.g., BL3).

[0134] Figure 12 is a circuit diagram illustrating a column decoder 130e according to an embodiment. In detail, Figure 12 Embodiments are illustrated in which the other ends of the boundary transistors BT1 and BT2 are connected to the first node N1 or the second node N2. The same or similar descriptions as those of Figure 9A are omitted.

[0135] Referring to Figure 12 , the column decoder 130e can include a first local decoder 131e, a second local decoder 132e, a global decoder 134e, and a plurality of boundary transistors (e.g., first and second boundary transistors) BT1 and BT2. One end of the first boundary transistor BT1 can be connected to the fifth bit line BL4, and the other end of the first boundary transistor BT1 can be connected to the first node N1. The first boundary transistor BT1 can electrically connect or disconnect the fifth bit line BL4 to or from the first node N1 according to a first bit line group selection signal Sel_BLG1. One end of the second boundary transistor BT2 can be connected to the fourth bit line BL3, and the other end of the second boundary transistor BT2 can be connected to the second node N2. The second boundary transistor BT2 can electrically connect or disconnect the fourth bit line BL3 to or from the second node N2 according to a second bit line group selection signal Sel_BLG2.

[0136] In an embodiment, when the fourth bit line BL3 is selected, the first node N1 can be pre-charged with the unselect voltage Vuns, and based on the first bit line group selection signal Sel BLG1, the first boundary transistor BT1 can connect the first node N1 to the fifth bit line BL4 to apply the unselect voltage Vuns to bias the fifth bit line BL4.

[0137] In an embodiment, the first node N1 and the second node N2 can have a voltage level of the unselect voltage Vuns, and based on the first bit line group selection signal Sel BLG1, the first boundary transistor BT1 can connect the first node N1 to the fifth bit line BL4 to apply the unselect voltage Vuns to bias the fifth bit line BL4.

[0138] Figure 13 is a block diagram illustrating a memory device 100f according to an embodiment. In detail, Figure 13 An embodiment in which each of the plurality of boundary transistors BT1 and BT2 receives a boundary selection signal Sel_BT1 and Sel_BT2 is illustrated. The detailed description of Figure 8 the same as or similar to that of

[0139] Referring to Figure 13 , the memory device 100f can include a first local decoder 131f, a second local decoder 132f, a global decoder 134f, a plurality of boundary transistors (e.g., first and second boundary transistors) BT1 and BT2, and a boundary decoder 170f. The first local decoder 131f, the second local decoder 132f, and the global decoder 134f can be the same as or similar to the first local decoder 131, the second local decoder 132, and the global decoder 134 of Figure 8 , and thus a detailed description thereof is omitted.

[0140] The boundary decoder 170f can receive an address ADDR, and based on the address ADDR, the boundary decoder 170f can output a first boundary selection signal Sel_BT1 to the first boundary transistor BT1 and can output a second boundary selection signal Sel_BT2 to the second boundary transistor BT2. In an embodiment, the boundary decoder 170f can be included in the control logic (140) of Figure 2 .

[0141] In an embodiment in which the first edge bit line EBL1 included in the first bit line group BLG1 is selected, the boundary decoder 170f can output the first boundary selection signal Sel_BT1 in an on state (e.g., a logic high level) and the second boundary selection signal Sel_BT2 in an off state (e.g., a logic low level) based on the address ADDR.

[0142] According to an on state of the first boundary selection signal Sel_BT1, the first boundary transistor BT1 can apply a non-selection voltage Vuns to bias a second edge bit line BL2 disposed closest to a first bit line group BLG1 among the second bit line group BLG2.

[0143] In Figure 13 , an example in which the boundary decoder 170f receives the address ADDR is shown, but in other embodiments, the boundary decoder 170f can receive a column address (X_ADDR) from the control logic 140) and can generate the first boundary selection signal Sel_BT1 and the second boundary selection signal Sel_BT2 according to the column address X_ADDR. Figure 2 Figure 2 In , an example in which the boundary decoder 170f receives the address ADDR is shown, but in other embodiments, the boundary decoder 170f can receive a column address (X_ADDR) from the control logic 140) and can generate the first boundary selection signal Sel_BT1 and the second boundary selection signal Sel_BT2 according to the column address X_ADDR.

[0144] Figure 14 Figure 14 is a circuit diagram illustrating a column decoder 130f according to an embodiment. In detail, Figure 9A embodiments described in are omitted.

[0145] Referring to Figure 13 and Figure 14 , the column decoder 130f can include a first partial decoder 131f, a second partial decoder 132f, a global decoder 134f, and a plurality of boundary transistors (e.g., first and second boundary transistors) BT1 and BT2. One end of the first boundary transistor BT1 can be connected to a fifth bit line BL4, and the other end of the first boundary transistor BT1 can be connected to a first global bit line GBL0. The first boundary transistor BT1 can electrically connect or disconnect the fifth bit line BL4 to or from the first global bit line GBL0 according to the first boundary selection signal Sel_BT1 received independently of the first bit line group selection signal Sel_BLG1.

[0146] One end of the second boundary transistor BT2 can be connected to a fourth bit line BL3, and the other end of the second boundary transistor BT2 can be connected to a fourth global bit line GBL3. The second boundary transistor BT2 can electrically connect or disconnect the fourth bit line BL3 to or from the fourth global bit line GBL3 according to the second boundary selection signal Sel_BT2 received independently of the second bit line group selection signal Sel_BLG2.

[0147] Figure 15 is a block diagram illustrating a memory device 100g according to an embodiment. In detail, Figure 15Embodiments are shown in which each of the plurality of local decoders (e.g., the first local decoder 131g and the second local decoder 132g) includes a CMOS edge transistor. As with Figure 8 The same or similar descriptions as those of the description of

[0148] Referring to Figure 15 , the memory device 100g can include a first local decoder 131g, a second local decoder 132g, and a global decoder 134g. The global decoder 134g can be the same as or similar to the global decoder 134 of Figure 8 , and thus a detailed description thereof is omitted.

[0149] The first local decoder 131g can include a first CMOS edge transistor CET1, and the second local decoder 132g can include a second CMOS edge transistor CET2. The first CMOS edge transistor CET1 can be connected to the first edge bit line EBL1, and the second CMOS edge transistor CET2 can be connected to the second edge bit line EBL2.

[0150] The first CMOS edge transistor CET1 can apply a non-selection voltage Vuns to the first edge bit line EBL1 when the first bit line group BLG1 is not selected, and the second CMOS edge transistor CET2 can apply the non-selection voltage Vuns to the second edge bit line EBL2 when the second bit line group BLG2 is not selected. In embodiments in which the first edge bit line EBL1 is selected, the second CMOS edge transistor CET2 can apply the non-selection voltage Vuns to the second edge bit line EBL2.

[0151] Figure 16 is a circuit diagram illustrating a column decoder 130g according to an embodiment. In detail, Figure 16 The column decoder 130g including a CMOS edge transistor is explained. Here, the same or similar descriptions as those of the description of Figure 9A and Figure 15 are omitted to avoid redundancy.

[0152] Referring to Figure 16 , the column decoder 130g can include a first local decoder 131g, a second local decoder 132g, and a global decoder 134g. The global decoder 134g can be the same as or similar to the global decoder 134A of Figure 9A , and thus a detailed description thereof is omitted.

[0153] The first local decoder 131g can include a first edge transistor ET1, a second edge transistor ET2, a first decode transistor DT1, a second decode transistor DT2, a third edge transistor ET3, and a fourth edge transistor ET4. The first edge transistor ET1 and the second edge transistor ET2 can configure a first CMOS edge transistor CET1, and the third edge transistor ET3 and the fourth edge transistor ET4 can configure a second CMOS edge transistor CET2.

[0154] The first CMOS edge transistor CET1 can connect the first bit line BL0 to one of the first global bit line GBL0 and a ground node according to the first bit line group selection signal Sel BLG1, and the second CMOS edge transistor CET2 can connect the fourth bit line BL3 to one of the fourth global bit line GBL3 and the ground node according to the first bit line group selection signal Sel BLG1.

[0155] The second local decoder 132g can include a fifth edge transistor ET5, a sixth edge transistor ET6, a seventh edge transistor ET7, and an eighth edge transistor ET8. The fifth edge transistor ET5 and the sixth edge transistor ET6 can configure a third CMOS edge transistor CET3, and the seventh edge transistor ET7 and the eighth edge transistor ET8 can configure a fourth CMOS edge transistor CET4.

[0156] The third CMOS edge transistor CET3 can connect the fifth bit line BL4 to one of the first global bit line GBL0 and the ground node according to the second bit line group selection signal Sel BLG2, and the fourth CMOS edge transistor CET4 can connect the eighth bit line BL7 to one of the fourth global bit line GBL3 and the ground node according to the second bit line group selection signal Sel BLG2.

[0157] In an embodiment in which the fourth bit line BL3 is selected, when the first bit line group selection signal Sel BLG1 is in an on state (e.g., a logic high level), the first CMOS edge transistor CET1 can connect the first bit line BL0 to the first global bit line GBL0, and a non-selection voltage Vuns (e.g., a ground voltage) can be applied to the first global bit line GBL0 through the global decoder 134g, so that the non-selection voltage Vuns can be applied to the first bit line BL0. When the first bit line group selection signal Sel BLG1 is in the on state (e.g., the logic high level), the second CMOS edge transistor CET2 can connect the fourth bit line BL3 to the fourth global bit line GBL3, and a selection voltage Vsel can be applied to the fourth global bit line GBL3 through the global decoder 134g, so that the selection voltage Vsel can be applied to the fourth bit line BL3.

[0158] Further, when the second bit line group selection signal Sel BLG2 is in an off state (e.g., a logic low level), the third CMOS edge transistor CET3 can connect the fifth bit line BL4 to a ground node, and the unselect voltage Vuns can be applied to the fifth bit line BL4. When the second bit line group selection signal Sel BLG2 is in an off state (e.g., a logic low level), the fourth CMOS edge transistor CET4 can connect the eighth bit line BL7 to a ground node, and the unselect voltage Vuns can be applied to the eighth bit line BL7.

[0159] According to embodiments, the first and second local decoders 131g and 132g can each include CMOS edge transistors, and when a bit line group is not selected, the CMOS edge transistors can bias the edge bit line to an unselect voltage, thereby preventing read / write disturbance.

[0160] In Figure 16 , an example is shown in which the CMOS edge transistors include PMOS transistors connected to a ground node and NMOS transistors connected to a global bit line. However, this is merely an example, and the inventive concept can be applied to embodiments in which the CMOS edge transistors include PMOS transistors connected to a ground node or an unselect voltage source node and NMOS transistors connected to a global bit line.

[0161] Figure 17A and Figure 17B are diagrams used for reference in describing the local decoders according to embodiments. In particular, Figure 17A and Figure 17B are used for reference in describing an example of the first local decoder 131g. Figure 16

[0162] Referring to Figure 17A , the first local decoder 131g according to embodiments can include a first edge transistor ET1, a second edge transistor ET2, a first decode transistor DT1, a second decode transistor DT2, a third edge transistor ET3, and a fourth edge transistor ET4. A gate of the first edge transistor ET1 and a gate of the second edge transistor ET2 can be connected to a common node for configuring a first CMOS edge transistor CET1 connected to a bit line BL0, and a gate of the third edge transistor ET3 and a gate of the fourth edge transistor ET4 can be connected to another common node for configuring a second CMOS edge transistor CET2 connected to a bit line BL3. In this example, the first decode transistor DT1 is gated to a bit line BL1, and the second decode transistor DT2 is gated to a bit line BL2.

[0163] Referring to Figure 17B ​The active region of the first edge transistor ET1 can be connected to the first bit line BL0 through the first via V1, the first metal layer ML1, the second via V2, the second metal layer ML2, the third via V3, the third metal layer ML3, and the fourth via V4. According to an embodiment, the active region of the second edge transistor ET2 can share the first via V1, the first metal layer ML1, the second via V2, the second metal layer ML2, and the third via V3 with the first edge transistor ET1, and can be connected to the first bit line BL0 by separately using the third metal layer ML3 and the fifth via V5. Accordingly, the second edge transistor ET2 can be disposed under a cell region Area_C in which the cell CL and the word line WL are disposed.

[0164] Figure 18 is a block diagram illustrating an example in which a memory device according to an embodiment is applied to a solid state drive (SSD) system.

[0165] Referring to Figure 18 The SSD system 1000 according to an embodiment can include a host 1100 and an SSD 1200. The SSD 1200 can transmit and receive a signal (SGL) to and from the host 1100 through a signal connector, and can supply power (PWR) through a power supply connector. The SSD 1200 can include an SSD controller 1210, an auxiliary power supply 1220, and a plurality of nonvolatile memory devices 1230, 1240, and 1250. At least one of the plurality of nonvolatile memory devices 1230, 1240, and 1250 can be a resistive memory device according to one or more embodiments described above.

[0166] The SSD controller 1210 can be connected to the plurality of nonvolatile memory devices 1230, 1240, and 1250 through a plurality of channels Ch1 to Chn, and can store data in or read data from the plurality of nonvolatile memory devices 1230, 1240, and 1250.

[0167] While the present concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A resistive memory device, comprising: a first bit line group including a first edge bit line; a second bit line group including a second edge bit line; and a first boundary transistor having one end connected to one of a plurality of global bit lines and the other end connected to the second edge bit line, and configured to be turned on when the first edge bit line is selected to apply a non-selection voltage provided by the one of the plurality of global bit lines to the second edge bit line, wherein the first edge bit line is disposed closest to the second bit line group in the first bit line group, and the second edge bit line is disposed closest to the first bit line group in the second bit line group. 2.The resistive memory device of claim 1, further comprising: a second boundary transistor configured to apply the non-selection voltage to the first edge bit line when the second edge bit line is selected; a first edge transistor configured to apply a selection voltage to the first edge bit line according to a first bit line group selection signal; and a second edge transistor configured to apply the selection voltage to the second edge bit line according to a second bit line group selection signal. the first boundary transistor is configured to apply the non-selection voltage to the second edge bit line according to the first bit line group selection signal, and the second boundary transistor is configured to apply the non-selection voltage to the first edge bit line according to the second bit line group selection signal.

3. The resistive memory device of claim 2, wherein, 4.The resistive memory device of claim 3, wherein the first edge transistor is connected to a first global bit line of the plurality of global bit lines, and the first bit line group selection signal is applied to a gate of the first boundary transistor, the one end of the first boundary transistor being connected to a second global bit line of the plurality of global bit lines. 5.The resistive memory device of claim 3, wherein the second bit line group further includes a third edge bit line, the resistive memory device further comprising: a third bit line group including a fourth edge bit line; a third boundary transistor configured to apply the non-selection voltage to the fourth edge bit line when the third edge bit line is selected; a fourth boundary transistor configured to apply the non-selection voltage to the third edge bit line when the fourth edge bit line is selected, and the third edge bit line is disposed closest to the third bit line group in the second bit line group, and the fourth edge bit line is disposed closest to the second bit line group in the third bit line group. the plurality of global bit lines are configured to deliver the selection voltage or the non-selection voltage to a plurality of bit lines included in each of the first bit line group to the third bit line group, wherein the one end of the first boundary transistor is connected to a first global bit line of the plurality of global bit lines, one end of the second boundary transistor is connected to a second global bit line of the plurality of global bit lines, 6. The resistive memory device of claim 5, wherein, one end of the third boundary transistor is connected to a third global bit line of the plurality of global bit lines, and one end of the fourth boundary transistor is connected to a fourth global bit line of the plurality of global bit lines. ​ ​ One end of the fourth boundary transistor is connected to a fourth global bit line of the plurality of global bit lines.

7. The resistive memory device of claim 6, further comprising a global decoder configured to select one global bit line from among the first global bit line to the fourth global bit line according to at least one global bit line select signal.

8. The resistive memory device of claim 7, wherein, The at least one global bit line select signal includes a first global bit line select signal, a second global bit line select signal, a third global bit line select signal, and a fourth global bit line select signal, and wherein the global decoder includes: a first global transistor configured to apply the select voltage to the first global bit line according to the first global bit line select signal; a second global transistor configured to apply the select voltage to the second global bit line according to the second global bit line select signal; a third global transistor configured to apply the select voltage to the third global bit line according to the third global bit line select signal; and a fourth global transistor configured to apply the select voltage to the fourth global bit line according to the fourth global bit line select signal.

9. The resistive memory device of claim 3, wherein, A ground voltage is applied to the one end of the first boundary transistor, and When the first edge bit line is selected, the ground voltage is applied to the second edge bit line.

10. The resistive memory device of claim 2, further comprising a boundary decoder configured to receive an address and to generate at least one of a first boundary select signal and a second boundary select signal according to the address, wherein the first boundary transistor is configured to apply the non-select voltage to the second edge bit line according to the first boundary select signal, and the second boundary transistor is configured to apply the non-select voltage to the first edge bit line according to the second boundary select signal.

11. The resistive memory device of claim 1, wherein, The second bit line group further includes a first intermediate bit line, and When the first edge bit line is selected, the first intermediate bit line is floated.

12. A resistive memory device, comprising: a first bit line group including a first edge bit line; a second bit line group including a second edge bit line; a first edge transistor configured to apply a select voltage to the first edge bit line according to a first select signal; a second edge transistor configured to apply the select voltage to the second edge bit line according to a second select signal; a third edge transistor configured to apply a non-select voltage to the first edge bit line according to the first select signal; and a fourth edge transistor configured to apply the non-select voltage to the second edge bit line according to the second select signal, wherein the first select signal is applied to a gate of the first edge transistor, one end of the first edge transistor is connected to a first global bit line of a plurality of global bit lines, and another end of the first edge transistor is connected to the first edge bit line, ​ the second selection signal is applied to a gate of the second edge transistor, one end of the second edge transistor is connected to a second global bit line of the plurality of global bit lines, and the other end of the second edge transistor is connected to the second edge bit line, the first selection signal is applied to a gate of the third edge transistor, one end of the third edge transistor is connected to the first edge bit line, and the non-selection voltage is applied to the other end of the third edge transistor, and the second selection signal is applied to a gate of the fourth edge transistor, one end of the fourth edge transistor is connected to the second edge bit line, and the non-selection voltage is applied to the other end of the fourth edge transistor.

13. The resistive memory device of claim 12, wherein, the first edge bit line is disposed closest to the second bit line group in the first bit line group, and the second edge bit line is disposed closest to the first bit line group in the second bit line group.

14. The resistive memory device of claim 12, wherein, each of the first edge transistor and the third edge transistor includes a complementary metal oxide semiconductor transistor, and each of the second edge transistor and the fourth edge transistor includes a complementary metal oxide semiconductor transistor.

15. The resistive memory device of claim 12, wherein, each of the first edge transistor and the second edge transistor includes an N-channel metal oxide semiconductor transistor, and each of the third edge transistor and the fourth edge transistor includes a P-channel metal oxide semiconductor transistor.

16. The resistive memory device of claim 12, further comprising: a first metal layer electrically connected to the first edge bit line; and a second metal layer connected to the first edge bit line through the first metal layer, wherein the first edge transistor is electrically connected to the third edge transistor through the second metal layer.

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