Switch Chip

Abstract

A switch chip includes a first switch element, a first electrostatic discharge protection device, and a second electrostatic discharge protection device. The first switch element is electrically coupled between a first pad and a second pad. The first electrostatic discharge protection device is electrically coupled to a third pad, and the third pad is electrically coupled to the first pad through a first wire. The second electrostatic discharge protection device is electrically coupled to a fourth pad, and the fourth pad is electrically coupled to the second pad through a second wire.

Description

Technical Field

[0001] The present invention relates to a multiplexer and a demultiplexer, and in particular to a bidirectional passive N:M multiplexer and an M:N demultiplexer which utilize complementary metal oxide semiconductor (CMOS) technology and packaged bond wires to replace die routing, and are applied to data stream transmission of high-speed signals (where N is greater than M). Background Art

[0002] Although processors often process data in parallel, data is communicated in serial form between points. At the transmitting end of a communication circuit, a serializer circuit is often used to serialize parallel data, while at the receiving end, a deserializer circuit is more often used to parallelize serial data. Bidirectional communication circuits often use devices that perform serialization and deserialization, which are called serializers and deserializers, or more commonly SerDes.

[0003] In some applications, data can be transmitted from one point to another point, or from one point to any number of other points, at different transmission rates. When sending data at different transmission rates, the SerDes devices used in the communication circuit operate at correspondingly different frequencies. Summary of the invention

[0004] The present invention proposes a switch chip (multiplexer / demultiplexer) and uses packaged wires (bondwires) to replace metal traces in the crystal grain, so that the inductance value between each component in the crystal grain can be more accurately controlled, and the design flexibility is increased. In addition, since the impedance value of the wire is small, the conduction loss is reduced, and the wire does not have the dielectric loss of the metal traces in the crystal grain. In addition, the use of wires to couple different components in the crystal grain helps to expand the operating bandwidth of the switch chip, so that the switch chip can achieve the purpose of wide operating bandwidth, low insertion loss, low return loss and high isolation.

[0005] In view of this, the present invention proposes a switch chip. The switch chip includes a first switch element, a first electrostatic discharge protection device and a second electrostatic discharge protection device. The first switch element is electrically coupled between a first pad and a second pad. The first electrostatic discharge protection device is electrically coupled to a third pad, wherein the third pad is electrically coupled to the first pad through a first wire. The second electrostatic discharge protection device is electrically coupled to a fourth pad, wherein the fourth pad is electrically coupled to the second pad through a second wire.

[0006] The present invention further proposes a switch chip, which includes a first switch element, a second switch element, a first electrostatic discharge protection device, a second electrostatic discharge protection device and a third electrostatic discharge protection device. The first switch element is electrically coupled between a first pad and a second pad. The second switch element is electrically coupled between the first pad and a third pad. The first electrostatic discharge protection device is electrically coupled to a fourth pad, wherein the fourth pad is electrically coupled to the first pad through a first wire. The second electrostatic discharge protection device is electrically coupled to a fifth pad, wherein the fifth pad is electrically coupled to the second pad through a second wire. The third electrostatic discharge protection device is electrically coupled to a sixth pad, wherein the sixth pad is electrically coupled to the third pad through a third wire.

[0007] The present invention further proposes a switch chip, the switch chip includes a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, a sixth switch element, a first electrostatic discharge protection device, a second electrostatic discharge protection device, a third electrostatic discharge protection device, a fourth electrostatic discharge protection device and a fifth electrostatic discharge protection device. The first switch element is electrically coupled between a first pad and a second pad. The second switch element is electrically coupled between the second pad and a third pad. The third switch element is electrically coupled between a fourth pad and a fifth pad. The fourth switch element is electrically coupled between the fifth pad and a sixth pad. The fifth switch element is electrically coupled between a seventh pad and an eighth pad. The sixth switch element is electrically coupled between the eighth pad and a ninth pad. The first electrostatic discharge protection device is electrically coupled to a tenth pad, wherein the tenth pad is electrically coupled to the first pad through a first wire, electrically coupled to the fourth pad through a second wire, and electrically coupled to the seventh pad through a third wire. The second electrostatic discharge protection device is electrically coupled to an eleventh pad, wherein the eleventh pad is electrically coupled to the third pad through a fourth wire, electrically coupled to the sixth pad through a fifth wire, and electrically coupled to the ninth pad through a sixth wire. The third electrostatic discharge protection device is electrically coupled to a twelfth pad, wherein the twelfth pad is electrically coupled to the second pad through a seventh wire. The fourth electrostatic discharge protection device is electrically coupled to a thirteenth pad, wherein the thirteenth pad is electrically coupled to the fifth pad through an eighth wire. The fifth electrostatic discharge protection device is electrically coupled to a fourteenth pad, wherein the fourteenth pad is electrically coupled to the eighth pad through a ninth wire.

[0008] The present invention further provides a switch chip, the switch chip comprising a first pin, a second pin and a die. The first pin is electrically coupled to a first pad via a first wire. The second pin is electrically coupled to a second pad via a second wire. The die comprises a first switch element, one end of the first switch element is coupled to the first pad via a third wire, and the other end of the first switch element is coupled to the second pad via a fourth wire.

[0009] The present invention further proposes a switch chip, the switch chip comprising a first pin, a second pin, a third pin and a die. The first pin is electrically coupled to a first pad via a first wire. The second pin is electrically coupled to a second pad via a second wire. The third pin is electrically coupled to a third pad via a third wire. The die comprises a first switch element and a second switch element. One end of the first switch element is electrically coupled to the second pad via a fourth wire, one end of the second switch element is electrically coupled to the third pad via a fifth wire, and the other end of the first switch element and the other end of the second switch element are electrically coupled to the first pad via a sixth wire.

[0010] The present invention further proposes a switch chip, the switch chip comprising a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a die. The first pin is electrically coupled to a first pad through a first wire. The second pin is electrically coupled to a second pad through a second wire. The third pin is electrically coupled to a third pad through a third wire. The fourth pin is electrically coupled to a fourth pad through a fourth wire. The fifth pin is electrically coupled to a fifth pad through a fifth wire. The die comprises a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element and a sixth switch element. One end of the first switch element is electrically coupled to the first pad through a sixth wire. One end of the second switch element is electrically coupled to the second pad through a seventh wire, and the other end of the first switch element and the other end of the second switch element are electrically coupled to the third pad through an eighth wire. One end of the third switch element is electrically coupled to the first pad via a ninth wire. One end of the fourth switch element is electrically coupled to the second pad via a tenth wire, and the other end of the third switch element and the other end of the fourth switch element are electrically coupled to the fourth pad via an eleventh wire. One end of the fifth switch element is electrically coupled to the first pad via a twelfth wire. One end of the sixth switch element is electrically coupled to the second pad via a thirteenth wire, and the other end of the fifth switch element and the other end of the sixth switch element are electrically coupled to the fifth pad via a fourteenth wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram showing a switch chip according to an embodiment;

[0012] Figure 2 is a schematic diagram showing a switch chip according to an embodiment of the present invention;

[0013] Figure 3 is an equivalent circuit diagram showing a switch chip according to an embodiment of the present invention;

[0014] Figure 4 is a schematic diagram showing a 1:2 demultiplexer or a 2:1 multiplexer composed of a plurality of switch elements according to another embodiment of the present invention; and

[0015] Figure 5 It is a schematic diagram showing a 2:3 demultiplexer or a 3:2 multiplexer formed by a plurality of switch elements according to another embodiment of the present invention.

[0016]

Explanation of symbols

[0017] 100, 200, 400, 500: switch chip

[0018] 110, 210, 410, 510: Grain

[0019] 120, 420, 520: First pin

[0020] 130, 430, 530: Second pin

[0021] 111, 211, 411, 511: first switch element

[0022] 300: Equivalent circuit

[0023] 412, 512: second switch element

[0024] 513: third switch element

[0025] 514: fourth switch element

[0026] 515: fifth switch element

[0027] 516: Sixth switch element

[0028] 440, 540: Third pin

[0029] 550: Fourth pin

[0030] 560: Fifth pin

[0031] ESD1: The first electrostatic discharge protection device

[0032] ESD2: Second electrostatic discharge protection device

[0033] ESD3: The third electrostatic discharge protection device

[0034] PAD1: First pad

[0035] PAD2: Second pad

[0036] PAD3: The third pad

[0037] PAD4: The fourth pad

[0038] PAD5: The fifth pad

[0039] PAD6: The sixth pad

[0040] PAD7: seventh pad

[0041] PAD8: The eighth pad

[0042] PAD9: Ninth pad

[0043] PAD10: The tenth pad

[0044] PAD11: 11th pad

[0045] PAD12: 12th pad

[0046] PAD13: The thirteenth pad

[0047] PAD14: pad 14

[0048] BL1: First wire

[0049] BL2: Second wire

[0050] BL3: The third wire

[0051] BL4: The fourth wire

[0052] BL5: Fifth wire

[0053] BL6: Sixth wire

[0054] BL7: Seventh wire

[0055] BL8: Eighth wire

[0056] BL9: The ninth wire

[0057] BL10: Tenth wire

[0058] BL11: Eleventh wire

[0059] BL12: 12th wire

[0060] BL13: Thirteenth wire

[0061] PAD14: 14th wire

[0062] TR1: First trace

[0063] TR2: Second routing

[0064] TR3: The third line

[0065] TR4: The fourth line

[0066] LBL1: First wire inductance

[0067] LBL2: Second wire inductance

[0068] LBL3: Third wire inductance

[0069] LBL4: Fourth wire inductance

[0070] CESD1: First electrostatic discharge protection device capacitor

[0071] CESD2: Second electrostatic discharge protection device capacitor

[0072] SW: Ideal switch

[0073] C1: First (parasitic) capacitance

[0074] C2: Second (parasitic) capacitance

[0075] CPCB1: First circuit board capacitor

[0076] CPCB2: Second circuit board capacitor

[0077] S1: First signal

[0078] S2: Second signal

[0079] S3: The third signal

[0080] S4: The fourth signal

[0081] S5: The fifth signal DETAILED DESCRIPTION

[0082] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as limiting the present invention. The scope of the present invention should be determined by the scope of the claims.

[0083] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present disclosure.

[0084] It is noteworthy that the following disclosed content can provide multiple embodiments or examples for practicing the different features of the present invention. The special component examples and arrangements described below are only used to simply and concisely explain the spirit of the present invention, and are not used to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of reuse is only to provide a simplified and clear description, and is not used to limit the relationship between multiple embodiments and / or configurations discussed below. In addition, the description of a feature described in the following description being connected to, coupled to and / or formed on another feature, etc., can actually include multiple different embodiments, including that these features are in direct contact, or that other additional features are formed between these features, etc., so that these features are not in direct contact.

[0085] Multiplexers (MUX) and demultiplexers (DEMUX) are commonly used components in high-speed signal specifications (such as USB, SATA, PCIe, etc.), which are used to change the transmission / reception path and direction of the connected high-speed data stream. Generally speaking, the related circuits of the multiplexer and demultiplexer include ESD protection circuits, transistors (MOSFET), gate control signals, and metal wires connecting the transistors to the input and output ends of the data stream. The N:M multiplexer and M:N demultiplexer in the present invention are suitable for the transmission of high-speed data streams (such as 1Gbps or higher), where N is greater than M. Generally speaking, if the parasitic capacitance (Parasitics) generated by the ESD protection circuit and the transistor is not absorbed, it will increase the signal loss of the data stream passing through the multiplexer and demultiplexer, and affect the signal integrity of the data stream, thereby reducing the transmission speed of the data stream that can be used by the multiplexer and demultiplexer. In order to reduce the adverse effects of these parasitic capacitances on multiplexers and demultiplexers, a common method is to use the thick metal layer provided by the wafer factory to realize inductance to absorb these parasitic capacitances, thereby reducing the effects of these parasitic capacitances. Another method is to use the complementary metal oxide semiconductor-silicon on insulator (CMOS SOI) process. Although the above two methods can reduce the adverse effects of parasitic capacitances on multiplexers and demultiplexers, they also increase the cost of the product.

[0086] Since a multiplexer and a demultiplexer are composed of at least one switch element, the following description will first be made using a switch element. Figure 1 is a schematic diagram showing a switch chip according to an embodiment. Figure 1 As shown, in one embodiment, the switch chip 100 is a packaged chip with a lead frame, wherein the switch chip 100 includes a die 110, a first lead 120, and a second lead 130. The die 110 includes a first switch element 111, a first electrostatic discharge protection device ESD1, a second electrostatic discharge protection device ESD2, a first pad PAD1, and a second pad PAD2.

[0087] The first switch element 111 is coupled to the first pad PAD1 through the first trace TR1, and is coupled to the second pad PAD2 through the second trace TR2. The first electrostatic discharge protection device ESD1 is electrically coupled to the first pad PAD1, and the second electrostatic discharge protection device ESD2 is electrically coupled to the second pad PAD2. According to one embodiment of the present invention, the first trace TR1 and the second trace TR2 are metal traces in the die 110. According to one embodiment of the present invention, the third trace TR3 and the fourth trace TR4 are metal traces in the die 110. The first electrostatic discharge protection device ESD1 is coupled to the first pad PAD1 through the third trace TR3, and the second electrostatic discharge protection device ESD2 is coupled to the second pad PAD2 through the fourth trace TR4. The first electrostatic discharge protection device ESD1 and the second electrostatic discharge protection device ESD2 are used to protect the first switch element 111 from electrostatic discharge received by the first pad PAD1 and the second pad PAD2.

[0088] The distances between the first ESD protection device ESD1 and the first pad PAD1 and between the second ESD protection device ESD2 and the second pad PAD2 are extremely short, so the effects of the traces TR3 and TR4 between the first ESD protection device ESD1 and the first pad PAD1 and between the second ESD protection device ESD2 and the second pad PAD2 are ignored to simplify the description.

[0089] like Figure 1 As shown, the first pad PAD1 of the chip 110 is electrically coupled to the first pin 120 through the first wire BL1, and the second pad PAD2 of the chip 110 is electrically coupled to the second pin 130 through the second wire BL2, so that the chip 110 can be electrically coupled to other external circuits through the first pin 120 and the second pin 130.

[0090] In order to make the switch chip 100 applicable to a wide bandwidth and achieve the application purposes of low insertion loss, low return loss and high isolation, since the switch chip 100 is a passive component, how to reduce the dielectric loss and conduction loss of the first trace TR1 and the second trace TR2 will become the key to the design.

[0091] In addition, since the accuracy of the etching process during the manufacturing process of the die 110 is difficult to control, the width and length of the first trace TR1 and the second trace TR2 often drift, thereby affecting impedance matching and causing signal loss.

[0092] The present invention proposes a method of using packaging wires (bondwires) to replace the metal traces in the die as the connection between the two ends of the switch element and the input and output ends of the data stream. In one embodiment, the switch element may be a transistor, and the traces on the drain and source of the transistor will be replaced by packaging wires (bondwires). Because the use of wires as inductors can better absorb the parasitic capacitance mentioned above, and the wires have a higher Q value than the metal traces used in the process, the conduction loss of the data stream is reduced, while also maintaining the integrity of the signal under high-speed transmission, thereby achieving a wide-band, low-loss, and low return loss design.

[0093] Since a multiplexer and a demultiplexer are composed of at least one switch element, the present invention will be described below using a switch element. Figure 2 is a schematic diagram showing a switch chip according to an embodiment of the present invention. Figure 2 As shown, in one embodiment, the switch chip 200 is a packaged chip with a lead frame, wherein the switch chip 200 includes a die 210, a first lead 120, and a second lead 130. The die 210 includes a first switch element 211, a first electrostatic discharge protection device ESD1, a second electrostatic discharge protection device ESD2, a first pad PAD1, a second pad PAD2, a third pad PAD3, a fourth pad PAD4, a third wire BL3, and a fourth wire BL4.

[0094] like Figure 2 As shown, the first switch element 211 is electrically coupled between the first pad PAD1 and the second pad PAD2, the first electrostatic discharge protection device ESD1 is electrically coupled to the third pad PAD3, and the second electrostatic discharge protection device ESD2 is electrically coupled to the fourth pad PAD4. In addition, the first pad PAD1 is electrically coupled to the third pad PAD3 through the third wire BL3, and the second pad PAD2 is electrically coupled to the fourth pad PAD4 through the fourth wire BL4.

[0095] According to one embodiment of the present invention, the distance between the first switch element 211 and the first pad PAD1 and the second pad PAD2 is extremely short, so the effect of the wiring therebetween can be ignored. According to one embodiment of the present invention, the distance between the first electrostatic discharge protection device ESD1 and the third pad PAD3 and the distance between the second electrostatic discharge protection device ESD2 and the fourth pad PAD4 is extremely short, so the effect of the wiring therebetween can be ignored. According to many embodiments of the present invention, the first switch element 211 is an N-type transistor or a P-type transistor. According to other embodiments of the present invention, the first switch element 211 can be other electronic components that can be used as switches.

[0096] Will Figure 2 The grain 210 and Figure 1 Compared with the grain 110, Figure 1 The first trace TR1 is replaced by the third wire BL3, Figure 1 According to an embodiment of the present invention, the third wire BL3 and the fourth wire BL4 are metal wires used to connect pads and lead frames in the package, and the first wire BL1 and the second wire BL2 are also metal wires used to connect pads in the die.

[0097] Figure 3 is an equivalent circuit diagram showing a switch chip according to an embodiment of the present invention. Figure 3 As shown, the equivalent circuit 300 is an equivalent circuit of the switch chip 200. The first wire inductance LBL1, the second wire inductance LBL2, the third wire inductance LBL3 and the fourth wire inductance LBL4 are the equivalent inductances of the first wire BL1, the second wire BL2, the third wire BL3 and the fourth wire BL4 respectively, and the first electrostatic discharge protection device capacitor CESD1 and the second electrostatic discharge protection device capacitor CESD2 are the parasitic capacitances generated by the first electrostatic discharge protection device ESD1 and the second electrostatic discharge protection device ESD2 respectively.

[0098] The first switch element 211 is equivalent to an ideal switch SW, a first (parasitic) capacitor C1 and a second (parasitic) capacitor C2. The parasitic capacitance of the external circuit board coupled to the first pin 120 can be equivalent to the first circuit board capacitor CPCB1. The parasitic capacitance of the external circuit board coupled to the second pin 130 can be equivalent to the second circuit board capacitor CPCB2.

[0099] According to one embodiment of the present invention, Figure 3As shown, the switch chip 200 can be equivalent to an LC ladder filter, and the operating bandwidth of the switch chip 200 is expanded by designing an LC ladder filter. In addition, since the inductance value of the wire is related to its length, the inductance value of the wire is easier to accurately control than the width and length of the internal wiring of the grain, which is difficult to control due to the limitations of the etching process. In addition, the wire has the characteristic of low impedance, and using the wire to replace the internal wiring of the grain helps to reduce signal loss. Therefore, using a wire to replace the internal wiring of the grain helps the switch chip 200 to more easily achieve the application goals of wide bandwidth, low insertion loss, low return loss and high isolation.

[0100] Figure 4 FIG. 2 is a schematic diagram showing a 1:2 demultiplexer or a 2:1 multiplexer composed of a plurality of switch elements according to another embodiment of the present invention. Figure 4 As shown, in one embodiment, the switch chip 400 is a packaged chip having a leadframe, wherein the switch chip 400 includes a die 410 , a first pin 420 , a second pin 430 and a third pin 440 .

[0101] The die 410 includes a first switch element 411 , a second switch element 412 , a first electrostatic discharge protection device ESD1 , a second electrostatic discharge protection device ESD2 , a third electrostatic discharge protection device ESD3 , a first pad PAD1 , a second pad PAD2 , a third pad PAD3 , a fourth pad PAD4 , a fifth pad PAD5 and a sixth pad PAD6 .

[0102] The first switch element 411 is electrically coupled between the first pad PAD1 and the second pad PAD2, and the second switch element 412 is electrically coupled between the first pad PAD1 and the third pad PAD3. According to an embodiment of the present invention, the distances between the first switch element 411 and the second switch element 412 and the first pad PAD1, the second pad PAD2 and the third pad PAD3 are extremely short, so the effect of the wiring therebetween can be ignored. The fourth pad PAD4 is electrically coupled to the first pin 420 through the first wire BL1, the fifth pad PAD5 is electrically coupled to the second pin 430 through the second wire BL2, and the sixth pad PAD6 is electrically coupled to the third pin 440 through the third wire BL3.

[0103] The first electrostatic discharge protection device ESD1 is electrically coupled to the fourth pad PAD4, the second electrostatic discharge protection device ESD2 is electrically coupled to the fifth pad PAD5, and the third electrostatic discharge protection device ESD3 is electrically coupled to the sixth pad PAD6. According to one embodiment of the present invention, since the distances between the first electrostatic discharge protection device ESD1 and the fourth pad PAD4, the second electrostatic discharge protection device ESD2 and the fifth pad PAD5, and the third electrostatic discharge protection device ESD3 and the sixth pad PAD6 are extremely short, the effects of the wiring between the first electrostatic discharge protection device ESD1 and the fourth pad PAD4, the second electrostatic discharge protection device ESD2 and the fifth pad PAD5, and the third electrostatic discharge protection device ESD3 and the sixth pad PAD6 are ignored.

[0104] The first pad PAD1 is electrically coupled to the fourth pad PAD4 through the fourth wire BL4 , the second pad PAD2 is electrically coupled to the fifth pad PAD5 through the fifth wire BL5 , and the third pad PAD3 is electrically coupled to the sixth pad PAD6 through the sixth wire BL6 .

[0105] According to one embodiment of the present invention, the first pin 420 receives the first signal S1. According to one embodiment of the present invention, when the first switch element 411 is turned on and the second switch element 412 is not turned on, the switch chip 400 provides the first signal S1 to the second pin 430. According to another embodiment of the present invention, when the first switch element 411 is not turned on and the second switch element 412 is turned on, the switch chip 400 provides the first signal S1 to the third pin 440. At this time, the switch chip 400 is equivalent to a 1:2 demultiplexer (its control terminal is not shown).

[0106] According to another embodiment of the present invention, the second pin 430 receives the second signal S2 and the third pin 440 receives the third signal S3. According to one embodiment of the present invention, when the first switch element 411 is turned on and the second switch element 412 is not turned on, the switch chip 400 provides the second signal S2 to the first pin 420. According to another embodiment of the present invention, when the first switch element 411 is not turned on and the second switch element 412 is turned on, the switch circuit 400 provides the third signal S3 to the first pin 420. At this time, the switch chip 400 is equivalent to a 2:1 multiplexer (the control terminal thereof is not shown).

[0107] In other words, the switch chip 400 can provide the signal received by the first pin 420 to the second pin 430 and / or the third pin 430 according to whether the first switch element 411 and the second switch element 412 are turned on. On the other hand, the switch chip 400 can also selectively provide the signal received by the second pin 430 or the signal received by the third pin 440 to the first pin 420 according to whether the first switch element 411 and the second switch element 412 are turned on. In one embodiment, the switch chip 400 can be used as one of a serializer and a deserializer, which is applied to high-speed transmission signal transmission, such as transmission signals (TX, RX, etc.) in specifications such as USB, SATA, PCIE, etc., but is not limited thereto.

[0108] Figure 4 The switch chip 400 is used to transmit and / or receive a single-ended signal, and two identical switch chips 400 can be used to transmit and / or receive a differential signal. In order to simplify the description, only the transmission and / or reception of a single-ended signal is used as an example for explanation, and is not limited to this in any form.

[0109] Figure 5 FIG. 2 is a schematic diagram showing a 2:3 demultiplexer or a 3:2 multiplexer composed of a plurality of switch elements according to another embodiment of the present invention. Figure 5 As shown, in one embodiment, the switch chip 500 is a packaged chip with a leadframe, wherein the switch chip 500 includes a die 510 , a first pin 520 , a second pin 530 , a third pin 540 , a fourth pin 550 and a fifth pin 560 .

[0110] The chip 510 includes a first switch element 511, a second switch element 512, a third switch element 513, a fourth switch element 514, a fifth switch element 515, a sixth switch element 516, a first pad PAD1, a second pad PAD2, a third pad PAD3, a fourth pad PAD4, a fifth pad PAD5, a sixth pad PAD6, a seventh pad PAD7, an eighth pad PAD8 and a ninth pad PAD9.

[0111] The first switch element 511 is electrically coupled between the first pad PAD1 and the second pad PAD2, the second switch element 512 is electrically coupled between the second pad PAD2 and the third pad PAD3. The third switch element 513 is electrically coupled between the fourth pad PAD4 and the fifth pad PAD5, the fourth switch element 514 is electrically coupled between the fifth pad and the sixth pad PAD6. The fifth switch element 515 is electrically coupled between the seventh pad PAD7 and the eighth pad PAD8, and the sixth switch element 516 is electrically coupled between the eighth pad PAD8 and the ninth pad PAD9.

[0112] According to one embodiment of the present invention, since the distances between the first switch element 511, the second switch element 512 and the third switch element 513 and the pads PAD1, PAD2, PAD3, PAD4, PAD5 are extremely short, and the distances between the fourth switch element 514, the fifth switch element 515 and the sixth switch element 516 and the pads PAD5, PAD6, PAD7, PAD8, PAD9 are extremely short, the effects of the wiring between the switch elements and the pads are ignored.

[0113] like Figure 5 As shown, the die 510 further includes a tenth pad PAD10, an eleventh pad PAD11, a twelfth pad PAD12, a thirteenth pad PAD13, and a fourteenth pad PAD14. The tenth pad PAD10 is electrically coupled to the first pin 520 through the first wire BL1, the eleventh pad PAD11 is electrically coupled to the second pin 530 through the second wire BL2. The twelfth pad PAD12 is electrically coupled to the third pin 540 through the third wire BL3, the thirteenth pad PAD13 is electrically coupled to the fourth pin 550 through the fourth wire BL4, and the fourteenth pad PAD14 is electrically coupled to the fifth pin 560 through the fifth wire BL5.

[0114] like Figure 5 As shown, the die 510 further includes a first electrostatic discharge protection device ESD1, a second electrostatic discharge protection device ESD2, a third electrostatic discharge protection device ESD3, a fourth electrostatic discharge protection device ESD4, and a fifth electrostatic discharge protection device ESD5. The first electrostatic discharge protection device ESD1 is electrically coupled to the tenth pad PAD10, the second electrostatic discharge protection device ESD2 is electrically coupled to the eleventh pad PAD11, the third electrostatic discharge protection device ESD3 is electrically coupled to the twelfth pad PAD12, the fourth electrostatic discharge protection device ESD4 is electrically coupled to the thirteenth pad PAD13, and the fifth electrostatic discharge protection device ESD5 is electrically coupled to the fourteenth pad PAD14.

[0115] According to one embodiment of the present invention, since the distances between the first electrostatic discharge protection device ESD1, the second electrostatic discharge protection device ESD2, the third electrostatic discharge protection device ESD3, the fourth electrostatic discharge protection device ESD4 and the fifth electrostatic discharge protection device ESD5 to the tenth pad PAD10, the eleventh pad PAD11, the twelfth pad PAD12, the thirteenth pad PAD13 and the fourteenth pad PAD14 are extremely short, the effects of the wiring between each electrostatic discharge protection device and the pads are ignored here.

[0116] like Figure 5As shown, the first pad PAD1 is electrically coupled to the tenth pad PAD10 through the sixth wire BL6. The second pad PAD2 is electrically coupled to the twelfth pad PAD12 through the seventh wire BL7. The third pad PAD3 is electrically coupled to the eleventh pad PAD11 through the eighth wire BL8. The fourth pad PAD4 is electrically coupled to the tenth pad PAD10 through the ninth wire BL9. The fifth pad PAD5 is electrically coupled to the thirteenth pad PAD13 through the tenth wire BL10. The sixth pad PAD6 is electrically coupled to the eleventh pad PAD11 through the eleventh wire BL11.

[0117] The seventh pad PAD7 is electrically coupled to the tenth pad PAD10 through the twelfth wire BL12. The eighth pad PAD8 is electrically coupled to the fourteenth pad PAD14 through the thirteenth wire BL13. The ninth pad PAD9 is electrically coupled to the eleventh pad PAD11 through the fourteenth wire BL14.

[0118] According to an embodiment of the present invention, when the first pin 520 receives the first signal S1 and the second pin 530 receives the second signal S2, the switch chip 500 provides the first signal S1 and / or the second signal S2 to any one of the third pin 540, the fourth pin 550 and the fifth pin 560 respectively according to whether the first switch element 511, the second switch element 512, the third switch element 513, the fourth switch element 514, the fifth switch element 515 and the sixth switch element 516 are turned on. At this time, the switch chip 500 is equivalent to a 2:3 demultiplexer (its control terminal is not shown).

[0119] According to another embodiment of the present invention, when the third pin 540 receives the third signal S3, the fourth pin 550 receives the fourth signal S4, and the fifth pin 560 receives the fifth signal S5, the switch chip 500 selects to provide at least one of the third signal S3, the fourth signal S4, and the fifth signal S5 to the first pin 520 and / or the second pin 530 according to whether the first switch element 511, the second switch element 512, the third switch element 513, the fourth switch element 514, the fifth switch element 515, and the sixth switch element 516 are turned on. At this time, the switch chip 500 is equivalent to a 3:2 multiplexer (the control end thereof is not shown).

[0120] In one embodiment, the switch chip 500 can be used as a serializer or a deserializer, and is applied in high-speed signal transmission, such as USB, SATA, PCIE and other specifications, but is not limited thereto.

[0121] According to other embodiments of the present invention, two identical switch chips 500 may be used to transmit and / or receive differential signals. To simplify the description, only the transmission and / or reception of single-ended signals is used as an example for explanation, and is not limited thereto in any form.

[0122] As mentioned above, only the parts related to the present invention are shown in the switch chips 100 , 200 , 400 , and 500 , and other irrelevant circuits are not shown.

[0123] The present invention proposes a switch chip (multiplexer / demultiplexer) and uses packaged wires (bondwires) to replace metal traces in the crystal grain, so that the inductance value between each component in the crystal grain can be more accurately controlled, and the design flexibility is increased. In addition, since the impedance value of the wire is small, the conduction loss is reduced, and the wire does not have the dielectric loss of the metal traces in the crystal grain. In addition, the use of wires to couple different components in the crystal grain helps to expand the operating bandwidth of the switch chip, so that the switch chip can achieve the purpose of wide operating bandwidth, low insertion loss, low return loss and high isolation.

[0124] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that those skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Those skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present disclosure. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment.

Claims

1. A switch chip, comprising: A first switch element is directly coupled between the first pad and the second pad; A first electrostatic discharge protection device electrically coupled to a third pad, wherein the third pad is electrically coupled to the first pad via a first conductive wire; as well as The second electrostatic discharge protection device is electrically coupled to the fourth pad, wherein the fourth pad is electrically coupled to the second pad through a second conductive wire. 2 . The switch chip as claimed in claim 1 , wherein the first switch element, the first electrostatic discharge protection device, the second electrostatic discharge protection device, the first pad, the second pad, the third pad and the fourth pad are located in a die.

3. The switch chip according to claim 2, further comprising: The first pin is electrically coupled to the third pad via a third wire; as well as The second pin is electrically coupled to the fourth pad through a fourth wire. 4 . The switch chip as claimed in claim 3 , wherein the die, the first pin and the second pin are located in a package.

5. A switch chip, comprising: A first switch element, electrically coupled between the first pad and the second pad; A second switch element, electrically coupled between the first pad and the third pad; A first electrostatic discharge protection device electrically coupled to a fourth pad, wherein the fourth pad is electrically coupled to the first pad via a first conductive wire; A second electrostatic discharge protection device electrically coupled to a fifth pad, wherein the fifth pad is electrically coupled to the second pad via a second conductive wire; as well as The third electrostatic discharge protection device is electrically coupled to the sixth pad, wherein the sixth pad is electrically coupled to the third pad through a third wire. 6 . The switch chip as claimed in claim 5 , wherein the first switch element, the second switch element, the first electrostatic discharge protection device, the second electrostatic discharge protection device and the third electrostatic discharge protection device are located in a die.

7. The switch chip according to claim 6, further comprising: The first pin is electrically coupled to the fourth pad via a fourth wire; The second pin is electrically coupled to the fifth pad via a fifth wire; as well as The third pin is electrically coupled to the sixth pad through a sixth wire. 8 . The switch chip as claimed in claim 7 , wherein the die, the first pin, the second pin and the third pin are located in a package.

9. The switch chip as claimed in claim 7, wherein the first pin receives a first signal, wherein when the first switch element is conductive and the second switch element is non-conductive, the first signal is provided to the second pin, wherein when the first switch element is non-conductive and the second switch element is conductive, the first signal is provided to the third pin.

10. The switch chip as claimed in claim 7, wherein the second pin receives a first signal, and the third pin receives a second signal, wherein when the first switch element is conductive and the second switch element is non-conductive, the first signal is provided to the first pin, and when the first switch element is non-conductive and the second switch element is conductive, the second signal is provided to the first pin. 11 . The switch chip as claimed in claim 5 , wherein the switch chip is one of a serializer, a deserializer, an N:M multiplexer, and an M:N demultiplexer, wherein N is greater than M.

12. A switch chip, comprising: A first switch element, electrically coupled between the first pad and the second pad; A second switch element, electrically coupled between the second pad and the third pad; A third switch element, electrically coupled between the fourth pad and the fifth pad; a fourth switch element, electrically coupled between the fifth pad and the sixth pad; a fifth switch element, electrically coupled between the seventh pad and the eighth pad; a sixth switch element, electrically coupled between the eighth pad and the ninth pad; a first electrostatic discharge protection device electrically coupled to a tenth pad, wherein the tenth pad is electrically coupled to the first pad via a first wire, electrically coupled to the fourth pad via a second wire, and electrically coupled to the seventh pad via a third wire; a second electrostatic discharge protection device electrically coupled to a tenth pad, wherein the tenth pad is electrically coupled to the third pad via a fourth wire, electrically coupled to the sixth pad via a fifth wire, and electrically coupled to the ninth pad via a sixth wire; A third electrostatic discharge protection device electrically coupled to a twelfth pad, wherein the twelfth pad is electrically coupled to the second pad via a seventh wire; a fourth electrostatic discharge protection device electrically coupled to the thirteenth pad, wherein the thirteenth pad is electrically coupled to the fifth pad through an eighth wire; as well as The fifth electrostatic discharge protection device is electrically coupled to the fourteenth pad, wherein the fourteenth pad is electrically coupled to the eighth pad through a ninth wire. 13 . The switch chip as claimed in claim 12 , wherein the first to sixth switch elements and the first to fifth electrostatic discharge protection devices are located in a die.

14. The switch chip according to claim 13, further comprising: A first pin electrically coupled to the tenth pad via a tenth wire; The second pin is electrically coupled to the tenth pad through a tenth wire; The third pin is electrically coupled to the twelfth pad through a twelfth wire; The fourth pin is electrically coupled to the thirteenth pad through a thirteenth wire; as well as The fifth pin is electrically coupled to the fourteenth pad through a fourteenth wire. 15 . The switch chip as claimed in claim 14 , wherein the die, the first pin, the second pin, the third pin, the fourth pin and the fifth pin are located in a package.

16. The switch chip as claimed in claim 14, wherein the first pin receives a first signal and the second pin receives a second signal, wherein the switch chip provides the first signal and / or the second signal to one of the third pin, the fourth pin and the fifth pin respectively according to whether the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element and the sixth switch element are turned on.

17. The switch chip as described in claim 14, wherein the third pin receives a third signal, the fourth pin receives a fourth signal, and the fifth pin receives a fifth signal, wherein the switch chip selects to provide at least one of the third signal, the fourth signal and the fifth signal to the first pin and / or the second pin according to whether the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element and the sixth switch element are turned on. 18 . The switch chip as claimed in claim 12 , wherein the switch chip is one of an N:M multiplexer and an M:N demultiplexer, wherein N is greater than M.

19. A switch chip, comprising: A first pin electrically coupled to a first pad via a first wire; A second pin electrically coupled to a second pad via a second wire; as well as The die includes a first switch element, wherein one end of the first switch element is directly coupled to the first pad through a third wire, and the other end of the first switch element is directly coupled to the second pad through a fourth wire. 20 . The switch chip as claimed in claim 19 , wherein the first pad, the second pad, the third conductive line, and the fourth conductive line are all located in the die.

21. The switch chip as claimed in claim 19, wherein the die further comprises: A first electrostatic discharge protection device electrically coupled to the first pad; as well as The second electrostatic discharge protection device is electrically coupled to the second pad.

22. A switch chip, comprising: A first pin electrically coupled to a first pad via a first wire; A second pin electrically coupled to a second pad via a second wire; A third pin is electrically coupled to a third pad via a third wire; as well as Dies, including: A first switch element, wherein one end of the first switch element is electrically coupled to the second pad through a fourth wire; as well as a second switch element, wherein one end of the second switch element is electrically coupled to the third pad via a fifth wire, and the other end of the first switch element and the other end of the second switch element are electrically coupled to the first pad via a sixth wire, The first wire, the second wire, the third wire, the fourth wire, the fifth wire and the sixth wire are all metal wires used to connect pads and lead frames in a package. 23 . The switch chip as claimed in claim 22 , wherein the first pad, the second pad, the third pad, the fourth wire, the fifth wire, and the sixth wire are all located in the die.

24. The switch chip as claimed in claim 22, wherein the die further comprises: A first electrostatic discharge protection device electrically coupled to the first pad; A second electrostatic discharge protection device electrically coupled to the second pad; as well as The third electrostatic discharge protection device is electrically coupled to the third pad. 25 . The switch chip as claimed in claim 22 , wherein the switch chip is any one of a serializer, a deserializer, an N:M multiplexer, and an M:N demultiplexer, wherein N is greater than M.

26. The switch chip as described in claim 22, wherein the first pin receives a first signal, wherein when the first switch element is conductive and the second switch element is non-conductive, the first signal is provided to the second pin, wherein when the first switch element is non-conductive and the second switch element is conductive, the first signal is provided to the third pin.

27. The switch chip as described in claim 22, wherein the second pin receives a first signal, and the third pin receives a second signal, wherein when the first switch element is conductive and the second switch element is non-conductive, the first signal is provided to the first pin, and when the first switch element is non-conductive and the second switch element is conductive, the second signal is provided to the first pin.

28. A switch chip, comprising: A first pin electrically coupled to a first pad via a first wire; A second pin electrically coupled to a second pad via a second wire; A third pin is electrically coupled to a third pad via a third wire; A fourth pin, electrically coupled to a fourth pad via a fourth wire; A fifth pin, electrically coupled to a fifth pad via a fifth wire; as well as Dies, including: A first switch element, wherein one end of the first switch element is electrically coupled to the first pad through a sixth wire; A second switch element, wherein one end of the second switch element is electrically coupled to the second pad via a seventh wire, and the other end of the first switch element and the other end of the second switch element are electrically coupled to the third pad via an eighth wire; A third switch element, wherein one end of the third switch element is electrically coupled to the first pad through a ninth wire; A fourth switch element, wherein one end of the fourth switch element is electrically coupled to the second pad via a tenth wire, and the other end of the third switch element and the other end of the fourth switch element are both electrically coupled to the fourth pad via a tenth wire; a fifth switch element, wherein one end of the fifth switch element is electrically coupled to the first pad through a twelfth wire; and A sixth switch element, wherein one end of the sixth switch element is electrically coupled to the second pad via a thirteenth wire, and the other end of the fifth switch element and the other end of the sixth switch element are electrically coupled to the fifth pad via a fourteenth wire. 29 . The switch chip as claimed in claim 28 , wherein the first pad, the second pad, the third pad, the fourth pad, and the fifth pad are all located in the die.

30. The switch chip as claimed in claim 28, wherein the die further comprises: A first electrostatic discharge protection device electrically coupled to the first pad; A second electrostatic discharge protection device electrically coupled to the second pad; A third electrostatic discharge protection device electrically coupled to the third pad; a fourth electrostatic discharge protection device electrically coupled to the fourth pad; as well as The fifth electrostatic discharge protection device is electrically coupled to the fifth pad.

31. The switch chip as claimed in claim 28, wherein the switch chip is one of an N:M multiplexer and an M:N demultiplexer, wherein N is greater than M.

32. The switch chip as described in claim 28, wherein the first pin receives a first signal and the second pin receives a second signal, wherein the switch chip provides the first signal and / or the second signal to one of the third pin, the fourth pin and the fifth pin respectively according to whether the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element and the sixth switch element are turned on.

33. The switch chip as described in claim 28, wherein the third pin receives a third signal, the fourth pin receives a fourth signal, and the fifth pin receives a fifth signal, wherein the switch chip selects to provide at least one of the third signal, the fourth signal and the fifth signal to the first pin and / or the second pin according to whether the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element and the sixth switch element are turned on.

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