Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

This invention provides a semiconductor device and a method for manufacturing a semiconductor device, reducing manufacturing costs while improving performance. The semiconductor device (10) has an insulating circuit board (22) having: a heat sink (25) having a front side; a resin substrate (23) having a front side and a back side fixed to the front side, and containing resin; and circuit patterns (24a, 24b) having a front side and a back side fixed to the front side. The semiconductor device (10) has at least one of a first semiconductor chip (21a), a second semiconductor chip (21b), and an external connection terminal (41a) bonded to the front side, and at least one pair of opposing sides of the circuit pattern (24b) are each supported by the resin substrate (23). In such a semiconductor device (10), when the external connection terminal (41a) is bonded to the circuit pattern (24b) by ultrasonic bonding, the circuit pattern (24b) will not peel off from the resin substrate (23) because it is supported by the resin substrate (23).

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] A semiconductor device includes a semiconductor chip and a control IC (Integrated Circuit). The semiconductor chip uses switching elements of a power device. Examples of switching elements include IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors). The control IC drives and controls the semiconductor chip. Such a semiconductor device includes a substrate on which the semiconductor chip is disposed, a housing containing the substrate, and an encapsulating resin encapsulating the interior of the housing. Wiring components and control terminals are embedded in the housing. The wiring components are electrically connected to the main electrodes of the semiconductor chip via bonding wires. Furthermore, the control terminals are also electrically connected to the control IC via bonding wires.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-146704 Summary of the Invention

[0006] Technical issues

[0007] However, to manufacture the aforementioned semiconductor device, the following steps are performed. First, a forming step is performed to integrally form the wiring components and control terminals with the housing. Next, a bonding step is performed to attach the substrate to the housing. Then, a bonding step is performed, in which the circuit pattern on which the semiconductor chip is disposed and the wiring components integrally formed with the housing are electrically connected via bonding wires. Thus, manufacturing a semiconductor device requires a large number of steps and components, thereby increasing manufacturing costs. In particular, the bonding step is time-consuming for the following reasons: As the power capacity of the semiconductor device increases, the current also increases. Therefore, the number of bonding wires must also increase. Consequently, the bonding step will take more time than before.

[0008] The present invention has been made in view of this, and its object is to provide a semiconductor device and a method of manufacturing a semiconductor device that reduce manufacturing costs and improves characteristics.

[0009] Technical solution

[0010] According to one aspect of the present invention, a semiconductor device is provided, comprising: an insulating circuit substrate having a heat sink, a resin substrate, and a circuit pattern, the heat sink having a first front side, the resin substrate having a second front side and a second back side fixed to the first front side and the resin substrate containing resin, the circuit pattern having a third front side and a third back side fixed to the second front side; and at least one of a semiconductor chip and a wiring component bonded to the third front side, wherein at least a pair of opposite sides of the circuit pattern are each supported by the resin substrate.

[0011] Furthermore, according to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: a preparation step of preparing a heat sink, a circuit pattern, and wiring components; a prepreg substrate forming step of forming a prepreg substrate, the prepreg substrate containing a thermosetting resin in a semi-cured state; a resin substrate manufacturing step of disposing the prepreg substrate on a first front side of the heat sink, disposing the circuit pattern on a second front side of the prepreg substrate, pressing the circuit pattern toward the first front side and heating the prepreg substrate to cure the prepreg substrate, thereby manufacturing a resin substrate, the resin substrate having the circuit pattern fixedly attached to it in such a way that it supports at least a pair of opposite sides of the circuit pattern; and a bonding step of bonding the wiring components to a third front side of the circuit pattern.

[0012] Technical effect

[0013] Based on the publicly available technology, it is possible to reduce manufacturing costs and improve performance. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating the appearance of the semiconductor device according to the embodiment.

[0015] Figure 2 This is a side cross-sectional view of the semiconductor device according to the embodiment.

[0016] Figure 3 This is a top cross-sectional view of the semiconductor device according to the implementation method.

[0017] Figure 4 This is a flowchart (one) illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0018] Figure 5 This is a flowchart (part two) illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0019] Figure 6 This is a diagram illustrating the bonding process of external connection terminals included in a method for manufacturing a semiconductor device according to an embodiment.

[0020] Figure 7This is a diagram illustrating the bonding process of a semiconductor chip and electronic components, and the bonding process based on bonding wires, in a method for manufacturing a semiconductor device according to an embodiment.

[0021] Figure 8 This is a diagram illustrating the packaging process included in a method for manufacturing a semiconductor device according to an embodiment.

[0022] Figure 9 This is one of the diagrams illustrating the bonding circuit pattern of a prepreg substrate in a semi-cured state according to an embodiment.

[0023] Figure 10 This is a diagram (part two) illustrating the circuit pattern of bonding a semi-cured substrate to a semi-cured substrate in the semi-cured state according to an embodiment.

[0024] Figure 11 This is a diagram (Part 3) illustrating the circuit pattern of bonding a semi-cured substrate to a semi-cured state in an embodiment.

[0025] Figure 12 This is Figure 4 illustrating the circuit pattern of the bonding circuit to the semi-cured substrate in the semi-cured state according to the embodiment.

[0026] Figure 13 This is Figure 5 illustrating the circuit pattern of bonding a semi-cured substrate to a semi-cured state in an embodiment.

[0027] Figure 14 This is one of the diagrams showing an additional insulating circuit board of a semiconductor device according to an embodiment.

[0028] Figure 15 This is a diagram (second one) showing another insulating circuit board of a semiconductor device according to an embodiment.

[0029] Symbol Explanation

[0030] 10 Semiconductor device, 21a First semiconductor chip, 21b Second semiconductor chip, 22 Insulating circuit board, 22a Component area, 23 Resin substrate, 23a Constraint protrusion, 23b Bonding constraint protrusion, 24, 24a, 24b, 24c, 24d Circuit pattern, 25 Heat sink, 26 Bonding wire, 30, 31, 32, 33 Control terminal, 30a Control area, 34 Control wiring section, 40, 41a, 41b, 41c, 41d External connection terminal, 41a1 Junction, 41a2 Connection, 41a3 Terminal section, 50 Electronic component, 60 Packaging component, 80 Molding mold, 81 Upper mold, 82 Lower mold, 83 Flow path, 84 Cavity, 241 Burr, 242 Collapsed edge Detailed Implementation

[0031] The embodiments will now be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "top surface" are used interchangeably. Figure 2 In the semiconductor device 10, the surface facing upwards is indicated. Similarly, "upper" is used in... Figure 2 In semiconductor device 10, the upper side is indicated. "Back side" and "lower surface" are... Figure 2 In the semiconductor device 10, the downward-facing surface is indicated. Similarly, "down" is used in... Figure 2 The direction shown in the semiconductor device 10 is the lower side. The same directionality may be shown in other figures as needed. The terms "front," "upper surface," "upper," "back side," "lower surface," "lower," and "side" are merely convenient expressions for determining relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily indicate the plumb direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity.

[0032] use Figures 1-3 A semiconductor device for describing an implementation method. Figure 1 This is a diagram illustrating the appearance of the semiconductor device according to the embodiment. It should be noted that... Figure 1 (A) is the semiconductor device 10 (from Figure 1 (B) Side view viewed from the top or bottom. Figure 1 (B) is a top view of semiconductor device 10. Figure 2 This is a side cross-sectional view of the semiconductor device according to the embodiment. Furthermore, Figure 3 This is a top cross-sectional view of the semiconductor device according to the embodiment. It should be noted that... Figure 2 yes Figure 3 A cross-sectional view at the point marked by the single-dotted line XX. Figure 3 yes Figure 2 A cross-sectional view at the point indicated by the dashed line XX. Furthermore, Figure 3 Corresponding to Figure 1 (B) Top view.

[0033] First, such as Figure 1 As shown, the entire semiconductor device 10 is encapsulated by a packaging member 60 and has a three-dimensional shape. It should be noted that the packaging member 60 of the semiconductor device 10 can be three-dimensional and has curvature at its corners. Furthermore, a plurality of control terminals 30 and a plurality of external connection terminals 40 extend from both sides of the long side of the packaging member 60. It should be noted that in this embodiment, control terminals 30 and external connection terminals 40 are described as such without specifically distinguishing between them.

[0034] Such a semiconductor device 10 Figure 2 and Figure 3The components shown are packaged by a packaging member 60. That is, the semiconductor device 10 includes: six sets of first semiconductor chips 21a and second semiconductor chips 21b, an insulating circuit board 22, control terminals 30 (including control terminals 31-33), external connection terminals 40 (including external connection terminals 41a-41d), and electronic components 50. Furthermore, in the semiconductor device 10, the control terminals 30, electronic components 50, first semiconductor chips 21a, second semiconductor chips 21b, and external connection terminals 40 are suitably electrically connected by bonding wires 26. It should be noted that in... Figure 3 The bonding wires connecting to the electronic component 50 are omitted from the illustration. Furthermore, such components of the semiconductor device 10 are packaged by the packaging member 60. It should be noted that the bonding wires 26 are made of metals with excellent conductivity, such as aluminum or copper, or alloys containing at least one of these metals. In addition, the diameter of the bonding wires 26 is preferably 100 μm or more and 1 mm or less.

[0035] The first semiconductor chip 21a includes switching elements such as IGBTs and power MOSFETs. When the first semiconductor chip 21a is an IGBT, it has a collector as the main electrode on the back side and a gate electrode and an emitter electrode as the main electrode on the front side. When the first semiconductor chip 21a is a power MOSFET, it has a drain electrode as the main electrode on the back side and a gate electrode and a source electrode as the main electrode on the front side. The back side of the first semiconductor chip 21a is bonded to the circuit patterns 24a, 24b, 24c, and 24d on the insulating circuit board 22 by solder (not shown). The second semiconductor chip 21b includes, for example, SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes, and FWDs (Free Wheeling Diodes). This second semiconductor chip 21b has an output electrode (cathode) as the main electrode on the back side and an input electrode (anode) as the main electrode on the front side. The back side of the aforementioned second semiconductor chip 21b is bonded to circuit patterns 24a, 24b, 24c, and 24d by solder (illustration omitted). It should be noted that an RC (Reverse-Conducting) IGBT, which combines the functions of an IGBT and a FWD, can also be used instead of the first semiconductor chip 21a and the second semiconductor chip 21b. Furthermore, in Figure 3 The diagram only shows the case where six groups of the first semiconductor chip 21a and the second semiconductor chip 21b are provided. It is not limited to six groups; the number of groups can be set to correspond to the specifications of the semiconductor device 10, etc.

[0036] The insulating circuit board 22 includes a resin substrate 23, circuit patterns 24a, 24b, 24c, 24d, and a heat sink 25. The resin substrate 23 contains any one of epoxy resin, polyimide, or polytetrafluoroethylene. Furthermore, in addition to these resins, the resin substrate 23 may also contain inorganic fillers. It should be noted that the thickness of the resin substrate 23 is preferably 0.09 mm or more and 0.15 mm or less.

[0037] Circuit patterns 24a, 24b, 24c, and 24d are formed on the front side of the resin substrate 23. At least one pair of opposite sides of circuit patterns 24a, 24b, 24c, and 24d are each supported by the resin substrate 23. Details of the formation of circuit patterns 24a, 24b, 24c, and 24d on the front side of the resin substrate 23 will be described later. Such circuit patterns 24a, 24b, 24c, and 24d are made of a metal with excellent conductivity. Such a metal is, for example, copper or a copper alloy. It should be noted that... Figure 2 and Figure 3 The shapes of the circuit patterns 24a, 24b, 24c, and 24d are examples. The circuit patterns 24a, 24b, 24c, and 24d are generated by etching a conductive plate or foil formed on the front side of the resin substrate 23. Alternatively, the circuit patterns 24a, 24b, 24c, and 24d are formed by attaching a conductive plate to the front side of the resin substrate 23. It should be noted that the thickness of the circuit patterns 24a, 24b, 24c, and 24d is preferably 0.10 mm or more and 1.00 mm or less, more preferably 0.20 mm or more and 0.50 mm or less. Furthermore, as... Figure 2 and Figure 3 As shown, circuit patterns 24a, 24b, 24c, and 24d are formed on the component area 22a of the main surface of the insulating circuit board 22. The circuit patterns 24a, 24b, 24c, and 24d are respectively bonded to the first semiconductor chip 21a and the second semiconductor chip 21b via solder (not shown). It should be noted that the shape, arrangement, and number of circuit patterns 24a, 24b, 24c, and 24d, and the arrangement of the first semiconductor chip 21a and the second semiconductor chip 21b, are examples and are not limited to specific cases. Figure 2 and Figure 3 The appropriate settings are made according to the design and specifications. It should be noted that, depending on the circumstances, circuit patterns 24a, 24b, 24c, and 24d may sometimes be described as circuit pattern 24.

[0038] A heat sink 25 is formed on the back side of the resin substrate 23. This heat sink 25 is made of a metal with excellent thermal conductivity. Such metals include, for example, aluminum, iron, silver, copper, or alloys containing at least one of these metals. Furthermore, to improve corrosion resistance, materials such as nickel can be formed on the surface of the heat sink 25 through a plating process, for example. Other materials besides nickel include nickel-phosphorus alloys and nickel-boron alloys. Furthermore, a cooler (not shown) can be mounted on the back side of the heat sink 25 via solder or silver solder. This further improves the heat dissipation of the semiconductor device 10. In this case, the cooler is made of a metal with excellent thermal conductivity. Such metals include, for example, aluminum, iron, silver, copper, or alloys containing at least one of these metals. Furthermore, as a cooler, heat sinks or heat sinks composed of multiple heat sinks, as well as cooling devices utilizing water cooling, can be used. In addition, the heat sink 25 can be integrated with such a cooler. In this case, the heat sink 25 is also made of a metal with excellent thermal conductivity as described above. Furthermore, for the cooler, the same method described above can be used to form a material on the surface of the cooler to improve corrosion resistance. It should be noted that the thickness of the heat dissipation plate 25 is preferably 0.1 mm or more and 2.0 mm or less.

[0039] One end of one of the multiple external connection terminals 40, which serve as wiring components, is disposed on the insulating circuit board 22. Figure 3 On the right side, the other end is from the semiconductor device 10 Figure 3The right-side side extends outward. External connection terminals 41b, 41a, 41c, and 41d of the plurality of external connection terminals 40 are respectively bonded to circuit patterns 24a, 24b, 24c, and 24d on the insulating circuit board 22. Furthermore, external connection terminal 41a includes a joining portion 41a1, a connecting portion 41a2, and a terminal portion 41a3. The joining portion 41a1 is parallel to the front surface of the insulating circuit board 22 and is bonded to the circuit pattern 24b. The connecting portion 41a2 is inclined and integrally connects the joining portion 41a1 and the terminal portion 41a3. The inclination of the terminal portion 41a3 and the connecting portion 41a2 is correspondingly separated from the front surface of the insulating circuit board 22, and extends outward from the insulating circuit board 22 parallel to the front surface. It should be noted that, although not shown in the figure, external connection terminals 41b, 41c, and 41d also form the same structure as external connection terminal 41a. It should be noted that the wiring components are not limited to external connection terminals 40. The wiring component electrically connects the components within the semiconductor device 10. For example, the wiring component connects the first semiconductor chip 21a and the second semiconductor chip 21b to circuit patterns 24a, 24b, 24c, and 24d. Furthermore, the wiring component connects the circuit patterns 24a, 24b, 24c, and 24d to each other. Additionally, the wiring component electrically connects the circuit patterns 24a, 24b, 24c, and 24d to external connection terminals 40. Such a wiring component is a lead frame, bonding tape, or bonding wire.

[0040] Multiple control terminals 30 (including control terminals 31, 32, and 33) are disposed in the control area 30a of the package member 60. The control area 30a is an area adjacent to another side of the insulating circuit board 22, which is opposite to a side of the insulating circuit board 22 to which multiple external connection terminals 40 are joined. The control area 30a is located higher than the front surface of the insulating circuit board 22. The control terminals 30 are located from the semiconductor device 10... Figure 3 The left-side side extends outward. Multiple control terminals 30 also include control wiring portions 34. Control wiring portions 34 are disposed in control area 30a. Furthermore, electronic components 50 are mounted on the control wiring portions 34 via solder (not shown). The control wiring portions 34 are located at the same height as the portion of the control terminals 30 extending outward from the side. The control wiring portions 34 are located at a position higher than the positions where the external connection terminals 40 engage with circuit patterns 24a, 24b, 24c, and 24d. Furthermore, the control terminals 30 are at the same height as the terminal portions 41a3 of the external connection terminals 41a, 41b, 41c, and 41d (the terminal portions of the external connection terminals 41b, 41c, and 41d are not shown).

[0041] The multiple external connection terminals 40 and control terminals 30 (including control terminals 31, 32, and 33) are made of a metal with excellent conductivity. Such a metal is, for example, copper or a copper alloy. Furthermore, the surfaces of the multiple external connection terminals 40 and control terminals 30 (including control terminals 31, 32, and 33) can be covered with a metal such as nickel or a nickel alloy.

[0042] Electronic components 50 are bonded to control wiring section 34 via solder (not shown). A required number of electronic components 50 are provided to enable the semiconductor device 10 to perform the desired functions. Furthermore, to achieve such functions, control ICs, thermistors, capacitors, resistors, etc., are suitably used as electronic components 50. A package member 60 encapsulates the components described above. Such a package member 60 contains thermosetting resins such as epoxy resin, phenolic resin, and maleimide resin, and fillers contained in the thermosetting resin. As an example of the package member 60, epoxy resin containing fillers is used. Inorganic fillers are used. Examples of inorganic fillers include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0043] Next, use Figures 4-8 This describes a method for manufacturing such a semiconductor device 10. Figure 4 and Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 6 This is a diagram illustrating the bonding process of external connection terminals included in a method for manufacturing a semiconductor device according to an embodiment. Figure 7 This diagram illustrates the bonding process of a semiconductor chip and electronic components, and the bonding process based on bonding wires, in a method for manufacturing a semiconductor device according to an embodiment. Furthermore, Figure 8 This is a diagram illustrating the packaging process included in a method for manufacturing a semiconductor device according to an embodiment. It should be noted that... Figures 6-8 Is with Figure 3 The cross-sectional view corresponding to the position of the single-dot dashed line XX in the diagram.

[0044] First, the raw materials for the resin substrate, a metal pattern, a heat sink 25, a first semiconductor chip 21a, a second semiconductor chip 21b, a lead frame (not shown), electronic components 50, and other constituent components of the semiconductor device 10 are prepared. The lead frame is formed by connecting multiple control terminals 30 and multiple external connection terminals 40 via tie bars. It should be noted that the metal pattern corresponds to the circuit pattern 24. The metal pattern is formed by cutting from a metal plate. Alternatively, as described later, the metal pattern is formed by etching a metal plate disposed on a prepreg substrate. Alternatively, the metal pattern is formed by punching from a metal plate. The metal pattern formed by punching from a metal plate produces burrs and collapsed edges. It should be noted that at least one of the burrs and collapsed edges can be removed as needed through post-processing of the metal pattern. Next, the prepreg substrate in a prepreg state is formed using the raw materials for the resin substrate (step S2). Here, the details of step S2 (steps S2a to S2d) are further explained.

[0045] First, a liquid resin (stage A) is prepared as a thermosetting resin, and an inorganic filler mixed with the liquid resin is prepared (step S2a). Resins used here include phenolic resin, epoxy resin, and melamine resin. Furthermore, silica filler is used as a release agent in the inorganic filler. As an inorganic filler, there is no need to combine it with halogen-based, antimony-based, or metal hydroxide-based flame retardants; high flame retardancy can be maintained by using silica filler. Next, at least 90% of the inorganic filler is mixed into the liquid resin. The liquid resin mixed with the inorganic filler is heated to generate a semi-cured raw material (stage B) (step S2b). It should be noted that the heating time at this stage is appropriately set according to the production cycle time and depends on the type of catalyst in the resin. For example, the heating temperature is 100°C or higher and 200°C or lower. Next, the semi-cured raw material is pulverized (step S2c). Next, the powdered semi-cured material is filled into a predetermined mold, pressed, and then the mold is separated. Thus, a semi-cured, flat, semi-cured substrate is formed (step S2d). Through the above process, the formation of the semi-cured substrate is completed. It should be noted that steps S1 and S2 only need to be completed before step S3 below; the order of steps S1 and S2 can be reversed or performed simultaneously.

[0046] Next, the prepreg substrate thus formed is placed on the heat sink 25 (step S3). The top view dimensions of the prepreg substrate are approximately the same as those of the heat sink 25. Next, the metal pattern is laminated to the prepreg substrate by stamping, and then the metal pattern is pressed towards the heat sink 25 using a predetermined press. As a result, the lower part of the metal pattern is embedded in the prepreg substrate. Thus, the metal pattern is bonded to the prepreg substrate (step S4). It should be noted that the embedding depth of the metal pattern in the prepreg substrate can be different according to the pressure applied at this time. Next, the prepreg substrate with the metal pattern bonded thereto and the heat sink 25 are heated together. As a result, the prepreg substrate with the embedded metal pattern is cured, thereby producing a resin substrate 23 with the circuit pattern 24 fixedly attached (step S5). Thus, an insulating circuit board 22 having the heat sink 25, the resin substrate 23, and the circuit pattern 24 is obtained. It should be noted that the heating temperature at this time is 120°C or higher and 180°C or lower. Alternatively, post-curing can be performed in a process following step S5 to fully cure the semi-cured substrate.

[0047] Next, the control terminal 30 included in the lead frame (in Figure 6 The control wiring portion 34 (showing control terminals 31, 32, 33) is located in the control area 30a. Simultaneously, the joint portion 41a1 (the joint portions of external connection terminals 41b, 41c, 41d are not shown) of the external connection terminals 41a (and similarly for external connection terminals 41b, 41c, 41d) included in the lead frame is located in the circuit pattern 24b of the insulating circuit board 22 (and similarly for circuit patterns 24a, 24c, 24d). It should be noted that at this time, a predetermined fixture (not shown) is used to maintain the control terminals 30 and the control wiring portion 34 in the control area 30a at a position higher than the main surface of the insulating circuit board 22. Then, as... Figure 6 As shown, the joint portion 41a1 (in the direction of the arrow) of the external connection terminal 41a included in the lead frame of the circuit pattern 24b provided on the insulating circuit board 22 is joined by ultrasonic bonding. Similarly, the external connection terminals 41b, 41c, and 41d included in the lead frames of the circuit patterns 24a, 24c, and 24d provided on the insulating circuit board 22 are also joined by ultrasonic bonding (step S6). It should be noted that the ultrasonic bonding at this time has a frequency of 20 kHz or more and 80 kHz or less, a bonding load of 20 N or more and 150 N or less, and an oscillation time of 50 msec or more and 500 msec or less. As described above, the lower part of the circuit pattern 24 is embedded in the resin substrate 23. Therefore, even if the circuit patterns 24a, 24b, 24c, and 24d on the resin substrate 23 are ultrasonically bonded, the circuit patterns 24a, 24b, 24c, and 24d can reliably transmit ultrasonic vibrations without peeling off from the resin substrate 23, and can stably bond to the external connection terminal 40.

[0048] Next, as Figure 7 As shown, the first semiconductor chip 21a and the second semiconductor chip 21b are respectively bonded to the circuit pattern 24a using solder. Similarly, the first semiconductor chip 21a and the second semiconductor chip 21b are respectively bonded to the circuit patterns 24b, 24c, and 24d using solder. Furthermore, the electronic component 50 is bonded to the control wiring section 34 using solder (step S7). Next, as... Figure 7 As shown, the control terminal 30, electronic component 50, first semiconductor chip 21a, second semiconductor chip 21b, and external connection terminal 40 are connected by bonding wire 26. Figure 7 A suitable electrical connection is made between the external connection terminals 41a and the ground (step S8).

[0049] Next, the upper mold 81 and lower mold 82 of the forming mold 80 are used to clamp the mold configured as follows. Figure 7 The apparatus shown. Therefore, as... Figure 8 As shown, the insulating circuit board 22, the multiple control terminals 30 of the lead frame, and the multiple external connection terminals 40 are housed in a cavity 84 formed by an upper mold 81 and a lower mold 82. Then, the raw material for the encapsulation member 60 is injected from the flow path 83 of the lower mold 82 to fill the cavity 84. Thus, the insulating circuit board 22, the multiple control terminals 30 of the lead frame, and the multiple external connection terminals 40 are encapsulated by the encapsulation member 60. At this time, the insulating circuit board 22 is kept horizontal and encapsulated by the external connection terminals 41a, 41b, 41c, and 41d. After molding, the upper mold 81 and the lower mold 82 are separated, and the semiconductor device 10 is removed. Finally, burrs on the encapsulation member 60, the connecting rods of the lead frame, and portions extending from the semiconductor device 10, etc., are removed. Thus, a product is obtained. Figures 1-3 The semiconductor device 10 shown (step S9).

[0050] Next, use Figures 9-13 The resin substrate 23, which is manufactured by step S5 in the flowchart illustrating the above-described semiconductor device manufacturing method, and is bonded with the circuit pattern 24, is described. Figures 9-13 This diagram illustrates the bonding circuit pattern to the semi-cured substrate in a semi-cured state according to an embodiment. It should be noted that... Figures 9-13 It shows the relationship with Figure 2 The cross-sectional view corresponds to the resin substrate 23 with the circuit pattern 24 bonded thereto. Furthermore, Figures 9-13 This only indicates the resin substrate 23 with the circuit pattern 24 bonded to it. The description of the heat sink 25 is omitted.

[0051] Figure 9This refers to a resin substrate 23 with the circuit pattern 24 bonded to it. In step S1 of the above flowchart, a metal pattern cut from a metal plate with a rectangular cross-section is prepared. The metal pattern is bonded to a prepreg substrate (step S4), and after step S5, a resin substrate 23 with the circuit pattern 24 bonded to it is obtained. Figure 9 In any of (A) to (C), the front side of the circuit pattern 24 is exposed from the resin substrate 23, and the back side is embedded in the resin substrate 23. That is, Figure 9 (A) to (C) indicate a position where the back side of circuit pattern 24 is located below the front side of resin substrate 23. It should be noted that, here, "above" and "below" refer to the direction from the back side of resin substrate 23 towards the front side and the direction from the front side towards the back side, respectively. The side moving away from the back side of resin substrate 23 towards the front side is indicated as "above," and the side moving closer to the back side from the front side of resin substrate 23 is indicated as "below." Thus, in Figure 9 In either case, the sides of the circuit pattern 24 are supported by the resin substrate 23. Therefore, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the flowchart above, the circuit pattern 24 can be prevented from peeling off from the resin substrate 23. The ultrasonic vibration can be reliably transmitted to the circuit pattern 24 through the external connection terminal 40, and the external connection terminal 40 can be properly bonded to the circuit pattern 24.

[0052] also, Figure 9 (A) shows the case where the front side of the circuit pattern 24 is positioned above the front side of the resin substrate 23. Figure 9 (B) shows the case where the front side of the circuit pattern 24 is on the same plane as the front side of the resin substrate 23. Furthermore, Figure 9 (C) shows the case where the front side of the circuit pattern 24 is positioned below the front side of the resin substrate 23. Figure 9 In (A), the front side of the circuit pattern 24 protrudes from the front side of the resin substrate 23. Therefore, when bonding wiring components to the circuit pattern 24 in subsequent processes, the bonding tool can easily access the surface, allowing for convenient bonding of the external connection terminals 40. On the other hand, Figure 9 (B) and (C) are the same as Figure 9 Compared to (A), the contact area between the side of circuit pattern 24 and resin substrate 23 is increased. Therefore, Figure 9 (B) and (C) are more capable than Figure 9 (A) more effectively connects the external connection terminal 40 to the circuit pattern 24.

[0053] However, in Figure 9In cases (B) and (C), when bonding the metal pattern to the prepreg substrate, the material of the prepreg substrate may adhere to the front side of the metal pattern. If the resin substrate 23 is manufactured with the material of the prepreg substrate adhered to the front side of the metal pattern, the bonding area on the front side of the circuit pattern 24 is reduced. Furthermore, when the external connection terminal 40 is bonded to the circuit pattern 24 in this state, electrical defects may occur. Therefore, in Figure 9 In (B) and (C), it is necessary to remove the attachments on the front side of the circuit pattern 24.

[0054] In addition, Figure 9 In case (C), the front side of the circuit pattern 24 is positioned below the front side of the resin substrate 23. If there are adjacent circuit patterns 24, the creepage distance between these circuit patterns 24 can be maintained. On the other hand, if the distance between the back side of the circuit pattern 24 and the back side of the resin substrate 23 is too close, insulation of the heat sink 25 to the back side of the resin substrate 23 may sometimes be unsustainable. Therefore, the distance between the front side of the circuit pattern 24 and the front side of the resin substrate 23, and the distance between the back side of the circuit pattern 24 and the back side of the resin substrate 23, must be appropriately set to maintain this insulation.

[0055] Figure 10 also with Figure 9 Similarly, a resin substrate 23 with a rectangular cross-section circuit pattern 24 is also shown. However, Figure 10 This refers to the case where, in step S4, a constraint protrusion is generated covering the side portion of the metal pattern when the metal pattern is pressed onto the semi-cured substrate, and a resin substrate 23 with the circuit pattern 24 is manufactured in this state. Figure 10In any of (A) to (D), the front side of the circuit pattern 24 protrudes from the resin substrate 23, the back side contacts the resin substrate 23, and the sides are covered by the constraint protrusions 23a and the bonding constraint protrusions 23b of the resin substrate 23. It should be noted that, in top view, all sides of the circuit pattern 24 can be completely covered by the constraint protrusions 23a and the bonding constraint protrusions 23b of the resin substrate 23, or only partially covered. This is sufficient as long as the constraint protrusions 23a and the bonding constraint protrusions 23b are present at least on a pair of opposite sides of the circuit pattern 24. Furthermore, in cross-sectional view, from the back side of the circuit pattern 24 toward the front side, all sides of the circuit pattern 24 can be covered by the constraint protrusions 23a and the bonding constraint protrusions 23b, or even partially covered. It should be noted that, in this case, preferably, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the above flowchart, the opposite pair of sides face each other in the direction of ultrasonic vibration. By having a constraint protrusion 23a and a combined constraint protrusion 23b in the direction of ultrasonic vibration, ultrasonic vibration can be reliably transmitted, and the external connection terminal 40 can be properly connected to the circuit pattern 24.

[0056] Figure 10 In (A), the back side of the circuit pattern 24 is on the same plane as the front side of the resin substrate 23. Furthermore, it is shown that the side of the circuit pattern 24 is supported by the constraint protrusion 23a. Figure 10 (B) is also with Figure 10 (A) is the same. However, in Figure 10 In (B), a case is shown where constraint protrusions with gaps between adjacent circuit patterns 24 are joined together to form a combined constraint protrusion 23b. Figure 10 (C) shows relative to Figure 10 In case (A), the back side of the circuit pattern 24 is further positioned below the front side of the resin substrate 23. Therefore, in Figure 10 In (C), the circuit pattern 24 is supported on the resin substrate 23 by the back side of the circuit pattern 24 located below the front side of the resin substrate 23 and the side covered by the constraint protrusion 23a. Figure 10 (D) shows relative to Figure 10 In case (B), the back side of the circuit pattern 24 is further positioned below the front side of the resin substrate 23. Therefore, in Figure 10In (D), the circuit pattern 24 is supported on the resin substrate 23 by the back side of the circuit pattern 24, which is located below the front side of the resin substrate 23, and the side covered by the constraint protrusion 23a and the connecting constraint protrusion 23b. Here, "above" and "below" refer to the direction from the back side of the resin substrate 23 toward the front side and the direction from the front side toward the back side, respectively. The side that moves away from the back side of the resin substrate 23 toward the front side is indicated as "above," and the side that moves closer to the back side of the resin substrate 23 is indicated as "below."

[0057] In this case, also with Figure 9 Similarly, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the flowchart above, the circuit pattern 24 is prevented from peeling off from the resin substrate 23. Ultrasonic vibrations can be reliably transmitted to the circuit pattern 24 through the external connection terminal 40, ensuring proper bonding of the external connection terminal 40 to the circuit pattern 24. Furthermore, Figure 10 (C) and (D) are the same as Figure 10 Compared to (A) and (B), the contact area between the side of circuit pattern 24 and resin substrate 23 is increased. Therefore, Figure 10 (C) and (D) are more capable than Figure 10 (A) and (B) more effectively connect the external connection terminal 40 to the circuit pattern 24.

[0058] exist Figure 11 The diagram illustrates the process in which, in step S1 of the flowchart above, a metal pattern punched from a metal plate is bonded to a prepreg substrate (step S4), and after step S5, a resin substrate 23 with the circuit pattern 24 bonded to it is obtained. This circuit pattern 24 has protruding protrusions (burrs 241) formed on a pair of opposing edges on its back side, and curved collapsed edges 242 formed on the front side opposite the burrs 241. Furthermore, the back side of the circuit pattern 24 with the burrs 241 is provided on the front side of the resin substrate 23. It should be noted that, in this case, preferably, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the flowchart above, the pair of opposing edges face each other in the direction of ultrasonic vibration.

[0059] Figure 11 In any of (A) to (D), the front side of the circuit pattern 24 protrudes from the resin substrate 23, the back side contacts the resin substrate 23, and the burr 241 is embedded in the resin substrate 23. That is, Figure 11Figures (A) to (D) show the case where the burr 241 of the circuit pattern 24 is located below the front surface of the resin substrate 23. It should be noted that here, "above" and "below" refer to the direction from the back surface of the resin substrate 23 toward the front surface and the direction from the front surface toward the back surface, respectively. "Above" refers to the direction moving away from the back surface of the resin substrate 23 toward the front surface, and "below" refers to the direction moving closer to the back surface of the resin substrate 23.

[0060] Figure 11 (A) shows the case where the back side of the circuit pattern 24 is on the same plane as the front side of the resin substrate 23, and the burrs 241 of the circuit pattern 24 extend into the front side of the resin substrate 23. Figure 11 (B) shows from Figure 11 In case (A), the back side of the circuit pattern 24 is further located below the front side of the resin substrate 23. Figure 11 (C) shows from Figure 11 In case (B), the front side of the circuit pattern 24 is further aligned with the front side of the resin substrate 23. Furthermore, Figure 11 (D) shows from Figure 11 In case (C), the front side of the circuit pattern 24 is further positioned below the front side of the resin substrate 23. Furthermore, in Figure 11 In case (D), the collapsed edge 242 of the circuit pattern 24 is covered by the resin substrate 23 and pressed towards the center of the circuit pattern 24. Therefore, the circuit pattern 24 is firmly fixed to the resin substrate 23.

[0061] In this case, also with Figure 9 Similarly, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the flowchart above, the circuit pattern 24 is prevented from peeling off from the resin substrate 23. Ultrasonic vibrations can be reliably transmitted to the circuit pattern 24 through the external connection terminal 40, ensuring proper bonding of the external connection terminal 40 to the circuit pattern 24. In particular, in Figure 11 In this case, because the burrs 241 of the circuit pattern 24 enter the resin substrate 23, therefore with Figure 9 , Figure 10 Compared to the previous case, the circuit pattern 24 is more firmly bonded to the resin substrate 23. Figure 11 In (A) and (B), the front side of the circuit pattern 24 protrudes from the front side of the resin substrate 23. Therefore, when bonding wiring components to the circuit pattern 24 in subsequent processes, the bonding tool can easily access the surface, allowing for convenient bonding of the external connection terminal 40. On the other hand, Figure 11 (C) and (D) are the same as Figure 11 Compared to (A) and (B), the contact area between the side of circuit pattern 24 and resin substrate 23 is increased. Therefore, Figure 11 (C) and (D) are more capable than Figure 11 (A) and (B) more effectively connect the external connection terminal 40 to the circuit pattern 24.

[0062] Figure 12 and Figure 11 Similarly, the process shown in step S1 of the above flowchart, where a metal pattern punched from a metal plate is bonded to a prepreg substrate (step S4), and then proceeds to step S5, thereby obtaining a resin substrate 23 with the circuit pattern 24 bonded thereto. This circuit pattern 24 has protruding protrusions (burrs 241) formed on a pair of opposing edges on its back side, and the collapsed edges 242 on the front side opposite to the burrs 241 are removed, resulting in a generally planar front side. Furthermore, the back side of the circuit pattern 24 with the burrs 241 is provided on the front side of the resin substrate 23.

[0063] exist Figure 12 In any of (A) to (D), the front side of the circuit pattern 24 protrudes from the resin substrate 23, the back side contacts the resin substrate 23, and the burr 241 is embedded in the resin substrate 23. That is, Figure 12 Figures (A) to (D) show the case where the burr 241 of the circuit pattern 24 is located below the front surface of the resin substrate 23. It should be noted that here, "above" and "below" refer to the direction from the back surface of the resin substrate 23 toward the front surface and the direction from the front surface toward the back surface, respectively. "Above" refers to the direction moving away from the back surface of the resin substrate 23 toward the front surface, and "below" refers to the direction moving closer to the back surface of the resin substrate 23.

[0064] Figure 12 (A) and Figure 11 Similarly, (A) shows a case where the back side of the circuit pattern 24 is on the same plane as the front side of the resin substrate 23, and the burrs 241 of the circuit pattern 24 enter the front side of the resin substrate 23. Figure 12 (B) and Figure 11 Similarly, (B) shows from Figure 12 In case (A), the back side of the circuit pattern 24 is further located below the front side of the resin substrate 23. Figure 12 (C) shows from Figure 12 In case (B), the front side of the circuit pattern 24 is further aligned with the front side of the resin substrate 23. Furthermore, Figure 12 (D) shows from Figure 12 In case (C), the front side of the circuit pattern 24 is further positioned below the front side of the resin substrate 23.

[0065] In this case, also with Figure 9Similarly, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the flowchart above, the circuit pattern 24 is prevented from peeling off from the resin substrate 23. Ultrasonic vibrations can be reliably transmitted to the circuit pattern 24 through the external connection terminal 40, ensuring proper bonding of the external connection terminal 40 to the circuit pattern 24. In particular, in Figure 12 In this case, because the burrs 241 of the circuit pattern 24 enter the resin substrate 23, therefore with Figure 9 , Figure 10 Compared to the previous case, the circuit pattern 24 is more firmly bonded to the resin substrate 23. Furthermore, in Figure 12 In (A) and (B), the front side of the circuit pattern 24 protrudes from the front side of the resin substrate 23. Therefore, when bonding wiring components to the circuit pattern 24 in subsequent processes, the bonding tool can easily access the surface, allowing for convenient bonding of the external connection terminal 40. On the other hand, Figure 12 (C) and (D) are the same as Figure 12 Compared to (A) and (B), the contact area between the side of circuit pattern 24 and resin substrate 23 is increased. Therefore, Figure 12 (C) and (D) are more capable than Figure 12 (A) and (B) more effectively connect the external connection terminal 40 to the circuit pattern 24.

[0066] Figure 13 China is the opposite Figure 10 The situation applied Figure 11 , Figure 12 The circuit pattern 24 is formed. That is, Figure 13 This illustrates the case where, in step S1 of the above flowchart, a metal pattern punched from a metal plate is bonded to a prepreg substrate (step S4), and after step S5, a resin substrate 23 with the circuit pattern 24 bonded is obtained. Figure 13 The circuit patterns 24 of (A) and (C) have protruding burrs 241 formed on a pair of opposing edges on their back side, and curved collapsed edges 242 formed on the front side opposite to the burrs 241. On the other hand, Figure 13 In (B) and (D), the collapsed edge 242 of the front edge of the circuit pattern 24 is removed, and the front surface is generally flat. In addition, the back side of the circuit pattern 24 with burrs 241 is provided on the front side of the resin substrate 23.

[0067] exist Figure 13 In any of (A) to (D), the front side of the circuit pattern 24 protrudes from the resin substrate 23, the back side contacts the resin substrate 23, the sides are covered by the constraint protrusions 23a of the resin substrate 23, and the burrs 241 are embedded in the resin substrate 23. That is, Figure 13(A) to (D) show the case where the burr 241 of the circuit pattern 24 is located below the front side of the resin substrate 23.

[0068] Figure 13 (A) shows Figure 11 The back side of the circuit pattern 24 is on the same plane as the front side of the resin substrate 23, and the side of the circuit pattern 24 is supported by the constraint protrusion 23a. Figure 13 (B) shows Figure 12 The back side of the circuit pattern 24 is on the same plane as the front side of the resin substrate 23, and the side of the circuit pattern 24 is supported by the constraint protrusion 23a. Figure 13 (C) shows relative to Figure 13 In case (A), the back side of the circuit pattern 24 is further located below the front side of the resin substrate 23. Figure 13 (D) shows relative to Figure 13 In case (B), the back side of the circuit pattern 24 is further located below the front side of the resin substrate 23.

[0069] In this case, also with Figure 9 Similarly, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the flowchart above, the circuit pattern 24 is prevented from peeling off from the resin substrate 23. Ultrasonic vibrations can be reliably transmitted to the circuit pattern 24 through the external connection terminal 40, ensuring proper bonding of the external connection terminal 40 to the circuit pattern 24. In particular, in Figure 13 In this case, because the burrs 241 of the circuit pattern 24 enter the resin substrate 23, therefore with Figure 9 , Figure 10 Compared to the previous case, the circuit pattern 24 is more firmly bonded to the resin substrate 23. Furthermore, Figure 13 (C) and (D) are the same as Figure 13 Compared to (A) and (B), the contact area between the side of circuit pattern 24 and resin substrate 23 is increased. Therefore, Figure 13 (C) and (D) are more capable than Figure 13 (A) and (B) more reliably connect the external connection terminal 40 to the circuit pattern 24. Furthermore, Figure 13 The collapsed edge 242 of the circuit pattern 24 in (C) is covered by the resin substrate 23, which is more effective than other circuits. Figure 13 (A), (B), and (D) more effectively connect the external connection terminal 40 to the circuit pattern 24.

[0070] In the circuit pattern 24 formed on the insulating circuit board 22 of the semiconductor device 10, preferably, the circuit pattern 24 that is ultrasonically bonded to at least the external connection terminal 40 is bonded to the resin substrate 23 and at least one pair of opposing sides are supported by the resin substrate 23. Figure 14 and Figure 15 This illustrates another example of such an insulating circuit board 22. Figure 14 and Figure 15 This is a diagram illustrating another insulating circuit board of the semiconductor device according to an embodiment. It should be noted that, in Figure 14 and Figure 15 The image shows the insulating circuit board 22 and the external connection terminal 41a in the semiconductor device 10.

[0071] For example, such as Figure 14 As shown, circuit patterns 24a and 24b of approximately equal thickness are mounted on a resin substrate 23. Circuit pattern 24b, which connects to the external connection terminal 41a, is bonded to the resin substrate 23, and its two sides are supported by the resin substrate 23. On the other hand, the back side of circuit pattern 24a, to which the first semiconductor chip 21a and the second semiconductor chip 21b are bonded, is approximately flush with and fixed to the front side of the resin substrate 23, and its sides are not supported by the resin substrate 23. In this case, the front side of circuit pattern 24b is located below the front side of circuit pattern 24a. Furthermore, the back side of circuit pattern 24b is located below the back side of circuit pattern 24a. That is, the resin substrate 23 below circuit pattern 24a is thicker. Therefore, stress caused by the heat generated by the semiconductor chips 21a and 21b can be mitigated.

[0072] In addition, such as Figure 15 As shown, circuit patterns 24a and 24b of different thicknesses are mounted on a resin substrate 23. Circuit pattern 24a is processed to be thinner than circuit pattern 24b. Circuit pattern 24b, which connects to the external connection terminal 41a, is bonded to the resin substrate 23, and its two sides are supported by the resin substrate 23. On the other hand, the back side of circuit pattern 24a, to which the first semiconductor chip 21a and the second semiconductor chip 21b are bonded, is substantially flush with the front side of the resin substrate 23 and is fixed thereto, and its sides are not supported by the resin substrate 23. In this case, the front side of circuit pattern 24b is at approximately the same height as the front side of circuit pattern 24a. Furthermore, the back side of circuit pattern 24b is located below the back side of circuit pattern 24a. That is, the resin substrate 23 below circuit pattern 24a is thicker. Therefore, stress caused by the heat generated by the semiconductor chips 21a and 21b can be mitigated.

[0073] The semiconductor device 10 described above includes an insulating circuit board 22, which has: a heat sink 25 having a front side; a resin substrate 23 having a back side and a front side fixed to the front side and comprising resin; and a circuit pattern 24 having a back side and a front side fixed to the front side. The semiconductor device 10 has at least one of a first semiconductor chip 21a, a second semiconductor chip 21b, and an external connection terminal 40 bonded to the front side, and at least one pair of opposing sides of the circuit pattern 24 are respectively supported by the resin substrate 23. It should be noted that, in this case, preferably, when the external connection terminal 40 is ultrasonically bonded to the circuit pattern 24 in step S6 of the above flowchart, the opposing pair of sides face each other in the direction of ultrasonic vibration. In such a semiconductor device 10, since the circuit pattern 24 is supported by the resin substrate 23 when the external connection terminal 40 is bonded to the circuit pattern 24 by ultrasonic bonding, the circuit pattern 24 will not peel off from the resin substrate 23. Therefore, ultrasonic waves from the external connection terminal 40 are transmitted to the circuit pattern 24, and bonding can be reliably achieved. Then, the external connection terminal 40 is directly bonded to the circuit pattern 24. Therefore, compared to bonding the external connection terminal 40 to the circuit pattern 24 via bonding wires, the resistance can be reduced. Furthermore, the semiconductor device 10 uses an insulating circuit board 22. Therefore, the semiconductor device 10 can efficiently dissipate heat from the first semiconductor chip 21a and the second semiconductor chip 21b from the heat sink 25, suppressing temperature rise. Moreover, the control area 30a, where the control wiring portion 34 included in the control terminal 30 is located higher than the component area 22a of the insulating circuit board 22. Therefore, the effects of noise generated in each area can be suppressed, and the semiconductor device 10 can be driven stably. Thus, the characteristics of the semiconductor device 10 can be improved. Furthermore, the semiconductor device 10 does not use a housing integrally formed with the control terminal 30 and the external connection terminal 40. Therefore, the process of forming such a housing and the process of bonding the insulating circuit board 22 to the housing are eliminated. Therefore, the manufacturing process of the semiconductor device 10 can be simplified, reducing manufacturing costs.

Claims

1. A semiconductor device, characterized by comprising: having: an insulating circuit substrate having a heat dissipation plate, a resin substrate, and a circuit pattern, the heat dissipation plate having a first front surface, the resin substrate having a second front surface and a second back surface fixed to the first front surface and containing a resin, the circuit pattern having a third front surface and a third back surface fixed to the second front surface; a semiconductor chip joined to the third front surface; and a lead frame joined to the third front surface by ultrasonic joining, at least a pair of side portions of the circuit pattern joined by the ultrasonic joining are each supported by the resin substrate.

2. The semiconductor device according to claim 1, wherein the circuit pattern is joined in a manner that the third back surface is positioned lower than the second front surface of the resin substrate.

3. The semiconductor device according to claim 2, wherein the circuit pattern is joined in a manner that the third front surface is positioned at the same position as the second front surface of the resin substrate or is positioned lower than the second front surface.

4. The semiconductor device according to claim 1, wherein a side portion of the circuit pattern is supported by a protrusion-shaped restraint protrusion of the second front surface of the resin substrate.

5. The semiconductor device according to claim 4, wherein in a case where a plurality of the circuit patterns are provided with a gap therebetween, a joining restraint protrusion is formed in the gap, the joining restraint protrusion being configured by the restraint protrusions being connected.

6. The semiconductor device according to claim 1, wherein a protrusion-shaped protrusion portion is formed in a pair of edge portions of the third back surface of the circuit pattern, the protrusion portion entering the second front surface of the resin substrate.

7. The semiconductor device according to claim 6, wherein a curved shape-shaped beading is formed in an edge portion of the third front surface of the circuit pattern opposite to the protrusion portion.

8. The semiconductor device according to claim 1, wherein the resin is any one of a phenol resin, an epoxy resin, and a melamine resin.

9. A method for manufacturing a semiconductor device, characterized by including: a preparation step of preparing a heat dissipation plate, a circuit pattern, and a lead frame; a semi-cured substrate forming step of forming a semi-cured substrate containing a thermosetting resin in a semi-cured state; a resin substrate manufacturing step of arranging the semi-cured substrate on a first front surface of the heat dissipation plate, arranging the circuit pattern on a second front surface of the semi-cured substrate, pressing the circuit pattern toward the first front surface and heating the semi-cured substrate to cure the semi-cured substrate, thereby manufacturing a resin substrate having the circuit pattern fixed thereto in a manner of supporting at least a pair of side portions of the circuit pattern opposite to each other; and a joining step of joining the lead frame to a third front surface of the circuit pattern by ultrasonic joining.

10. The manufacturing method of the semiconductor device according to claim 9, wherein In the semi-cured substrate forming step, a step of mixing a liquid thermosetting resin with a powder inorganic filler and heating to form a powder semi-cured raw material is included.

11. The method according to claim 10, wherein In the semi-cured substrate forming step, a step of filling the semi-cured raw material into a predetermined mold and pressing the semi-cured raw material in the mold to form the semi-cured substrate is included.

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