Compensation circuit for compensating a clock signal and memory device comprising the same

Abstract

A memory device includes a delay-locked loop (DLL), a clock compensation circuit, and data input / output (I / O) circuitry. The DLL outputs a first clock signal and a second clock signal. The clock compensation circuit adjusts the voltage level of an output node and generates an internal clock signal based on the voltage level of the output node. The data I / O circuitry outputs data to an external device based on the internal clock signal. The clock compensation circuit includes a first pulse adjustment circuit and a second pulse adjustment circuit. The first pulse adjustment circuit is connected to the first output node and outputs a first regulated current based on the first clock signal and the voltage level of the first output node. The second pulse adjustment circuit is connected to the second output node and outputs a second regulated current based on the second clock signal and the voltage level of the second output node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0164400, filed on December 11, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of the inventive concept described herein relate to a compensation circuit, and more specifically, to a compensation circuit for compensating clock signals and a memory device including the compensation circuit. Background Technology

[0004] Semiconductor memory devices can be classified into volatile memory devices or non-volatile memory devices. Volatile memory devices are memory devices that lose the data stored in them when power is disconnected. As a volatile memory device, Dynamic Random Access Memory (DRAM) is used in various devices, such as mobile systems, servers, and graphics devices.

[0005] Memory devices can operate synchronously with a clock applied externally to the memory device. A memory device may include a delay-locked loop (DLL). The DLL can delay the externally applied clock and can generate an internal clock used within the memory device. Based on the internal clock, the memory device can control components within the memory device or send data to the memory controller.

[0006] The clock generation circuitry of a memory device can generate clock pulse signals based on an internal clock with a period set by the user or the memory controller. However, if the clock generation circuitry fails to output clock pulse signals due to variations in process, voltage, and temperature (PVT), the memory device may be unable to send data to the memory controller, or data transmission may be delayed. Summary of the Invention

[0007] Embodiments of the present invention provide a compensation circuit for compensating for internal clock signals.

[0008] According to an exemplary embodiment, a clock compensation circuit may include a first switching circuit, a first pulse adjustment circuit, a second switching circuit, and a second pulse adjustment circuit. The first switching circuit can determine whether to electrically connect a first node to a second node based on a first clock signal. The first pulse adjustment circuit is connected to a first output node, and when the second node is electrically disconnected from the first node, it can output a first adjustment current based on the voltage level of the first output node, and can block the first adjustment current in response to the first clock signal. The second switching circuit can determine whether to electrically connect a third node to a fourth node based on a second clock signal different from the first clock signal. When the fourth node is electrically disconnected from the third node, the second pulse adjustment circuit can output a second adjustment current based on the voltage level of the second output node, and can block the second adjustment current in response to the second clock signal. The first pulse adjustment circuit and the second pulse adjustment circuit can provide feedback on the voltages of the first and second output nodes and can adjust the voltage levels of the second and fourth nodes.

[0009] According to an exemplary embodiment, a memory device may include a delay-locked loop (DLL), a clock compensation circuit, and data input / output (I / O) circuitry. The DLL may output a first clock signal and a second clock signal different from the first clock signal. The clock compensation circuitry is connected to an output node and may adjust the voltage level of the output node based on the first and second clock signals, and may generate an internal clock signal based on the voltage level of the output node. The data I / O circuitry may output data to an external location of the memory device based on the internal clock signal. The clock compensation circuitry may include a first pulse adjustment circuit and a second pulse adjustment circuit. The first pulse adjustment circuitry is connected to a first output node and may determine whether to output a first regulated current based on the first clock signal and the voltage level of the first output node. The second pulse adjustment circuitry is connected to a second output node and may determine whether to output a second regulated current based on the second clock signal and the voltage level of the second output node.

[0010] According to an exemplary embodiment, the clock compensation circuit may include a first switching circuit, a first pulse adjustment circuit, a second switching circuit, and a second pulse adjustment circuit. The first switching circuit can determine whether to electrically connect a first node to a second node based on a first clock signal. The first pulse adjustment circuit can output a first adjustment current based on the voltage level of the first clock signal and the voltage level of the second node to adjust the voltage level of the first output node, and when the first node is electrically disconnected from the second node, it can feed back the voltage of the first output node to adjust the voltage level of the second node. The second switching circuit can determine whether to electrically connect a third node to a fourth node based on a second clock signal different from the first clock signal. The second pulse adjustment circuit can output a second adjustment current based on the voltage level of the second clock signal and the voltage level of the fourth node to adjust the voltage level of the second output node, and when the third node is electrically disconnected from the fourth node, it can feed back the voltage of the second output node to adjust the voltage level of the fourth node. Attached Figure Description

[0011] The above and other objects and features of the present invention will become apparent from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

[0012] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 2 It is used to describe according to the example embodiments Figure 1 The block diagram of the compensation circuit.

[0014] Figure 3 This illustrates an example embodiment. Figure 2 A block diagram of an embodiment of the compensation circuit.

[0015] Figure 4 It is used to describe according to the example embodiments Figure 3 Timing diagram of the operation of the compensation circuit.

[0016] Figure 5 It is used to describe according to the example embodiments Figure 3 The flowchart shows the operation of the compensation circuit.

[0017] Figure 6 It is used to describe according to the example embodiments Figure 3 The flowchart shows the operation of the compensation circuit.

[0018] Figure 7 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram illustrating the operation of the compensation circuit.

[0019] Figure 8It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram illustrating the operation of the compensation circuit.

[0020] Figure 9 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram illustrating the operation of the compensation circuit.

[0021] Figure 10 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram illustrating the operation of the compensation circuit.

[0022] Figure 11 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram illustrating the operation of the compensation circuit.

[0023] Figure 12 This illustrates an example embodiment. Figure 1 A block diagram of an embodiment of the compensation circuit.

[0024] Figure 13 This illustrates an example embodiment. Figure 12 A block diagram of an embodiment of the compensation circuit.

[0025] Figure 14 It is used to describe according to the example embodiments Figure 13 Timing diagram of the operation of the compensation circuit.

[0026] Figure 15 It is used to describe according to the example embodiments Figure 13 The flowchart shows the operation of the compensation circuit. Detailed Implementation

[0027] The embodiments of the present invention will now be described in detail and clearly to the extent that those skilled in the art can readily implement the present invention.

[0028] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present invention. (Reference) Figure 1 Semiconductor device 10000 may include memory device 1000 and memory controller 2000. Semiconductor device 10000 may be a memory system.

[0029] The memory device 1000 can receive a clock signal CK, a reset signal RESET, a command CMD, an address ADD, a data strobe signal DQS, and a data signal DQ from the memory controller 2000. The memory device 1000 can operate synchronously with the clock signal CK. In an embodiment, the memory device 1000 may be a dynamic random access memory (DRAM). However, the inventive concept is not limited to this. For example, the memory device 1000 may include volatile memory (such as static RAM (SRAM) or synchronous DRAM (SDRAM)), or non-volatile memory (such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)).

[0030] Figure 1 Examples of memory systems shown may include flash memory-based data storage media such as memory cards, USB storage devices, and SSDs (solid-state drives), but are not limited to these examples.

[0031] In some examples, memory controller 2000 can be connected to a host (not shown) and memory device 1000. Memory controller 2000 can be configured to access memory device 1000 in response to a request from the host. Memory controller 2000 can be configured to provide an interface between memory device 1000 and the host.

[0032] After power is supplied to the semiconductor device 10000, the memory controller 2000 may send a reset signal RESET to the memory device 1000. The memory device 1000 may receive the reset signal RESET to perform a reset operation. The memory device 1000 may perform an initialization operation depending on the reset operation. Alternatively, the memory device 1000 may receive a separate initialization command along with the reset signal RESET to perform an initialization operation.

[0033] The memory device 1000 can execute operations corresponding to the command CMD. In an embodiment, the command CMD may include an activation command ACT, a read command RD, and a write command WR. The memory device 1000 can perform read and write operations based on the address ADD.

[0034] The memory device 1000 can output a data strobe signal DQS and a data signal DQ. The memory device 1000 can output the data strobe signal DQS and the data signal DQ based on a clock signal CK and a command CMD. For example, upon receiving a read command, the memory device 1000 can delay the clock signal CK and generate the data strobe signal DQS. The memory device 1000 can then send the data signal DQ, which includes the read data, along with the data strobe signal DQS to the memory controller 2000.

[0035] Memory device 1000 may include a delay-locked loop (DLL) 1100, a compensation circuit 100, and a data output circuit 1200. The delay-locked loop 1100 may delay a clock signal CK to output an internal clock signal. The compensation circuit 100 may generate a data strobe signal DQS based on the internal clock signal output from the delay-locked loop 1100. The data output circuit 1200 may output a data signal DQ together with the data strobe signal DQS. The data output circuit 1200 may include a driver (not shown) for driving the output of each signal.

[0036] The delay-locked loop 1100 can output an internal clock signal by delaying the clock signal CK by up to a determined delay amount. The phase of the internal clock signal can be locked depending on the determined delay amount.

[0037] The compensation circuit 100 can output a data strobe signal DQS using an internal clock signal. The data strobe signal DQS can be a pulse signal with a pulse per cycle, the cycle being set by the user or memory controller. The compensation circuit 100 can generate the pulses of the data strobe signal DQS depending on the voltage level of the internal clock signal. However, if the internal clock signal is advanced or delayed about a predetermined time due to PVT variations, the duty cycle of the data strobe signal DQS may change, or pulse failure may occur. In the specification, "pulse failure" means that due to PVT variations, the pulse signal fails to reach a high level and remains low when it is supposed to switch to a high level, or fails to reach a low level and remains high when it is supposed to switch to a low level.

[0038] The compensation circuit 100 of this invention can compensate for the data strobe signal DQS and can provide a memory device 1000 that is insensitive to PVT variations. In the following description, "compensation signal" means that the voltage level of the signal is adjusted to a target level depending on the set period. For example, by using the compensation circuit 100, this invention can prevent abrupt changes in the duty cycle of the data strobe signal DQS or pulse failures due to PVT variations.

[0039] Furthermore, the data output circuit 1200 can output the data signal DQ to the memory controller 2000 without delay. Therefore, the reliability of the input / output data of the memory device 1000 can be improved.

[0040] Figure 2 It is used to describe according to the example embodiments Figure 1 The block diagram of the compensation circuit.

[0041] The delay-locked loop 1100 can output multiple internal clock signals in1 and in2. Internal clock signals in1 and in2 can be signals with the same phase, but the invention is not limited to this. For example, internal clock signals in1 and in2 can be signals with different phases. Furthermore, a delay circuit, such as an inverter, can be present between the delay-locked loop 1100 and the compensation circuit 100, and can adjust the phase difference between the internal clock signals in1 and in2.

[0042] The compensation circuit 100 can generate a data strobe signal DQS using internal clock signals in1 and in2 received from the delay-locked loop 1100. For example, the compensation circuit 100 can adjust the voltage level of node p0 using the internal clock signals in1 and in2, and can generate the data strobe signal DQS based on the voltage level of node p0. For example, the compensation circuit 100 can compensate for the data strobe signal DQS by adjusting the voltage level of node p0.

[0043] The compensation circuit 100 may include a first delay circuit 110, a first switching circuit 120, a first pulse conditioning circuit 130, a fixing circuit 140, a second delay circuit 150, a second switching circuit 160, and a second pulse conditioning circuit 170. During periods when the voltage level of node p0 increases, the compensation circuit 100 can compensate for the voltage of node p0 by using the first switching circuit 120 and the first pulse conditioning circuit 130. Furthermore, during periods when the voltage level of node p0 decreases, the compensation circuit 100 can compensate for the voltage of node p0 by using the second delay circuit 150, the second switching circuit 160, and the second pulse conditioning circuit 170.

[0044] The first delay circuit 110 may include one or more inverters. In the following description, it is assumed that the first delay circuit 110 includes two inverters, but the inventive concept is not limited thereto. The first delay circuit 110 may receive an internal clock signal in1. The first delay circuit 110 may delay the received internal clock signal in1. The first delay circuit 110 may output the delayed internal clock signal in1 to node n1.

[0045] The first switching circuit 120 can receive an internal clock signal in1 and an inverted internal clock signal / in1. The first switching circuit 120 can determine whether to electrically connect node n1 to node n2 based on the received internal clock signal in1 and inverted internal clock signal / in1. When node n2 is electrically connected to node n1, the delayed internal clock signal in1 can be transmitted from node n1 to node n2 through the first switching circuit 120. In this case, the voltage level of node n2 can be equal to the voltage level of node n1. When node n2 is electrically disconnected from node n1, the delayed internal clock signal in1 may not be transmitted to node n2. In this case, the voltage level of node n2 may be independent of the voltage level of node n1.

[0046] The first pulse regulation circuit 130 can output a first regulated current from the power (VDD) supply terminal to node p0 based on the internal clock signal in1 and the voltage level of node n2. Components 110 to 170 of the compensation circuit 100 can be provided with a drive voltage from the power supply terminal. The level of voltage VDD can be higher than the level of voltage VSS. In the following, voltage VDD corresponds to the power supply terminal, and voltage VSS corresponds to the ground terminal.

[0047] The first pulse regulation circuit 130 can operate in such a way that the voltage level of node n2 varies depending on the voltage level of node p0. For example, the first pulse regulation circuit 130 can be a feedback circuit that receives the voltage of node p0 and regulates the voltage level of node p0. The first pulse regulation circuit 130 can output a first regulating current until the voltage level of node p0 reaches a first target level, and can stop outputting the first regulating current when the voltage level of node p0 reaches the first target level. When outputting the first regulating current, the first target level can be higher than the voltage level of node p0.

[0048] The fixed circuit 140 may include latching circuitry. In this specification, the fixed circuit 140 is shown as an inverter ring, wherein two inverters are cross-coupled, but the inventive concept is not limited thereto. In this specification, "inverter ring" means a circuit in which the input and output terminals of one of the two inverters are respectively connected to the output and input terminals of the other inverter. When there is no current output from or input to node p0, the fixed circuit 140 can uniformly maintain the voltage level of node p1. For ease of description, it is assumed below that there is no voltage drop in the sections connected only by wires. Therefore, it is assumed that the voltage level of node p1 is equal to the voltage level of node p0.

[0049] The second delay circuit 150 may include one or more inverters. In the following description, it is assumed that the second delay circuit 150 includes two inverters, but the inventive concept is not limited thereto. The second delay circuit 150 may receive an internal clock signal in2. The second delay circuit 150 may delay the received internal clock signal in2. The second delay circuit 150 may output the delayed internal clock signal in2 to node n5.

[0050] The second switching circuit 160 can receive an internal clock signal in2 and an inverted internal clock signal / in2. The second switching circuit 160 can determine whether to electrically connect node n5 to node n6 based on the received internal clock signal in2 and inverted internal clock signal / in2. When node n6 is electrically connected to node n5, the delayed internal clock signal can be transmitted from node n5 to node n6 through the second switching circuit 160. In this case, the voltage level of node n6 can be equal to the voltage level of node n5. When node n6 is electrically disconnected from node n5, the delayed internal clock signal in2 may not be transmitted to node n6. In this case, depending on the operation of the second pulse adjustment circuit 170, the voltage level of node n6 may be independent of the voltage level of node n5.

[0051] The second pulse regulation circuit 170 can output a second regulating current from node p0 to the ground terminal based on the internal clock signal in2 and the voltage level of node n6. The second pulse regulation circuit 170 can operate in such a way that the voltage level of node n6 varies depending on the voltage level of node p0. For example, the second pulse regulation circuit 170 can be a feedback circuit that receives the voltage of node p0 and regulates the voltage level of node p0. The second pulse regulation circuit 170 can output the second regulating current until the voltage level of node p0 reaches a second target level, and can stop outputting the second regulating current when the voltage level of node p0 reaches the second target level. The second target level can be lower than the first target level. Furthermore, when outputting the second regulating current, the second target level can be lower than the voltage level of node p0.

[0052] For example, the first switching circuit 120 can electrically disconnect nodes n2 from node n1 during the period when the voltage at node p0 increases. Therefore, during the period when the voltage at node p0 increases, the voltage level at node n2 can be independent of the voltage level at node n1 and can vary depending on the voltage level at node p0. The first pulse regulation circuit 130 can output a first regulating current until the voltage level at node n2 indicates that the voltage level at node p0 has reached a first target level. When the voltage level at node n2 indicates that the voltage level at node p0 has reached the first target level, the first pulse regulation circuit 130 may not output the first regulating current.

[0053] The second switching circuit 160 can electrically disconnect nodes n6 from n5 during the period when the voltage of node p0 decreases. Therefore, during the period when the voltage of node p0 decreases, the voltage level of node n6 can be independent of the voltage level of node n5 and can vary depending on the voltage level of node p0. The second pulse regulation circuit 170 can output a second regulating current until the voltage level of node n6 indicates that the voltage level of node p0 has reached a second target level. When the voltage level of node n6 indicates that the voltage level of node p0 has reached the second target level, the second pulse regulation circuit 170 can stop outputting the second regulating current.

[0054] For example, the compensation circuit 100 can provide feedback on the voltage of node p0 to adjust the voltage level of node p0, thereby preventing abrupt changes in the duty cycle of the data strobe signal DQS or preventing pulse failure.

[0055] Figure 3 This illustrates an example embodiment. Figure 2 A block diagram of an embodiment of the compensation circuit. Figure 4 It is used to describe according to the example embodiments Figure 3 The timing diagram for the operation of the compensation circuit will be described together. Figure 3 and Figure 4 Reference Figures 7 to 11 A more comprehensive description Figure 4 The compensation circuit shown operates in each of the time periods 't0' to 't1', 't1' to 't2', 't2' to 't3', 't3' to 't4', and 't4' to 't5'. In the following description, reference is assumed. Figure 2 The first target level and the second target level are described as first level Lv1 and second level Lv2, respectively.

[0056] The delay-locked loop 1100 can output internal clock signals in1 and in2. Internal clock signals in1 and in2 can be signals with the same phase.

[0057] The first delay circuit 110 may include two inverters. The first delay circuit 110 can delay the internal clock signal in1. However, for the sake of convenience, it is assumed that the delay of the first delay circuit 110 does not exist.

[0058] The first switching circuit 120 can be a gate circuit composed of different transistors. One of the transistors can be a p-channel metal-oxide-semiconductor (PMOS) transistor, and the other can be an n-channel metal-oxide-semiconductor (NMOS) transistor. The first terminal of the PMOS transistor can be connected to node n1, and the second terminal of the PMOS transistor can be connected to node n2. An inverted internal clock signal / in1 can be applied to the gate terminal of the PMOS transistor. Based on the inverted internal clock signal / in1, the PMOS transistor can determine whether to output current from node n1 to node n2. The first terminal of the NMOS transistor can be connected to node n1, and the second terminal of the NMOS transistor can be connected to node n2. An internal clock signal in1 can be applied to the gate terminal of the NMOS transistor. Based on the internal clock signal in1, the NMOS transistor can determine whether to output current from node n1 to node n2.

[0059] When the voltage level of the internal clock signal in1 is the second level Lv2, the PMOS transistor and the NMOS transistor can respectively receive the inverted internal clock signal / in1 (first level Lv1) and the internal clock signal in1 (second level Lv2). The first level signal means that its voltage level is the first level Lv1. Furthermore, the second level signal means that its voltage level is the second level Lv2.

[0060] The first level Lv1 signal can correspond to a digital signal with a logic value of "0". The second level Lv2 signal can correspond to a digital signal with a logic value of "1". In this specification, for ease of description, it is assumed that the first level Lv1 and the second level Lv2 are equal to the levels of voltage VSS and voltage VDD, respectively.

[0061] In the following description, it is assumed that when a first-level signal Lv1 is applied to the gate terminal of the PMOS transistor, the PMOS transistor outputs current from the first terminal to the second terminal, and when a second-level signal Lv2 is applied to the gate terminal of the PMOS transistor, the PMOS transistor does not output current from the first terminal to the second terminal. Furthermore, it is assumed that when a second-level signal Lv2 is applied to the gate terminal of the NMOS transistor, the NMOS transistor outputs current from the first terminal to the second terminal, and when a first-level signal Lv1 is applied to the gate terminal of the NMOS transistor, the NMOS transistor does not output current.

[0062] As shown in the time period 't0' to 't1', when the internal clock signal in1 of the second level Lv2 and the inverted internal clock signal / in1 of the first level Lv1 are received, the first switching circuit 120 can output current from node n1 to node n2. As shown in the time period 't1' to 't2', when the internal clock signal in1 of the first level Lv1 and the inverted internal clock signal / in1 of the second level Lv2 are received, the first switching circuit 120 may not output current from node n1 to node n2.

[0063] In the following description, node n1 being electrically connected to node n2 means that current flows from node n1 to node n2. Conversely, node n1 being electrically disconnected from node n2 means that current does not flow from node n1 to node n2.

[0064] When node n1 is electrically connected to node n2, the voltage level of node n2 can be equal to the voltage level of node n1. When node n2 is electrically disconnected from node n1, the voltage level of node n2 can be determined by... Figure 2 The operation of the first pulse adjustment circuit 130 is determined.

[0065] The first pulse regulation circuit 130 may include transistors 131, 133, 134 and 135 and a latch circuit 132.

[0066] Latch circuit 132 can invert the phase of the signal input to node n2. Latch circuit 132 can output the inverted phase signal of node n2 to node n3. For example, latch circuit 132 can be an inverter loop. For example, latch circuit 132 can operate such that when the voltage level of node n2 is a first level Lv1, the voltage level of node n3 is a second level Lv2. Furthermore, latch circuit 132 can operate such that when the voltage level of node n2 is a second level Lv2, the voltage level of node n3 is a first level Lv1.

[0067] Transistor 131 may be a PMOS transistor. A first terminal of transistor 131 may be connected to the VDD supply terminal, and a second terminal of transistor 131 may be connected to the first terminal of transistor 133. Furthermore, an internal clock signal in1 may be applied to the gate terminal of transistor 131. Transistor 131 may determine whether to output a first regulating current from the VDD supply terminal to transistor 133 based on the internal clock signal in1. However, the inventive concept is not limited to this. For example, transistor 131 may be an NMOS transistor. In this case, an inverted internal clock signal / in1 may be applied to the gate terminal of transistor 131. In this specification, an NMOS transistor may be replaced by a PMOS transistor, and vice versa. However, in this case, the signal input to the gate terminal of the replaced transistor may be a signal with a phase opposite to the signal input to the gate terminal of the original transistor. Furthermore, the transistor of the inventive concept may be replaced by a switch that operates in response to a control signal being input to the gate terminal of the transistor.

[0068] When the internal clock signal in1 of the first level Lv1 is received, transistor 131 can output a first regulating current from the VDD supply terminal to transistor 133. When the internal clock signal in1 of the second level Lv2 is received, transistor 131 may not output the first regulating current from the VDD supply terminal to transistor 133.

[0069] Transistor 133 can be a PMOS transistor. A first terminal of transistor 133 can be connected to a second terminal of transistor 131, and its second terminal can be connected to node p0. Furthermore, a signal a0 can be applied to the gate terminal of transistor 133. Signal a0 can be a voltage signal output from node n3 to transistor 133. The voltage level of signal a0 can be equal to the voltage level of node n3. Transistor 133 can determine whether to output a first regulating current from transistor 131 to node p0 based on signal a0.

[0070] When receiving a signal a0 of the first level Lv1, transistor 133 can output a first regulating current to node p0. When receiving a signal a0 of the second level Lv2, transistor 133 may not output the first regulating current to node p0.

[0071] For example, as shown in time intervals 't1' to 't2', when the internal clock signal in1 of the first level Lv1 and the signal a0 of the first level Lv1 are applied to transistors 131 and 133 respectively, transistors 131 and 133 can output a first regulating current from the VDD supply terminal to node p0. When the first regulating current is output to node p0, the voltage level of node p0 can increase.

[0072] Transistor 134 can be an NMOS transistor. The first terminal of transistor 134 is connected to node n2, and its second terminal is connected to the first terminal of transistor 135. A signal as0 can be applied to the gate terminal of transistor 134. Signal as0 can be output from node p0 to transistor 134. The voltage level of signal as0 can be equal to the voltage level of node p0. Transistor 134 can determine whether to output a third regulating current from node n2 to transistor 135 based on signal as0.

[0073] When receiving the first-level Lv1 signal as0, transistor 134 may not output the third regulating current from node n2 to transistor 135. When receiving the second-level Lv2 signal as0, transistor 134 may output the third regulating current from node n2 to transistor 135.

[0074] Transistor 135 may be an NMOS transistor. The first terminal of transistor 135 is connected to the second terminal of transistor 134, and its second terminal is connected to ground. An inverted internal clock signal / in1 may be applied to the gate terminal of transistor 135. Transistor 135 may determine whether to output a third regulated current from transistor 134 to ground based on the inverted internal clock signal / in1.

[0075] When the transistor 135 receives the inverted internal clock signal / in1 of the first level Lv1, it may not output the third regulating current to the ground terminal. When the transistor 135 receives the inverted internal clock signal / in1 of the second level Lv2, it may output the third regulating current to the ground terminal.

[0076] As shown in time intervals 't2' to 't3', when the signal as0 of the second level Lv2 and the inverted internal clock signal / in1 of the second level Lv2 are applied to transistors 134 and 135 respectively, transistors 134 and 135 can output a third regulating current from node n2 to the ground terminal. When the third regulating current is output from node n2 to the ground terminal, the voltage level of node n2 can become lower than the second level Lv2, and the voltage level of node n3 can become higher than the first level Lv1. Therefore, transistor 133 can stop outputting the first regulating current to node p0.

[0077] For example, transistors 131 and 133 can output a first regulating current until the voltage level of node p0 increases to the second level Lv2, and can stop outputting the first regulating current when the voltage level of node p0 reaches the second level Lv2.

[0078] The second delay circuit 150 may include two inverters. The second delay circuit 150 can delay the internal clock signal in2. However, for the sake of convenience, it is assumed that the delay of the second delay circuit 150 does not exist.

[0079] The second switching circuit 160 can be a gate circuit composed of different transistors. One of the transistors can be a PMOS transistor, while the other can be an NMOS transistor. The second switching circuit 160 can provide essentially the same operation as the first switching circuit 120. Therefore, additional descriptions will be omitted to avoid redundancy.

[0080] As shown in time intervals 't0' to 't1', when the second level Lv2 internal clock signal in2 and the inverted internal clock signal / in2 of the first level Lv1 are received, the second switching circuit 160 cannot output current from node n5 to node n6. As shown in time intervals 't1' to 't2', when the first level Lv1 internal clock signal in2 and the inverted internal clock signal / in2 of the second level Lv2 are received, the second switching circuit 160 can output current from node n5 to node n6.

[0081] When node n5 is electrically connected to node n6, the voltage level of node n6 can be equal to the voltage level of node n5. However, when node n5 is electrically disconnected from node n6, the voltage level of node n6 may not be equal to the voltage level of node n5. In this case, the voltage level of node n6 can be determined by... Figure 2 The operation of the second pulse adjustment circuit 170 is determined.

[0082] The second pulse regulation circuit 170 may include transistors 171, 173, 174 and 175 and latch circuit 172.

[0083] Latch circuit 172 can invert the phase of the signal input to node n6. Latch circuit 172 can provide essentially the same operation as latch circuit 132.

[0084] Transistor 171 can be an NMOS transistor. A first terminal of transistor 171 can be connected to node p0, and a second terminal can be connected to the first terminal of transistor 173. Furthermore, a signal b0 can be applied to the gate terminal of transistor 171. Signal b0 can be a signal output from node n7 to the gate terminal of transistor 171. The voltage level of signal b0 can be equal to the voltage level of node n7. Transistor 171 can determine whether to output a second regulating current from node p0 to transistor 173 based on signal b0.

[0085] When receiving a signal b0 of the first level Lv1, transistor 171 may not output the second regulating current from node p0 to transistor 173. When receiving a signal b0 of the second level Lv2, transistor 171 may output the second regulating current from node p0 to transistor 173.

[0086] Transistor 173 can be an NMOS transistor. The first terminal of transistor 173 can be connected to the second terminal of transistor 171, and its second terminal can be connected to ground. Furthermore, an internal clock signal in2 can be applied to the gate terminal of transistor 173. Transistor 173 can determine whether to output a second regulated current from transistor 171 to ground based on the internal clock signal in2.

[0087] When the transistor 173 receives the internal clock signal in2 of the first level Lv1, it may not output the second regulating current to the ground terminal. When the transistor 173 receives the internal clock signal in2 of the second level Lv2, it may output the second regulating current to the ground terminal.

[0088] For example, as shown in time intervals 't4' to 't5', when the signal b0 of the second level Lv2 and the internal clock signal in2 of the second level Lv2 are applied to transistors 171 and 173 respectively, transistors 171 and 173 can output a second regulating current from node p0 to the ground terminal. When the second regulating current is output from node p0 to the ground terminal, the voltage level of node p0 decreases.

[0089] Transistor 174 can be a PMOS transistor. The first terminal of transistor 174 can be connected to the VDD supply terminal, and its second terminal can be connected to the first terminal of transistor 175. An inverted internal clock signal / in2 can be applied to the gate terminal of transistor 174. Transistor 174 can determine whether to output a fourth regulating current from the VDD supply terminal to transistor 175 based on the inverted internal clock signal / in2.

[0090] When the inverted internal clock signal / in2 of the first level Lv1 is received, transistor 174 can output the fourth regulating current from the VDD supply terminal to transistor 175. When the inverted internal clock signal / in2 of the second level Lv2 is received, transistor 174 cannot output the fourth regulating current from the VDD supply terminal to transistor 175.

[0091] Transistor 175 can be a PMOS transistor. The first terminal of transistor 175 can be connected to the second terminal of transistor 174, and its second terminal can be connected to node n6. A signal as0 can be applied to the gate terminal of transistor 175. Signal as0 can be output from node p0 to transistor 175. Transistor 175 can determine whether to output a fourth regulating current from transistor 174 to node n6 based on signal as0.

[0092] When receiving the first-level Lv1 signal as0, transistor 175 can output the fourth regulating current to node n6. When receiving the second-level Lv2 signal as0, transistor 175 may not output the fourth regulating current to node n6.

[0093] As shown in time intervals 't4' to 't5', when the inverted internal clock signal / in2 of the first level Lv1 and the signal as0 of the first level Lv1 are applied to transistors 174 and 175 respectively, transistors 174 and 175 can output a fourth regulating current from the VDD supply terminal to node n6. When the fourth regulating current is output from the VDD supply terminal to node n6, the voltage level of node n6 can become higher than the first level Lv1, and the voltage level of node n7 can become lower than the second level Lv2.

[0094] For example, transistors 171 and 173 can output a second regulating current until the voltage level of node p0 drops to the first level Lv1, and can stop outputting the second regulating current when the voltage level of node p0 reaches the first level Lv1.

[0095] Figure 5 It is used to describe according to the example embodiments Figure 3 The flowchart shows the operation of the compensation circuit.

[0096] Reference Figure 5 describe Figure 3 The compensation circuit 100 in Figure 4 The operations during the time period from 't1' to 't2'.

[0097] In operation S110, the compensation circuit 100 can receive the internal clock signal in1 of the first level Lv1.

[0098] In operation S120, when the internal clock signal in1 of the first level Lv1 is received, the first switching circuit 120 can electrically disconnect node n1 from node n2. In this case, the voltage level of node n2 can be maintained at the voltage level determined before time 't1'. The voltage level of node n3 can be maintained at the first level Lv1 by the latching circuit 132.

[0099] In operation S130, transistors 131 and 133 can respectively receive the internal clock signal in1 and the signal a0 of the first level Lv1. Based on the internal clock signal in1 and the signal a0, transistors 131 and 133 can output a first regulating current from the VDD supply terminal to node p0.

[0100] In operation S140, depending on whether the voltage level of node p0 reaches the second level Lv2, transistor 134 can determine whether to output a third regulating current from node n2 to transistor 135.

[0101] If the voltage level at node p0 does not reach the second level Lv2, operation S130 can be executed again. Furthermore, transistor 134 may not output the third regulating current from node n2 to transistor 135.

[0102] When the voltage level at node p0 reaches the second level Lv2, operation S150 can be executed. In operation S150, transistor 134 can output a third regulating current from node n2 to transistor 135. Transistor 135 can also output a third regulating current that is thus transferred to the ground terminal. Therefore, the voltage level at node n2 can be reduced.

[0103] In operation S160, when the voltage level of node n2 is lower than the second level Lv2, transistor 133 can stop outputting the first regulating current to node p0.

[0104] Figure 6 It is used to describe according to the example embodiments Figure 3 The flowchart shows the operation of the compensation circuit.

[0105] Reference Figure 6 describe Figure 3 The compensation circuit 100 in Figure 4 The operations during the time period from 't3' to 't4'.

[0106] In operation S210, the compensation circuit 100 can receive the internal clock signal in2 of the second level Lv2.

[0107] In operation S220, when the internal clock signal in2 at the second level Lv2 is received, the second switching circuit 160 can electrically disconnect nodes n5 and n6. In this case, the voltage level of node n6 can be maintained at the voltage level determined before time 't3'. The latching circuit 172 can maintain the voltage level of node n7 at the second level Lv2.

[0108] In operation S230, transistors 171 and 173 can respectively receive the internal clock signal in2 of the second level Lv2 and the signal b0 of the second level Lv2. Based on the internal clock signal in2 and the signal b0, transistors 171 and 173 can output a third regulating current from the ground terminal to node p0.

[0109] In operation S240, depending on whether the voltage level of node p0 reaches the first level Lv1, transistor 175 can determine whether to output the fourth regulating current from transistor 174 to node n6.

[0110] If the voltage level at node p0 does not reach the first level Lv1, operation S230 can be executed again. Furthermore, transistor 175 may not output the fourth regulating current from transistor 174 to node n6.

[0111] When the voltage level at node p0 reaches the first level Lv1, operation S250 can be executed. In operation S250, transistor 174 can output a fourth regulating current from the VDD supply terminal to transistor 175. Transistor 175 can output the fourth regulating current thus passed to node n6. Therefore, the voltage level at node n6 can be increased.

[0112] In operation S260, when the voltage level of node n6 is higher than the first level Lv1, transistor 171 can stop outputting the second regulating current from node p0.

[0113] Figure 7 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram of the operation of the compensation circuit. (Refer to...) Figure 7 describe Figure 3 The compensation circuit 100 in Figure 4 The operation occurs during the time period 't0' to 't1'. In the diagram below, the expression "in1 = 1" means that the voltage level of the internal clock signal in1 is the second level Lv2. Furthermore, the expression "in1 = 0" means that the voltage level of the internal clock signal in1 is the first level Lv1. The above expressions also apply to the remaining signals.

[0114] Because the internal clock signal in1 with a second level Lv2 is applied, the first switching circuit 120 can electrically connect nodes n1 and n2. Therefore, the voltage level of node n2 can be equal to the second level Lv2. Since the voltage level of node n2 is the second level Lv2, the voltage level of node n3 can be the first level Lv1.

[0115] When the internal clock signal in1 of the second level Lv2 is applied, transistor 131 may not output the first regulating current from the VDD supply terminal to transistor 133. Therefore, regardless of the voltage level of signal a0, the first regulating current will not be output to node p0.

[0116] Assuming the voltage at node p0 is the first level Lv1, transistor 134 can avoid outputting the third regulating current from node n2 to transistor 135. Therefore, it is possible to avoid outputting the third regulating current from node n2 to the ground terminal, regardless of the voltage level of the inverting internal clock signal / in1.

[0117] Because the internal clock signal in2 with a first level Lv1 is applied, the second switching circuit 160 can electrically connect nodes n5 and n6. Therefore, the voltage level of node n6 can be equal to the first level Lv1. Since the voltage level of node n6 is the first level Lv1, the voltage level of node n7 can be the second level Lv2.

[0118] When the internal clock signal in2 of the first level Lv1 is applied, transistor 173 may not output the second regulating current to the ground terminal. Therefore, the second regulating current may not be output from node p0 to the ground terminal, regardless of the voltage level of signal b0.

[0119] When the inverted internal clock signal / in2 of the second level Lv2 is applied, transistor 174 cannot output the fourth regulating current from the VDD supply terminal to transistor 175. Therefore, the fourth regulating current can be withheld from the VDD supply terminal to node n6 regardless of the voltage level of signal as0.

[0120] Since the first and third regulating currents are not output, the voltage level of node p0 can be maintained at the first level Lv1.

[0121] Figure 8 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram of the operation of the compensation circuit. (Refer to...) Figure 8 describe Figure 3 The compensation circuit 100 in Figure 4 The operations during the time period from 't1' to 't2'.

[0122] Because an internal clock signal in1 of level Lv1 is applied, the first switching circuit 120 can electrically disconnect nodes n1 from node n2. Therefore, the voltage level of node n2 can be maintained at level Lv2, regardless of the voltage level of node n1. Since the voltage level of node n2 is level Lv2, the voltage level of node n3 can be level Lv1.

[0123] When the internal clock signal in1 with the first level Lv1 is applied, transistor 131 can output a first regulating current from the VDD supply terminal to transistor 133. Furthermore, since the voltage level of node n3 is the first level Lv1, transistor 133 can also output the first regulating current thus passed to node p0.

[0124] Since the voltage at node p0 has not reached the second level Lv2, transistor 134 does not need to output the third regulating current from node n2 to transistor 135. Therefore, the third regulating current does not need to be output from node n2 to the ground terminal, regardless of the inverting internal clock signal / in1.

[0125] Since the voltage level of the internal clock signal in2 is equal to the voltage level during the time period 't0' to 't1', the operation of components 150, 160, and 171 to 175 can be compared with the reference. Figure 7 The operations described are the same. Therefore, it is not necessary to output the second and fourth regulating currents.

[0126] Since only the first regulating current is output and not the second regulating current, the voltage level of node p0 can be increased from the first level Lv1 to the second level Lv2.

[0127] Figure 9 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram of the operation of the compensation circuit. (Refer to...) Figure 9 describe Figure 3 The compensation circuit 100 in Figure 4 The operations during the time period from 't2' to 't3'.

[0128] Since the voltage level of the internal clock signal in1 is equal to the voltage level during the time period 't1' to 't2', the operation of components 110 and 120 can be synchronized with the reference. Figure 8 The operations described are the same. Therefore, the voltage level of node n2 may be independent of the voltage level of node n1.

[0129] Since the voltage at node p0 reaches the second level Lv2, transistor 134 can output the third regulating current from node n2 to transistor 135. Furthermore, due to the application of the inverted internal clock signal / in1 at the second level Lv2, transistor 135 can output the third regulating current thus delivered to the ground terminal. Therefore, the voltage level at node n2 can decrease from the second level Lv2 to the first level Lv1. As the voltage at node n2 changes, the voltage level at node n3 can increase from the first level Lv1 to the second level Lv2.

[0130] As the voltage level of node n3 increases to the second level Lv2, the amount of the first regulating current output to node p0 through transistor 133 can be reduced. Once the voltage level of node n3 changes to the second level Lv2, transistor 133 can stop outputting the first regulating current to node p0.

[0131] Since the voltage level of the internal clock signal in2 is equal to the voltage level during the time period 't0' to 't1', the operation of components 150, 160, and 171 to 174 can be compared with the reference. Figure 7 The operations described are the same. Transistor 175 can be disconnected at node p0 based on the second level Lv2. Therefore, the second and fourth regulating currents can be omitted.

[0132] For example, since the first and second regulating currents are not output from the time when the voltage level of node n3 changes to the second level Lv2, the voltage level of node p0 can be maintained at the second level Lv2 by the fixed circuit 140.

[0133] Figure 10 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram of the operation of the compensation circuit. (Refer to...) Figure 10 describe Figure 3 The compensation circuit 100 in Figure 4 The operations during the time period from 't3' to 't4'.

[0134] Since the voltage level of the internal clock signal in1 is equal to the voltage level during time intervals 't2' to 't3', the operation of components 110, 120, and 131 to 135 can be compared with the reference. Figure 9 The operations described are the same. Therefore, it is possible to output only the third regulating current instead of the first regulating current.

[0135] Because the internal clock signal in2 at the second level Lv2 is applied, the second switching circuit 160 can electrically disconnect nodes n5 and n6. Therefore, the voltage level of node n6 can be maintained at the first level Lv1, regardless of the voltage level of node n5. Since the voltage level of node n6 is the first level Lv1, the voltage level of node n7 can be the second level Lv2.

[0136] Since the voltage level at node n7 is the second level Lv2, transistor 171 can output the second regulating current from node p0 to transistor 173. Furthermore, due to the application of the internal clock signal in2 at the second level Lv2, transistor 173 can output the third regulating current transferred from transistor 171 to the ground terminal.

[0137] Since the voltage at node p0 has not reached the first level Lv1, transistor 175 does not need to output the fourth regulating current to node n6. Therefore, the fourth regulating current can be withheld from the VDD supply terminal to node n6, regardless of the voltage level of the internal clock signal in2.

[0138] Since only the second regulating current is output and not the first regulating current, the voltage at node p0 can be reduced from the second level Lv2 to the first level Lv1.

[0139] Figure 11 It is used to describe, according to the example embodiment, within a specific time period Figure 3 A block diagram of the operation of the compensation circuit. (Refer to...) Figure 11 describe Figure 3 The compensation circuit 100 in Figure 4 The operations during the time period from 't4' to 't5'.

[0140] Since the voltage level of the internal clock signal in1 is equal to the voltage level during the time period 't0' to 't1', the operation of components 110, 120, and 131 to 135 can be compared with the reference. Figure 7 The operations described are the same. Therefore, it is not necessary to output the first and third regulating currents.

[0141] Since the voltage level of the internal clock signal in2 is equal to the voltage level during the time period 't3' to 't4', the operation of components 150 and 160 can be synchronized with the reference. Figure 10 The operations described are the same. Therefore, the voltage level of node n6 may be independent of the voltage level of node n5.

[0142] When the inverted internal clock signal / in2 of the first level Lv1 is applied, transistor 174 can output a fourth regulating current from the VDD supply terminal to transistor 175. Furthermore, since the voltage level at node p0 is the first level Lv1, transistor 175 can output the fourth regulating current transferred from transistor 174 to node n6. Therefore, the voltage level at node n6 can increase from the first level Lv1 to the second level Lv2. As the voltage at node n6 changes, the voltage level at node n7 can decrease from the second level Lv2 back to the first level Lv1.

[0143] As the voltage level of node n7 decreases to the first level Lv1, the amount of the second regulating current output from node p0 through transistor 171 can be reduced. Once the voltage level of node n7 returns to the first level Lv1, transistor 171 can stop outputting the second regulating current from node p0.

[0144] For example, since the first regulating current and the second regulating current are not output from the time when the voltage level of node n7 changes to the first level Lv1, the voltage level of node p0 can be maintained at the first level Lv1 by the fixed circuit 140.

[0145] Figure 12 This illustrates an example embodiment. Figure 1 A block diagram of an embodiment of the compensation circuit.

[0146] Compensation circuit 100a corresponds to Figure 1 An embodiment of the compensation circuit 100. Components 210, 220, 250, and 260 can provide [something related to compensation circuit 100]. Figure 2 Components 110, 120, 150, and 160 operate essentially the same; therefore, additional descriptions will be omitted to avoid redundancy. (Refer to...) Figure 12 The description given will focus on components 230 and 270.

[0147] The first pulse regulation circuit 230 can output a fifth regulation current from the VDD supply terminal to node m2 based on the internal clock signal im1 and the voltage level of node m4. The voltage level of node m2 can vary depending on the fifth regulation current output to node m2.

[0148] The first pulse adjustment circuit 230 can operate in such a way that the voltage level of node m4 varies depending on the internal clock signal im1 and the voltage level of node m2. For example, the first pulse adjustment circuit 230 can be a feedback circuit that receives the voltage level of node m4 and adjusts the voltage level of node m4.

[0149] The first pulse regulation circuit 230 can output a fifth regulation current until the voltage level of node m4 reaches the second target level, and can stop outputting the fifth regulation current when the voltage level of node m4 reaches the second target level. When outputting the fifth regulation current, the second target level can be higher than the voltage level of node m4. (See reference...) Figure 3 and Figure 4 As described, the second target level can be the second level Lv2.

[0150] The second pulse regulation circuit 270 can output a sixth regulation current from the VDD supply terminal to node m7 based on the internal clock signal im2 and the voltage level of node m9. The voltage level of node m7 can vary depending on the sixth regulation current output to node m7.

[0151] The second pulse adjustment circuit 270 can operate in such a way that the voltage level of node m9 varies depending on the internal clock signal im2 and the voltage level of node m7. For example, the second pulse adjustment circuit 270 can be a feedback circuit that receives the voltage level of node m9 and adjusts the voltage level of node m9.

[0152] The second pulse regulation circuit 270 can output a sixth regulating current until the voltage level of node m9 reaches the second target level, and can stop outputting the sixth regulating current when the voltage level of node m9 reaches the second target level. When outputting the sixth regulating current, the first target level can be lower than the voltage level of node m9. (See reference...) Figure 3 and Figure 4 As described, the first target level can be the first level Lv1.

[0153] The fixed circuit 240 can be a set / reset (SR) latch circuit. However, the inventive concept is not limited thereto. For example, the fixed circuit 240 can be a circuit that controls the voltage levels of nodes q0 and q1 based on the voltage levels of nodes m4 and m9. The fixed circuit 240 can adjust the voltage levels of nodes q0 and q1 based on the voltage levels of nodes m4 and m9. Furthermore, the compensation circuit 100a can generate a data strobe signal DQS based on the voltage levels of nodes q0 and q1.

[0154] The compensation circuit 100a can feed back the voltage of node m4 to adjust the voltage level of node m4, and can also feed back the voltage of node m9 to adjust the voltage level of node m9. For example, when adjusting the voltage levels of nodes m4 and m9, the compensation circuit 100a can respond less sensitively to PVT changes. Therefore, when feeding back the voltages of nodes m4 and m9, the compensation circuit 100a can prevent pulse failure at the data strobe signal DQS.

[0155] Figure 13 This illustrates an example embodiment. Figure 12 A block diagram of an embodiment of the compensation circuit.

[0156] Components 210, 220, 250, and 260 can provide with Figure 3 Components 110, 120, 150, and 160 operate essentially the same; therefore, additional descriptions will be omitted to avoid redundancy. (Refer to...) Figure 12 The descriptions given will focus on components 231 to 234 and 271 to 274.

[0157] The delay-locked loop 1100 can output internal clock signals im1 and im2. There may be a phase difference between the internal clock signals im1 and im2.

[0158] The first delay circuit 210 can delay the internal clock signal im1. However, for the sake of convenience, it is assumed that the delay of the first delay circuit 210 does not exist.

[0159] The first switching circuit 220 can be a gate circuit composed of different transistors. One of the transistors can be a PMOS transistor, and the other can be an NMOS transistor. The PMOS transistor can determine whether to output current from node m1 to node m2 based on an internal clock signal im1 applied to its gate terminal. The NMOS transistor can determine whether to output current from node m1 to node m2 based on an inverted internal clock signal / im1 applied to its gate terminal.

[0160] When node m1 is electrically connected to node m2, the voltage level of node m2 can be equal to the voltage level of node m1. However, when node m1 is electrically disconnected from node m2, the voltage level of node m2 may not be equal to the voltage level of node m1. In this case, the voltage level of node m2 can be determined by... Figure 12 The operation of the first pulse adjustment circuit 230 is determined.

[0161] The first pulse adjustment circuit 230 may include transistors 231 and 232, a latch circuit 233, and a logic gate 234.

[0162] The latch circuit 233 can operate in such a way that when the voltage level of node m2 is the first level Lv1, the voltage level of node m3 is the second level Lv2. Furthermore, the latch circuit 233 can operate in such a way that when the voltage level of node m2 is the second level Lv2, the voltage level of node m3 is the first level Lv1.

[0163] Transistor 231 can be a PMOS transistor. The first terminal of transistor 231 can be connected to the VDD supply terminal, and its second terminal can be connected to the first terminal of transistor 232. An inverted internal clock signal / im1 can be applied to the gate terminal of transistor 231. Transistor 231 can determine whether to output a fifth regulating current from the VDD supply terminal to transistor 232 based on the inverted internal clock signal / im1.

[0164] Transistor 232 can be a PMOS transistor. The first terminal of transistor 232 can be connected to the second terminal of transistor 231, and its second terminal can be connected to node m2. Furthermore, signal as1 can be applied to the gate terminal of transistor 232. Signal as1 can be a voltage signal output from node m4 to transistor 232. The voltage level of signal as1 can be equal to the voltage level of node m4. Transistor 232 can determine whether to output a fifth regulating current from transistor 231 to node m2 based on signal as1.

[0165] Logic gate 234 can perform logical operations on the voltage level of node m3 and the voltage level of the internal clock signal im1, and can adjust the voltage level of node m4. In the following description, it is assumed that logic gate 234 is a NAND gate, but the inventive concept is not limited thereto. For example, logic gate 234 can be a NOR gate. When both the voltage level of node m3 and the voltage level of the internal clock signal im1 are at the second level Lv2, logic gate 234 can adjust the voltage level of node m4 to the first level Lv1. When at least one of the voltage level of node m3 and the voltage level of the internal clock signal im1 is at the first level Lv1, logic gate 234 can adjust the voltage level of node m4 to the second level Lv2.

[0166] For example, transistors 231 and 232 can determine whether to output the fifth regulating current based on the voltage level of node m4 and the voltage level of the inverted internal clock signal / im1. When the fifth regulating current is output to node m2 through transistors 231 and 232, the voltage level of node m2 can change. As the voltage level of node m2 changes, the voltage level of node m4 can also change.

[0167] Components 250, 260 and 271 to 274 can provide substantially the same operation as components 210, 220 and 231 to 234, therefore, additional descriptions will be omitted to avoid redundancy.

[0168] Figure 14 It is used to describe according to the example embodiments Figure 13 Timing diagram of the operation of the compensation circuit.

[0169] During the time period from 't0' to 't1', the internal clock signal im1 of the first level Lv1 and the internal clock signal im2 of the second level Lv2 can be received.

[0170] Since the internal clock signal im1 with a first level Lv1 is applied, the first switching circuit 220 can electrically connect nodes m1 and m2. Therefore, the voltage level of node m2 and the voltage level of node m3 can be the first level Lv1 and the second level Lv2, respectively.

[0171] Since the voltage level of the internal clock signal im1 is the first level Lv1, and is independent of the voltage level of node m3, logic gate 234 can output the voltage level of node m4, which has the second level Lv2. Because the voltage level of node m4 is the second level Lv2, transistor 232 does not need to output the fifth regulating current to node m2.

[0172] Since the voltage level of the internal clock signal im2 is equal to the second level Lv2, the second switching circuit 260 can electrically disconnect nodes m6 and m7. Therefore, the voltage levels of nodes m7, m8, and m9 can be maintained at their previous voltage levels.

[0173] Since the voltage levels of both node m4 and node m9 are at the second level Lv2, when the voltage level of node q1, which has the second level Lv2, is output, the fixed circuit 240 can output the voltage level of node q0, which has the first level Lv1. Alternatively, when the voltage level of node q1, which has the first level Lv1, is output, the fixed circuit 240 can output the voltage level of node q0, which has the second level Lv2.

[0174] During the time period 't1' to 't2', the internal clock signal im1 of the second level Lv2 and the internal clock signal im2 of the first level Lv1 can be received.

[0175] Since the internal clock signal im1 of the second level Lv2 is applied to the first switching circuit 220, the first switching circuit 220 can electrically disconnect node m1 from node m2. Therefore, the voltage level of node m2 can be changed by the fifth regulating current output from transistor 232.

[0176] When node m1 is electrically disconnected from node m2, since the voltage level of node m3 is the second level Lv2 and the voltage level of the internal clock signal im1 is the second level Lv2, logic gate 234 can adjust the voltage level of node m4 to the first level Lv1.

[0177] Since the voltage level of node m4 and the voltage level of the inverting internal clock signal / im1 are both at the first level Lv1, transistors 231 and 232 can output a fifth regulating current to node m2. Therefore, the voltage level of node m2 can be increased to the second level Lv2. As the voltage of node m2 increases, the voltage level of node m3 can decrease to the first level Lv1.

[0178] Since the voltage level of node m2 reaches the second level Lv2, logic gate 234 can adjust the voltage level of node m4 to the second level Lv2.

[0179] Since the internal clock signal im2 of the first level Lv1 is applied during the time period 't1' to 't2', components 250, 260, and 271 to 274 can operate identically to components 210, 220, and 231 to 234 as described during the reference time period 't0' to 't1'. Therefore, the voltage level of node m9 can be maintained at the second level Lv2.

[0180] Since the voltage level of node m4 is the first level Lv1 and the voltage level of node m9 is the second level Lv2, the fixed circuit 240 can output the voltage level of node q0 with the second level Lv2.

[0181] During the time period 't2' to 't3', the internal clock signal im1 of the second level Lv2 and the internal clock signal im2 of the first level Lv1 can be received.

[0182] Because the internal clock signal im1 of the second level Lv2 is continuously applied during the time period 't2' to 't3', components 210, 220, and 231 to 234 can maintain operation during time 't2'. Therefore, the voltage level of node m4 can be maintained at the second level Lv2.

[0183] Since the internal clock signal im2 of the first level Lv1 is continuously applied during the time period 't1' to 't2', components 250, 260, and 271 to 274 can operate as described in the reference time period 't1' to 't2'. Therefore, the voltage level of node m9 can be maintained at the second level Lv2.

[0184] Since the voltage level of node m4 is the second level Lv2, and the voltage level of node m9 is the second level Lv2, the fixed circuit 240 can output the voltage level of node q0 with the second level Lv2.

[0185] During the time period 't3' to 't4', the internal clock signal im1 of the second level Lv2 and the internal clock signal im2 of the first level Lv1 can be received.

[0186] Because the internal clock signal im1 of the second level Lv2 is continuously applied during the time period 't3' to 't4', components 210, 220, and 231 to 234 can maintain operation during time 't2'. Therefore, the voltage level of node m4 can be maintained at the second level Lv2.

[0187] Since the internal clock signal im2 of the first level Lv1 is received during the time period 't3' to 't4', components 250, 260, and 271 to 274 can maintain operation during time 't2'. Therefore, the voltage level of node m9 can be maintained at the second level Lv2.

[0188] Since the voltage level of node m4 is the second level Lv2, and the voltage level of node m9 is the second level Lv2, the fixed circuit 240 can output the voltage level of node q0 with the second level Lv2.

[0189] During the time period 't4' to 't5', the internal clock signal im1 of the first level Lv1 and the internal clock signal im2 of the second level Lv2 can be received.

[0190] Since the internal clock signal im1 of the first level Lv1 is applied during the time period 't4' to 't5', components 210, 220, and 231 to 234 can operate in the same way as during the time period 't0' to 't1'. Therefore, the voltage level of node m4 can be maintained at the second level Lv2.

[0191] Since the internal clock signal im2 of the second level Lv2 is received during time periods 't3' to 't4', components 250, 260, and 271 to 274 can operate in the same way as components 210, 220, and 231 to 234 during time periods 't1' to 't2'. Therefore, the voltage level of node m9 can be the first level Lv1.

[0192] Since the voltage level of node m4 is the second level Lv2 and the voltage level of node m9 is the first level Lv1, the fixed circuit 240 can output the voltage level of node q0, which has the first level Lv1.

[0193] For example, the compensation circuit 100a can adjust the voltage levels of nodes m4 and m9 based on the feedback voltage levels of nodes m4 and m9 as described above.

[0194] Figure 15 It is used to describe according to the example embodiments Figure 13 The flowchart shows the operation of the compensation circuit.

[0195] Reference Figure 15 describe Figure 13 The compensation circuit 100a in Figure 14 The operations during the time period 't1' to 't2'. (Refer to...) Figure 15 This section primarily describes the operation of components 220 and 231 through 235. (Refer to...) Figure 15 The described operations may correspond to the operations of components 220 and 231 to 235 in the time period 't3' to 't4'.

[0196] In operation S310, the compensation circuit 100a can receive the internal clock signal im1 of the second level Lv2.

[0197] In operation S320, when the internal clock signal im1 of the second level Lv2 is received, the first switching circuit 220 can electrically disconnect node m1 from node m2. In this case, the voltage level of node m2 may be independent of the voltage level of node m1.

[0198] Since the voltage level of node m4 is the first level Lv1, in operation S330, transistor 232 can output the fifth regulating current to node m2.

[0199] In operation S340, depending on whether the voltage level of node m4 is the second level Lv2, transistor 232 can determine whether to output the fifth regulating current to node m2.

[0200] If the voltage level of node m4 does not reach the second level Lv2, operation S330 can be executed again.

[0201] When the voltage level at node m4 reaches the second level Lv2, operation S350 can be executed. In operation S350, transistor 232 can stop outputting the fifth regulating current to node m2.

[0202] The compensation circuit of the embodiment of the present invention can prevent the duty cycle of the data strobe signal DQS from changing drastically due to PVT variations or from pulse failure. Therefore, the memory device of the present invention can output the data signal DQ to the memory controller without delay. For example, the reliability of the input / output data of the memory device can be maintained.

[0203] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A clock compensation circuit, comprising: A first switching circuit is configured to determine whether to electrically connect the first node to the second node based on a first clock signal; The first pulse adjustment circuit is connected to the first output node and configured as follows: When the second node is electrically disconnected from the first node, a first regulating current is output based on the voltage level of the first output node, and In response to the first clock signal, the first regulating current is blocked; The second switching circuit is configured to determine whether to electrically connect the third node to the fourth node based on a second clock signal that is different from the first clock signal. as well as The second pulse adjustment circuit is connected to the second output node and configured as follows: When the fourth node is electrically disconnected from the third node, a second regulating current is output based on the voltage level of the second output node, and In response to the second clock signal, the second regulating current is blocked. The first pulse adjustment circuit and the second pulse adjustment circuit are respectively configured to feed back the voltage of the first output node and the voltage of the second output node to adjust the voltage level of the second node and the voltage level of the fourth node.

2. The clock compensation circuit according to claim 1 further includes: A latching circuit, connected to the first output node and the second output node, is configured to output an output signal based on the voltage level of the first output node and the voltage level of the second output node. The clock compensation circuit is configured to generate a compensated clock signal based on the output signal from the latch circuit.

3. The clock compensation circuit according to claim 1, in, The first switching circuit includes a transmission gate placed between the first node and the second node, and The second switching circuit includes a transmission gate placed between the third and fourth nodes.

4. The clock compensation circuit according to claim 1, in, First switching circuit: When the voltage level of the first clock signal is the first level, the first node is electrically disconnected from the second node, and When the voltage level of the first clock signal is the second level, the first node is electrically connected to the second node, and The first level is different from the second level.

5. The clock compensation circuit according to claim 1, in, The first pulse adjustment circuit includes a first transistor and a second transistor. Wherein, the first transistor and the second transistor: When the second node is electrically disconnected from the first node and the voltage level of the second node is the first level, a third regulating current is output to the first output node, and When the voltage level of the second node is lower than the first level, the third regulating current is blocked, and Specifically, when the voltage level of the first output node reaches the first level, the first pulse adjustment circuit adjusts the voltage level of the second node to the second level.

6. The clock compensation circuit according to claim 5, in, The first pulse adjustment circuit also includes a latch circuit placed between the second node and the fifth node. The first transistor is a PMOS transistor located between the power supply terminal and the second transistor and receiving the first clock signal. The second transistor is a PMOS transistor located between the first transistor and the first output node and receiving voltage signals from the fifth node.

7. The clock compensation circuit according to claim 5, in, The first pulse conditioning circuit also includes a third transistor and a fourth transistor, and Among them, the third transistor and the fourth transistor: When the second node is electrically disconnected from the first node and the voltage level of the first output node is the first level, a first regulating current is output from the second node to the ground terminal, and When the voltage level of the first output node is the second level, the first regulating current is blocked.

8. The clock compensation circuit according to claim 7, in, The third transistor is an NMOS transistor positioned between the second and fourth transistors and receiving a voltage signal from the first output node. The fourth transistor is an NMOS transistor located between the third transistor and the ground terminal and receiving the inverted first clock signal.

9. The clock compensation circuit according to claim 1, in, The second pulse regulation circuit includes a first transistor and a second transistor. Wherein, the first transistor and the second transistor: When the fourth node is electrically disconnected from the third node and the voltage level of the fourth node is the second level, a third regulating current is output from the second output node to the ground terminal, and When the voltage level of the fourth node is higher than the first level of the second level, the third regulating current is blocked. Specifically, when the voltage level of the second output node reaches the second level, the second pulse adjustment circuit adjusts the voltage level of the fourth node to the first level, and The first output node and the second output node are the same node.

10. The clock compensation circuit according to claim 9, in, The second pulse adjustment circuit also includes a latch circuit located between the fourth and sixth nodes. The first transistor is an NMOS transistor located between the second output node and the second transistor, and receiving a voltage signal from the sixth node. The second transistor is an NMOS transistor placed between the first transistor and the ground terminal and receiving the second clock signal.

11. The clock compensation circuit according to claim 10, in, The second pulse conditioning circuit also includes a third transistor and a fourth transistor, and Among them, the third transistor and the fourth transistor: When the fourth node is electrically disconnected from the third node and the voltage level of the second output node is the second level, a second regulating current is output to the fourth node, and When the voltage level of the second output node is the first level, the second regulating current is blocked.

12. The clock compensation circuit according to claim 11, in, The third transistor is a PMOS transistor positioned between the power supply terminal and the fourth transistor, receiving an inverted second clock signal. The fourth transistor is a PMOS transistor located between the third transistor and the fourth node and receiving voltage from the second output node.

13. A memory device, comprising: The delay-locked loop (DLL) is configured to output a first clock signal and a second clock signal different from the first clock signal. The clock compensation circuit is connected to the output node and configured as follows: The voltage level of the output node is adjusted based on the first clock signal and the second clock signal. An internal clock signal is generated based on the voltage level of the output node; as well as The data input / output (I / O) circuitry is configured to output data to an external memory device based on an internal clock signal. The clock compensation circuit includes: A first pulse regulation circuit, connected to a first output node, is configured to determine whether to output a first regulation current based on a first clock signal and the voltage level of the first output node. The second pulse regulation circuit is connected to the second output node and is configured to determine whether to output the second regulation current based on the second clock signal and the voltage level of the second output node.

14. The memory device according to claim 13, in, Based on the first clock signal, the first pulse regulation circuit outputs a first regulation current from the first node to the ground terminal when the voltage level of the first output node is a first level, and blocks the first regulation current in response to the first clock signal. Specifically, based on the second clock signal, the second pulse regulation circuit outputs a second regulation current from the power supply terminal to the second node when the voltage level of the second output node is a second level different from the first level, and blocks the second regulation current in response to the second clock signal. The first output node and the second output node are the same node.

15. The memory device according to claim 13, in, Based on the first clock signal, the first pulse regulation circuit outputs a first regulation current from the power supply terminal to the first node when the voltage level of the first output node is the second level, and blocks the first regulation current in response to the first clock signal. Specifically, based on the second clock signal, the second pulse adjustment circuit outputs a second adjustment current when the voltage level of the second output node is at the second level, and blocks the second adjustment current in response to the second clock signal. The first output node is different from the second output node.

16. A clock compensation circuit, comprising: A first switching circuit is configured to determine whether to electrically connect the first node to the second node based on a first clock signal; The first pulse adjustment circuit is configured as follows: Based on the voltage level of the first clock signal and the voltage level of the second node, a first regulating current is output to regulate the voltage level of the first output node, and When the first node is electrically disconnected from the second node, the voltage of the first output node is fed back to adjust the voltage level of the second node; The second switching circuit is configured to determine whether to electrically connect the third node to the fourth node based on a second clock signal that is different from the first clock signal. as well as The second pulse adjustment circuit is configured as follows: A second regulating current is output based on the voltage level of the second clock signal and the voltage level of the fourth node to regulate the voltage level of the second output node. When the third node is electrically disconnected from the fourth node, the voltage of the second output node is fed back to adjust the voltage level of the fourth node.

17. The clock compensation circuit according to claim 16, further comprising: A latching circuit, connected to the first output node and the second output node, is configured to output an output signal based on the voltage level of the first output node and the voltage level of the second output node. The clock compensation circuit is configured to generate a compensated clock signal for sending data to an external device based on the output signal from the latch circuit.

18. The clock compensation circuit according to claim 17, wherein, The first pulse adjustment circuit includes: Logic gates are configured to perform logical operations on the voltage levels of a first clock signal and a second node; and A transistor is configured to output a first regulated current to a second node depending on the voltage level of the first output node.

19. The clock compensation circuit according to claim 18, wherein, The logic gate is a NAND gate placed between the second node and the first output node.

20. The clock compensation circuit according to claim 18, wherein, The transistor is a PMOS transistor located between the power supply terminal and the second node and receiving a voltage signal from the first output node.

Images