Memory array with access line control

Abstract

The present application is directed to a memory array with access line control. An exemplary device includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source / drain region, a second source / drain region, and a gate opposite to a channel connecting the first source / drain region and the second source / drain region. Each access device also includes a storage node. The exemplary device also includes a plurality of sense lines coupled to the first source / drain regions of different corresponding memory cells in the memory cell array. The exemplary device also includes a plurality of access lines, wherein each access line includes at least one conductive path formed between the access line and a source / drain region of an access device coupled to the access line. The exemplary device also includes a shunt sense line coupled to an additional access device formed with the conductive path.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods, and more particularly to a memory array with access line control. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), and flash memory, among others. Some types of memory devices may be non-volatile memory (e.g., ReRAM) and may be used in various electronic applications requiring high memory density, high reliability, and low power consumption. Compared to non-volatile memory cells (e.g., flash memory cells) that retain their storage state when power is off, volatile memory cells (e.g., DRAM cells) require power to maintain their stored data state (e.g., via a refresh process). However, various volatile memory cells such as DRAM cells can be operated (e.g., programmed, read, erased, etc.) faster than various non-volatile memory cells such as flash memory cells. Summary of the invention

[0003] In one aspect, the present application is directed to a device 101, comprising: a memory cell array 200, 311, 442, 770, each memory cell comprising: an access device 113, 213, 313, 413, wherein the access device 113, 213, 313, 413 comprises a first source / drain region 108, a second source / drain region 109, and a gate opposite to a channel 103 connecting the first source / drain region 108 and the second source / drain region 109; and a storage node 114; a plurality of sense lines 104, 204, 304, 404, each coupled to a first electrode of a different corresponding memory cell in the memory cell array 200, 311, 442, 770; a source / drain region 108; a plurality of access lines 122, 222, 322, 422, wherein each access line 122, 222, 322, 422 comprises at least one conductive path 205, 305, 405 formed between the access line 122, 222, 322, 422 and a source / drain region 108, 109 of an additional access device 113, 213, 313, 413 coupled to the access line 122, 222, 322, 422; and a shunt sensing line 210, 310, 410 coupled to the additional access device 113, 213, 313, 413 formed with the conductive path 205, 305, 405.

[0004] On the other hand, the present application is directed to a method comprising: coupling a vertical thin film transistor TFT to a shunt sensing line 210, 310, 410 at the intersection of the shunt sensing line 210, 310, 410 and the access line 122, 222, 322, 422; providing current to the shunt sensing line 210, 310, 410; and disconnecting the access line 122, 222, 322, 422 by applying a low logic voltage 546 across the shunt sensing line 210, 310, 410 when providing current to the shunt sensing line 210, 310, 410 to reduce a voltage 548 across the access line 122, 222, 322, 422.

[0005] In another aspect, the present application is directed to a device 101 comprising: a sense line 104, 204, 304, 404; an access line 122, 222, 322, 422, the access line being orthogonally coupled to the sense line 104, 204, 304, 404; and a vertical thin film transistor (TFT) 113, 213, 313, 413, the vertical thin film transistor being coupled to the sense line 104, 204, 304, 404 at a point where the sense line 104, 204, 304, 404 crosses the access line 122, 222, 322, 422, wherein the vertical TFT 113 , 213 , 313 , 413 are coupled to conductive paths 205 , 305 , 405 formed between access lines 122 , 222 , 322 , 422 and source / drain regions 108 , 109 of the vertical TFTs 113 , 213 , 313 , 413 . BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An exemplary cross-sectional view of a memory cell of a device according to various embodiments of the present disclosure is shown.

[0007] Figure 2 Exemplary cross-sectional views of a memory array with access line control according to various embodiments of the present disclosure are shown.

[0008] Figure 3 An exemplary top view of a memory array with access line control according to various embodiments of the present disclosure is shown.

[0009] Figure 4 Another exemplary top view of a memory array with access line control according to various embodiments of the present disclosure is shown.

[0010] Figure 5 is an exemplary timing diagram for disconnecting an access line according to various embodiments of the present disclosure.

[0011] Figure 6 is a flow chart of an exemplary method of operating a memory array with access line control according to various embodiments of the present disclosure.

[0012] Figure 7 is a functional block diagram of a computing system including at least one memory array with access line control according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Various types of memory devices are disclosed, the memory devices including arrays of volatile and / or nonvolatile memory cells (e.g., memory arrays) wherein access devices are formed at the intersection of access lines and sense lines. The access devices on the sense lines may be short-circuited to form diodes that may reduce the precharge response time of the access lines. As used herein, the term "short circuit" may refer to forming a low resistance path for current to allow it to flow to another point in the circuit. As design rules shrink and aspect ratios increase, there is less space available to add semiconductor structures to memory arrays. Therefore, a configuration for reducing the precharge response time of access lines without adding drivers to the memory array may be beneficial. In addition, reducing the precharge response time of access lines may allow the access lines to be disconnected faster. Faster disconnection of access lines may improve the performance of memory cells. Exemplary embodiments herein disclose a configuration for reducing the precharge response time of access lines without adding additional drivers.

[0014] Reducing the precharge response time of an access line according to an embodiment of the present disclosure may include coupling a shunt sense line to the access line. As used herein, the term "shunt sense line" may refer to a sense line that is not coupled to a memory cell. For example, a conductive path may be formed on the shunt sense line, between the access line and a source / drain region of an access device coupled to the shunt sense line. This may allow the voltage across the access line to be pulled down based on (e.g., utilizing) the voltage across the shunt sense line. Pulling down the voltage across the access line using the voltage across the shunt sense line may allow the access line to be disconnected more quickly than if the shunt sense line were not coupled to the access line.

[0015] Shorting the access device on the shunt sense line can form a diode and allow the shunt sense line to pull the voltage across the access line down to the voltage level of the shunt sense line. For example, a metal oxide semiconductor (MOS) diode can connect the access line and the shunt sense line. When the MOS diode is turned off, the current of the access line may not affect the voltage across the shunt sense line. However, when the MOS diode is closed, the current of the access line can be provided to the shunt sense line. This can reduce the voltage across the access line and disconnect the access line.

[0016] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part of the present disclosure and in which are shown by way of illustration how one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it should be understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure. As used herein, "plurality" may sometimes refer to one or more such things. For example, a plurality of column lines may refer to at least one column.

[0017] Figure 1A cross-sectional view of a memory cell of device 101 is shown having a storage node 114, transistor 113 (also referred to as an access device), access lines 122-1, 122-2 (individually or collectively referred to as access line 122), and sense line 104. In some embodiments, device 101 may be a three-dimensional (3D) DRAM memory cell. In some embodiments, transistor 113 may be a vertical thin film transistor (TFT) used as an access device for the memory cell.

[0018] Transistor 113 may be an n-channel or p-channel transistor. Transistor 113 may include source / drain regions 108, 109 and channel 103. Transistor 113 may be configured to electrically couple a plurality of semiconductor structures. For example, transistor 113 may be configured to couple storage node 114 and sense line 104. In some embodiments, source / drain region 108 may be coupled to sense line 104, and source / drain region 109 may be coupled to storage node 114.

[0019] In some embodiments, storage node 114 may be a capacitor. For example, storage node 114 may include two electrical conductors (e.g., electrical plates) separated by a dielectric material and a ground plane. For ease of illustration, the two electrical conductors, the dielectric material, and the ground plane are not shown in the figure. In some embodiments, coupling transistor 113 to storage node 114 may form a one transistor one capacitor (1T1C) memory cell.

[0020] Access line 122 may also be referred to as a select line or a word line. Dielectric materials 112-1, 112-2 (individually or collectively referred to as dielectric material 112) may separate transistor 113 and access line 122. In some embodiments, dielectric materials 112-1, 112-2 may be the same dielectric material. In some embodiments, dielectric materials 112-1, 112-2 may be different dielectric materials. In some embodiments, apparatus and methods for reducing the formation of air gaps above access line 122 may occur in any area of ​​a memory device that is conducive to reducing unintended communication between adjacent wires. Access line 122 may extend perpendicular to the plane of the drawing, for example, off the page. In addition, access line 122 may extend orthogonal to sense line 104. In Figure 1 In the exemplary illustration of FIG. 1 , the sensing lines 104 are shown to be actually recessed into the page parallel to the plane of the drawing.

[0021] Figure 2An exemplary cross-sectional view of a memory array 200 with access line control according to various embodiments of the present disclosure is shown. The memory array 200 may include a capacitor plate 202 coupled to a plurality of capacitors 204. Each respective capacitor in the plurality of capacitors 204 may be coupled to a different respective access line 222. A driver may provide a voltage across the access line 222. In some embodiments, the driver may provide a high logic voltage to the access line 222.

[0022] As used herein, the term "high" logic voltage may refer to a voltage corresponding to a particular (e.g., high) logic level. A logic level is a state that a digital signal can have. Logic levels refer to binary logic, where a logic level can be either a logic 1 (high state) or a logic 0 (low state). In some circuits, a high logic voltage may be five volts (V), while a low logic voltage may be ground voltage.

[0023] Each corresponding access line 222 may be coupled to a different corresponding sense line 204. In some embodiments, one of the sense lines may be a shunt sense line 210. The shunt sense line 210 may not be coupled to any of the plurality of capacitors 214. Instead, a conductive path 205 may be formed between the access line 222 and a source / drain region of an access device (e.g., a vertical TFT) 213 coupled to the access line 222, and the shunt sense line 210 may be coupled to the access device 213 in which the conductive path 205 is formed. The conductive path 205 may be formed by coupling a contact 207 to the access device 213 using a connector 206. In some embodiments, both the connector 206 and the contact 207 may be formed of a metal material. This may allow the voltage across the access line 222 to be affected by the current provided to the shunt sense line 210. In some embodiments, the shunt sense line 210 may have a low logic voltage applied thereto. As used herein, a "low" logic voltage may refer to a voltage corresponding to a logic level 0. In some embodiments, the low logic voltage may be a ground voltage. In some embodiments, the ground voltage may be less than zero volts (V). The voltage across the shunt sense line 210 may pull down the voltage across the access line 222. Pulling down the voltage across the access line 222 may cause the voltage across the access line 222 to match the voltage across the shunt sense line 210. This may disconnect the access line 222 more quickly than if the shunt sense line 210 did not pull down the voltage across the access line 222. If the access line 222 is not disconnected due to the use of the shunt sense line 210 to pull down its voltage, the access line may be disconnected when the driver provides a low logic voltage across the access line 222.

[0024] exist Figure 2In the example shown, the shunt sensing line 210 is formed at the end of each corresponding access line 222. However, the embodiment is not limited thereto. For example, in some embodiments, the shunt sensing line 210 may be formed in the middle of each corresponding access line 222 (eg, between other sensing lines 210).

[0025] In some embodiments, a high voltage may be provided across the shunt sense line 210. In some embodiments, the high voltage provided across the shunt sense line 210 may be less than the high voltage provided across the access line 222. For example, the high logic voltage provided across the shunt sense line 210 may be a threshold voltage (e.g., the high voltage minus the threshold voltage) that is lower than the high logic voltage. The threshold voltage may be lower than the voltage across the access line 222. The threshold voltage may be the minimum amount of voltage that may be applied to a transistor to cause conduction between the source terminal and the drain terminal of the transistor. Maintaining the voltage of the shunt sense line 210 at a threshold voltage lower than the voltage of the working access line 222 may keep the access device 213 disconnected and reduce leakage between the access line 222 and the sense line 204. Applying a voltage that is a threshold voltage that is less than the high logic voltage may result in less leakage of the access line 222, faster disconnection operation of the access line 222, and lower voltage for better reliability than applying a high logic voltage to the shunt sense line 210.

[0026] The shunt sense line 210 may be provided with a high logic voltage so that its voltage is not pulled up by the access line 222. If no voltage is provided to the shunt sense line 210, the voltage across the shunt sense line 210 may be pulled up by the access line 222. If the voltage across the shunt sense line 210 is pulled up by the access line 222, the shunt sense line 210 may experience parasitic capacitance. Due to the time required for the voltage across the shunt sense line 210 to decrease from the pull-up voltage to the low logic voltage, the time required for the shunt sense line 210 to pull down the voltage across the access line 222 may be increased. Providing a threshold voltage across the shunt sense line 210 may reduce (e.g., prevent) the access line 222 from pulling up the voltage across the shunt sense line 210 and reduce the precharge response time compared to the case where the access line 222 is allowed to pull up the voltage across the shunt sense line 210. Since the voltage across the shunt sense line 210 may be less than the voltage across the access line 222, the time required for the voltage to decrease to the low voltage is less than the time required for the high voltage to decrease to the low voltage. When a voltage as a threshold voltage lower than the high voltage is applied to the shunt sense line 210, this may cause the shunt sense line 210 to pull down the voltage across the access line 222 faster than when the access line 222 pulls up the voltage across the shunt sense line 210. Therefore, applying a voltage as a threshold voltage lower than the high voltage across the shunt sense line 210 may allow the access line 222 to be disconnected faster than when the voltage across the shunt sense line 210 is pulled up by the access line 222.

[0027] Figure 3 An exemplary top view of a memory array 311 with access line control according to various embodiments of the present disclosure is shown. The memory array 311 includes a working access line 322-1 and an idle access line 322-2 (individually or collectively referred to as access line 322) connected to a shunt sense line 310 and a sense line 318. Access devices 313-1 and 313-2 (collectively or individually referred to as access devices 313) may be formed at the intersection of the shunt sense line 310 and the access line 322. An access line driver 332 coupled to the access line 322 at the end of each respective access line may provide a voltage across the access line 322. In some embodiments, the access line driver 332 may provide a high voltage across the working access line 322-1 to turn on the working access line 322-1. As used herein, the term "working" access line may refer to an access line that receives a high voltage. As used herein, the term "idle" access line may refer to an access line that does not receive a high voltage.

[0028] The shunt sense line 310 may be coupled to more than one access line 322. Figure 3 As shown, shunt sense line 310 may be coupled to working access line 322-1 and idle access line 322-2. In some embodiments, access device 313 may be coupled to shunt sense line 310 at each intersection of shunt sense line 310 and access line 322. Access devices 313-1 and 313-2 (individually or collectively referred to as access devices 313) may include conductive paths 305-1 and 305-2 (collectively or individually referred to as conductive paths 305) formed by shorting access line 322 to source / drain regions of access devices 313. Forming conductive paths 305 may form a diode (e.g., causing access device 313 to function as a diode).

[0029] The behavior of the access device 313 may vary depending on whether the access device 313 is coupled to the shunt sense line 310 at the intersection of the shunt sense line 310 and the working access line 322-1 or at the intersection of the shunt sense line 310 and the idle access line 322-2. For example, if the access device 313-2 is coupled to the shunt sense line 310 that intersects the idle access line 322-2, the access device 313-2 may act as a reverse biased diode and prevent current from flowing through the access device 313-2. However, if the access device 313-1 is coupled to the shunt sense line 310 that intersects the working access line 322-1, the access device 313-1 may act as a forward biased diode and allow current to flow. This may also pre-charge the working access line 322-1. As used herein, the term "pre-charge" may refer to the process of limiting the amount of current that will flow from the power supply to the capacitive component during the initial activation of the circuit. This can protect circuit components from experiencing stress caused by receiving a higher current level than the components are configured to receive during initial activation of the circuit. Allowing current to flow from the working access line 322-1 to the shunt sense line 310 can allow the shunt sense line 310 to pull down the voltage of the working access line 322-1 by allowing current from the working access line 322-1 to flow to the shunt sense line 310, and the low voltage of the shunt sense line can pull down the high voltage of the working access line 322-1.

[0030] Figure 4 4 shows another exemplary top view of a memory array 442 with access line control according to various embodiments of the present disclosure. The memory array 442 may include a plurality of access lines 422, a plurality of sense lines 404, and a plurality of shunt sense lines 410-1 and 410-2 (individually and collectively referred to as shunt sense lines 410). Figure 4 As shown, access device 413 can be coupled to shunt sense line 410 at each intersection of shunt sense line 410 and access line 422. Access device 413 at each intersection of shunt sense line 410 and access line 422 can be shorted to form a conductive path 405 between access line 422 and the source / drain region of access device 413.

[0031] The shorted access device 413 may be coupled to the shunt sense line 410 at each intersection of the shunt sense line 410 and the access line 422 to improve the precharge response time of each access line 422. As described above, the shunt sense line 410 may pull down the voltage of the access line 422 to allow the access line 422 to be disconnected more quickly. In some embodiments, the access line 422 may be disconnected and turned on sequentially. For example, the access line 422 may be configured to wait until the first access line 422 in the sequence of access lines 422 is disconnected and then turned on. In this example, any delay in disconnecting the access line 422 may affect any later access line 422 in the sequence. These delays may be superimposed on each other and cause the performance of the memory device to be degraded. By shorting the access device 413, the shunt sense line 410 may pull down the voltage across the access line 422 and allow the access line to be disconnected more quickly than if the shunt sense line 410 did not pull down the voltage across the access line 422. This reduction in precharge response time may also affect subsequent access lines 422 in the sequence of access lines 422. The reduction in precharge response time for each access line 422 may add up to each other and result in improved performance of the memory device.

[0032] In some embodiments, multiple shunt sense lines 410 may be coupled to access line 422. As described above, each access device 413 may be coupled to shunt sense line 410 at each intersection of shunt sense line 410 and access line 422. Thus, access line 422 may be shorted to source / drain regions or cell contacts of access device 413 at multiple locations of access line 422. Figure 4 As shown, the conductive path 405 may include a conductive path 405 of multiple access devices 413 on multiple shunt sense lines 410 coupled to one access line 422. Shorting multiple access devices 413 to one access line 422 may provide benefits to the memory device. For example, shorting multiple access devices 413 to access line 422 may allow more current to be driven to access line 422 because more shunt sense lines 410 will be coupled to access line 422 and therefore more current can be driven through multiple shunt sense lines 410 to access line 422.

[0033] Figure 5 A timing diagram 544 for disconnecting an access line according to various embodiments of the present disclosure is shown. The timing diagram 544 shows a voltage 546 across a shunt sense line and a voltage 548 across an access line coupled to the shunt sense line. Figure 5 As shown, the voltage 546 applied across the shunt sense line can be less than the voltage 548 applied across the access line. For example, voltage 546 can be approximately 2.5 volts, and voltage 548 can be approximately 3 volts. Voltage 546 can be a voltage that is applied to the access device (e.g., Figure 2, and voltage 548 may be a high logic voltage applied to the access line.

[0034] like Figure 5 As shown, voltage 546 can be driven below ground. In some embodiments, the ground voltage can be approximately 0V. Figure 5 In the example of FIG. 5A , at about 33 nanoseconds (ns), voltage 546 may be reduced to about -1V. As voltage 546 is reduced, it may pull voltage 548 down. By reducing voltage 546 below ground, it may pull voltage 548 down faster than if voltage 546 were reduced to ground. The difference between voltage 548 and the voltage below ground is greater than the difference between voltage 548 and ground. This increased voltage difference may allow the voltage below ground to pull voltage 548 down faster than ground. This may result in a further reduction in precharge response time and an improvement in the disconnect time of the access line.

[0035] At approximately 43 ns, voltage 546 may be increased to a ground voltage (e.g., approximately 0V). Voltage 546 may be increased to a ground voltage to avoid pulling voltage 548 across the access line below the ground voltage. If voltage 546 continues to be below ground, voltage 548 may eventually have been pulled below ground. By increasing voltage 546 to ground before voltage 546 pulls voltage 548 below ground, voltage 548 may not be pulled below ground. This process may allow voltage 546 to pull voltage 548 down faster than if voltage 546 were driven to ground throughout the process. Voltage 546 may take advantage of the increased speed of pulling down below ground and then increase its voltage to ground before voltage 548 reaches the ground level. This may cause voltage 546 to pull voltage 548 to ground faster than if voltage 546 were at ground during the entire pull-down process.

[0036] Figure 6 650 is a flow chart of an exemplary method 650 of operating a memory array with access line control according to various embodiments of the present disclosure. Unless explicitly stated, the elements of the methods described herein are not limited to a particular order or sequence. In addition, multiple method embodiments or elements thereof described herein may be performed at the same or substantially the same time point.

[0037] At box 652, method 650 may include coupling a vertical TFT to a shunt sense line at the intersection of the shunt sense line and the access line. In some embodiments, a diode configuration may be formed by coupling the shunt sense line to the source / drain region of the vertical TFT. In some embodiments, the vertical TFT may be short-circuited to the access line. Shorting the vertical TFT to the access line may cause the vertical TFT to conduct in one direction, thus acting as a diode. In some embodiments, the diode may be a metal oxide semiconductor (MOS) diode. In some embodiments, the sense line may be a shunt sense line. A shunt sense line may be formed to keep the structure of the memory cell consistent. The shunt sense line may not be coupled to the memory cell. This may cause the shunt sense line to behave differently than a non-shunt sense line. For example, in contrast to a non-shunt sense line, a shunt sense line may not be used to locate a cell. Since the shunt sense line may not be connected to the cell, it may not be able to locate the memory cell in the memory array. However, the shunt sense line may be used to control the access line.

[0038] At block 654, method 650 may include providing current to the shunt sense line. As described above, the sense line may be a shunt sense line. In some embodiments, the memory device in which the shunt sense line is formed may be a DRAM memory device. In a DRAM memory device configuration, a non-shunt sense line may carry a signal from a cell to an external input / output interface. In contrast, a shunt sense line may be used for power delivery purposes. For example, a shunt sense line may be used to drive a current of an access line. In addition, a shunt sense line may be used to control a voltage of an access line.

[0039] The DRAM memory device in which the shunt sense lines are formed may be a three-dimensional (3D) DRAM or a two-dimensional (2D) DRAM. Figures 1 to 4 Represents the structure of the memory array in the 3D DRAM structure. Figures 1 to 4 As shown, the access lines and sense lines in the 3D DRAM structure can be straight lines. The 3D DRAM structure can include semiconductor structures stacked in layers on top of other semiconductor structures. The architecture of the layered stacking of semiconductor structures can allow the access lines and sense lines to be manufactured as straight lines before other semiconductor structures are manufactured around the access lines and sense lines. In contrast, the access lines and sense lines in the 2D DRAM memory device can adjust their manufacturing paths so that the access lines and sense lines are not straight lines. For example, the access lines in the 2D DRAM structure can bend their shape to pass between multiple sense lines to couple to the intended cell contacts of the sense lines.

[0040] At block 656, method 650 may include disconnecting the access line by applying a low logic voltage across the shunt sense line to reduce the voltage across the access line when current is provided to the shunt sense line. As described above, the sense line may be a shunt sense line. The shunt sense line may be coupled to a vertical TFT that is shorted from the gate of the vertical TFT to the access line. This may allow the vertical TFT to act as a diode and allow current to flow from the access line to the shunt sense line. Applying a low logic voltage across the shunt sense line when current is provided to the shunt sense line may allow the shunt sense line to pull the voltage across the access line down to the low logic voltage. In some embodiments, the low logic voltage may be a ground voltage. In some embodiments, the ground voltage may be less than 0V. In some embodiments, a voltage that is a threshold voltage lower than the high logic voltage may be applied to the shunt sense line to prevent the voltage of the shunt sense line from being pulled up and causing parasitic capacitance.

[0041] Using a shunt sense line to pull down the voltage of the access line may shorten the precharge response time of the access line and allow the access line to disconnect faster than if the shunt sense line did not pull down the voltage of the access line. In some embodiments, when the access line voltage is pulled down using a shunt sense line, the access line can be disconnected faster in the range of 1ns to 5ns. For example, the time for the access line to disconnect can be reduced from 13.5ns to 10ns. The benefit of faster disconnect time may be more complicated because each access line in the sequence of access lines may wait for the previous access line in the sequence to disconnect before turning on. Reducing each disconnect time by 3.5ns may be cumulative and result in improved performance of the memory device.

[0042] Figure 7 is a functional block diagram of a computing system 756 including at least one memory array with access line control according to one or more embodiments of the present disclosure. Figure 7 The numbering convention used does not follow the Figures 1 to 6 The memory system 762 may be, for example, a solid state drive (SSD).

[0043] exist Figure 7In the embodiment shown in , the memory system 762 may include a memory interface 764, a plurality of memory devices 768-1, ..., 768-N, and a controller 766 selectively coupled to the memory interface 764 and the memory devices 768-1, ..., 768-N. The memory interface 764 can be used to transfer information between the memory system 762 and another device (such as a host 758). The host 758 may include a processor (not shown). As used herein, a "processor" may be a plurality of processors, such as a parallel processing system, a plurality of coprocessors, etc. An exemplary host may include or be implemented in a laptop computer, a personal computer, a digital camera, a digital recording device and playback device, a mobile phone, a PDA, a memory card reader, an interface hub, etc. This host 758 may be associated with manufacturing operations performed on semiconductor devices and / or SSDs using processing equipment.

[0044] In various embodiments, the host 758 may be associated with (e.g., include or be coupled to) a host interface 760. The host interface 760 may enable input of scaling preferences (e.g., digitally and / or structurally defined gradients) to define, for example, a critical dimension (CD) of a final structure or an intermediate structure of a memory device (e.g., as shown at 768) and / or a memory cell array (e.g., as shown at 770) formed on the memory device for implementation by a processing device. The array may include an access device with access line control implemented according to embodiments described herein. The scaling preferences may be provided to the host interface 760 via input of a plurality of preferences stored by the host 758, input of preferences from another storage system (not shown), and / or input of preferences of a user (e.g., an operator).

[0045] The memory interface 764 may be in the form of a standardized physical interface. For example, when the memory system 762 may be used for information (e.g., data) storage in the computing system 756, the memory interface 764 may be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, or a universal serial bus (USB) interface, as well as other physical connectors and / or interfaces. However, in general, the memory interface 764 may provide an interface for passing control, addresses, information, scaling preferences, and / or other signals between the controller 766 of the memory system 762 and the host 758 (e.g., via the host interface 760).

[0046] Controller 766 may include, for example, firmware and / or control circuitry (e.g., hardware). Controller 766 may be operably coupled to and / or included on the same physical device (e.g., die) as one or more memory devices 768-1, ..., 768-N. For example, controller 766 may be or may include an ASIC that is hardware operably coupled to a circuit (e.g., printed circuit board) that includes memory interface 764 and memory devices 768-1, ..., 768-N. Alternatively, controller 766 may be included on a separate physical device that is communicatively coupled to a physical device (e.g., die) that includes one or more of memory devices 768-1, ..., 768-N.

[0047] The controller 766 may communicate with the memory devices 768-1, ..., 768-N to direct operations to sense (e.g., read), program (e.g., write) and / or erase information, as well as other functions and / or operations for management of the memory cells. The controller 766 may have circuits that may include multiple integrated circuits and / or discrete components. In various embodiments, the circuits in the controller 766 may include control circuits for controlling access across the memory devices 768-1, ..., 768-N and / or circuits for providing a translation layer between the host 758 and the memory system 762.

[0048] The memory devices 768-1, ..., 768-N may include, for example, a plurality of memory arrays 770 (e.g., arrays of volatile and / or non-volatile memory cells). For example, the memory devices 768-1, ..., 768-N may include arrays of memory cells, such as a portion of an exemplary memory device structured as including storage node contacts. At least one array may have access line control implemented therein according to embodiments disclosed herein. It should be understood that the memory cells in the memory arrays 770 of the memory devices 768-1, ..., 768-N may be in a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash memory architecture (e.g., NAND, NOR, etc.) 3D RAM and / or a flash memory cell architecture, or some other memory array architecture including pillars and adjacent trenches.

[0049] The memory devices 768 may be formed on the same die. The memory devices (e.g., memory device 768-1) may include one or more memory cell arrays 770 formed on the die. The memory devices may include sensing circuits 772 and control circuits 774 associated with one or more arrays 770 formed on the die or portions thereof. The sensing circuits 772 may be used to determine (sense) a specific data value (e.g., 0 or 1) stored at a specific memory cell in a row of the array 770. In response to commands from the host 758 and / or the host interface 760, in addition to directing the storage, erasure, etc. of the data value, the control circuits 774 may also be used to direct the sensing circuits 772 to sense a specific data value. The commands may be sent directly to the control circuits 774 via the memory interface 764, or sent to the control circuits 774 via the controller 766.

[0050] Figure 7 The embodiments shown in the drawings may include additional circuits that are not shown so as not to obscure the embodiments of the present disclosure. For example, the memory device 768 may include address circuits to latch address signals provided on the I / O connectors through the I / O circuits. The address signals may be received and decoded by the row decoders and column decoders to access the memory array 770. It should be understood that the number of address input connectors may depend on the density and / or architecture of the memory device 768 and / or the memory array 770.

[0051] In the above detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which is shown by way of illustration how one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is to be understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure.

[0052] It should be understood that the terms used herein are used only to describe specific embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a / an" and "the" include singular and plural referents, as do "multiple," "at least one," and "one or more" (e.g., multiple memory arrays may refer to one or more memory arrays), while "multiple" is intended to refer to more than one such thing. In addition, throughout the application, the words "may" and "can" are used in a permissive sense (i.e., there is the potential, ability to) rather than a mandatory sense (i.e., must). The term "including" and its derivatives mean "including but not limited to." Depending on the context, the terms "coupled" and "coupled" refer to physically connecting directly or indirectly, and unless otherwise specified, may include wireless connections to access and / or move (transmit) instructions (e.g., control signals, address signals, etc.) and data.

[0053] Although exemplary embodiments including various combinations and configurations of semiconductor materials, base materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, oxide materials, nitride materials, buffer materials, etching chemistry, etching process, solvents, memory devices, memory cells, openings, and other materials and / or components related to patterning materials over active regions for storage node contacts have been shown and described herein, embodiments of the present disclosure are not limited to those combinations explicitly stated herein. Other combinations and configurations of semiconductor materials, base materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, oxide materials, nitride materials, buffer materials, etching chemistry, etching process, solvents, memory devices, memory cells, sidewalls of openings, and / or trenches other than those combinations and configurations disclosed herein are explicitly included within the scope of the present disclosure.

[0054] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that arrangements intended to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adjustments or variations of one or more embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative manner and not restrictive. By reading the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents given by such claims.

[0055] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the present disclosure. The disclosed method should not be interpreted as reflecting the intention that the disclosed embodiments of the present disclosure must use more features than the features explicitly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the present invention lies in less than all the features of a single disclosed embodiment. Therefore, the attached claims are hereby incorporated into the detailed description, wherein each claim independently serves as a separate embodiment.

Claims

1. A device comprising: An array of memory cells, each memory cell comprising: an access device, wherein the access device comprises a first source / drain region, a second source / drain region, and a gate opposite a channel connecting the first source / drain region and the second source / drain region; as well as Storage nodes; a plurality of sense lines each coupled to the first source / drain region of a different corresponding memory cell in the memory cell array; a plurality of access lines, wherein each access line includes at least one conductive path formed between the access line and a source / drain region of an additional access device coupled to the access line, wherein the conductive path is formed by shorting the access line to the additional access device; as well as A shunt sense line is coupled to the additional access device formed with the conductive path.

2. The apparatus of claim 1, wherein at least one of the access lines comprises a plurality of conductive paths formed between the access line and source / drain regions of different corresponding additional access devices.

3. The apparatus of claim 1, wherein the apparatus comprises an access line driver coupled to the plurality of access lines at an end of each respective access line.

4. The apparatus of any one of claims 1 to 3, wherein the storage node of each respective memory cell is formed at an intersection of one of the sense lines and one of the access lines.

5. The apparatus of any one of claims 1 to 3, wherein the conductive path is formed on the shunt sense line.

6. The apparatus of any one of claims 1 to 3, wherein the shunt sense line is formed at the end of each respective access line.

7. The apparatus of any one of claims 1 to 3, wherein the shunt sense line is formed in the middle of each corresponding access line.

8. The apparatus of any one of claims 1 to 3, wherein the apparatus comprises a plurality of shunt sense lines.

9. The apparatus according to any one of claims 1 to 3, wherein the additional access device is a vertical thin film transistor (TFT).

10. A method comprising: coupling a vertical thin film transistor (TFT) to a shunt sense line at an intersection of the shunt sense line and an access line, wherein coupling the vertical TFT to the shunt sense line comprises coupling a source / drain region of the vertical TFT to the shunt sense line to form a diode configuration; providing current to the shunt sensing line; as well as The access line is disconnected by applying a low logic voltage across the shunt sense line to reduce the voltage across the access line while providing the current to the shunt sense line. The method of claim 10 , further comprising using a ground voltage as the low logic voltage.

12. The method of claim 11, further comprising using a voltage less than zero volts as the ground voltage.

13. The method of any one of claims 10 to 12, further comprising reducing the voltage across the access line to a voltage less than a ground voltage.

14. The method of any one of claims 10 to 12, further comprising applying a voltage to the shunt sense line that is a threshold voltage lower than a high logic voltage to prevent the voltage across the shunt sense line from being pulled up.

15. An apparatus comprising: Sensing line; an access line orthogonally coupled to the sense line; a vertical thin film transistor TFT coupled to the sense line at an intersection of the sense line and the access line, wherein the vertical TFT is coupled to a conductive path formed between the access line and a source / drain region of the vertical TFT; as well as The conductive path is formed by shorting the access line to the source / drain regions of the vertical TFT.

16. The device of claim 15, wherein the vertical TFT is short-circuited to create a diode.

17. The apparatus of claim 16, wherein the diode is a Metal Oxide Semiconductor (MOS) diode.

18. The apparatus of claim 15, wherein the sense line is a shunt sense line.

19. The apparatus of claim 18, wherein the shunt sense line is not coupled to a memory cell.

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