Chipset and Chip

Abstract

An embodiment of the present invention provides a chip combination and chip, comprising: a substrate and a first chip and a second chip stacked and arranged on the upper surface of the substrate, wherein the first chip is located above the second chip; a first pad pair is provided on the edge of the first side of the first chip and the second chip, and a second pad pair is provided on the edge of the second side of the first chip and the second chip, wherein the second pad pair is located between two adjacent functional units at the outermost sides of the second side edge of the first chip or the second chip, and the lower edge of the second pad pair is not lower than the lower edges of the two adjacent functional units; the difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the first pad pair of the first chip and the second pad pair of the second chip are positioned correspondingly. The technical solution of the present invention can reduce the chip size and the number of pads, and increase the number of chip stacking layers under the condition of limited internal cavity space of the chip package.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip combination and a chip. Background Art

[0002] Current low-power DRAM (Dynamic Random-Access Memory) typically has nearly a hundred or even more pads (pads), including data input and output ports, command address ports, clock ports, and multiple power / ground ports. Multiple power / ground ports, as part of a distributed power supply, can increase the balance and consistency of power / ground supply. Chip pad layouts generally fall into the following categories:

[0003] like Figure 1 As shown, placing the PAD and peripheral control logic circuit 103 in the middle of the chip, i.e., between the memory cell array 104, allows the distance between the power / ground PAD and both edges of the chip to be only half the chip height, reducing the parasitic resistance by half. Under the same width power / ground traces and current conditions, the voltage drop on the power / ground traces is reduced by half, thereby reducing noise and increasing drive capability, which is particularly beneficial for the high-frequency operating mode of the chip. However, this approach is not conducive to large-capacity stacked packaging. If stacked packaging is to be implemented, an RDL (Re-Distribution Layer) must be introduced to move the middle PAD to one side of the chip, which increases the complexity of the process and the manufacturing cost. Furthermore, the parasitic resistance generated by the RDL also weakens the low resistance benefit of placing the PAD in the middle.

[0004] like Figure 2 As shown, placing the PAD and peripheral control logic on one side of the chip, particularly the short side, creates the longest power / ground traces and the highest parasitic resistance. This results in the largest voltage drop at the far end of the chip, away from the PAD. This can cause performance at the far end of the chip to deteriorate significantly compared to that at the near end, especially in high-frequency operation. To ensure proper operation at the far end, the required power / ground traces must be widened, which in turn encroaches on space for other signal lines and complicates layout design.

[0005] like Figure 3 As shown, the peripheral control logic circuit and part of the PAD are arranged on one side of the chip, and part of the PAD is placed on the other side of the chip, where the PAD includes distributed power / ground pads 102 and other signal pads 101. This can also reduce the equivalent resistance and wiring area of ​​the power / ground wiring. However, the increase in the area of ​​one row of PADs directly leads to an increase in chip cost, and the PAD layout on both sides will have an adverse effect on the large capacity and miniaturization of the chip packaging.

[0006] The current packaging trend of low-power DRAM is large capacity and small size. In other words, it is hoped that multiple low-power DRAM particles can be packaged in one package cavity to increase capacity and reduce power consumption. This requires that DRAM chips can be stacked and packaged. Without considering the expensive TSV (Through Silicon Via) technology, such as Figure 4 and Figure 5 In the stacked package shown, the chip 401 is disposed on a substrate 402 . Stacked packaging can only be facilitated by placing the PAD at the edge of the chip.

[0007] The more layers of chips are stacked, the longer the bonding wires from the chip to the substrate will be, and the more space will be occupied. Under the condition of limited space inside the package cavity, the size of the chip, the number of pads connected on the substrate, and the number of stacked layers are mutually restricted. Smaller chip size and fewer pads allow for more stacked layers. Figure 5 The chip shown is smaller than Figure 6 The chip shown can therefore be stacked in larger numbers; Figure 7 More pads than shown Figure 8 As shown in the figure, the connection line from the chip to the substrate is long and at a large angle, thus taking up more space.

[0008] The large number of pads and small number of stacking layers in the chip combination are technical problems that need to be solved urgently.

[0009] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0010] An object of the embodiments of the present invention is to provide a chip assembly and a chip, thereby solving, at least to a certain extent, the problem of a large number of pads and a small number of stacked layers in the chip assembly.

[0011] Other features and advantages of the present invention will become apparent from the following detailed description, or may be learned in part by practice of the present invention.

[0012] According to a first aspect of an embodiment of the present invention, a chip combination is provided, comprising: the chip combination comprises a substrate and a first chip and a second chip stacked and arranged on the upper surface of the substrate, the first chip being located above the second chip; a first pad pair comprising a first reference potential pad and a second reference potential pad is provided on the edge of the first side of the first chip and the second chip, a second pad pair comprising a first reference potential pad and a second reference potential pad is provided on the edge of the second side of the first chip and the second chip, the second pad pair is located between the two outermost adjacent functional units on the second side edge of the first chip or the second chip, and the lower edge of the second pad pair is not lower than the lower edges of the two adjacent functional units; the difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the first pad pair of the first chip and the second pad pair of the second chip correspond in position to each other.

[0013] In some embodiments, the first reference potential is a positive pole of a power supply, and the second reference potential is a ground potential.

[0014] In some embodiments, the chip combination further includes a third chip and a fourth chip that are stacked, and the stacked third chip and the fourth chip are arranged side by side with the stacked first chip and the second chip on the substrate.

[0015] In some embodiments, gold fingers are provided on an upper surface of edges of the substrate corresponding to the first side and the second side of the first chip.

[0016] In some embodiments, the pad pair is disposed on upper surfaces of the first chip and the second chip.

[0017] In some embodiments, the pair of pads on the first chip and the second chip are coupled to the gold fingers through bonding wires.

[0018] In some embodiments, the pair of pads located on the first side of the first chip is connected to the pair of pads located on the second side of the first chip through a power cable.

[0019] In some embodiments, each of the chip combinations includes a first chip and a second chip that are stacked, and a third chip and a fourth chip that are stacked.

[0020] In some embodiments, the first chip includes a peripheral logic control circuit and a memory cell array, and the peripheral logic control circuit is located on a first side of the first chip.

[0021] In some embodiments, other signal pads of the first chip except the first reference potential pad and the second reference potential pad are disposed at an edge of the first side of the first chip.

[0022] In some embodiments, the first reference potential pad of the first pad pair of the first chip corresponds to the first reference potential pad position of the second pad pair of the second chip; the second reference potential pad of the first pad pair of the first chip corresponds to the second reference potential pad position of the second pad pair of the second chip.

[0023] According to a second aspect of an embodiment of the present invention, a chip is provided, wherein a first pad pair including a first reference potential pad and a second reference potential pad is provided on the edge of a first side of the chip, and a second pad pair including a first reference potential pad and a second reference potential pad is provided on the edge of a second side of the chip, the second pad pair is located between the two outermost adjacent functional units on the edge of the second side of the chip, and the lower edge of the second pad pair is not lower than the lower edges of the two adjacent functional units; after the chip is rotated 180 degrees within the plane in which it is located, the pad pair on the first side of the chip after the rotation corresponds to the position of the pad pair on the second side of the chip before the rotation.

[0024] In some embodiments, the first reference potential pad of the first pad pair of the chip after rotation corresponds to the first reference potential pad position of the second pad pair of the chip before rotation; the second reference potential pad of the first pad pair of the chip after rotation corresponds to the second reference potential pad position of the second pad pair of the chip before rotation.

[0025] In some embodiments, the chip includes a dynamic random access memory chip, and the functional unit of the chip includes a memory cell array.

[0026] The technical solution provided by the embodiment of the present invention may have the following beneficial effects:

[0027] In the technical solutions provided in some embodiments of the present invention, by respectively setting pad pairs on the first side and the second side of the first chip and the second chip, and the first pad pair of the first chip corresponds to the second pad pair of the second chip, the number of pads of the chip can be reduced, and the number of solder joints corresponding to the pad pairs on the substrate can be reduced, thereby increasing the number of stackable layers in a fixed packaging space; in addition, since the second pad pair is located between the two outermost adjacent functional units of the second side edge of the first chip or the second chip, the space of the chip can be further saved, thereby achieving the effect of setting pads on the second side of the chip but not occupying the second side edge space.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0030] Figure 1 A schematic diagram schematically shows a chip layout in the related art;

[0031] Figure 2 A schematic diagram schematically shows another chip layout in the related art;

[0032] Figure 3 A schematic diagram schematically shows another chip layout in the related art;

[0033] Figure 4 A top view schematically shows another chip layout in the related art;

[0034] Figure 5 A cross-sectional view schematically illustrates another chip layout in the related art;

[0035] Figure 6 A cross-sectional view schematically illustrates another chip layout in the related art;

[0036] Figure 7 A schematic diagram of connecting a chip and a substrate in the related art is shown schematically;

[0037] Figure 8 Schematically shows another schematic diagram of connecting a chip and a substrate in the related art;

[0038] Figure 9 The structure diagram of a chip according to an embodiment of the present invention is schematically shown;

[0039] Figure 10 Schematically shows a schematic diagram of pad pin changes in an embodiment of the present invention;

[0040] Figure 11 The schematic diagram shows the structure of the chip combination according to the embodiment of the present invention. DETAILED DESCRIPTION

[0041] The exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these examples are provided so that this disclosure will be more thorough and complete and will fully convey the concepts of the exemplary embodiments to those skilled in the art. Identical reference numerals in the figures represent identical or similar structures, and thus their detailed description will be omitted.

[0042] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustrations to another component, these terms are used in this specification for convenience only, such as the orientation of the examples described in the drawings. It is understood that if the modules of the illustrations are flipped so that they are upside down, the component described as "upper" will become the component "lower". Other relative terms such as "high", "low", "top", "bottom", "left", "right", etc. also have similar meanings. When a structure is "on" another structure, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0043] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0044] In the related art, within the same internal cavity space of a package, the more pads a chip of a chip combination has, the fewer layers of chips that can be stacked, which in turn affects the function of the chip combination.

[0045] To solve the above problems, an embodiment of the present invention provides a chip combination to reduce the number of pads of the chip and increase the number of stackable layers in a fixed packaging space.

[0046] Figure 9 The schematic diagram of the structure of a chip according to an embodiment of the present invention is shown schematically.

[0047] like Figure 9As described, a first pad pair 901 including a first reference potential pad and a second reference potential pad is provided on the edge of the first side of the chip of an embodiment of the present invention, and a second pad pair 902 including a first reference potential pad and a second reference potential pad is provided on the edge of the second side of the chip, the second pad pair 902 is located between the two outermost adjacent functional units on the edge of the second side of the chip, and the lower edge of the second pad pair 902 is not lower than the lower edges of the two adjacent functional units; after the chip is rotated 180 degrees in the plane where it is located, the pad pair on the first side of the chip after rotation corresponds to the position of the pad pair on the second side of the chip before rotation.

[0048] In this way, the first reference potential pad of the first pad pair of the rotated chip corresponds to the first reference potential pad position of the second pad pair of the chip before rotation; the second reference potential pad of the first pad pair of the rotated chip corresponds to the second reference potential pad position of the second pad pair of the chip before rotation.

[0049] Here, the chip may be a dynamic random access memory chip, and the functional unit may be the memory cell array 104. The first reference potential may be the positive electrode of the power supply, and the second reference potential may be the ground potential. Figure 10 As shown, according to the pad order recommended by JEDEC (Joint Electron Device Engineering Council Soild State Technology Association), according to the arrangement position of the memory cell array 104, appropriate VSSQ (digital I / O port ground) and VQQ (digital ground) are selected, such as pad 19, pad 39 and pad 60, and a positive power supply (VDD2) pad is added next to these VSSQ and VQQ, such as pad 18A, pad 38A and pad 60B. The added positive power supply (VDD2) pad and the adjacent ground potential PAD form a pad pair, i.e., a power / ground pair, to facilitate the remote PAD distribution design. Here, VSSQ and VSS are actually short-circuited, that is, they are the same node.

[0050] The chip combination provided by the exemplary embodiment of the present disclosure includes: a substrate and a first chip and a second chip stacked on the upper surface of the substrate, wherein the first chip is located above the second chip. Figure 9 The chip shown.

[0051] like Figure 11As shown, a first pad pair 901 including a first reference potential pad and a second reference potential pad is provided on the edge of the first side of the first chip. A second pad pair 902 including the first reference potential pad and the second reference potential pad is provided on the edge of the second side of the first chip. The second pad pair 902 is located between the two outermost adjacent functional units on the second side of the first chip, and the lower edge of the second pad pair 902 is no lower than the lower edges of the two adjacent functional units. A first pad pair including the first reference potential pad and the second reference potential pad is provided on the edge of the first side of the second chip. A second pad pair including the first reference potential pad and the second reference potential pad is provided on the edge of the second side of the second chip. The second pad pair is located between the two outermost adjacent functional units on the second side of the second chip, and the lower edge of the second pad pair is no lower than the lower edges of the two adjacent functional units. The orientation difference between the first side of the first chip and the first side of the second chip is 180 degrees, and the first pad pair of the first chip corresponds to the second pad pair of the second chip.

[0052] The technical solution of an embodiment of the present invention sets a pair of pads on the edges of the first side and the second side of the first chip and the second chip, and the first pad pair of the first chip corresponds to the second pad pair of the second chip in position. In this way, when the pad pair is welded to the gold fingers on the substrate, a pad on the first side of the first chip and a pad on the second side of the second chip can be connected to the same gold finger, thereby reducing the number of gold fingers.

[0053] In addition, the second pad pair is located between the two outermost adjacent functional units on the second side edge of the first chip or the second chip, saving space on the second side edge of the chip. Taking into account various factors such as packaging feasibility, layout of power / ground PADs, wiring resources and utilization, distribution of modules within the chip, chip area and manufacturing cost, a new power / ground PAD arrangement method is proposed. It can reduce the equivalent resistance of the power / ground wiring without increasing the area, thereby improving the high-frequency performance of the chip.

[0054] In an embodiment of the present invention, the first reference potential pad of the first pad pair of the first chip corresponds to the first reference potential pad of the second pad pair of the second chip; the second reference potential pad of the first pad pair of the first chip corresponds to the second reference potential pad of the second pad pair of the second chip.

[0055] like Figure 9As shown, the first side of the first chip is provided with three groups of pad pairs. Among them, the left pad of the first pad pair from left to right is the positive power pad, and the right pad is the ground potential pad; the left pads of the second and third pad pairs from left to right are the ground potential pads, and the right pads are the positive power pads. The second side of the first chip is provided with three groups of pad pairs. Among them, the left pads of the first and second pad pairs from left to right are the positive power pads, and the right pads are the ground potential pads; the left pads of the third pad pair from left to right are the ground potential pads, and the right pads are the positive power pads. The second chip can have the same structure as the first chip.

[0056] In this way, when the first pad pair of the first chip and the second pad pair of the second chip are arranged in corresponding positions, the three groups of power / ground PADs on the first side of the upper first chip coincide with the power / ground PADs on the second side of the lower second chip. No additional area is required to place the PAD, and no additional gold fingers need to be added to the substrate for connection during packaging.

[0057] In addition, some of the logic between the memory cell arrays 104, such as decoding logic, is connected up and down. Since there are no connecting lines at the bottom of the memory cell array, some logic can be simplified and deleted, and a power / ground PAD can be placed in the vacant position. In this way, the second pad pair can be set between the two outermost adjacent functional units on the second side edge of the first chip or the second chip to reduce the chip area.

[0058] like Figure 9 As shown, the pad pair located on the first side of the first chip is connected to the pad pair located on the second side via power bus 903. The first chip includes peripheral logic control circuitry 103 and memory cell array 104. Peripheral logic control circuitry 103 is located on the first side of the first chip. In addition to the first and second reference potential pads, the other signal pads of the first chip are located at the edge of the first side of the first chip. Here, the other signal pads include data input / output port pads, command address port pads, and clock port pads.

[0059] In an embodiment of the present invention, the chip combination further includes a stacked third chip and a fourth chip, and the stacked combination formed by the first chip and the second chip and the stacked combination formed by the third chip and the fourth chip are arranged side by side on the substrate.

[0060] like Figure 11The number of chips in the stacked combination formed by the first chip and the second chip on the substrate shown is two, but in actual applications, the number of chips in the stacked combination formed by the first chip and the second chip is not limited to this. Similarly, the number of chips in the stacked combination formed by the third chip and the fourth chip can also be two or more. For example, in one embodiment, each chip combination includes the first chip and the second chip stacked together, and the third chip and the fourth chip stacked together.

[0061] like Figure 11 As shown, first chip 1101 and second chip 1102 are stacked on substrate 402. Positive power pad 1105 and ground pad 1106 are coupled to gold fingers 1103 and 1104 via bonding wires 1107. In this embodiment of the present invention, gold fingers are provided on the upper surface of the substrate at the edges corresponding to the first and second sides of the first chip. The gold fingers are provided on the upper surface of the substrate, and pad pairs may also be provided on the upper surfaces of the first and second side edges of the first and second chips.

[0062] Similarly, pad pairs can also be provided on the upper surfaces of the third and fourth chips. The pad pairs on the third and fourth chips can also be coupled to the gold fingers via bonding wires. Here, the pad pairs can include a positive power pad 1105 and a ground potential pad 1106.

[0063] In the chip combination of the embodiment of the present invention, by respectively arranging pad pairs on the first side and the second side of the first chip and the second chip, and the first pad pair of the first chip corresponds to the second pad pair of the second chip in position, the number of pads of the chip can be reduced, and the number of solder joints corresponding to the pad pairs on the substrate can be reduced, thereby increasing the number of stackable layers in a fixed packaging space; in addition, since the second pad pair is located between the two outermost adjacent functional units of the second side edge of the first chip or the second chip, the space of the chip can be further saved, thereby achieving the effect of arranging pads on the second side of the chip but not occupying the space at the second side edge.

[0064] Other embodiments of the present invention will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

[0065] It should be understood that the present invention is not limited to the exact construction described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A chip, characterized in that: A first pad pair including a first reference potential pad and a second reference potential pad is provided on an edge of a first side of the chip, and a second pad pair including a first reference potential pad and a second reference potential pad is provided on an edge of a second side of the chip, wherein the second pad pair is located between two outermost adjacent memory cell arrays on the edge of the second side of the chip, and a lower edge of the second pad pair is not lower than the lower edges of the two adjacent memory cell arrays; After the chip is rotated 180 degrees in its own plane, the pad pair on the first side of the chip after rotation corresponds to the pad pair on the second side of the chip before rotation; The chip includes a peripheral logic control circuit and a plurality of memory cell arrays, the plurality of memory cell arrays including at least two adjacent memory cell arrays, and the peripheral logic control circuit is located on a first side of the chip; After the rotation, the first reference potential pad of the first pad pair of the chip corresponds to the first reference potential pad of the second pad pair of the chip before the rotation; after the rotation, the second reference potential pad of the first pad pair of the chip corresponds to the second reference potential pad of the second pad pair of the chip before the rotation; The other signal pads of the chip except the first reference potential pad and the second reference potential pad are arranged at an edge of the first side of the chip.

2. The chip according to claim 1, characterized in that The chip includes a dynamic random access memory chip.

3. The chip according to claim 1, characterized in that The first reference potential is the positive pole of the power supply, and the second reference potential is the ground potential.

4. The chip according to any one of claims 1 to 3, characterized in that: The pair of pads located on the first side of the chip is connected to the pair of pads located on the second side of the chip through a power cable.

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