Power module and substrate structure applicable to power module

Abstract

Embodiments of the present disclosure provide a substrate structure applicable to a power module. The substrate structure applicable to the power module includes an upper substrate and a lower substrate. The lower substrate includes: a device region, on which a plurality of semiconductor devices are disposed; a source signal electrode for transmitting a source signal to the semiconductor devices; and a gate signal electrode for transmitting a gate signal to the semiconductor devices. One of the source signal electrode and the gate signal electrode is connected to the upper substrate through a conductive column, and a signal transmitted through one of the source signal electrode and the gate signal electrode is transmitted to the semiconductor devices through the upper substrate.

Description

Technical Field

[0001] The present disclosure relates to a power module having conductive posts that electrically connect a lower substrate and an upper substrate, and a substrate structure suitable for the power module. Background Art

[0002] A power conversion device (e.g., an inverter), which is one of the core components of a hybrid vehicle and an electric vehicle, is a main component of an environmentally friendly vehicle, and many technologies are being developed. The development of a power module, which is a core component of the power conversion device and accounts for the highest cost, is a core technology in the field of environmentally friendly vehicles.

[0003] A plurality of semiconductor devices can be mounted in the power module. When a current is applied to the power module, the current is applied to the plurality of semiconductor devices, and the semiconductor devices convert the applied current. Therefore, when the currents applied to the semiconductor devices of the power module have the same density, the function of the power module can be maximized.

[0004] However, since a plurality of semiconductor devices are mounted on one substrate, the area for arranging the semiconductor devices is reduced, and thus the gap between the semiconductor devices is reduced. Since the gap between the semiconductor devices is reduced, interference is caused by the heat generated when the semiconductor devices operate, which leads to problems such as an increase in the operating temperature of the semiconductor devices or an increase in the thermal stress at the joint portion where the devices constituting the power module are joined. Summary of the Invention

[0005] An object of the present disclosure is to provide a power module and a substrate structure suitable for the power module. In order to increase the gap between semiconductor devices, a part of the source signal electrode is removed and a conductive post electrically connected to the source signal electrode is provided.

[0006] An object of the present disclosure is to provide a power module and a substrate structure suitable for the power module, including conductive posts for electrically connecting a lower substrate and an upper substrate to each other and maintaining a uniform gap between the lower substrate and the upper substrate.

[0007] An embodiment of the present disclosure provides a substrate structure suitable for a power module.

[0008] The substrate structure suitable for the power module includes an upper substrate and a lower substrate. The lower substrate includes: a device region on which a plurality of semiconductor devices are provided; a source signal electrode for transmitting a source signal to the semiconductor devices; and a gate signal electrode for transmitting a gate signal to the semiconductor devices. Either the source signal electrode or the gate signal electrode is connected to the upper substrate through a conductive post, and a signal transmitted through either the source signal electrode or the gate signal electrode is transmitted to the semiconductor devices through the upper substrate.

[0009] In an embodiment, the conductive post can maintain the gap between the upper substrate and the lower substrate.

[0010] In an embodiment, the conductive posts may be disposed adjacent to the corners of the lower substrate.

[0011] In an embodiment, the electrodes connected to the conductive posts may be disposed only on the edges of the lower substrate.

[0012] In an embodiment, the electrodes of the source signal electrode and the gate signal electrode that are not connected to the conductive posts may be disposed to surround the device region.

[0013] In an embodiment, the electrodes not connected to the conductive posts may be electrically connected to the semiconductor device through wires.

[0014] In an embodiment, the electrodes connected to the conductive posts may be disposed on one edge of the lower substrate adjacent to the lead frame that transmits the source signal and the gate signal to the lower substrate.

[0015] In an embodiment, the lower substrate may further include an input terminal region, the input terminals for applying power to the lower substrate are disposed in the input terminal region, and the electrodes connected to the conductive posts may be disposed on the edge of the lower substrate opposite to the input terminal region, and the lower substrate is between the lead frame and the input terminals.

[0016] In an embodiment, the lower substrate may further include: a first edge adjacent to the input terminal region, the input terminals for applying power to the lower substrate are disposed in the input terminal region; and a second edge disposed opposite to the first edge, and any one of the source signal electrode and the gate signal electrode connected to the conductive posts may be disposed on the second edge.

[0017] In an embodiment, any one of the source signal electrode and the gate signal electrode connected to the conductive posts may not be disposed on the third edge and the fourth edge that connect the first edge and the second edge to each other.

[0018] In an embodiment, the device region may include a high-side device region where a high-side semiconductor device is disposed and a low-side device region where a low-side semiconductor device is disposed, the source signal electrode may include a high-side source signal electrode adjacent to the high-side device region and a low-side source signal electrode adjacent to the low-side device region, and the gate signal electrode may include a high-side gate signal electrode adjacent to the high-side device region and a low-side gate signal electrode adjacent to the low-side device region.

[0019] In an embodiment, the conductive posts may include high-side conductive posts adjacent to the high-side device region and low-side conductive posts adjacent to the low-side device region, the high-side conductive posts may be electrically connected to any one of the high-side source signal electrode and the high-side gate signal electrode, and the low-side conductive posts may be electrically connected to any one of the low-side source signal electrode and the low-side gate signal electrode.

[0020] In an embodiment, an electrode not connected to the conductive column may be provided at an edge of the lower substrate, and the edge of the lower substrate is provided in a direction from the high-side device region toward the low-side device region.

[0021] In an embodiment, an isolator may be provided on the semiconductor device, and the isolator may be electrically connected to the upper substrate.

[0022] Embodiments of the present disclosure provide a power module. The power module includes: an upper substrate and a lower substrate to which power and signals are applied; a plurality of semiconductor devices provided on the lower substrate; and conductive columns that electrically connect the upper substrate and the lower substrate to each other, wherein the conductive columns are connected to any one of a source signal electrode and a gate signal electrode provided on the lower substrate, and the semiconductor devices are connected to any one of the source signal electrode and the gate signal electrode not connected to the conductive column through a wire.

[0023] In an embodiment, an input terminal for supplying power to the lower substrate may be provided, and any one of the source signal electrode and the gate signal electrode connected to the conductive column may be provided at an edge parallel to the setting direction of the input terminal on the lower substrate.

[0024] In an embodiment, any one of the source signal electrode and the gate signal electrode connected to the conductive column may be provided adjacent to an edge opposite to the edge where the input terminal is provided.

[0025] In an embodiment, the source signal electrode and the gate signal electrode may be electrically connected to a lead frame for transmitting the source signal and the gate signal to the lower substrate through a wire, and the semiconductor devices may be electrically connected to any one of the source signal electrode and the gate signal electrode not connected to the conductive column through a wire.

[0026] In an embodiment, the semiconductor device may receive a signal transmitted to the upper substrate through the conductive column through an isolator provided between the semiconductor device and the upper substrate.

[0027] According to an embodiment of the present disclosure, since there is no source signal electrode in one direction of the lower substrate, the gap between the semiconductor devices can be increased. Therefore, thermal interference between the semiconductor devices can be suppressed to the greatest extent and the operating temperature of the power module can be reduced.

[0028] According to an embodiment of the present disclosure, since there is no source signal electrode in one direction of the lower substrate, the channel for transmitting the current input from the input terminal to the semiconductor device can be widened. Therefore, heat generated due to current concentration can be suppressed.

[0029] According to an embodiment of the present disclosure, the conductive columns that electrically connect the upper substrate and the lower substrate to each other keep the gap between the upper substrate and the lower substrate uniform, so that defects caused by non-uniform thickness of the power module can be suppressed to the greatest extent. Description of the Drawings

[0030] The above and other objects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings, where:

[0031] Figure 1 is a view showing a lower substrate of a power module according to an embodiment of the present disclosure;

[0032] Figure 2 is a view showing a first region of the lower substrate according to an embodiment of the present disclosure;

[0033] Figure 3 is a view showing a second region of the lower substrate according to an embodiment of the present disclosure;

[0034] Figure 4 is along Figure 2 a cross-sectional view taken along line A-A'; and

[0035] Figure 5 is a side view of a power module according to an embodiment of the present disclosure. Detailed Description of the Embodiments

[0036] Advantages and features of the present disclosure and methods for realizing the advantages and features of the present disclosure will become clear by referring to exemplary embodiments that will be described in detail below with reference to the drawings. However, the present disclosure is not limited to the exemplary embodiments described below but can be implemented in various ways, and the exemplary embodiments are provided to make the description of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure, and the present disclosure is defined by the claims. Throughout the specification, the same reference numerals denote the same components.

[0037] Terms such as "~ unit" and "~ device" used herein denote units for processing at least one function or operation, and can be implemented by hardware, software, or a combination of hardware and software.

[0038] Throughout the specification, since some components have the same name, terms such as "first" and "second" are used for distinction, but are not necessarily limited to the order in the following description.

[0039] The specification provides examples of the present disclosure. In addition, the specification provides embodiments of the present disclosure, and the present disclosure can be used in various other combinations, changes, and environments. That is, changes or modifications can be made to the present disclosure within the scope of the present disclosure described herein, within the scope equivalent to the specification, and / or within the knowledge or technology of the relevant field. The embodiments show the best state for achieving the purpose of the present disclosure and can be changed in various ways for the detailed application fields and uses of the present disclosure. Therefore, the detailed description of the present disclosure is not intended to limit the present disclosure to the embodiments. In addition, the claims should be construed to include other embodiments.

[0040] Figure 1 is a view showing a lower substrate of a power module according to an embodiment of the present disclosure.

[0041] Refer to Figure 1, the power module 1 may include a first switching unit SW1 and a second switching unit SW2. The first switching unit SW1 may include a plurality of components mounted in a first region of the lower substrate 110, and the second switching unit SW2 may include a plurality of components mounted in a second region of the lower substrate 110. The first switching unit SW1 and the second switching unit SW2 may be electrically connected to each other. The first switching unit SW1 as a high-side switching unit may include high-side semiconductor devices 200a, 200b, 200c, and 200d, a first input terminal 410, and an output terminal 450. The second switching unit SW2 as a low-side switching unit may include low-side semiconductor devices 300a, 300b, 300c, and 300d, a second input terminal 510, and an AC terminal 430. For example, the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d may be MOSFETs made of one of silicon carbide (SiC), silicon (Si), and gallium nitride (GaN). The current converted by the high-side semiconductor devices 200a, 200b, 200c, and 200d may be applied to the second input terminal 510, and the current applied through the second input terminal 510 may be applied to the low-side semiconductor devices 300a, 300b, 300c, and 300d and the AC terminal 430. The current converted by the low-side semiconductor devices 300a, 300b, 300c, and 300d may be applied to the connection terminal 530. The current applied to the connection terminal 530 may be output through the output terminal 450 electrically connected to the connection terminal 530. The second input terminal 510 serves as a connection terminal for connecting the first switching unit SW1 and the second switching unit SW2 of the lower substrate 110 to each other, but the second input terminal 510 may also serve as an input terminal for applying current to the low-side semiconductor devices 300a, 300b, 300c, and 300d of the second switching unit SW2. The power module 1 according to an embodiment of the present disclosure may be configured in a two-in-one (2-in-1) form in which the first switching unit SW1 and the second switching unit SW2 are formed on one lower substrate 110. Therefore, there may be two AC terminals 430.

[0042] The lower substrate 110 may include a conductive layer. The power module 1 may be provided with the lower substrate 110 and an upper substrate (not shown). For example, the lower substrate 110 and the upper substrate (not shown) may transmit the applied current to the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d, and may be electrically connected to the plurality of terminals 410, 430, 450, 510, and 530. That is, the lower substrate 110 may provide an area for mounting the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d and the plurality of terminals 410, 430, 450, 510, and 530, and may electrically connect the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d and the plurality of terminals 410, 430, 450, 510, and 530.

[0043] The lower substrate 110 may be divided into a first region and a second region. The first region and the second region of the lower substrate 110 may be electrically insulated from each other. The high-side semiconductor devices 200a, 200b, 200c, and 200d, the first input terminal 410, and the output terminal 450 may be provided in the first region of the lower substrate 110. The low-side semiconductor devices 300a, 300b, 300c, and 300d, the second input terminal 510, and the AC terminal 430 may be provided in the second region of the lower substrate 110. The second input terminal 510 and the connection terminal 530 may be provided on the lower substrate 110 to electrically connect the first region and the second region of the lower substrate 110.

[0044] The high-side semiconductor devices 200a, 200b, 200c, and 200d may be arranged counterclockwise. The high-side semiconductor devices 200a, 200b, 200c, and 200d may include a first high-side semiconductor device 200a, a second high-side semiconductor device 200b, a third high-side semiconductor device 200c, and a fourth high-side semiconductor device 200d. The first high-side semiconductor device 200a and the fourth high-side semiconductor device 200d may be provided adjacent to the first input terminal 410. Specifically, the first high-side semiconductor device 200a may be provided adjacent to the first input terminal 410, and the fourth high-side semiconductor device 200d may be provided adjacent to the output terminal 450. However, the first high-side semiconductor device 200a and the fourth high-side semiconductor device 200d may be electrically insulated from the output terminal 450 by a pattern formed on the lower substrate 110.

[0045] Slit insulators 120 and 140 may be defined in a first region of the lower substrate 110. The slit insulators 120 and 140 may refer to spaces excluding a conductive layer that is a component of the lower substrate 110. The slit insulators 120 and 140 may prevent current applied through the first input terminal 410 from concentrating on the first high-side semiconductor device 200a and the fourth high-side semiconductor device 200d. Specifically, the slit insulators 120 and 140 may be defined between the first input terminal 410 and the first high-side semiconductor device 200a and the fourth high-side semiconductor device 200d, so that the current applied through the first input terminal 410 is guided to the high-side semiconductor devices 200a, 200b, 200c, and 200d after being transmitted to the space between the high-side semiconductor devices 200a, 200b, 200c, and 200d. That is, the slit insulators 120 and 140 may change the current transmission path to prevent the current applied through the first input terminal 410 from being directly transmitted to the first high-side semiconductor device 200a and the fourth high-side semiconductor device 200d.

[0046] The slit insulators 120 and 140 may be defined on a side of the high-side semiconductor devices 200a and 200d adjacent to the first input terminal 410 among the high-side semiconductor devices 200a, 200b, 200c, and 200d. Specifically, the slit insulators 120 and 140 may include: a first slit insulator 120 defined on the lower substrate 110 on a side of the first high-side semiconductor device 200a; and a second slit insulator 140 defined on the lower substrate 110 on a side of the fourth high-side semiconductor device 200d. The first slit insulator 120 and the second slit insulator 140 may extend from a first side of the lower substrate 110 where the first input terminal 410 is provided toward a second side opposite to the first side. In other words, the first slit insulator 120 may extend from the first high-side semiconductor device 200a toward the second high-side semiconductor device 200b, and the second slit insulator 140 may extend from the fourth high-side semiconductor device 200d toward the third high-side semiconductor device 200c. The first slit insulator 120 extending from the first side of the lower substrate 110 toward the second side may not protrude beyond an end of the first high-side semiconductor device 200a. The second slit insulator 140 extending from the first side of the lower substrate 110 toward the second side may not protrude beyond an end of the fourth high-side semiconductor device 200d. The first slit insulator 120 may extend closer to the second side than the second slit insulator 140. The first slit insulator 120 and the second slit insulator 140 may be defined in a space between the first high-side semiconductor device 200a and the fourth high-side semiconductor device 200d.

[0047] The low-side semiconductor devices 300a, 300b, 300c, and 300d may be arranged counterclockwise. The low-side semiconductor devices 300a, 300b, 300c, and 300d may include a first low-side semiconductor device 300a, a second low-side semiconductor device 300b, a third low-side semiconductor device 300c, and a fourth low-side semiconductor device 300d. The first low-side semiconductor device 300a and the fourth low-side semiconductor device 300d may be disposed adjacent to the second input terminal 510. However, the first low-side semiconductor device 300a and the fourth low-side semiconductor device 300d may be electrically insulated from the output terminal 450 by a pattern formed on the lower substrate 110.

[0048] Slit insulators 160 and 180 may be defined in a second region of the lower substrate 110. The slit insulators 160 and 180 may refer to spaces where a conductive layer, which is a component of the lower substrate 110, is removed. The slit insulators 160 and 180 may prevent the current applied through the second input terminal 510 from concentrating on the first low-side semiconductor device 300a and the fourth low-side semiconductor device 300d. Specifically, the slit insulators 160 and 180 may be defined between the second input terminal 510 and the first low-side semiconductor device 300a and the fourth low-side semiconductor device 300d such that the current applied through the second input terminal 510 is guided to the spaces between the low-side semiconductor devices 300a, 300b, 300c, and 300d after being transmitted to the spaces between the low-side semiconductor devices 300a, 300b, 300c, and 300d. That is, the slit insulators 160 and 180 may change the current transmission path to prevent the current applied through the second input terminal 510 from being directly transmitted to the first low-side semiconductor device 300a and the fourth low-side semiconductor device 300d.

[0049] The slit insulators 160 and 180 may be defined on one side of the low-side semiconductor devices 300a and 300d adjacent to the second input terminal 510 in the low-side semiconductor devices 300a, 300b, 300c, and 300d. Specifically, the slit insulators 160 and 180 may include: a third slit insulator 160 defined on one side of the first low-side semiconductor device 300a on the lower substrate 110; and a fourth slit insulator 180 defined on one side of the fourth low-side semiconductor device 300d on the lower substrate 110. The third slit insulator 160 and the fourth slit insulator 180 may extend from the first side of the lower substrate 110 where the second input terminal 510 is disposed toward the second side opposite to the first side. In other words, the third slit insulator 160 may extend from the first low-side semiconductor device 300a toward the second low-side semiconductor device 300b, and the fourth slit insulator 180 may extend from the fourth low-side semiconductor device 300d toward the third low-side semiconductor device 300c. The third slit insulator 160 extending from the first side of the lower substrate 110 toward the second side may not protrude beyond the end of the first low-side semiconductor device 300a. The fourth slit insulator 180 extending from the first side of the lower substrate 110 toward the second side may not protrude beyond the end of the fourth low-side semiconductor device 300d. The third slit insulator 160 may extend closer to the second side than the fourth slit insulator 180. The third slit insulator 160 and the fourth slit insulator 180 may be defined in the space between the first low-side semiconductor device 300a and the fourth low-side semiconductor device 300d.

[0050] The lower substrate 110 may include: source signal electrodes 101a and 101b that transmit source signals to the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d; and gate signal electrodes 103a and 103b that transmit gate signals. The source signal electrodes 101a and 101b and the gate signal electrodes 103a and 103b may be electrically insulated from each other. The source signal electrodes 101a and 101b and the gate signal electrodes 103a and 103b may be part of a conductive layer of the lower substrate 110. The source signal electrodes 101a and 101b may include a high-side source signal electrode 101a disposed in a first region of the lower substrate 110 and a low-side source signal electrode 101b disposed in a second region of the lower substrate 110. The gate signal electrodes 103a and 103b may include a high-side gate signal electrode 103a disposed in a first region of the lower substrate 110 and a low-side gate signal electrode 101b disposed in a second region of the lower substrate 110.

[0051] The high-side source signal electrodes 101a and the low-side source signal electrodes 101b may be disposed on one edge of the lower substrate 110. Specifically, the high-side source signal electrodes 101a and the low-side source signal electrodes 101b may be disposed adjacent to one of the four edges of the lower substrate 110. The high-side source signal electrodes 101a and the low-side source signal electrodes 101b may be disposed on the edge opposite to the edge where the first input terminal 410 and the AC terminal 430 for applying power to the lower substrate 110 are disposed. The high-side source signal electrodes 101a and the low-side source signal electrodes 101b may be disposed at positions opposite to the input terminal regions of the first input terminal 410 and the AC terminal 430 for applying power to the lower substrate 110. For example, the lower substrate 110 may include: a first edge 11 where the first input terminal 410, the AC terminal 430, and the output terminal 450 are disposed; a second edge 12 where the high-side source signal electrodes 101a and the low-side source signal electrodes 101b are disposed; and third and fourth edges 13 and 14 connecting the first edge and the second edge. The high-side source signal electrodes 101a and the low-side source signal electrodes 101b may not be disposed on the third edge 13 and the fourth edge 14. In other words, the high-side source signal electrodes 101a and the low-side source signal electrodes 101b may not be disposed on the edges 13 and 14 disposed in parallel with the setting direction of the first input terminal 410 and the AC terminal 430. The first edge 11 and the second edge 12 may be disposed opposite to each other.

[0052] The high-side gate signal electrodes 103a and the low-side gate signal electrodes 103b may be disposed to surround the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d. Specifically, the high-side gate signal electrode 103a may be disposed to surround the high-side semiconductor devices 200a, 200b, 200c, and 200d, and the low-side gate signal electrode 103b may be disposed to surround the low-side semiconductor devices 300a, 300b, 300c, and 300d. The high-side gate signal electrodes 103a and the low-side gate signal electrodes 103b may be disposed adjacent to the second edge 12, the third edge 13, and the fourth edge 14 of the lower substrate 110.

[0053] Any one of the source signal electrodes 101a and 101b and the gate signal electrodes 103a and 103b may be connected to the conductive posts 150a and 150b provided on the lower substrate 110. Although the conductive posts 150a and 150b are connected to the source signal electrodes 101a and 101b in the embodiments of the present disclosure, the present disclosure is not limited thereto. Embodiments in which the conductive posts 150a and 150b are connected to the source signal electrodes 101a and 101b are described below. The high-side source signal electrode 101a and the low-side source signal electrode 101b may be connected to the conductive posts 150a and 150b. The conductive posts 150a and 150b may be connected to the upper substrate (not shown) described above. The high-side source signal electrode 101a may be connected to the first conductive post 150a provided in the first region, and the low-side source signal electrode 101b may be connected to the second conductive post 150b provided in the second region. The conductive posts 150a and 150b may be provided adjacent to the corners of the lower substrate 110. For example, the first conductive post 150a may be provided adjacent to the corner where the second edge 12 and the third edge 13 intersect each other, and the second conductive post 150b may be provided adjacent to the corner where the second edge 12 and the fourth edge 14 intersect each other. The first conductive post 150a is electrically connected to the high-side source signal electrode 101a, but may be electrically insulated from the high-side semiconductor devices 200a, 200b, 200c, and 200d and the high-side gate signal electrode 103a.

[0054] The high-side gate signal electrode 103a and the low-side gate signal electrode 103b that are not connected to the conductive posts 150a and 150b may be electrically connected to the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d through wires.

[0055] The lead frame 480 includes a plurality of frame terminals and may be connected to an external controller (not shown) and the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d through at least one frame terminal. The lead frame 480 may transmit control signals (source signals and gate signals) of the external controller to the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d. Specifically, the lead frame 480 may be electrically connected to the source signal electrodes 101a and 101b and the gate signal electrodes 103a and 103b through wires (not shown). The lead frame 480 may be disposed opposite to the first input terminal 410, the AC terminal 430, and the output terminal 450, and the lower substrate 110 is between the lead frame 480 and the first input terminal 410, the AC terminal 430, and the output terminal 450. The source signal electrodes 101a and 101b may be provided on the second edge 12 of the lower substrate 110 adjacent to the lead frame 480.

[0056] According to an embodiment of the present disclosure, electrodes (i.e., source signal electrodes 101a and 101b) connected to conductive posts 150a and 150b may not be provided at the edges 13 and 14 of the lower substrate. The edges 13 and 14 of the lower substrate are provided in a direction from the device region where the high-side semiconductor devices 200a, 200b, 200c, and 200d are provided toward the device region where the low-side semiconductor devices 300a, 300b, 300c, and 300d are provided. That is, only the gate signal electrodes 103a and 103b may be provided in a first direction from the third edge 13 toward the fourth edge 14. Since only the gate signal electrodes 103a and 103b are provided in the first direction, the gap between the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d can be increased. When all the source signal electrodes 101a and 101b and the gate signal electrodes 103a and 103b are provided in the first direction, the gap between the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d is relatively small. Therefore, there is a problem that heat generated when the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d operate causes interference, so that the operating temperature of the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d increases. However, in the power module 1 according to an embodiment of the present disclosure, only the gate signal electrodes 103a and 103b are provided in the first direction, and the source signal electrodes 101a and 101b are connected to the conductive posts 150a and 150b, so that the gap between the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d can be increased. Therefore, the heat generated when switching the power module 1 can be released to the maximum extent, and the thermal interference between the semiconductor devices 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d can also be suppressed. Therefore, the operating temperature of the power module 1 can be reduced.

[0057] Figure 2 is a view showing a first region of a lower substrate according to an embodiment of the present disclosure. For simplicity of description, repeated descriptions are not provided.

[0058] Refer to Figure 2, the high-side source signal electrode 101a and the high-side gate signal electrode 103a can be disposed adjacent to the high-side device regions 205a, 205b, 205c, and 205d. The high-side source signal electrode 101a can be disposed on one side of the high-side device regions 205a, 205b, 205c, and 205d, and the high-side gate signal electrode 103a can be disposed to surround the high-side device regions 205a, 205b, 205c, and 205d. The high-side source signal electrode 101a can be connected to the first conductive pillar 150a. The first high-side semiconductor device 200a can be disposed in the first high-side device region 205a, the second high-side semiconductor device 200b can be disposed in the second high-side device region 205b, the third high-side semiconductor device 200c can be disposed in the third high-side device region 205c, and the fourth high-side semiconductor device 200d can be disposed in the fourth high-side device region 205d.

[0059] The first electrode insulator 135 can be disposed between the high-side source signal electrode 101a and the high-side gate signal electrode 103a. Thus, the high-side gate signal electrode 103a can be electrically insulated from the high-side source signal electrode 101a and the first conductive pillar 150a.

[0060] The second electrode insulator 137 can be disposed between the high-side gate signal electrode 103a and the high-side device regions 205a, 205b, 205c, and 205d. The high-side gate signal electrode 103a is not electrically connected to the high-side device regions 205a, 205b, 205c, and 205d through the conductive layer of the first region 110a, but can be electrically connected through the high-side wires 530a, 530b, 530c, and 530d. Specifically, the first high-side semiconductor device 200a can be electrically connected to the high-side gate signal electrode 103a through the first wire 530a, the second high-side semiconductor device 200b can be electrically connected to the high-side gate signal electrode 103a through the second wire 530b, the third high-side semiconductor device 200c can be electrically connected to the high-side gate signal electrode 103a through the third wire 530c, and the fourth high-side semiconductor device 200d can be electrically connected to the high-side gate signal electrode 103a through the fourth wire 530d. In this configuration, the high-side source signal electrode 101a can be not connected to the high-side semiconductor devices 200a, 200b, 200c, and 200d through a wire.

[0061] According to an embodiment of the present disclosure, since there is no high-side source signal electrode 101a in the lateral direction of the first region 110a (the direction from the first high-side semiconductor device 200a toward the fourth high-side semiconductor device 200d), the gap between the high-side semiconductor devices 200a, 200b, 200c, and 200d can be increased. Thus, the thermal interference between the high-side semiconductor devices 200a, 200b, 200c, and 200d can be suppressed to the greatest extent.

[0062] According to an embodiment of the present disclosure, since there is no high-side source signal electrode 101a in the lateral direction of the first region 110a, the channel for transmitting the current input from the first input terminal 410 to the high-side semiconductor devices 200a, 200b, 200c, and 200d can be widened. The channel may refer to the space between the first slit insulator 120 and the second slit insulator 140. That is, the space between the first high-side semiconductor device 200a and the fourth high-side semiconductor device 200d increases, so the path can be widened. Therefore, heat generated due to current concentration can be suppressed.

[0063] Figure 3 It is a view showing a second region of a lower substrate according to an embodiment of the present disclosure. For simplicity of description, repeated descriptions are not provided.

[0064] Referring to Figure 3 , the low-side source signal electrode 101b and the low-side gate signal electrode 103b can be disposed adjacent to the low-side device regions 305a, 305b, 305c, and 305d. The low-side source signal electrode 101b can be disposed on one side of the low-side device regions 305a, 305b, 305c, and 305d, and the low-side gate signal electrode 103b can be disposed to surround the low-side device regions 305a, 305b, 305c, and 305d. The low-side source signal electrode 101b can be connected to the second conductive post 150b. The first low-side semiconductor device 300a can be disposed in the first low-side device region 305a, the second low-side semiconductor device 300b can be disposed in the second low-side device region 305b, the third low-side semiconductor device 300c can be disposed in the third low-side device region 305c, and the fourth low-side semiconductor device 300d can be disposed in the fourth low-side device region 305d.

[0065] The third electrode insulator 155 can be disposed between the low-side source signal electrode 101b and the low-side gate signal electrode 103b. Therefore, the low-side gate signal electrode 103b can be electrically insulated from the low-side source signal electrode 101b and the second conductive post 150b.

[0066] The fourth electrode insulator 157 may be disposed between the low-side gate signal electrode 103b and the low-side device regions 305a, 305b, 305c, and 305d. The low-side gate signal electrode 103b and the low-side device regions 305a, 305b, 305c, and 305d are not electrically connected through the conductive layer of the second region 110b, but may be electrically connected through the low-side wires 550a, 550b, 550c, and 550d. Specifically, the first low-side semiconductor device 300a may be electrically connected to the low-side gate signal electrode 103b through the fifth wire 550a, the second low-side semiconductor device 300b may be electrically connected to the low-side gate signal electrode 103b through the sixth wire 550b, the third low-side semiconductor device 300c may be electrically connected to the low-side gate signal electrode 103b through the seventh wire 550c, and the fourth low-side semiconductor device 300d may be electrically connected to the low-side gate signal electrode 103b through the eighth wire 550d. In this configuration, the low-side source signal electrode 101b may not be connected to the low-side semiconductor devices 300a, 300b, 300c, and 300d through a wire.

[0067] According to an embodiment of the present disclosure, since there is no low-side source signal electrode 101b in the lateral direction of the second region 110b (the direction from the first low-side semiconductor device 300a toward the second low-side semiconductor device 300b), the gap between the low-side semiconductor devices 300a, 300b, 300c, and 300d can be increased. Therefore, thermal interference between the low-side semiconductor devices 300a, 300b, 300c, and 300d can be suppressed to the greatest extent.

[0068] According to an embodiment of the present disclosure, since there is no low-side source signal electrode 101b in the lateral direction of the second region 110b, the channel for transmitting the current input from the second input terminal 510 to the low-side semiconductor devices 300a, 300b, 300c, and 300d can be widened. The channel may refer to the space between the third slit insulator 160 and the fourth slit insulator 180. That is, the space between the first low-side semiconductor device 300a and the fourth low-side semiconductor device 300d is increased, so the path can be widened. Therefore, heat generated due to current concentration can be suppressed.

[0069] Figure 4 is a cross-sectional view taken along Figure 2 line A-A' of

[0070] Refer to Figure 2 and Figure 4, the substrate 100 may include a lower substrate 110a and an upper substrate 115a. The lower substrate 110a may include an upper conductive layer 111a, an insulating layer 112a, and a lower conductive layer 113a, and the upper substrate 115a may include an upper conductive layer 116a, an insulating layer 117a, and a lower conductive layer 118a. In an embodiment of the present disclosure, a configuration in which high-side semiconductor devices 200a, 200b, 200c, and 200d and a first conductive post 150a are disposed on the lower substrate 110a may be illustrated.

[0071] The high-side source signal electrode 101a is electrically connected to the first conductive post 150a, and the first conductive post 150a may transmit the source signal to the upper conductive layer 116a of the upper substrate 115a. The upper conductive layer 116a may be electrically connected to a second spacer 210b stacked on the second high-side semiconductor device 200b and a third spacer 210c stacked on the third high-side semiconductor device 200c. Therefore, the source signal transmitted by the first conductive post 150a may be transmitted to the second high-side semiconductor device 200b and the third high-side semiconductor device 200c.

[0072] The first conductive post 150a may be disposed between the lower substrate 110a and the upper substrate 115a so as to be able to maintain a gap between the lower substrate 110a and the upper substrate 115a. Therefore, the first conductive post 150a may maximally suppress defects caused by non-uniform thickness of the power module.

[0073] Figure 5 is a side view of a power module according to an embodiment of the present disclosure. Figure 5 is a view showing a first region of the lower substrate from the side. For simplicity of description, repeated descriptions are not provided.

[0074] Referring to Figure 1 , Figure 2 and Figure 5 , the high-side source signal electrode 101a and the high-side gate signal electrode 103a may be electrically connected to a lead frame 480 that transmits a source signal and a gate signal through wires 481 and 482. Specifically, the high-side source signal electrode 101a may be electrically connected to the lead frame 480 through the wire 481 and electrically connected to the upper substrate 115a through the first conductive post 150a. The high-side gate signal electrode 103a may be electrically connected to the lead frame 480 through the wire 482 and electrically connected to the high-side semiconductor devices 200a, 200b, 200c, and 200d through wires 530a, 530b, 530c, and 530d. The lower substrate 110a may receive power through a lower input terminal 400a, and the upper substrate 115a may receive power through an upper input terminal 400b.

[0075] Although the exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present disclosure can be implemented in various ways without changing the necessary features or gist of the present disclosure. Therefore, the above embodiments are merely examples and should not be construed as restrictive in all respects.

Claims

1. A substrate structure suitable for a power module, comprising: an upper substrate and a lower substrate, wherein the lower substrate includes: a device region, on which a plurality of semiconductor devices are disposed; a source signal electrode for transmitting a source signal to the plurality of semiconductor devices; and a gate signal electrode for transmitting a gate signal to the plurality of semiconductor devices, either the source signal electrode or the gate signal electrode is connected to the upper substrate through a conductive post, and a signal transmitted through either the source signal electrode or the gate signal electrode is transmitted to the semiconductor device through the upper substrate, a signal transmitted through the other of the source signal electrode and the gate signal electrode is transmitted to the semiconductor device through a wire.

2. The substrate structure according to claim 1, wherein the conductive post maintains a gap between the upper substrate and the lower substrate.

3. The substrate structure according to claim 1, wherein the conductive post is disposed adjacent to a corner of the lower substrate.

4. The substrate structure according to claim 1, wherein the electrode among the source signal electrode and the gate signal electrode that is connected to the conductive post is only disposed on an edge of the lower substrate.

5. The substrate structure according to claim 4, wherein the electrode among the source signal electrode and the gate signal electrode that is not connected to the conductive post is disposed to surround the device region.

6. The substrate structure according to claim 5, wherein the electrode not connected to the conductive post is electrically connected to the plurality of semiconductor devices through a wire.

7. The substrate structure according to claim 4, wherein the electrode connected to the conductive post is disposed on an edge of the lower substrate adjacent to a lead frame that transmits a source signal and a gate signal to the lower substrate.

8. The substrate structure according to claim 4, wherein the lower substrate further includes an input terminal region, an input terminal for applying power to the lower substrate is disposed in the input terminal region, and the electrode connected to the conductive post is disposed on an edge of the lower substrate opposite to the input terminal region, and the lower substrate is between the lead frame and the input terminal.

9. The substrate structure according to claim 1, wherein the lower substrate further includes: a first edge adjacent to the input terminal region, an input terminal for applying power to the lower substrate is disposed in the input terminal region; and a second edge disposed opposite to the first edge, and the electrode among the source signal electrode and the gate signal electrode that is connected to the conductive post is disposed on the second edge.

10. The substrate structure according to claim 9, wherein the electrode among the source signal electrode and the gate signal electrode that is connected to the conductive post is not disposed on a third edge and a fourth edge that connect the first edge and the second edge to each other.

11. The substrate structure according to claim 1, wherein the device region includes a high-side device region for setting a high-side semiconductor device and a low-side device region for setting a low-side semiconductor device, The source signal electrodes include a high-side source signal electrode adjacent to the high-side device region and a low-side source signal electrode adjacent to the low-side device region, and the gate signal electrodes include a high-side gate signal electrode adjacent to the high-side device region and a low-side gate signal electrode adjacent to the low-side device region.

12. The substrate structure according to claim 11, wherein, the conductive posts include a high-side conductive post adjacent to the high-side device region and a low-side conductive post adjacent to the low-side device region, the high-side conductive post is electrically connected to one of the high-side source signal electrode and the high-side gate signal electrode, and the low-side conductive post is electrically connected to one of the low-side source signal electrode and the low-side gate signal electrode.

13. The substrate structure according to claim 11, wherein, the electrodes not connected to the conductive posts are provided at an edge of the lower substrate, and the edge of the lower substrate is provided in a direction from the high-side device region toward the low-side device region.

14. The substrate structure according to claim 1, wherein, isolators are provided on the plurality of semiconductor devices, and the isolators are electrically connected to the upper substrate.

15. A power module, comprising: an upper substrate and a lower substrate, power and signals being applied to the upper substrate and the lower substrate; a plurality of semiconductor devices provided on the lower substrate; and conductive posts electrically connecting the upper substrate and the lower substrate to each other, wherein the conductive posts are connected to one of a source signal electrode and a gate signal electrode provided on the lower substrate, and the plurality of semiconductor devices are connected to the electrode of the source signal electrode and the gate signal electrode that is not connected to the conductive posts by wires, and signals transmitted through the other of the source signal electrode and the gate signal electrode are transmitted to the plurality of semiconductor devices through the upper substrate.

16. The power module according to claim 15, wherein, an input terminal for supplying power to the lower substrate is provided, and the electrode of the source signal electrode and the gate signal electrode that is connected to the conductive posts is provided at an edge parallel to the direction in which the input terminal is provided on the lower substrate.

17. The power module according to claim 16, wherein, the electrode of the source signal electrode and the gate signal electrode that is connected to the conductive posts is provided adjacent to an edge opposite to the edge where the input terminal is provided.

18. The power module according to claim 16, wherein, the source signal electrode and the gate signal electrode are electrically connected to a lead frame for transmitting source signals and gate signals to the lower substrate by wires, and the plurality of semiconductor devices are electrically connected to the electrode of the source signal electrode and the gate signal electrode that is not connected to the conductive posts by wires.

19. The power module according to claim 18, wherein, the plurality of semiconductor devices receive signals transmitted to the upper substrate through the conductive posts through isolators provided between the semiconductor devices and the upper substrate.

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