Semiconductor device

Abstract

A semiconductor device includes a first external dummy region and a second external dummy region, and a circuit region located between the first external dummy region and the second external dummy region. The circuit region includes a circuit active region and a circuit gate line. Each external dummy region includes an external dummy active region and an external dummy gate line that overlaps with the external dummy active region and is spaced apart from the circuit gate line. The external dummy active region has a linear shape extending in a first horizontal direction, or includes a shape in which active portions are isolated from each other and do not directly contact each other and sequentially extend in the first horizontal direction. The circuit active region is located between the first external dummy active region and the second external dummy active region, and includes a first plurality of circuit active regions sequentially extending in the first horizontal direction and a second plurality of circuit active regions sequentially extending in a second horizontal direction perpendicular to the first horizontal direction.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2019 - 0163999, filed with the Korean Intellectual Property Office on December 10, 2019, the entire disclosure of which is incorporated herein by reference for all purposes. Technical field

[0003] The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including an active region having a circuit active region and a dummy region having a dummy active region. Background art

[0004] As the demand for high - performance, high - speed, and / or multi - functionality of semiconductor devices increases, the integration degree of semiconductor devices also increases. As the integration degree of semiconductor devices increases, the size of components such as circuit active regions decreases. Therefore, the reliability of the circuit active regions with reduced size becomes low. Summary of the invention

[0005] Some example embodiments of the present inventive concept provide a semiconductor device that can improve the integration degree.

[0006] Some example embodiments of the present inventive concept provide a semiconductor device that can improve reliability while improving the integration degree.

[0007] According to some example embodiments of the present inventive concept, a semiconductor device includes: a first external dummy region; a second external dummy region; and a circuit region located between the first external dummy region and the second external dummy region. The circuit region includes a circuit active region and a circuit gate line, the first external dummy region includes a first external dummy active region and a first external dummy gate line that overlaps the first external dummy active region and is spaced apart from the circuit gate line, the second external dummy region includes a second external dummy active region and a second external dummy gate line that overlaps the second external dummy active region and is spaced apart from the circuit gate line, both the first external dummy active region and the second external dummy active region have: a linear shape extending in a first horizontal direction, or a shape having active portions arranged in the first horizontal direction while being spaced apart from each other, and the circuit active region is provided as a plurality of gate active regions arranged in the first horizontal direction between the first external dummy active region and the second external dummy active region, and is provided as a plurality of circuit active regions arranged in a second horizontal direction perpendicular to the first horizontal direction between the first external dummy active region and the second external dummy active region.

[0008] According to some example embodiments of the inventive concept, a semiconductor device includes: a circuit region; an external dummy region adjacent to the circuit region; and a gate cut insulating region positioned between the circuit region and the external dummy region. The external dummy region includes an external dummy active region and an external dummy gate line overlapping the external dummy active region. The circuit region includes: a plurality of circuit active regions facing the external dummy active region and arranged in a first horizontal direction, and a circuit gate line overlapping the plurality of circuit active regions. The external dummy active region has: a linear shape extending in the first horizontal direction, or a shape including active portions sequentially arranged in the first horizontal direction while being spaced apart from each other. The gate cut insulating region includes a gate cut pattern interposed between the circuit gate line and the external dummy gate line and separating the circuit gate line and the external dummy gate line, and the gate cut pattern is arranged in the first horizontal direction.

[0009] According to some example embodiments of the inventive concept, a semiconductor device includes: a circuit region; and an external dummy region adjacent to the circuit region. The external dummy region includes: an external dummy active region extending in a first horizontal direction, and an external dummy gate line overlapping the external dummy active region and extending in a second horizontal direction perpendicular to the first horizontal direction. The circuit region includes: a circuit active region facing the external dummy active region and arranged in plurality in the first horizontal direction, and a circuit gate line overlapping the circuit active region and extending in the second horizontal direction. The external dummy active region has a linear shape extending in the first horizontal direction, or a shape including active portions sequentially arranged in the first horizontal direction while being spaced apart from each other. The circuit active region includes a first-side circuit active region and a second-side circuit active region adjacent to the external dummy active region. The spacing distance between the external dummy active region and the first-side circuit active region is less than the spacing distance between the external dummy active region and the second-side circuit active region, and no other circuit active regions are interposed between the first external dummy active region and the first-side circuit active region and between the first external dummy active region and the second-side circuit active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1Ais a top view showing a semiconductor device according to some example embodiments;

[0012] Figure 1B and Figure 1C is a cross-sectional view showing a semiconductor device according to some example embodiments;

[0013] Figure 2A and Figure 2B is a cross-sectional view showing a modified example of a semiconductor device according to some example embodiments;

[0014] Figure 3 is a top view showing a modified example of a semiconductor device according to some example embodiments;

[0015] Figure 4 is a top view showing a modified example of a semiconductor device according to some example embodiments;

[0016] Figure 5 is a top view showing a modified example of a semiconductor device according to some example embodiments;

[0017] Figure 6 is a cross-sectional view showing a modified example of a semiconductor device according to some example embodiments; and

[0018] Figure 7A 、 Figure 7B and Figure 7C is a view showing a modified example of a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0019] Hereinafter, a semiconductor device according to some example embodiments and a method of forming the semiconductor device will be described with reference to the accompanying drawings.

[0020] First, a planar structure of a semiconductor device according to some example embodiments will be described with reference to Figure 1A is a top view showing a semiconductor device according to some example embodiments.

[0021] Figure 1A is a top view showing a semiconductor device according to some example embodiments.

[0022] Referring to Figure 1A , a semiconductor device 1 according to some example embodiments may include a first external dummy region DA1, a second external dummy region DA2, and a circuit region CA located between the first external dummy region DA1 and the second external dummy region DA2. It will be understood that in some example embodiments, at least one of the first external dummy region DA1 or the second external dummy region DA2 may be adjacent to the circuit region CA.

[0023] The semiconductor device 1 may include a first gate cut-off insulating region GC1 located between a first external dummy region DA1 and a circuit region CA, and a second gate cut-off insulating region GC2 located between a second external dummy region DA2 and the circuit region CA.

[0024] The circuit region CA may include a circuit active region 6c and a circuit gate line 30c. The circuit gate line 30c may include a gate line overlapping with the circuit active region 6c (e.g., overlapping in the vertical direction D3). Each circuit active region 6c may have a linear shape or a bar shape extending in a first horizontal direction D1. Each circuit gate line 30c may have a linear shape or a bar shape extending in a second horizontal direction D2 perpendicular to the first horizontal direction D1. As shown in the figure, the circuit gate lines 30c may be understood to be arranged in parallel in the first horizontal direction D1 such that the circuit gate lines 30c extend in parallel in the second horizontal direction D2. As shown in the figure, at least some of the circuit active regions 6c may be spaced apart from each other in the first horizontal direction D1 (e.g., isolated from each other without direct contact).

[0025] The circuit region CA may further include an internal dummy active region 6cd and an internal dummy gate line 30cd overlapping with the internal dummy active region 6cd.

[0026] The circuit active region 6c may include a first circuit active region 6ca and a second circuit active region 6cb, and the first circuit active region 6ca and the second circuit active region 6cb are spaced apart by a distance L3 greater than the allowable distance ranges L1 and L2 (e.g., isolated from each other without direct contact). The first circuit active region 6ca and the second circuit active region 6cb may be spaced apart from each other in the first horizontal direction D1.

[0027] Among the circuit active regions 6c arranged along the first horizontal direction D1, the remaining circuit active regions other than the first circuit active region 6ca and the second circuit active region 6cb are spaced apart from each other by the allowable distance range L1 or L2 (e.g., isolated from each other without direct contact), and the internal dummy active region 6cd may be provided between the first circuit active region 6ca and the second circuit active region 6cb. For example, among the circuit active regions 6c adjacent to each other in the first horizontal direction D1, some circuit active regions may be spaced apart by a first distance L1, some other circuit active regions may be spaced apart by a second distance L2 greater than the first distance L1, and some other circuit active regions may be spaced apart by a third distance L3 greater than the second distance L2. In this case, the first distance L1 and the second distance L2 may be within the allowable distance range, and the third distance L3 may include cases where both are greater than the allowable distance range L1 and the allowable distance range L2. The third distance L3 is not limited to a specific value or a specific dimensional value.

[0028] The interval distance L1 between the first circuit active region 6ca and the internally virtual active region 6cd and the interval distance L1 between the second circuit active region 6cb and the internally virtual active region 6cd can each be within the allowable distance range L1 and L2.

[0029] Each circuit active region 6c can include a circuit active pattern 12c. The circuit active pattern 12c can include line patterns parallel to each other. The line patterns of the circuit active pattern 12c can extend in the first horizontal direction D1.

[0030] Each circuit active region 6c can further include a circuit base pattern 9c that overlaps with the circuit active pattern 12c.

[0031] A part of the circuit active regions 6c can have different widths in the second horizontal direction D2.

[0032] The internally virtual active region 6cd can be provided between the first circuit active region 6ca and the second circuit active region 6cb. The internally virtual active region 6cd can be spaced apart from the first circuit active region 6ca and the second circuit active region 6cb. Each internally virtual active region 6cd can further include an internally virtual base pattern 9cd that overlaps with the internally virtual active pattern 12cd.

[0033] The distance L1 between the internally virtual active region 6cd and the first circuit active region 6ca and the distance L1 between the internally virtual active region 6cd and the second circuit active region 6cb can be the first distance L1.

[0034] The first external virtual region DA1 can include a first external virtual active region 6d1 and a first external virtual gate line 30d1 that overlaps with the first external virtual active region 6d1 (e.g., overlaps in the vertical direction D3) and is spaced apart from the circuit gate line 30c (e.g., isolated so as not to be in direct contact with the circuit gate line 30c). The second external virtual region DA2 can include a second external virtual active region 6d2 and a second external virtual gate line 30d2 that overlaps with the second external virtual active region 6d2 (e.g., overlaps in the vertical direction D3) and is spaced apart from the circuit gate line 30c. As Figure 1A shown, each of the first external virtual active region 6d1 and the second external virtual active region 6d2 can have a linear shape extending in the first horizontal direction D1.

[0035] Between a first externally virtual active region 6d1 and a second externally virtual active region 6d2, a circuit active region 6c includes a plurality of circuit active regions 6c arranged in a first horizontal direction D1 and a plurality of circuit active regions 6c arranged in a second horizontal direction D2. The circuit active regions 6c arranged in the first horizontal direction D1 (e.g., sequentially extending in the first horizontal direction) may be referred to as a first plurality of circuit active regions 6c, and the circuit active regions 6c arranged in the second horizontal direction D2 (e.g., sequentially extending in the second horizontal direction D2) may be referred to as a second plurality of circuit active regions 6c, and the second plurality of circuit active regions 6c may include one or more circuit active regions of the first plurality of circuit active regions 6c. As Figure 1A shown, at least one of the first externally virtual active region 6d1 or the second externally virtual active region 6d2 may extend further in the first horizontal direction D1 than the end of the circuit active region 6c that is the last circuit active region 6c among the circuit active regions 6c sequentially extending in the first horizontal direction (e.g., the last circuit active region 6c among the linearly arranged circuit active regions 6c extending in the first horizontal direction).

[0036] Some circuit active regions 6c may have different lengths in the first horizontal direction D1. Some circuit active regions 6c may have different widths in the second horizontal direction D2.

[0037] The circuit active region 6c may include a first-side circuit active region 6c1 and a second-side circuit active region 6c2, wherein both the first-side circuit active region 6c1 and the second-side circuit active region 6c2 are adjacent to the first externally virtual active region 6d1.

[0038] Other circuit active regions (e.g., the circuit active region 6c excluding the first-side circuit active region 6c1 and the second-side circuit active region 6c2) may not be provided between the first externally virtual active region 6d1 and the first-side circuit active region 6c1, and other circuit active regions may not be provided between the first externally virtual active region 6d1 and the second-side circuit active region 6c2.

[0039] In some example embodiments, the spacing distance S1 between the first externally virtual active region 6d1 and the first-side circuit active region 6c1 may be different from the spacing distance S2 between the first externally virtual active region 6d1 and the second-side circuit active region 6c2.

[0040] In some example embodiments, the spacing distance S1 between the first externally virtual active region 6d1 and the first-side circuit active region 6c1 may be less than the spacing distance S2 between the first externally virtual active region 6d1 and the second-side circuit active region 6c2.

[0041] The first external dummy region DA1 may further include a first edge gate line 30e1. The second external dummy region DA2 may further include a second edge gate line 30e2.

[0042] At least as Figure 1A shown, the first external dummy gate line 30d1 may have a shape of lines or stripes parallel to each other, and the second external dummy gate line 30d2 may have a shape of lines or stripes parallel to each other. At least as Figure 1A shown, the first external dummy gate line 30d1 may be located between the first edge gate line 30e1 and the circuit gate line 30c. At least as Figure 1A shown, the second external dummy gate line 30d2 may be located between the second edge gate line 30e2 and the circuit gate line 30c.

[0043] In some example embodiments, at least some (e.g., at least part) of the first edge gate lines 30e1 may have a "U" shape (e.g., may be in a "U" shape). At least some of the second edge gate lines 30e2 may have a "U" shape.

[0044] The first gate cutting region GC1 may include a first gate cutting pattern 45a1 arranged (e.g., extending) sequentially in the first horizontal direction D1. The first gate cutting pattern 45a1 may be disposed between the first external dummy gate line 30d1 of the first external dummy region DA1 and the circuit gate line 30c of the circuit region CA (e.g., such that each individual first gate cutting pattern 45a1 may be located between an individual first external dummy gate line 30d1 and an individual circuit gate line 30c) to separate the first external dummy gate line 30d1 from the circuit gate line 30c (e.g., isolate it from directly contacting the circuit gate line 30c). The first external dummy gate line 30d1 and the circuit gate line 30c may be separated (e.g., isolated from directly contacting each other) by being spaced apart in the second horizontal direction D2 by the first gate cutting pattern 45a1.

[0045] The second gate cutting region GC2 may include a second gate cutting pattern 45a2 arranged (e.g., extending) sequentially in the first horizontal direction D1. The second gate cutting pattern 45a2 may be interposed between the second external dummy gate line 30d2 of the second external dummy region DA2 and the circuit gate line 30c of the circuit region CA (e.g., such that each individual second gate cutting pattern 45a2 may be located between an individual second external dummy gate line 30d2 and an individual circuit gate line 30c). The second external dummy gate line 30d2 and the circuit gate line 30c may be separated (e.g., isolated from directly contacting each other) by being spaced apart in the second horizontal direction D2 by the second gate cutting pattern 45a2.

[0046] The circuit region CA may also include a circuit gate cutting pattern 45c that separates the circuit gate line 30c in the circuit region CA in the second horizontal direction D2.

[0047] The first external dummy region DA1 may also include a first edge cutting pattern 45b1 located between the first edge gate line 30e1 and the first external dummy gate line 30d1. The first edge cutting pattern 45b1 may separate the first edge gate line 30e1 and the first external dummy gate line 30d1 in the second horizontal direction D2 (e.g., isolate the first edge gate line 30e1 and the first external dummy gate line 30d1 from directly contacting each other). As shown, the first external dummy gate line 30d1 may be located between the first edge cutting pattern 45b1 and the first gate cutting pattern 45a1. In some example embodiments, at least a portion (e.g., some or all) of the first edge cutting pattern 45b1 and / or the second edge cutting pattern 45b2 may have a "U" shape.

[0048] The second external dummy region DA2 may also include a second edge cutting pattern 45b2 located between the second edge gate line 30e2 and the second external dummy gate line 30d2. The second edge cutting pattern 45b2 may separate the second edge gate line 30e2 and the second external dummy gate line 30d2 in the second horizontal direction D2.

[0049] In some example embodiments, the first gate cutting pattern 45a1 and the second gate cutting pattern 45a2, the circuit gate cutting pattern 45c, and the first edge cutting pattern 45b1 and the second edge cutting pattern 45b2 may be formed of the same insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0050] In some example embodiments, the first external dummy region DA1 and the second external dummy region DA2 may be formed in a mirror-symmetric structure, with the circuit region CA therebetween.

[0051] The first external dummy active region 6d1 may include a first dummy active pattern 12d1. The second external dummy active region 6d2 may include a second dummy active pattern 12d2.

[0052] Both the first external dummy active region 6d1 and the second external dummy active region 6d2 may have a linear shape extending in the first horizontal direction D1.

[0053] In some example embodiments, the first dummy active pattern 12d1 may include a plurality of line patterns parallel to each other. The line patterns of the first dummy active pattern 12d1 may extend in the first horizontal direction D1.

[0054] As Figure 1AAs shown, the line patterns of the first dummy active pattern 12d1 may be two, but the exemplary embodiments are not limited thereto. For example, the line patterns of the first dummy active pattern 12d1 may be two or more than two.

[0055] In some exemplary embodiments, the first external dummy active region 6d1 may further include a first dummy base pattern 9d1. The second external dummy active region 6d2 may further include a second dummy base pattern 9d2. The first dummy active pattern 12d1 may overlap with the first dummy base pattern 9d1. The second dummy active pattern 12d2 may overlap with the second dummy base pattern 9d2.

[0056] Next, reference will be made to Figure 1B and Figure 1C to describe the cross-sectional structure of a semiconductor device according to some exemplary embodiments.

[0057] Figure 1B is a cross-sectional view of a region taken along line I-I' of Figure 1A to describe a semiconductor device according to some exemplary embodiments, and Figure 1C is a cross-sectional view of a region taken along lines II-II' and III-III' of Figure 1A to describe a semiconductor device according to some exemplary embodiments. In the cross-sectional structure of the semiconductor device according to some exemplary embodiments with reference to Figure 1B and Figure 1C , components described with reference to Figure 1A will be directly referred to without further description. In addition, since the first external dummy region DA1 and the second external dummy region DA2 may be mirror-symmetric structures, the cross-sectional structure of the second external dummy region DA2 will not be described below. The cross-sectional structure of the second external dummy region DA2 may be mirror-symmetric to the cross-sectional structure of the first external dummy region DA1, and thus can be understood to be substantially the same as each other.

[0058] It will be understood that an element may be stated herein as being "the same" as another element, and it will further be understood that an element stated herein as being "the same" as another element may be "the same" or "substantially the same" as the other element, where an element being "substantially the same" as another element will be understood to be the same as the other element within manufacturing tolerances and / or material tolerances. An element being the same or substantially the same as another element may be the same or substantially the same in structure, the same or substantially the same in function, and / or the same or substantially the same in composition.

[0059] Referring to Figure 1A , Figure 1B and Figure 1C , the semiconductor device 1 may further include a semiconductor substrate 3 and an isolation region 18 located on the semiconductor substrate 3.

[0060] The circuit active pattern 12c can be disposed on the circuit base pattern 9c.

[0061] In the case of the circuit active pattern 12c, one or more circuit active patterns 12c can extend from the upper surface of the circuit base pattern 9c in the vertical direction D3. Accordingly, it will be understood that each circuit active region 6c can include the circuit base pattern 9c and one or more circuit active patterns 12c extending from the circuit base pattern 9c in the vertical direction. At least as Figure 1B shown, the width of the circuit base pattern 9c of the circuit active region 6c in the second horizontal direction can be greater than the width of each circuit active pattern 12c of one or more circuit active patterns 12c of the circuit active region 6c in the second horizontal direction. The vertical direction D3 can be a direction perpendicular to the upper surface 3s of the semiconductor substrate 3. The first dummy active pattern 12d1 can be disposed on the first dummy base pattern 9d1. In the case of the first dummy active pattern 12d1, one or more first dummy active patterns 12d1 can extend from the upper surface of the first dummy base pattern 9d1 in the vertical direction D3. Accordingly, it will be understood that each first external dummy active region 6d1 can include the first dummy base pattern 9d1 and one or more first dummy active patterns 12d1 extending from the first dummy base pattern 9d1 in the vertical direction. At least as Figure 1B shown, the width of the first dummy base pattern 9d1 of the first external dummy active region 6d1 in the second horizontal direction can be greater than the width of each first dummy active pattern 12d1 of one or more first dummy active patterns 12d1 of the first external dummy active region 6d1 in the second horizontal direction.

[0062] The isolation region 18 can include a first isolation region 20 and a second isolation region 22. The first isolation region 20 can define the first dummy active pattern 12d1 and the circuit active pattern 12c, and the second isolation region 22 can define the first dummy base pattern 9d1 and the circuit base pattern 9c.

[0063] Each circuit active region 6c can further include a circuit channel region 12cc extending from the circuit active pattern 12c in the vertical direction D3 and adjacent to the circuit source / drain region 24c.

[0064] The first external dummy active region 6d1 can further include a dummy channel region 12dc extending from the first dummy active pattern 12d1 in the vertical direction D3 and adjacent to the dummy source / drain region 24d.

[0065] Each circuit gate line 30c may include a first gate dielectric layer 33c, a first gate electrode 36c, and a first gate capping layer 39c. The first gate dielectric layer 33c may cover the side and bottom surfaces of the first gate electrode 36c. The first gate capping layer 39c may be disposed on the first gate electrode 36c.

[0066] Each first external dummy gate line 30d1 may include a second gate dielectric layer 33d, a second gate electrode 36d, and a second gate capping layer 39d. The second gate dielectric layer 33d may cover the side and bottom surfaces of the second gate electrode 36d. The second gate capping layer 39d may be disposed on the second gate electrode 36d.

[0067] The second gate dielectric layer 33d, the second gate electrode 36d, and the second gate capping layer 39d may be respectively referred to as a dummy gate dielectric layer, a dummy gate electrode, and a dummy gate capping layer.

[0068] Each first edge gate line 30e1 may include a third gate dielectric layer 33e, a third gate electrode 36e, and a third gate capping layer 39e. The third gate dielectric layer 33e may cover the side and bottom surfaces of the third gate electrode 36e. The third gate capping layer 39e may be disposed on the third gate electrode 36e.

[0069] At least as Figure 1B shown, at least one circuit gate line 30c may cover the upper and side surfaces of at least one circuit channel region 12cc of the circuit active pattern 12c (e.g., may directly contact the upper and side surfaces as shown), and may extend onto the isolation region 18.

[0070] At least as Figure 1B shown, at least one first external dummy gate line 30d1 may cover the upper and side surfaces of at least one dummy channel region 12dc of the first dummy active pattern 12d1 (e.g., may directly contact the upper and side surfaces as shown), and may extend onto the isolation region 18.

[0071] The upper surface of the first gate electrode 36c of the circuit gate line 30c and the upper surface of the second gate electrode 36d of the first external dummy gate line 30d1 may be at a horizontal height higher than the upper surface of the circuit channel region 12cc and the upper surface of the first dummy active pattern 12d1.

[0072] In some example embodiments, the semiconductor device 1 may further include a circuit source / drain region 24c and a dummy source / drain region 24d. Again, the circuit region CA may include a circuit source / drain region 24c located on the circuit active region 6c (e.g., above the circuit active region 6c), and at least the first external dummy region DA1 may include a dummy source / drain region 24d located on the first external dummy active region 6d1 (e.g., above the first external dummy active region 6d1).

[0073] On the circuit active pattern 12c, a plurality of circuit source / drain regions 24c may be provided and may be adjacent to the circuit channel region 12cc in a first horizontal direction D1.

[0074] The first horizontal direction D1 may be parallel to the upper surface 3s of the semiconductor substrate 3.

[0075] On the first dummy active pattern 12d1, a plurality of dummy source / drain regions 24d may be provided as the dummy source / drain regions 24d, and the dummy source / drain regions 24d may be adjacent to the dummy channel region 12dc in the first horizontal direction D1.

[0076] In some example embodiments, the semiconductor device 1 may further include an interlayer insulating layer 27 located on the isolation region 18.

[0077] A first circuit contact plug 48c may be provided on the circuit source / drain region 24c (e.g., directly on the circuit source / drain region 24c) such that the first circuit contact plug 48c is configured to be electrically connected to the circuit source / drain region 24c. A second circuit contact plug 48g may be provided on the first gate electrode 36c to penetrate the first gate covering layer 39c.

[0078] In some example embodiments, a dummy source / drain contact plug 48ds may be provided on the dummy source / drain region 24d.

[0079] In some example embodiments, a dummy gate contact plug 48dg that penetrates the first gate covering layer 39c may be provided on the second gate electrode 36d.

[0080] In some example embodiments, the semiconductor device 1 may further include a first gate spacer 42c, a second gate spacer 42d, and a third gate spacer 42e.

[0081] The first gate spacer 42c may be interposed between the circuit gate line 30c and the first circuit contact plug 48c and between the circuit gate line 30c and the interlayer insulating layer 27.

[0082] The second gate spacer 42d may be interposed between the first external dummy gate line 30d1 and the dummy source / drain contact plug 48ds, and may be interposed between the first external dummy gate line 30d1 and the interlayer insulating layer 27. The third gate spacer 42e may be interposed between the first edge gate line 30e1 and the interlayer insulating layer 27.

[0083] The first to third gate spacers 42c, 42d, and 42e may be formed of an insulating material such as silicon nitride, silicon oxynitride, silicon oxide, or the like.

[0084] In some example embodiments, the semiconductor device 1 may further include a first contact spacer 47c and a second contact spacer 47d. The first contact spacer 47c and the second contact spacer 47d may be formed of an insulating material such as silicon oxide.

[0085] The first contact spacer 47c may surround a side surface of the first circuit contact plug 48c. The second contact spacer 47d may surround a side surface of the dummy source / drain contact plug 48ds.

[0086] In some example embodiments, the semiconductor device 1 may further include an upper insulating layer 51 disposed on the interlayer insulating layer 27, the circuit gate line 30c, the first external dummy gate line 30d1, and the first edge gate line 30e1.

[0087] In some example embodiments, the semiconductor device 1 may further include a first circuit via 54c and a second circuit via 54g that penetrate the upper insulating layer 51.

[0088] The first circuit via 54c may be located on the first circuit contact plug 48c and in contact with the first circuit contact plug 48c such that the first circuit via 54c is configured to be electrically connected to the first circuit contact plug 48c, and the second circuit via 54g may be in contact with the second circuit contact plug 48g.

[0089] In some example embodiments, the semiconductor device 1 may include a first circuit wiring 57c, a second circuit wiring 57g, and a dummy wiring 57d, which are disposed at the same height level on the upper insulating layer 51 (e.g., disposed at the same distance from the upper surface 3s of the semiconductor substrate 3 such that the dummy wiring 57d overlaps the dummy source / drain region 24d in the vertical direction D3).

[0090] The first circuit wiring 57c can be electrically connected to the first circuit path 54c (e.g., by contacting the first circuit path 54c), and the second circuit wiring 57g can be electrically connected to the second circuit path 54g. The dummy wiring 57d can be electrically isolated (e.g., electrically insulated from the dummy source / drain region 24d). For example, the dummy wiring 57d can overlap with the dummy source / drain region 24d and can be electrically insulated from the dummy source / drain region 24d.

[0091] Next, with reference to Figure 2A description Figure 1B modifications to the cross-sectional structure of the region taken along line I-I'.

[0092] Figure 2A is a cross-sectional view showing Figure 1B modifications to the cross-sectional structure.

[0093] In a variant, with reference to Figure 2A , the dummy gate contact plug in Figure 1B (48dg in Figure 1B ) can be omitted. A dummy gate path 54dg (e.g., "dummy path") that penetrates the upper insulating layer 51 and contacts the upper surface of the second gate covering layer 39d can be provided. The dummy gate path 54dg can be electrically insulated from the second gate electrode (e.g., the second gate electrode 36d). Thus, the first external dummy region DA1 can include either the dummy gate contact plug (48dg in Figure 1B ) or the dummy gate path (54dg in Figure 2A ) on the second gate electrode 36d and can exclude the other (e.g., can include the dummy gate contact plug 48dg and not include the dummy gate path 54dg such that the dummy gate contact plug 48dg is electrically connected to the dummy source / drain region 24d and can be electrically insulated from the dummy wiring 57d, or can include the dummy gate path 54dg and not include the dummy gate contact plug 48dg such that the dummy gate path 54dg is electrically insulated from the dummy source / drain region 24d and can be electrically connected to the dummy wiring 57d).

[0094] Next, with reference to Figure 2B description Figure 1C modifications to the cross-sectional structure of the region taken along line II-II'.

[0095] Figure 2B is a cross-sectional view showing Figure 1C modifications to the cross-sectional structure.

[0096] In a variant, with reference to Figure 2B , the interlayer insulating layer 27 can be used to fill and remove the omitted Figure 1C dummy source / drain contact plug described inFigure 1C of the 48ds) and the second contact spacer ( Figure 1C region of the 47d). Accordingly, the entire upper surface of the dummy source / drain region 24d can be covered by the interlayer insulating layer 27.

[0097] The dummy source / drain via 54ds can be formed to penetrate the upper insulating layer 51 above the dummy source / drain region 24d and can contact the interlayer insulating layer 27. The dummy source / drain via 54ds can contact Figure 1C the dummy wiring 57d of. Accordingly, it will be understood that in some example embodiments, the first external dummy region DA1 can include one of the dummy source / drain contact plug 48ds or the dummy source / drain via 54ds, wherein when the first external dummy region DA1 includes the dummy source / drain contact plug 48ds and does not include the dummy source / drain via 54ds (e.g., as Figure 1C shown), the dummy source / drain contact plug 48ds is electrically connected to the dummy source / drain region 24d and is electrically insulated from the dummy wiring 57d, and when the first external dummy region DA1 does not include the dummy source / drain contact plug 48ds and includes the dummy source / drain via 54ds (e.g., as Figure 2B shown), the dummy source / drain via 54ds is electrically insulated from the dummy source / drain region 24d and is electrically connected to the dummy wiring 57d.

[0098] The first external dummy region DA1 can include the dummy source / drain contact plug described in Figure 1C above the dummy source / drain region 24d ( Figure 1C the 48ds in ) or Figure 2B the dummy source / drain via 54ds in, and can not include the other of them. Accordingly, the dummy source / drain region 24d can be electrically insulated from the dummy wiring 57d.

[0099] Next, a modified example of the components constituting Figure 3 the first dummy region DA1 will be described with reference to Figure 1A .

[0100] Figure 3 is a partial enlarged top view showing Figure 1A the first dummy region DA1, the first gate cut insulating region GC1, and a part of the circuit region CA.

[0101] In the modified example, referring to Figure 3 , in the first dummy region DA1, the first edge cut pattern 45b1 of Figure 1A can be omitted, and Figure 1A the first edge gate line 30e1 of Figure 1AThe first external dummy gate lines 30d1 may be connected to each other to form a dummy gate line 130d. At least as Figure 3 shown, when viewed in a top view, Figure 1A the first edge gate line 30e1 of Figure 1A and the first external dummy gate lines 30d1 of

[0102] A dummy gate line 130d may include line portions 130da and 130db and a connection portion 130dc connecting the line portions 130da and 130db. The line portions 130da and 130db may have the shape of lines or strips parallel to each other, and the connection portion 130dc may have a "U" shape.

[0103] Next, a modified example of the components constituting Figure 4 the first dummy region Da1 of Figure 1A will be described with reference to

[0104] Figure 4 is a partially enlarged top view showing Figure 1A the first dummy region DA1, the first gate cut insulating region GC1, and a part of the circuit region CA of

[0105] In the modified example, with reference to Figure 4 in the first dummy region DA1, the first edge gate line 30e1 described with reference to Figure 1A may be replaced with a first edge cut pattern ( Figure 1A 45b1 in Figure 1A ). Thus, the first dummy region DA1 may include an edge dummy pattern, at least a part of which is "U" shaped. The edge dummy pattern may be an edge cut pattern 145b, which may be formed of the same material as the material of the first gate cut pattern 45a1, or the edge dummy pattern may be the first edge gate line 30e1, which may be formed of the same material as the material of the first external dummy gate lines 30d1, and the first external dummy gate lines 30d1 are located between the edge dummy pattern (e.g., 145b or 30e1) and the first gate cut pattern 45a1. For example, the structure of the first edge gate line 30e1 of Figure 1A may be replaced with a cross-sectional structure the same as that of the first edge cut pattern 45b1 of Figure 1A The first edge gate line 30e1 of Figure 1A and the first edge cut pattern 45b1 of Figure 1AThe cross-sectional structure of the first edge cutting pattern 45b1 is the same cross-sectional structure.

[0106] Next, reference will be made to Figure 5 to describe a modification example of the components constituting Figure 1A the first dummy region DA1.

[0107] Figure 5 is a partial enlarged top view showing Figure 1A a part of the first dummy region DA1, the first gate cutting insulation region GC1, and the circuit region CA.

[0108] In the modification, referring to Figure 5 , in the first dummy region DA1, the first external dummy active region ( Figure 1A 6d1 in

[0109] ) that extends in the first horizontal direction D1 and can be (e.g., have) a linear shape can be replaced with an external dummy active region 106d including active portions that are spaced apart (e.g., isolated from each other so as not to be in direct contact) from each other in the first horizontal direction D1 and are arranged in sequence (e.g., sequentially extend, successively extend, continuously extend, etc.). It will be understood that elements that extend sequentially in one direction can be referred to as the elements in a linear order.

[0110] Each active portion of the external dummy active region 106d can have a shape of a line or a strip extending in the first horizontal direction D1. Figure 5 At least as

[0111] shown, the circuit active region 6c can include a plurality of circuit active regions 6c that are arranged in sequence (e.g., sequentially extend, successively extend, continuously extend, etc.) in the first horizontal direction D1 while facing the active portions of the external dummy active region 106d. Figure 1A Figure 1A Each active portion of the external dummy active region 106d can include a dummy active pattern 112d and a dummy base pattern 109d that overlaps the dummy active pattern 112d. The dummy active pattern 112d and the dummy base pattern 109d can respectively correspond to

[0112] Figure 5 the first dummy active pattern 12d1 of Figure 3 and Figure 4 the first dummy base pattern 9d1 of

[0113] Figure 6 Next, reference will be made to Figure 6Describe a modification of a semiconductor device according to some example embodiments.

[0114] Figure 6 is a cross-sectional view showing Figure 1B a modified example of the cross-sectional structure.

[0115] Referring to Figure 6 , the reference Figures 1A to 5 described basic patterns 9c, 9d1, 9d2, and 109d can be omitted. For example, the first dummy basic pattern 9d1 of Figure 1B and Figure 1B the circuit basic pattern 9c of Figure 1B can be omitted. Thus, the first dummy active pattern 12d1 of Figure 1B can be replaced with a dummy active pattern 212d extending in the vertical direction D3 from the upper surface 3s of the semiconductor substrate 3 (including a dummy channel region 212dc extending from the dummy active pattern 212d in the vertical direction D3). The circuit active pattern 212c ( Figure 1B 12c of

[0116] described with reference to Figure 1B ) can be replaced with a circuit active pattern 212c extending in the vertical direction D3 from the upper surface 3s of the semiconductor substrate 3 (including a circuit channel region 212cc extending from the circuit active pattern 212c in the vertical direction D3). The vertical direction D3 can be perpendicular to the upper surface 3s of the semiconductor substrate 3.

[0117] Next, a modified example of the planar structure of a semiconductor device according to some example embodiments (including the example embodiments described with reference to Figure 7A ) will be described with reference to Figure 1A .

[0118] Figure 7A is a top view that can correspond to the top view of Figure 1A .

[0119] Referring to Figure 7A , a semiconductor device 300 according to some example embodiments can include a first external dummy region DA1, a second external dummy region DA2, and a circuit region CA located between the first external dummy region DA1 and the second external dummy region DA2, which are the same as those in Figure 1ASubstantially the same as the description. The semiconductor device 300 may include a first gate cut insulating region GC1 located between the first external dummy region DA1 and the circuit region CA, and may include a second gate cut insulating region GC2 located between the second external dummy region DA2 and the circuit region CA. The second external dummy region DA2 and the circuit region CA may be substantially the same as those referred to Figure 1A Substantially the same as the description.

[0120] The circuit region CA may include a circuit active region 306c and a circuit gate line 330c. The circuit gate line 330c may have a planar shape substantially the same as that of the circuit gate line ( Figure 1A 30c) referred to in the description. Figure 1A of).

[0121] The circuit active region 306c may have a planar shape substantially similar to that of the circuit active region ( Figure 1A 6c) referred to in the description. Figure 1A of).

[0122] The circuit region CA may further include an internal dummy active region 306cd corresponding to the internal dummy active region ( Figure 1A 6cd in) located between the circuit active regions 306ca and 306cb and an internal dummy gate line 330cd corresponding to the internal dummy gate line ( Figure 1A 30cd in) referred to in the description. Figure 1A Substantially the same as the description. Figure 1A of).

[0123] The first external dummy region DA1 may further include a first external dummy active region 306d1 that may correspond to the first external dummy active region 6d1 of Figure 1A and a first external dummy gate line 330d1 that may correspond to the first external dummy gate line 30d1 of Figure 1A . The first external dummy region may further include a first edge gate line 330e1 that may correspond to the first edge gate line 30e1 of Figure 1A .

[0124] In some example embodiments, the spacing distance S1' between the first external dummy active region 306d1 and the first side circuit active region 306c1 may be different from (e.g., less than) the spacing distance S2' between the first external dummy active region 306d1 and the second side circuit active region 306c2.

[0125] The second external dummy region DA2 may include a second external dummy active region 306d2 that may correspond to the second external dummy active region 6d2 of Figure 1A and a second external dummy gate line 330d2 that may correspond to Figure 1AThe second external dummy gate line 330d2 corresponding to the second external dummy gate line 330d2. The second external dummy region DA2 may further include a second edge gate line 330e2 that may correspond to Figure 1A the second edge gate line 30e2.

[0126] The first gate cutting region GC1 may include a first gate cutting pattern 345a1 corresponding to Figure 1A the first gate cutting pattern 45a1. The second gate cutting region GC2 may include a second gate cutting pattern 345a2 corresponding to Figure 1A the second gate cutting pattern 45a2. The circuit region CA may further include a circuit gate cutting pattern 345c that may correspond to Figure 1A the circuit gate cutting pattern 45c.

[0127] The first external dummy region DA1 may further include a first edge cutting pattern 345b1 that may correspond to Figure 1A the first edge cutting pattern 45b1. The second external dummy region DA2 may further include a second edge cutting pattern 345b2 that may correspond to Figure 1A the second edge cutting pattern 45b2.

[0128] Next, reference will be made to Figure 7B and Figure 7C to describe modifications of a semiconductor device according to some example embodiments.

[0129] Figure 7B is a cross-sectional view of a region taken along line Ia-Ia' of Figure 7A to describe a semiconductor device according to some example embodiments, and Figure 7C is a cross-sectional view of a region taken along line IIa-IIa' of Figure 7A and a region taken along line IIIa-IIIa' of Figure 7A to describe a semiconductor device according to some example embodiments.

[0130] Referring to Figure 7A 、 Figure 7B and Figure 7C the semiconductor device 300 may further include a semiconductor substrate 303 and an isolation region 320 located on the semiconductor substrate 303.

[0131] The circuit active region 306c may include a circuit active pattern 312c extending in a vertical direction D3 from the upper surface 303s of the semiconductor substrate 303, and circuit active layers 312cc located on the circuit active pattern 312c and spaced apart from each other in the vertical direction D3 (e.g., isolated from each other not to be in direct contact and sequentially extending from the circuit active pattern 312c in the vertical direction D3) and adjacent to the circuit source / drain regions 324c.

[0132] The first external dummy active region 306d1 may include a dummy active pattern 312d extending in a vertical direction D3 from the upper surface 303s of the semiconductor substrate 303, and dummy active layers 312dc located on the dummy active pattern 312d and spaced apart from each other in the vertical direction D3 (e.g., isolated from each other not to be in direct contact and sequentially extending from the dummy active pattern 312d in the vertical direction D3). The isolation region 320 may define the dummy active pattern 312d and the circuit active pattern 312c and be adjacent to the dummy source / drain regions 324d.

[0133] Each circuit gate line 330c may include a first gate dielectric layer 333c, a first gate electrode 336c, and a first gate capping layer 339c. The first gate dielectric layer 333c may cover the side and bottom surfaces of the first gate electrode 336c. The first gate capping layer 339c may be disposed on the first gate electrode 336c.

[0134] Each first external dummy gate line 330d1 may include a second gate dielectric layer 333d, a second gate electrode 336d, and a second gate capping layer 339d. The second gate dielectric layer 333d may cover the side and bottom surfaces of the second gate electrode 336d. The second gate capping layer 339d may be disposed on the second gate electrode 336d.

[0135] Each first edge gate line 330e1 may include a third gate dielectric layer 333e, a third gate electrode 336e, and a third gate capping layer 339e. The third gate dielectric layer 333e may cover the side and bottom surfaces of the third gate electrode 336e. The third gate capping layer 339e may be disposed on the third gate electrode 336e.

[0136] The circuit gate lines 330c may extend onto the isolation region 320 while surrounding the corresponding circuit active layers 312cc. For example, at least as Figure 7B shown, at least one circuit gate line 330c may extend in a second horizontal direction D2 to cover the upper, bottom, and one or more (or all) side surfaces of each circuit active layer 312cc.

[0137] The first external dummy gate line 330d1 may extend over the isolation region 320 while surrounding the dummy active layer 312dc. For example, at least one first external dummy gate line 330d1 may extend in the second horizontal direction D2 to cover the upper surface, bottom surface, and one or more (or all) side surfaces of each dummy active layer 312dc.

[0138] In some example embodiments, the semiconductor device 300 may further include a circuit source / drain region 324c and a dummy source / drain region 324d.

[0139] On the circuit active pattern 312c, the circuit source / drain regions 324c may be provided in plurality and may be adjacent to the circuit active layer 312cc in the first horizontal direction D1.

[0140] On the dummy active pattern 312d, the dummy source / drain regions 324d may be provided in plurality and may be adjacent to the dummy active layer 312dc in the first horizontal direction D1.

[0141] In some example embodiments, the semiconductor device 300 may further include an interlayer insulating layer 327 over the isolation region 320.

[0142] The first circuit contact plug 348c may be provided on the circuit source / drain region 324c. The second circuit contact plug 348g penetrating the first gate capping layer 339c may be provided on the first gate electrode 336c.

[0143] In some example embodiments, the dummy source / drain contact plugs 348ds may be provided on the dummy source / drain regions 324d.

[0144] In some example embodiments, the dummy gate contact plugs 348dg may be provided on the second gate electrode 336d to penetrate the first gate capping layer 339c.

[0145] In some example embodiments, the semiconductor device 300 may further include a first gate spacer 342c, a second gate spacer 342d, and a third gate spacer 342e.

[0146] The first gate spacer 342c may be interposed between the circuit gate line 330c and the first circuit contact plug 348c and between the circuit gate line 330c and the interlayer insulating layer 327.

[0147] The second gate spacer 342d may be interposed between the first external dummy gate line 330d1 and the dummy source / drain contact plug 348ds, and may be interposed between the first external dummy gate line 330d1 and the interlayer insulating layer 327. The gate spacer 342e may be interposed between the first edge gate line 330e1 and the interlayer insulating layer 327.

[0148] In some example embodiments, the semiconductor device 300 may further include a first contact spacer 347c and a second contact spacer 347d. The first contact spacer 347c and the second contact spacer 347d may be formed of an insulating material such as silicon oxide.

[0149] The first contact spacer 347c may surround a side surface of the first circuit contact plug 348c. The second contact spacer 347d may surround a side surface of the dummy source / drain contact plug 348ds.

[0150] In some example embodiments, the semiconductor device 300 may further include an upper insulating layer 351 disposed on the interlayer insulating layer 327, the circuit gate line 330c, the first external dummy gate line 330d1, and the first edge gate line 330e1.

[0151] In some example embodiments, the semiconductor device 300 may further include a first circuit via 354c and a second circuit via 354g that penetrate the upper insulating layer 351.

[0152] The first circuit via 354c may be in contact with the first circuit contact plug 348c, and the second circuit via 354g may be in contact with the second circuit contact plug 348g.

[0153] In some example embodiments, the semiconductor device 300 may include a first circuit wiring 357c, a second circuit wiring 357g, and a dummy wiring 357d, which are disposed at the same height level on the upper insulating layer 351.

[0154] The first circuit wiring 357c may be electrically connected to the first circuit via 354c, and the second circuit wiring 357g may be electrically connected to the second circuit via 354g. The dummy wiring 357d may overlap with the dummy source / drain region 324d and may be electrically insulated from the dummy source / drain region 324d.

[0155] In some example embodiments, the dummy source / drain contact plug 348ds may be omitted. However, as Figure 2B shown, a dummy source / drain via ( Figure 2B 54ds in

[0156] In some example embodiments, the first externally dummy active region 306d1 and the circuit active region 306c may respectively replace Figures 1A to 5 the first externally dummy active region 6d1 and the circuit active region 6c shown.

[0157] According to some example embodiments, by providing a first externally dummy region DA1 and a second externally dummy region DA2 adjacent to the circuit region CA, the reliability of the circuit active regions 6c and 306c at the ends of the circuit gate lines 30c and 330c in the second horizontal direction D2 can be improved.

[0158] According to some example embodiments, the semiconductor devices 1 and 300 may include a first externally dummy region DA1 and a second externally dummy region DA2 adjacent to the circuit region CA, thereby preventing a reduction in the reliability of the circuit active regions 6c and 306c even when the sizes of the circuit active regions 6c and 306c are reduced to increase the integration degree.

[0159] Therefore, it is possible to provide a semiconductor device having a planar layout capable of improving the reliability of the circuit active regions 6c and 306c at the ends of the circuit gate lines 30c and 330c in the second horizontal direction D2, and a semiconductor device having a cross-sectional structure provided by such a layout.

[0160] As described above, according to some example embodiments, it is possible to provide a layout capable of improving the reliability of a circuit active region adjacent to an end of a gate line, and a semiconductor device provided by such a layout.

[0161] Although example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A first external dummy region; A second external dummy region; And A circuit region, the circuit region being located between the first external dummy region and the second external dummy region, Wherein, the circuit region includes a circuit active region and circuit gate lines, Wherein, the first external dummy region includes a first external dummy active region and a first external dummy gate line that overlaps with the first external dummy active region in the vertical direction, and the first external dummy gate line is isolated from not directly contacting the circuit gate lines, Wherein, the second external dummy region includes a second external dummy active region and a second external dummy gate line that overlaps with the second external dummy active region in the vertical direction, and the second external dummy gate line is isolated from not directly contacting the circuit gate lines, Wherein, each of the first external dummy active region and the second external dummy active region has: A linear shape extending in a first horizontal direction, or A shape including active portions isolated from not directly contacting each other and sequentially extending in the first horizontal direction, Wherein, the circuit gate lines all extend in a second horizontal direction perpendicular to the first horizontal direction, and Wherein, the circuit active region is located between the first external dummy active region and the second external dummy active region in the second horizontal direction, and the circuit active region includes: A first plurality of circuit active regions sequentially extending in the first horizontal direction, and A second plurality of circuit active regions sequentially extending in the second horizontal direction.

2. The semiconductor device according to claim 1, the semiconductor device further comprising: A first gate cut insulating region, the first gate cut insulating region being located between the first external dummy region and the circuit region; And A second gate cut insulating region, the second gate cut insulating region being located between the second external dummy region and the circuit region, Wherein, the first gate cut insulating region includes a first gate cut pattern located between the circuit gate lines and the first external dummy gate lines, Wherein, the second gate cut insulating region includes a second gate cut pattern located between the circuit gate lines and the second external dummy gate lines.

3. The semiconductor device according to claim 1, wherein, The first external dummy region further includes a first edge gate line, The first external dummy gate line is located between the first edge gate line and the circuit gate lines, The first external dummy gate line has a shape of lines or strips parallel to each other, and At least a part of the first edge gate line is in a "U" shape.

4. The semiconductor device according to claim 3, wherein, The first external dummy region further includes a first edge cut pattern, the first edge cut pattern being located between the first edge gate line and the first external dummy gate line to isolate the first edge gate line and the first external dummy gate line from not directly contacting each other.

5. The semiconductor device according to claim 3, wherein, When observed in a top view, the first edge gate line and the first external dummy gate line are part of a single continuous material block.

6. The semiconductor device according to claim 3, wherein, the first externally dummy active region includes active portions that are isolated from each other and do not directly contact each other while sequentially extending in the first horizontal direction, each of the active portions has a shape of a line or a strip extending in the first horizontal direction, and the circuit active region includes an active region that sequentially extends in the first horizontal direction while facing the active portions of the first externally dummy active region.

7. The semiconductor device according to claim 1, wherein, the circuit active region includes a first-side circuit active region and a second-side circuit active region, both the first-side circuit active region and the second-side circuit active region are adjacent to the first externally dummy active region, the distance between the first externally dummy active region and the first-side circuit active region is less than the distance between the first externally dummy active region and the second-side circuit active region, and no other circuit active regions of the circuit active region are located between the first externally dummy active region and the first-side circuit active region, and are not located between the first externally dummy active region and the second-side circuit active region.

8. The semiconductor device according to claim 1, the semiconductor device further includes: a first gate cut pattern that isolates the circuit gate line and the first externally dummy gate line from directly contacting each other, the first gate cut pattern is located between the circuit gate line and the first externally dummy gate line, wherein, the first externally dummy region further includes a first edge cut pattern, wherein, the first externally dummy gate line is located between the first edge cut pattern and the first gate cut pattern, wherein, the first gate cut pattern and the first edge cut pattern include the same insulating material, wherein, the first externally dummy gate line has a shape of lines or strips parallel to each other, and wherein, at least a part of the first edge cut pattern has a "U" shape.

9. The semiconductor device according to claim 1, wherein, the circuit region further includes an internally dummy active region, the circuit active region is isolated from each other and does not directly contact each other in the first horizontal direction, the circuit active region includes a first circuit active region and a second circuit active region that are isolated from each other and do not directly contact each other at a distance greater than an allowable distance range, among the circuit active regions that sequentially extend in the first horizontal direction, the remaining circuit active regions other than the first circuit active region and the second circuit active region are isolated from each other and do not directly contact each other within the allowable distance range, and the internally dummy active region is located between the first circuit active region and the second circuit active region.

10. The semiconductor device according to claim 9, wherein, The distances between the first circuit active region and the internally dummy active region and between the second circuit active region and the internally dummy active region are both within the allowable distance range.

11. The semiconductor device according to claim 1, wherein, the circuit region further includes: a circuit source / drain region located on the circuit active region, A circuit contact plug located on the circuit source / drain region such that the circuit contact plug is configured to be electrically connected to the circuit source / drain region, A circuit path located on the circuit contact plug such that the circuit path is configured to be electrically connected to the circuit contact plug, and A circuit wiring electrically connected to the circuit path, The first external dummy region further includes: A dummy source / drain region located on the first external dummy active region, and A dummy wiring overlapping with the dummy source / drain region in the vertical direction and located at the same height level as the circuit wiring, and The dummy wiring is electrically insulated from the dummy source / drain region.

12. The semiconductor device according to claim 11, wherein, The first external dummy region further includes a dummy contact plug and does not include a dummy path, such that the dummy contact plug is electrically connected to the dummy source / drain region and is electrically insulated from the dummy wiring, or The first external dummy region further includes a dummy path and does not include a dummy contact plug, such that the dummy path is electrically insulated from the dummy source / drain region and is electrically connected to the dummy wiring.

13. The semiconductor device according to claim 1, wherein, The circuit region further includes: A circuit source / drain region located on the circuit active region, A circuit contact plug located on the circuit source / drain region such that the circuit contact plug is configured to be electrically connected to the circuit source / drain region, A circuit path located on the circuit contact plug such that the circuit path is configured to be electrically connected to the circuit contact plug, and A circuit wiring electrically connected to the circuit path, The first external dummy region further includes a dummy source / drain region located on the first external dummy active region, The first external dummy region further includes a dummy contact plug and does not include a dummy path, such that the dummy contact plug is electrically connected to the dummy source / drain region, or the first external dummy region further includes a dummy path and does not include a dummy contact plug, such that the dummy path is electrically insulated from the dummy source / drain region.

14. The semiconductor device according to claim 1, wherein, The circuit region further includes a circuit source / drain region, The first external dummy region further includes a dummy source / drain region, Each circuit active region in the circuit active region includes a circuit active pattern and a circuit channel region extending in the vertical direction from the circuit active pattern and adjacent to the circuit source / drain region, The first external dummy active region includes a dummy active pattern and a dummy channel region extending in the vertical direction from the dummy active pattern and adjacent to the dummy source / drain region, At least one of the circuit gate lines covers the upper surface and the side surface of the circuit channel region, and At least one of the first external dummy gate lines covers the upper surface and the side surfaces of the dummy channel region.

15. The semiconductor device according to claim 1, wherein, the circuit region further includes a circuit source / drain region, the first external dummy region further includes a dummy source / drain region, each of the circuit active regions in the circuit active region includes a circuit active pattern and a circuit active layer located on the circuit active pattern, the circuit active layers being isolated from each other and not in direct contact, and sequentially extending from the circuit active pattern in the vertical direction and adjacent to the circuit source / drain region, the first external dummy active region includes a dummy active pattern and a dummy active layer located on the dummy active pattern, the dummy active layers being isolated from each other and not in direct contact, and sequentially extending from the dummy active pattern in the vertical direction and adjacent to the dummy source / drain region, at least one of the circuit gate lines extends in the second horizontal direction to cover the upper surface, the bottom surface, and the side surfaces of each of the circuit active layers in the circuit active layer, and at least one of the first external dummy gate lines extends in the second horizontal direction to cover the upper surface, the bottom surface, and the side surfaces of each of the dummy active layers in the dummy active layer.

16. The semiconductor device according to claim 1, wherein, At least one of the first external dummy active region or the second external dummy active region extends farther in the first horizontal direction than the end of the circuit active region which is the last one of the circuit active regions sequentially extending in the first horizontal direction.

17. A semiconductor device, the semiconductor device comprising: a circuit region; an external dummy region adjacent to the circuit region; and a gate cut isolation region located between the circuit region and the external dummy region, wherein the external dummy region includes an external dummy active region and an external dummy gate line overlapping with the external dummy active region in the vertical direction, wherein the circuit region includes: a circuit active region facing the external dummy active region and sequentially extending in a first horizontal direction, and a circuit gate line overlapping with the circuit active region in the vertical direction, wherein the external dummy active region has: a linear shape extending in the first horizontal direction, or a shape including active portions isolated from each other and not in direct contact and sequentially extending in the first horizontal direction, wherein the gate cut isolation region includes a gate cut pattern located between the circuit gate line and the external dummy gate line and isolating the circuit gate line and the external dummy gate line from being in direct contact with each other, and wherein the gate cut pattern sequentially extends in the first horizontal direction.

18. The semiconductor device according to claim 17, wherein, the external dummy region further includes an edge dummy pattern, At least a part of the edge dummy pattern is in a "U" shape. The external dummy gate line is located between the edge dummy pattern and the gate cut pattern, and the edge dummy pattern is: an edge gate line formed of the same material as that of the external dummy gate line, or an edge cut pattern formed of the same material as that of the gate cut pattern.

19. A semiconductor device, the semiconductor device comprising: a circuit region; and an external dummy region adjacent to the circuit region, wherein the external dummy region includes: an external dummy active region extending in a first horizontal direction, and an external dummy gate line overlapping the external dummy active region in a vertical direction and extending in a second horizontal direction perpendicular to the first horizontal direction, wherein the circuit region includes: a circuit active region facing the external dummy active region and sequentially extending in the first horizontal direction, and a circuit gate line overlapping the circuit active region in the vertical direction and extending parallel in the second horizontal direction, wherein the external dummy active region has: a linear shape extending in the first horizontal direction, or a shape including active portions isolated from each other and not in direct contact and sequentially extending in the first horizontal direction, wherein the circuit active region includes a first-side circuit active region and a second-side circuit active region, and both the first-side circuit active region and the second-side circuit active region are adjacent to the external dummy active region, wherein the distance between the external dummy active region and the first-side circuit active region is less than the distance between the external dummy active region and the second-side circuit active region, and wherein no other circuit active regions in the circuit active region are located between the external dummy active region and the first-side circuit active region, and are not located between the external dummy active region and the second-side circuit active region.

20. The semiconductor device according to claim 19, the semiconductor device further comprising: a semiconductor substrate; and an isolation region located on the semiconductor substrate, wherein each circuit active region in the circuit active region includes a circuit base pattern and one or more circuit active patterns extending in the vertical direction from the circuit base pattern, wherein the external dummy active region includes a dummy base pattern and one or more dummy active patterns extending in the vertical direction from the dummy base pattern, wherein the width of the circuit base pattern in the second horizontal direction is greater than the width of each circuit active pattern in the one or more circuit active patterns in the second horizontal direction, and wherein the width of the dummy base pattern in the second horizontal direction is greater than the width of each dummy active pattern in the one or more dummy active patterns in the second horizontal direction.

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