Semiconductor structure

Abstract

A semiconductor structure includes: a substrate, a gate structure on the substrate, and source and drain structures on both sides of the gate structure. The gate structure includes a gate electrode disposed on the substrate and a gate metal layer disposed on the gate electrode. The gate metal layer has at least one notch, and the notch exposes the gate electrode below. The potential of the source structure is different from the potential of the gate structure.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures having gate field plates. Background Technology

[0002] Gallium nitride (GaN)-based semiconductor materials possess many excellent material properties, such as high heat resistance, wide bandgap, and high electron saturation velocity. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light-emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

[0003] With the development of gallium nitride (GaN)-based semiconductor materials, semiconductor devices using these materials are being applied in more demanding operating environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, semiconductor devices using GaN-based materials still require further improvement to overcome the challenges they present. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor structure comprising: a substrate, a gate structure on the substrate, and source and drain structures on the substrate and on both sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, and the notch exposes the aforementioned gate electrode below. The potential of the source structure is different from the potential of the gate structure.

[0005] Some embodiments of the present invention also provide a semiconductor structure comprising: a substrate, a gate structure on the substrate, and source and drain structures on the substrate and on both sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. In a top view of the gate electrode and the gate metal layer projected onto the substrate, the gate metal layer is U-shaped and partially overlaps with the gate electrode. Attached Figure Description

[0006] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0007] Figure 1This is a partial perspective view of an exemplary semiconductor structure, drawn according to some embodiments of the present invention;

[0008] Figure 2 The present invention provides a perspective view illustrating an exemplary portion of a semiconductor structure.

[0009] Figure 3 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 A partial top-projected view of the semiconductor structure shown;

[0010] Figures 4 to 11 This is a partial projected top view of a semiconductor structure according to another embodiment of the present invention;

[0011] Figure 12 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 The diagram shows a cross-sectional view of the semiconductor structure along line segment A-A'.

[0012] Figure 13 A partial perspective view of an exemplary semiconductor structure is shown in another embodiment of the present invention.

[0013] Figure 14 According to other embodiments of the present invention, the diagrams corresponding to Figure 13 The diagram shows a cross-sectional view of the semiconductor structure along line segment B-B'.

[0014] Figure 15 A cross-sectional schematic diagram of a semiconductor structure is shown in another embodiment of the present invention;

[0015] Figure 16 A partial perspective view of an exemplary semiconductor structure is shown according to other embodiments of the present invention.

[0016] Figure 17 A partial perspective view of an exemplary semiconductor structure is shown according to other embodiments of the present invention.

[0017] Figure 18 According to other embodiments of the present invention, the diagrams corresponding to Figure 17 The diagram shows a cross-sectional view of the semiconductor structure along line C-C'.

[0018] [Symbol Explanation]

[0019] 100, 200, 300, 400 ~ Semiconductor Structure

[0020] 102~Substrate

[0021] 110 ~ Compound semiconductor layer

[0022] 112 ~ Buffer Layer

[0023] 114~Channel Layer

[0024] 116 ~ Barrier Layer

[0025] 120, 130 ~ Dielectric layer

[0026] 140 ~ Source Structure

[0027] 142 ~ Source Electrode

[0028] 144 ~ Source Contact

[0029] 146 ~ Source Metal Layer

[0030] 147~(Opening of the source metal layer)

[0031] 148 ~ Source Metal Layer

[0032] 149 ~ (The opening of the additional source metal layer)

[0033] 150~ Gate structure

[0034] 152 ~ Gate electrode

[0035] 154 ~ Gate metal layer

[0036] 154a – Outline of the gate metal layer on both sides of the notch

[0037] 155 ~ (Gate metal layer) notch

[0038] 156 ~ Doped compound semiconductor layer

[0039] 160~Drain structure

[0040] 162 - Drain electrode

[0041] 164 - Drain Contact

[0042] 166 ~ Drain metal layer

[0043] 170 ~ Dielectric layer

[0044] L ~ Length

[0045] T1 ~ Thickness

[0046] WN ~ (width of the gap)

[0047] WG ~ (gate electrode width)

[0048] WGM1 ~ (Minimum width of the gate metal layer)

[0049] WGM2 ~ (Maximum width of the gate metal layer)

[0050] WO1 ~ (width of the opening in the source metal layer)

[0051] WO2 ~ (width of the opening in the additional source metal layer)

[0052] A-A', B-B', C-C' ~ Sections (Section Lines) Detailed Implementation

[0053] Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When the description refers to a first component being formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, the embodiments of the invention may use repeated component symbols in many examples. These repetitions are for simplicity and clarity only and do not represent a specific relationship between the various embodiments and / or configurations discussed.

[0054] Furthermore, spatial terms such as "above," "below," "above," "below," and similar terms encompass not only the orientation shown in the diagram but also the different orientations of the device in use or operation. When the device is turned to another orientation (rotated 90 degrees or to another orientation), the spatial relative descriptions used here can also be interpreted according to the orientation after rotation.

[0055] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0056] The semiconductor structure provided in this invention reduces the risk of the gate structure being subjected to a high electric field by extending the gate metal layer along the direction of the drain structure and serving as a gate field plate. Furthermore, the gate field plate has at least one notch to effectively reduce the gate-to-drain capacitance (C). gd ) and gate-to-source capacitance (C gs This reduces switching losses and also minimizes malfunctions during rapid switching. Therefore, the semiconductor structure provided in this embodiment of the invention can reduce input capacitance (C...). gs +C gd This can more effectively reduce switching losses, thereby improving the performance of the semiconductor structure.

[0057] Figure 1 According to some embodiments of the present invention, a partial perspective three-dimensional view of an exemplary semiconductor structure is shown. As Figure 1 shown, the semiconductor structure 100 includes a compound semiconductor layer 110 on a substrate 102, a dielectric layer 120 on the compound semiconductor layer 110, and a dielectric layer 130. The semiconductor structure 100 also includes a gate structure 150 on the semiconductor compound layer 110, and source and drain structures 140 and 160 on both sides of the gate structure.

[0058] In some embodiments, the substrate 102 may be a doped (e.g., doped with p-type or n-type dopants) or undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or a similar semiconductor substrate. In some embodiments, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate. In other embodiments, the substrate 102 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide substrate (Al2O3) (or sapphire substrate), or other similar substrates.

[0059] In some embodiments, the compound semiconductor layer 110 includes a buffer layer 112, a channel layer 114 on the buffer layer 112, and a barrier layer 116 on the channel layer 114. The buffer layer 112 can relieve the strain of the channel layer 114 formed subsequently on the buffer layer 112 to prevent defects from forming in the overlying channel layer 114. The strain is caused by the mismatch between the channel layer 114 and the substrate 102. In some embodiments, the material of the buffer layer 112 can be AlN, GaN, Al x Ga 1-x N (where 0 < x < 1), the foregoing combinations, or other similar materials. The buffer layer 112 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), the foregoing combinations, or similar methods. It should be noted that although the buffer layer 112 is a single-layer structure in the Figure 1 shown embodiment, the buffer layer 112 can also be a multi-layer structure (not shown) in other embodiments.

[0060] In some embodiments, a two-dimensional electron gas (2DEG) (not shown) is formed at the heterogeneous interface between the channel layer 114 and the barrier layer 116. For example... Figure 1 The semiconductor structure 100 shown is a high electron mobility transistor (HEMT) that utilizes a two-dimensional electron gas (2DEG) as the conductive carrier. In some embodiments, the channel layer 114 may be a gallium nitride (GaN) layer, and the barrier layer 116 formed on the channel layer 114 may be an aluminum gallium nitride (AlGaN) layer, wherein the gallium nitride layer and the aluminum gallium nitride layer may be doped (e.g., n-type doped or p-type doped) or undoped. Both the channel layer 114 and the barrier layer 116 may be formed by epitaxial growth processes, such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), combinations thereof, or other similar methods.

[0061] Continue to refer to Figure 1 Next, dielectric layers 120 and 130, gate structure 150, and source structure 140 and drain structure 160 on both sides of gate structure 150 are formed on compound semiconductor layer 110 by deposition and patterning processes.

[0062] In some embodiments, the gate structure 150 includes a gate electrode 152 and a gate metal layer 154 electrically connected to the gate electrode 152. In some embodiments, the gate electrode 152 is disposed on a barrier layer 116 and buried in a dielectric layer 120, while the gate metal layer 154 is disposed on the dielectric layer 120 and covered by a dielectric layer 130. In other embodiments, an optional doped compound semiconductor layer 156 may be included between the gate electrode 152 and the barrier layer 116, details of which will be described further later.

[0063] In some embodiments, the source structure 140 includes a source electrode 142, a source contact 144, and a source metal layer 146. In some embodiments, the source electrode 142 is embedded in a dielectric layer 120, and the source metal layer 146 is disposed on a dielectric layer 130, wherein the source electrode 142 and the source metal layer 146 are electrically connected via the source contact 144 embedded in the dielectric layer 130. The potential of the source metal layer 146 electrically connected to the source electrode 142 is different from the potential of the gate metal layer 154 electrically connected to the gate electrode 152. In this embodiment, the source metal layer 146 reduces the electric field strength by extending along the direction of the drain structure and serving as a source field plate.

[0064] In some embodiments, the drain structure 160 includes a drain electrode 162, a drain contact 164, and a drain metal layer 166. In some embodiments, the drain electrode 162 is buried in the dielectric layer 120, and the drain metal layer 166 is disposed on the dielectric layer 130, wherein the drain electrode 162 and the drain metal layer 166 are electrically connected by the drain contact 164 buried in the dielectric layer 130. In some embodiments, the source electrode 142 and the drain electrode 162 on both sides of the gate electrode 152 pass through the barrier layer 116 and contact the channel layer 114.

[0065] In some embodiments, the gate electrode 152 may be made of a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or the aforementioned multilayer structures. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The aforementioned conductive material may be formed on the barrier layer 116 by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods, and then the gate electrode 152 may be formed by a patterning process.

[0066] In some embodiments, before forming the gate electrode 152, a doped compound semiconductor layer 156 may be formed on the barrier layer 116, and then the gate electrode 152 may be formed on the doped compound semiconductor layer 156. By disposing the doped compound semiconductor layer 156 between the gate electrode 152 and the barrier layer 116, the generation of two-dimensional electron gas (2DEG) below the gate electrode 152 can be suppressed, thereby achieving the normally off state of the semiconductor structure 100. In some embodiments, the material of the doped compound semiconductor layer 156 may be gallium nitride (GaN) doped with p-type or n-type. The step of forming the doped compound semiconductor layer 156 may include forming it at the location corresponding to the predetermined formation of the gate electrode 152 by epitaxial growth and etch-back processes.

[0067] In some embodiments, the materials of the source electrode 142 and drain electrode 162 formed on both sides of the gate electrode 152 may be selected from the materials used to form the gate electrode 152. Furthermore, the gate electrode 152 and the source electrode 142 and drain electrode 162 on both sides thereof may be formed in the same process, and therefore will not be described further here. In other embodiments, the gate electrode 152 and the source electrode 142 and drain electrode 162 on both sides thereof may be formed in different processes.

[0068] In some embodiments, the gate metal layer 154, source contact 144, source metal layer 146, drain contact 164, and drain metal layer 166 may be formed by deposition and patterning processes, and the materials may include conductive materials such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxides, metal alloys, other suitable conductive materials, or combinations thereof.

[0069] In some embodiments, dielectric layers 120 and 130 may each comprise one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric materials, and / or other suitable dielectric materials. Low dielectric constant dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), other suitable methods, or combinations thereof can be used to form dielectric layers 120 and 130.

[0070] Continue to refer to Figure 1 According to some embodiments of the present invention, the semiconductor structure 100 has a length direction X, a width direction Y, and a height direction Z. In this embodiment, the direction toward the source structure is defined as the -Y direction, and the direction toward the drain structure is defined as the +Y direction.

[0071] Continue to refer to Figure 1 According to some embodiments of the present invention, the gate metal layer 154 has a notch 155 and exposes the underlying gate electrode 152 to improve switching speed. In other words, the dielectric layer 130 passes through the notch in the gate metal layer 154 and directly contacts the gate electrode 152. Compared to the comparative embodiment where the gate metal layer has no notch, in the embodiments of the present invention, the dielectric layer covering the gate metal layer passes through the gate metal layer and contacts the gate electrode.

[0072] In some embodiments, as viewed in the above view, the notch 155 may be oriented towards the direction of the source structure (-Y direction) to simultaneously reduce the gate-to-source capacitance (C). gs ) and gate-to-drain capacitance (C gd ).

[0073] Compared to the high electron mobility transistor (HEMT) device of the comparative embodiment, it places a field plate structure in the high electric field region of the semiconductor device to reduce the peak electric field in the high electric field region. One type of field plate is a field plate connected to the source (i.e., source field plate), and the other type is a field plate connected to the gate (i.e., gate field plate), both of which can reduce the electric field strength of the gate on the drain side. However, the configuration of the field plate structure increases the gate-to-drain capacitance (C). gd ) and gate-to-source capacitance (C gs The significant increase in switching losses leads to severe switching losses.

[0074] Therefore, in some embodiments of the present invention, by creating at least one notch 155 in the gate metal layer 154, the coverage of the source field plate (source metal layer 146) over the gate field plate (gate metal layer 154) can be reduced, thereby reducing the gate-to-source capacitance (C). gs This also reduces the coverage of the gate field plate over the two-dimensional electron gas (2DEG) (not shown) formed between the channel layer 114 and the barrier layer 116, and also reduces the gate-to-drain capacitance (C). gd ). In reducing input capacitance (C) gs +C gdAt the same time, it improves the switching speed and reduces switching loss. It is worth noting that the coverage of the source metal layer 146 over the gate metal layer 154 provided in this embodiment of the invention is only illustrative and can be adjusted according to the actual product design and the required switching speed.

[0075] Now refer to Figure 2 . Figure 2 The present invention provides a perspective view illustrating an exemplary portion of a semiconductor structure. Figure 2 Only a perspective view of the gate electrode 152 and the gate metal layer 154 is shown, and it is also applicable to... Figure 1 The X, Y, and Z directions are used to describe their relative positions. The gate metal layer 154 has a thickness T1 (in the Z direction), a maximum width WGM1, a minimum width WGM2 (in the Y direction), and a length L (in the X direction) on both sides of the notch 155. The notch 155 has a width WN (in the Y direction), while the gate electrode 152 has a width WG (in the Y direction).

[0076] In one embodiment, the minimum width WGM2 of the gate metal layer 154 is greater than or equal to the difference between the maximum width WGM1 of the gate metal layer 154 and the width WG of the gate electrode 152. That is, the width WN of the notch 155 is less than or equal to the width WG of the gate electrode 152. For example, the width WG of the gate electrode 152 is 1 μm, while the width WN of the notch 155 can be 1 μm, 0.5 μm, or 0.2 μm. When the width WN of the notch is greater than the width WG of the gate electrode, a drop in breakdown voltage is more likely to occur.

[0077] In one embodiment, the length L of the gate metal layer 154 on both sides of the notch 155 is greater than or equal to five times the thickness T1 of the gate metal layer 154. For example, the thickness T1 of the gate electrode 152 is 0.2 μm, while the length L of the gate metal layer 154 can be 1 μm, 1.5 μm, or 2 μm. When the length L of the gate metal layer 154 on both sides of the notch 155 is less than five times the thickness T1 of the gate metal layer 154, device failure is likely to occur.

[0078] It should be understood that, in order to concisely describe the embodiments of the present invention and highlight its technical features, [the invention is not described in detail here]. Figure 1 All components of the semiconductor structure 100 shown are illustrated in Figure 2 middle.

[0079] Figure 3 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 The top view of a partial projection of the semiconductor structure shown. Figure 3 Also applicable Figure 1The coordinates in, however Figure 3 This is a planar view, therefore only showing the X and Y directions. In the top view of the gate electrode 152 and gate metal layer 154 projected onto the substrate 102, the gate metal layer 154 is U-shaped, and the gate metal layer 154 partially overlaps with the gate electrode 152, as shown... Figure 3 As shown. The overlap area between the gate metal layer 154 and the gate electrode 152 can occupy approximately 10%, approximately 30%, approximately 50%, or approximately 70% of the area of ​​the gate electrode 152, in order to reduce the input capacitance (C) while reducing the electric field strength. gs +C gd ).

[0080] Continue to refer to Figure 3 In some embodiments, the notch 155 exposes one side of the gate electrode 152, and the notch 155 is aligned with the other side of the gate electrode 152. That is, the width WN of the notch is the same as the width WG of the gate electrode, and the notch faces the -Y direction. In some embodiments, the gate metal layers 154 on both sides of the notch 155 can have the same shape; that is, the gate metal layers 154 are symmetrical with respect to the centerline of the gate metal layers 154 in the length direction (X direction). In some embodiments, the gate metal layers 154a on both sides of the notch 155 can have a rectangular outline; that is, the notch 155 can be rectangular. Figure 3 In the illustrated embodiment, the width WN of the notch can be adjusted according to the actual product design and the required switching speed, so that the area of ​​the gate electrode exposed by the notch varies.

[0081] Figures 4 to 11 This is a partial projected top view of a semiconductor structure according to another embodiment of the present invention. Figures 4 to 11 Also applicable Figure 3 The coordinates in the figure have X and Y directions (not shown). In the top view of the gate electrode 152 and the gate metal layer 154 projected onto the substrate 102, the gate metal layer 154 may have two notches 155, such as Figure 4 As shown, or four gaps of 155, as Figure 5 As shown. The gate metal layer 154 can also be in a comb shape, such as... Figure 5 As shown. It should be noted that, although at Figure 4 and Figure 5 Only a limited number of gaps are shown in the diagram, but improvements can be made according to actual needs, and this is not the only limitation.

[0082] In some embodiments, the plurality of notches 155 in the gate metal layer 154 may have the same shape and size as each other, such as Figure 4 The figures shown can also be different, such as Figure 6As shown. That is, the switching speed can be adjusted by changing the size of the notch according to the actual situation. Specifically, the larger the notch's width, the greater the input capacitance (C). gs +C gd The lower the value of ), the faster the switching speed.

[0083] In some embodiments, the gate metal layer 154 on both sides of the notch 155 on the gate electrode 152 may have an arcuate profile or a trapezoidal profile, such as Figure 7 As shown. In some embodiments, the notch 155 can be triangular, such as... Figure 8 As shown, notch 155 can also be trapezoidal, such as... Figure 9 As shown. The area and shape of the gate electrode exposed by the notch affect the shape and area of ​​the gate metal layer on both sides of the notch, and can therefore be adjusted according to the actual product design and the required switching speed.

[0084] In some embodiments, the notch 155 can vary linearly along the gate electrode; that is, the width of the gate metal layer can vary linearly along the extension direction of the gate electrode, such as... Figure 9 As shown, the width of the gate metal layer varies in different electron flow directions within the semiconductor structure, thus reducing C gd At the same time, it suppresses the excessive rise of the gate resistance (Rg), thereby improving the switching speed of the device.

[0085] In some embodiments, portions of the gate metal layer 154 on both sides of the notch 155 extend beyond the gate electrode 152, such as... Figure 10 As shown. The area of ​​the gate metal layer extending beyond the gate electrode on both sides of the notch can be twice the area of ​​the gate metal layer overlapping the gate electrode. The area of ​​the gate metal layer extending beyond the gate electrode can be adjusted to achieve the desired switching speed.

[0086] In some embodiments, the notch 155 exposes one side of the gate electrode 152 and covers the other side of the gate electrode 152; that is, the width of the notch 155 is smaller than the width of the gate electrode 152. Figure 11 As shown, when C is reduced gd At the same time, it suppresses the excessive rise of the gate resistance (Rg), thereby improving the switching speed of the device.

[0087] It should be understood that, in order to concisely describe the embodiments of the present invention and highlight its technical features, [the invention is not described in detail here]. Figure 1 All components of the semiconductor structure 100 shown are illustrated in Figures 3 to 11 middle.

[0088] Figure 12 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 The diagram shows a cross-sectional view of the semiconductor structure along line segment A-A'. Figure 12 Also applicable Figure 1 The coordinates in, however Figure 12 It is a planar diagram, therefore it only has the Y and Z directions. Figure 12 In the illustrated embodiment, the source metal layer 146 extends toward the drain structure 160 (in the +Y direction) and extends beyond the gate metal layer 154 to optimize the electric field distribution and effectively reduce the electric field strength of the gate electrode on the drain side.

[0089] Please refer to the matching instructions. Figures 13 to 15 . Figure 13 According to other embodiments of the present invention, a partial perspective view of an exemplary semiconductor structure is drawn, and Figure 14 According to other embodiments of the present invention, the diagrams corresponding to Figure 13 The diagram shows a cross-sectional view of the semiconductor structure along line segment B-B'. Additionally, Figure 15 This is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0090] Figure 13 Also applicable Figure 1 The X, Y, and Z directions, and Figure 14 and 15 Also applicable Figure 12 The Y and Z directions are used to describe their relative positions.

[0091] Figure 13 The semiconductor structure shown in the figure is roughly similar to 200. Figure 1 The semiconductor structure 100 differs from the semiconductor structure 200 in that the source metal layer 146 has an opening 147 to further reduce the gate-to-source capacitance (C). gs ).exist Figure 14 and Figure 15 In the cross-sectional view shown, the opening 147 in the source metal layer 146 has a width WO1, the gate electrode 152 has a width WG, and the gate metal layer 154 has a width WGM2.

[0092] In some embodiments, since the side of the gate electrode 152 facing the drain structure 160 (+Y direction) is adjacent to the side of the gate metal layer 154 facing the source structure 140 (-Y direction), the width of the opening 147 can be less than the sum of the width WG of the gate electrode 152 and the width WGM2 of the gate metal layer 154, such as... Figure 14As shown. In this embodiment, the projections of the source metal layer 146, the gate metal layer 154, and the gate electrode 152 onto the substrate 102 are such that the source metal layer 146 partially overlaps with both the gate metal layer 154 and the gate electrode 152. In other embodiments, the width of the opening 147 may also be greater than the sum of the width WG of the gate electrode 152 and the width WGM2 of the gate metal layer 154 (not shown).

[0093] Because the notch 155 in the gate metal layer 154 exposes the gate electrode 152, the source-to-gate capacitance (C) is reduced. gs Furthermore, the opening 147 of the source metal layer 146 further reduces the coverage area between the source metal layer 146 and the gate structure 150, thus further reducing the source-to-gate capacitance (C). gs To adjust the switching speed.

[0094] In other embodiments, the width WO1 of the opening 147 can be equal to the sum of the width WG of the gate electrode 152 and the width WGM2 of the gate metal layer 154, such as... Figure 15 As shown. In this embodiment, the two sides of the opening 147 are substantially aligned with the side of the gate metal layer 154 facing the drain structure 160 (+Y direction) and the side of the gate electrode 152 facing the source structure 140 (-Y direction). That is, the projection of the source metal layer 146, the gate metal layer 154, and the gate electrode 152 onto the substrate 102 is such that the opening 147 is aligned with the gate metal layer 154 and the gate electrode 152, in order to further reduce the gate-to-source capacitance (C). gs ).

[0095] By providing an opening on the source metal layer and adjusting the size of the opening according to actual needs, the source-to-gate capacitance (C) can be further reduced. gs To adjust the switching speed.

[0096] Figure 16 The present invention provides some embodiments thereof, which illustrate a partial perspective view of an exemplary semiconductor structure. Figure 16 Also applicable Figure 1 The X, Y, and Z directions are used to describe their relative positions.

[0097] Figure 16 The semiconductor structure shown in the figure is roughly similar to 300. Figure 1 The semiconductor structure 100 differs from the semiconductor structure 300 in that it also includes an additional source metal layer 148. Specifically, the semiconductor structure 300 also includes a dielectric layer 170 on the source metal layer 146 and the dielectric layer 130, and a source metal layer 148 on the dielectric layer 170.

[0098] In some embodiments, the source metal layer 148 may serve as an additional source field plate and is electrically connected to the source electrode 142 and the source metal layer 146 via the source contact 144. The potentials of the source metal layers 146 and 148 electrically connected to the source electrode 142 are different from the potential of the gate metal layer 154 electrically connected to the gate electrode 152. In this embodiment, the side of the gate electrode 152 facing the drain structure 160 (+Y direction) is adjacent to the side of the gate metal layer 154 facing the source structure 140 (-Y direction), and the width of the additional source metal layer 148 is greater than the width of the source metal layer 146, that is, the additional source metal layer 148 can completely cover the source metal layer 146.

[0099] Because the notch 155 in the gate metal layer 154 exposes the gate electrode 152, the source-to-gate capacitance (C) is reduced. gs The additional source metal layer 148 further reduces the electric field strength, thus reducing the input capacitance (C). gs +C gd In the case of ), the risk of the gate structure being subjected to a high electric field is reduced.

[0100] In other embodiments, the width of the additional source metal layer 148 may be smaller than or equal to the width of the source metal layer 146 (not shown). The electric field strength and input capacitance can be reduced by providing an additional source metal layer. It should be noted that although only one additional source metal layer 148 is shown in this embodiment, its number and size can be adjusted according to the actual product design and the required switching speed, and are not limited thereto.

[0101] Please refer to the matching instructions. Figure 17 and Figure 18 . Figure 17 According to other embodiments of the present invention, a partial perspective perspective view of an exemplary semiconductor structure is shown, and Figure 18 According to other embodiments of the present invention, the diagrams corresponding to Figure 17 The diagram shows a cross-sectional view of the semiconductor structure along line C-C'. Figure 17 Also applicable Figure 1 The X, Y, and Z directions, and Figure 18 Also applicable Figure 12 The Y and Z directions are used to describe their relative positions.

[0102] Figure 17 The semiconductor structure shown in the figure is roughly similar to 400. Figure 1 The difference between semiconductor 100 and semiconductor structure 400 is that the source metal layer 146 has an opening 147 and the additional source metal layer 148 also has an opening 149, in order to further reduce the gate-to-source capacitance (C).gs Specifically, the semiconductor structure 400 includes a source metal layer 146 with an opening 147, a dielectric layer 170 disposed on the source metal layer 146 and the dielectric layer 130, and a source metal layer 148 disposed on the dielectric layer 170 and having an opening 149. Figure 18 In the cross-sectional view shown, the opening 147 in the source metal layer 146 has a width WO1, the opening 149 in the additional source metal layer 148 has a width WO2, the gate electrode 152 has a width WG, and the gate metal layer 154 has a width WGM2.

[0103] In some embodiments, the width WO2 of the opening 149 may be smaller than the width WO1 of the opening 147, such as... Figure 18 As shown. In this embodiment, the side of the gate electrode 152 facing the drain structure 160 is adjacent to the side of the gate metal layer 154 facing the source structure 140, and the projections of the source metal layer 146 and the additional source metal layer 148 on the substrate 102 completely overlap. A similar description of the gate electrode 152 and the gate metal layer 154 is provided below. Figure 13-15 As mentioned above, I will not go into details here.

[0104] Because the notch 155 in the gate metal layer 154 exposes the gate electrode, the capacitance from the source to the gate 152 is reduced (C). gs Furthermore, the source metal layer 146 with opening 147 further reduces the source-to-gate capacitance (C). gs Furthermore, the additional source metal layer 148 with opening 149 further reduces the electric field strength and lowers the source-to-gate capacitance (C). gs Therefore, it is possible to reduce the input capacitance (C). gs +C gd In the case of ), the risk of the gate structure being subjected to a high electric field is reduced.

[0105] The electric field strength can be further reduced by providing openings on the source metal layer and then providing additional source metal layers, which also have openings. It should be noted that although only a source metal layer 146 with opening 147 and a source metal layer 148 with opening 149 are shown in this embodiment, the number and size of the source metal layers, as well as the number and size of the openings in the source metal layers, can be adjusted according to the actual product design and the required switching speed, and are not limited thereto.

[0106] It is worth noting that in the semiconductor structure provided in the embodiments of the present invention, the number and size of the notches in the gate metal layer, the number and size of the source metal layer, and the number, size, and shape of the openings located above the gate metal layer and the gate electrode in the source metal layer are not limited to the above embodiments. For example, notches and / or openings of various polygons (e.g., pentagons, hexagons, or octagons), circles, or irregular arc-shaped contours can also be applied to the semiconductor structure provided in the embodiments of the present invention. Depending on the actual product design and the required switching speed, the number, size, and shape of the notches and / or openings described in the different embodiments above can be integrated into a single semiconductor structure to adjust the coverage of the source metal layer as the source field plate over the gate metal layer as the gate field plate and the coverage of the gate metal layer as the gate field plate over the two-dimensional electron gas (2DEG).

[0107] In summary, the semiconductor structure provided by the embodiments of the present invention can reduce the risk of the gate structure being subjected to high electric fields by means of a gate field plate, and optimize the electric field distribution and reduce the gate-to-drain capacitance (C) by means of a source field plate. gd Furthermore, by forming a notch in the gate metal layer, the coverage of the source field plate over the gate field plate and the coverage of the gate field plate over the two-dimensional electron gas (2DEG) can be adjusted, thereby simultaneously reducing the gate-to-source capacitance (C). gs ) and gate-to-drain capacitance (C gd This achieves the goal of reducing switching losses. Therefore, the semiconductor structure provided in this embodiment of the invention, in addition to having a breakdown voltage and an input capacitance (C), also has other properties. gs +C gd A good balance between these factors can more effectively reduce switching losses, thereby improving the performance of the semiconductor structure.

[0108] The foregoing outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. It should be understood by those skilled in the art that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. It should also be understood by those skilled in the art that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate; a gate structure on the substrate, wherein the gate structure comprises: a gate electrode on the substrate; and a gate metal layer on the gate electrode, wherein the gate electrode and the gate metal layer project into a top view of the substrate, the gate metal layer comprises a U-shaped portion and a gap between sidewalls of the U-shaped portion, wherein the U-shaped portion comprises a pair of sidewall portions and a connecting portion connecting the pair of sidewall portions, and the pair of sidewall portions respectively overlaps with a portion of the gate electrode, and the gap exposes the underlying gate electrode; and a drain structure and a source structure on two sides of the gate structure, wherein a potential of the gate structure is different from a potential of the source structure. The gap is directed toward the source structure.

2. The semiconductor structure of claim 1, wherein, The gate metal layer on two sides of the gap is arc-shaped, rectangular, or trapezoidal in profile.

3. The semiconductor structure of claim 1, wherein, The gap is rectangular, trapezoidal, or triangular.

4. The semiconductor structure of claim 1, wherein, A width of the gate metal layer changes linearly along a direction of extension of the gate electrode.

5. The semiconductor structure of claim 1, wherein, Portions of the gate metal layer on two sides of the gap extend beyond the gate electrode.

6. The semiconductor structure of claim 1, wherein, The gap exposes a first side of the gate electrode and covers a second side of the gate electrode opposite the first side.

7. The semiconductor structure of claim 1, wherein, The gap exposes a first side of the gate electrode and aligns with a second side of the gate electrode opposite the first side.

8. The semiconductor structure of claim 1, wherein, A length of the gate metal layer on two sides of the gap is greater than or equal to five times a thickness of the gate metal layer.

9. The semiconductor structure of claim 1, wherein, The source structure comprises:

10. The semiconductor structure of claim 1, wherein, a source electrode on the substrate; and a source metal layer on the source electrode and electrically connected to the source electrode. The source metal layer extends toward the drain structure and beyond the gate metal layer.

11. The semiconductor structure of claim 10, wherein, The source metal layer has at least one opening.

12. The semiconductor structure of claim 10, wherein, The source structure further comprises another source metal layer on the source metal layer, and the another source metal layer is electrically connected to the source electrode.

13. The semiconductor structure of claim 10, wherein, The another source metal layer extends toward the drain structure and beyond the source metal layer.

14. The semiconductor structure of claim 13, wherein, The another source metal layer has at least one opening.

15. The semiconductor structure of claim 13, wherein, A width of the opening of the another source metal layer is less than a width of an opening of the source metal layer.

16. The semiconductor structure of claim 15, wherein, Further comprising an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer passes through the gate metal layer and contacts the gate electrode.

17. The semiconductor structure of claim 1, wherein, The gate metal layer is comb-shaped.

18. The semiconductor structure of claim 1, wherein, The gate metal layer is symmetric with respect to a midline of a length direction of the gate metal layer.

19. The semiconductor structure of claim 1, wherein, ​

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