Reference-Free Frequency Detector with High Jitter Tolerance

Abstract

A sampling device for a reference - free frequency detector with high jitter tolerance is configured to sample a clock signal according to a data signal to generate a first sampling signal; sample the clock signal according to a delay signal to generate a second sampling signal; and a control circuit coupled to the sampling device, wherein the control circuit is configured to adjust the frequency of the clock signal based on the first sampling signal and the second sampling signal.

Description

[0001] Cross-application of related applications

[0002] This application claims priority to U.S. non-provisional patent application No. 14 / 925,716, filed on October 28, 2015, entitled “REFERENCE-LESS FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE,” the entire contents of which are incorporated herein by reference. Background Art

[0003] Data transmitted through high-speed systems, such as between two chips on a highly integrated system or between circuits within a single chip, is typically sent without an accompanying clock signal. Although clockless data transmission reduces complexity and power consumption, a data receiver is required to generate a clock signal to recover the data. The receiver can use a clock and data recovery (CDR) circuit to generate a clock signal that is synchronized with the phase and frequency of the received data. Therefore, accurately detecting the phase and frequency of the received data or the phase and frequency offset between the clock signal and the data signal is important for ensuring high-quality data communications, especially for high-speed data systems operating at about 10 gigabits per second (Gbps) to about 100 Gbps. Summary of the invention

[0004] In one embodiment, the present invention includes an apparatus comprising: a first sampling circuit for sampling a clock signal according to a data signal to generate a first sampling signal; a second sampling circuit for sampling the clock signal according to a delayed data signal to generate a second sampling signal; and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a NAND operation according to the first sampling signal and the second sampling signal to generate an activation signal for activating frequency adjustment of the clock signal.

[0005] In another embodiment, the present invention includes a method comprising: sampling a clock signal according to a data signal to generate a first sampling signal; delaying the data signal by a duration of one quarter of a time unit to generate a delayed signal; sampling the clock signal according to the delayed signal to generate a second sampling signal; and performing a NAND operation based on the first sampling signal and the second sampling signal to generate an activation signal for activating a charge pump to align the frequency of the clock signal to the frequency of the data signal.

[0006] In yet another embodiment, the present invention includes an apparatus comprising: a NAND gate including a first NAND gate input port, a second NAND gate input port, and a NAND gate output port; and a voltage-to-current (V2I) converter including a V2I conversion activation port and a V2I conversion output current port, wherein the V2I conversion activation port is coupled to the NAND gate output and the V2I conversion output current port is coupled to a frequency detection loop filter.

[0007] These and other features will be more clearly understood in the following detailed description in conjunction with the drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To understand the present invention more thoroughly, reference is now made to the following brief description, taken in conjunction with the accompanying drawings and detailed description, in which like reference numerals represent like parts.

[0009] Figure 1 Schematic diagram of a reference-free frequency detector.

[0010] Figure 2 For showing Figure 1 Graph of waveforms simulated by the reference-free frequency detector under locked conditions.

[0011] Figure 3 For showing Figure 1 Graph of waveforms captured by the reference-free frequency detector during jitter.

[0012] Figure 4 For showing Figure 1 Graph of eye diagrams captured by the reference-free frequency detector during jitter.

[0013] Figure 5 Schematic diagram of a jitter-tolerant reference-free frequency detector according to an embodiment of the present invention.

[0014] Figure 6 Schematic diagram of a solution for implementing a jitter-tolerant reference-free frequency detector according to an embodiment of the present invention.

[0015] Figure 7 Schematic diagram of an inverter circuit according to an embodiment of the present invention.

[0016] Figure 8 Schematic diagram of a buffer circuit according to an embodiment of the present invention.

[0017] Figure 9 Schematic diagram of a current-mode logic to complementary metal oxide semiconductor (CML-to-CMOS) level conversion circuit according to an embodiment of the present invention.

[0018] Figure 10Schematic diagram of a NAND gate circuit according to an embodiment of the present invention.

[0019] Figure 11 Shows according to an embodiment of the present invention Figure 5 Graph of the waveform captured by the jitter-tolerant reference-free frequency detector when experiencing jitter.

[0020] Figure 12 Shows according to an embodiment of the present invention Figure 5 Graph of the eye diagram captured by the jitter-tolerant reference-free frequency detector when experiencing jitter.

[0021] Figure 13 Flowchart of a method for performing reference-free frequency detection when experiencing jitter according to an embodiment of the present invention. Detailed implementation

[0022] First, it should be understood that although the following provides illustrative implementations of one or more embodiments, the disclosed systems and / or methods can be implemented using any number of techniques, whether currently known or existing. The present invention should in no way be limited to the illustrative implementations, drawings, and techniques described below, including the exemplary designs and implementations illustrated and described herein, but can be modified within the full scope of the appended claims and their equivalents.

[0023] Frequency detectors are typically used in phase-locked loop (PLL)-based CDRs to recover timing information from data. A reference-free frequency detector refers to a frequency detector that includes a frequency detection loop that automatically activates in the unlocked state and automatically deactivates after frequency capture is completed, without using a reference clock or a lock detector. Omitting the reference clock and the lock detector reduces the number of hardware components and lowers power consumption. Therefore, a reference-free frequency detector can provide an attractive solution for CDRs.

[0024] Figure 1Schematic diagram of a reference - free frequency detector 100. The frequency detector 100 includes three D - type flip - flops (DFFs) 111, 112, and 113, a delay buffer 120, and a charge pump 130. The DFFs 111, 112, and 113 include data input ports 114 shown as D, clock input ports 115, and output ports 116 shown as Q. The DFFs 111, 112, and 113 also each include circuitry for sampling digital data signals at the data input ports 114 by a clock signal at the clock input ports 115 and outputting the sampled signals through the output ports 116. The above - mentioned sampling can be performed at the rising edge or the falling edge of the clock cycle. The delay buffer 120 includes circuitry for delaying an input signal for a period of time, which can be about one - quarter of the duration of a time unit. The charge pump 130 includes circuitry for controlling the current flow in a loop filter. For example, the charge pump 130 can be a V2I converter including a current source that drives the current arriving at or from the loop filter.

[0025] The frequency detector 100 receives a data signal V B and a clock signal CK as inputs. The clock signal CK is generated by a voltage - controlled oscillator (VCO). The clock signal CK is provided to the DFFs 111 and 112 through the corresponding data input ports 114. The data signal V B is provided to the DFF 111 through the clock input port 115 of the DFF 111. The data signal is delayed by the delay buffer 120 for about one - quarter of a time unit to produce a delayed signal V D , and this delayed signal V D is provided to the DFF 112 through the clock input port 115 of the DFF 112. The DFF 111 samples the clock signal CK at the rising edge of the data signal V B and outputs a sampled output signal Q 1 through the output port 116 of the DFF 111. Similarly, the DFF 112 samples the clock signal CK at the rising edge of the delayed signal V D and outputs a sampled output signal Q 2 through the output port 116 of the DFF 112. The output signals Q 1 and Q 2 include the same period, which is proportional or inversely proportional to the frequency difference between the data signal V B and the clock signal CK. The relative phase shift between the output signals Q 1 and Q 2 represents the polarity of the frequency difference. When the output signal Q 1 is greater than the output signal Q 2 , the frequency of the clock signal CK is less than the frequency of the data signal V B . When the output signal Q 1Less than the output signal Q 2 When, the frequency of the clock signal CK is greater than the frequency of the data signal V B .

[0026] DFF 113 is coupled to the output ports 116 of DFF 111 and 112. DFF 113 receives the output signal Q through the data input port 114 of DFF 113 1 and receives the output signal Q through the clock input port 115 of DFF 113 2 . DFF 113 samples the output signal Q 2 through the output signal Q 1 . When the output signal Q 1 is greater than the output signal Q 2 , DFF 113 generates an output signal Q with a logic high level 3 . When the output signal Q 1 is less than the output signal Q 2 , DFF 113 generates an output signal Q with a logic low level 3 . A logic high level represents the binary value 1, and a logic low level represents the binary value 0. The voltage levels of the logic high level and the logic low level depend on the supply voltage used by the frequency detector 100. Since the output signal Q 3 carries the polarity of the frequency difference between the data signal V B and the clock signal CK, the output signal Q 3 can be used to indicate whether the charge pump 130 charges or discharges the loop filter. The output voltage of the loop filter increases or decreases as the loop filter is charged or discharged. Therefore, the output voltage of the loop filter can be used to control the VCO, where the frequency of the clock signal CK is proportional to the output voltage. For example, the charge pump 130 is used to charge the loop filter when the output signal Q 3 is at a high level, and is used to discharge the loop filter when the output signal Q 3 is at a low level. When the frequency of the clock signal CK is locked to the frequency of the data signal V B , it is necessary to deactivate the charging or discharging of the loop filter. As shown in the figure, the output signal Q 2 is used to control the activation and deactivation of the charge pump 130. The activation of the charge pump 130 is active low, so the inverted signal of the output signal Q 2 is used to activate and deactivate the charge pump 130, as shown by the bubble 140. After correcting the clock signal CK to match the frequency of the data signal V B , the signal CK can be used to retime or sample a copy of the data signal V B or the data signal V B for data recovery, as described more fully below.

[0027] Figure 2 FIG. 200 showing waveforms simulated by the reference - free frequency detector 100 under locked conditions. The locked condition refers to the condition where the frequency of the clock signal used to sample the input data signal is approximately equal to the frequency of the input data signal. In FIG. 200, the x - axis represents time in some constant units, and the y - axis represents voltage in some constant units. Waveform V B 210 corresponds to the data signal V in the frequency detector 100 B . Waveform V D 220 corresponds to the delayed signal V in the frequency detector 100 D . Waveform V C 230 corresponds to the data signal V with a duration delayed by approximately one - eighth of the time unit B . Waveform CK 240 corresponds to the clock signal CK in the frequency detector 100. Waveform Q 1 250 corresponds to the output signal Q of DFF 111 in the frequency detector 100 1 . Waveform Q 2 260 corresponds to the output signal Q of DFF 112 in the frequency detector 100 2 . As shown, when the frequency of the clock signal CK is locked to the frequency of the data signal V B , bit transitions in the data signal V B always occur when the clock signal CK is low, as indicated by the dotted line 271, while bit transitions in the data signal V D always occur when the clock signal CK is high, as indicated by the dotted line 272. Therefore, under locked conditions, the signal Q 1 remains at a constant logic low level, and the signal Q 2 remains at a constant logic high level. Thus, the signals Q 1 and Q 2 include the logic state 01 under locked conditions. Additionally, the rising edge of the waveform CK 240 is aligned with the bit transition in the waveform V C 230, as indicated by the dotted line 273. Therefore, the original data bits can be recovered by sampling the signal of the waveform V C 230 at the falling edge of the clock signal CK

[0028] However, if V B and V D experience jitter, the rising edge of the clock signal CK can instantaneously drift left or right. There are many reasons for jitter, such as noise on the transmission line, inter - symbol interference (ISI) in the received data stream, and noise in the original transmission source data stream. When the drift exceeds the timing margin 281 or 282, the drift can cause V B and VD Transitions occur both when the clock signal CK is low or when the clock signal CK is high, thus switching the signal Q 1 and Q 2 . The switching changes the logic states of Q 1 and Q 2 , causing the frequency detector 100 to erroneously detect a loss of lock and make an unnecessary correction to the frequency of the clock signal CK.

[0029] Figure 3 FIG. 300 shows the waveforms captured by the reference - free frequency detector 100 during jitter. In FIG. 300, the x - axis represents time in some constant units, and the y - axis represents the signal amplitude in volts. The waveform Q 1 310 corresponds to the output signal Q 1 in the frequency detector 100. The waveform Q 2 320 corresponds to the output signal Q 2 in the frequency detector 100. The waveform Q 3 330 corresponds to the output signal Q 3 in the frequency detector 100. The signals Q 1 , Q 2 and Q 3 are differential signals, each consisting of a pair of positive and negative signals with equal amplitudes and opposite polarities. The solid curve corresponds to the positive signal, and the dotted curve corresponds to the negative signal. The waveform 340 corresponds to the control voltage generated by the loop filter driven by the charge pump 130. The control voltage is used to drive the VCO, which generates the clock signal CK in the frequency detector. The region 390 corresponds to the period of time when jitter exists. As shown, the positive and negative signals in the waveform Q 2 320 switch in the presence of jitter, causing the signals Q 1 and Q 2 to transition from the locked state 01 to the state 00 or the state 11. When Q 1 and Q 2 instantaneously transition to the state 11, since Q 2 remains high and the charge pump 130 is low - active as described above, the charge pump 130 remains inactive. However, when Q 1 and Q 2 instantaneously transition to the state 00, since Q 2 is low, the charge pump 130 is erroneously activated, thus causing the loop filter to make an unnecessary change to the control voltage, as shown by the waveform V CTRL 340. The change in the drive voltage causes the VCO to become unstable, so the frequency of the VCO is no longer locked to the input data frequency.

[0030] Figure 4FIG. 400 shows an eye diagram 410 captured by the reference-free frequency detector 100 when experiencing jitter. The x-axis represents time in certain constant units, and the y-axis represents signal amplitude in certain constant units. The eye diagram 410 corresponds to the data signal retimed by the frequency detector 100. The retimed data signal refers to the sampling of a copy of the original input data signal by a clock signal, which is adjusted by a frequency detector such as the frequency detector 100. As shown, the eye diagram 410 is almost closed due to jitter, so data bits cannot be correctly recovered from the retimed data signal.

[0031] Embodiments of a reference-free frequency detector for providing high jitter tolerance are disclosed herein. The disclosed embodiments employ a reference-free frequency detector including three sampling circuits. The first sampling circuit samples the clock signal generated by the VCO according to the input data signal to produce a first output signal Q 1 . The second sampling circuit samples the clock signal according to a delayed copy of the input data signal to produce a second output signal Q 2 , where the delay is for a duration of approximately one-quarter of a time unit. The third sampling circuit samples the first output signal by the second output signal to produce a third output signal. The third output signal indicates the current flow of the charge pump control loop filter to align the frequency of the VCO to the frequency of the input data signal. However, the disclosed embodiments activate the charge pump only when Q 1 is at a logic high level and Q 2 is at a logic low level, rather than directly activating the charge pump based on Q 2 in the frequency detector 100. The disclosed embodiments implement the activation condition by inserting a NAND gate at the input of the charge pump, where Q 1 and Q 2 serve as inputs. In one embodiment, the first, second, and third sampling circuits are implemented by DFFs including CML logic circuits, and the NAND gate is implemented by a CMOS logic circuit. Therefore, before applying the CML-to-CMOS level converter to the output of the NAND gate, the CML-to-CMOS level converter is used to convert the first output signal Q 1 and the second output signal Q 2 from CML differential signals to CMOS rail-to-rail signals. The use of the NAND gate avoids the frequency detector wrongly triggering VCO frequency correction during high jitter. The disclosed frequency detector is suitable for use in high-speed systems such as optical modules operating at approximately 10 Gbps to approximately 100 Gbps.

[0032] Figure 5Schematic diagram of a jitter-insensitive reference-free frequency detector 500 according to an embodiment of the present invention. The frequency detector 500 uses logic components to avoid over-driving the VCO by the frequency detector 500 and unnecessary correction of the frequency of the VCO during jitter. The frequency detector 500 includes three DFFs 511, 512, and 513, a delay buffer 520, a charge pump 530, and a NAND gate 540. The DFFs 511, 512, and 513 are similar to the DFFs 111, 112, and 113. The delay buffer 520 is similar to the delay buffer 120. The charge pump 530 is similar to the charge pump 130. The DFF 511 samples the clock signal CK through the data signal V B to generate a first output signal Q 1 , wherein the clock signal CK is generated by a local VCO. The delay buffer 520 delays the data signal V B for a duration of approximately one-quarter of a time unit to generate a delayed signal V D . The DFF 512 samples the clock signal CK through the delayed signal V D to generate a second output signal Q 2 .

[0033] To avoid erroneously activating the charge pump 530 due to jitter when the frequency of the VCO is locked to the frequency of the data signal V B , the frequency detector 500 uses the NAND gate 540 to perform an activation condition only when the first output signal Q 1 is high and the second output signal Q 2 is low. The NAND gate 540 is coupled to the DFFs 511 and 512 and is used to receive the inverted signal of the second output signal Q 2 and the first output signal Q 1 as inputs. The NAND gate 540 performs a NAND operation on the inverted signal of the second output signal Q 2 and the first output signal Q 1 . The following table summarizes the logic of the NAND gate 540:

[0034]

[0035]

[0036] Table 1: Logic of the NAND gate 540

[0037] As shown in Table 1, the NAND gate 540 performs an operation only when Q 1 and Q 2It includes an output that generates a logic low level when the logic state is 10. Since the charge pump 530 is active low, the output signal of the NAND gate 540, shown as on / off, is inverted before using the signal on / off to activate the charge pump 530.

[0038] The DFF 513 samples Q 2 to generate an error signal Q 1 indicating the polarity of the frequency difference between the data signal V B and the clock signal CK. 3 The error signal Q 3 drives the charge pump 530 to charge or discharge the loop filter, which generates a control voltage for adjusting the frequency of the VCO to match the frequency of the data signal V B . The frequency detector 500 can be used to perform the frequency comparison as shown using DFFs 511, 512, and 513 or can be used to implement a similar function using other suitable logic circuits.

[0039] Figure 6 FIG. 600 is a schematic diagram of a solution 600 for implementing an isochronous jitter-free reference frequency detector such as the frequency detector 500 according to an embodiment of the present invention. The solution 600 uses three DFF modules 611, 612, and 613, a V2I module 630, two CML to CMOS modules 641 and 642, a NAND module 650, a buffer module 660, and an inverter module 670 to implement the frequency detector 500. The solution 600 uses a differential circuit and represents a pair of differential positive and negative signal components by the letters P and M respectively. The negative signal component is the reverse component of the positive signal component. The solution 600 operates on a pair of differential data signals VBM and VBP, a pair of differential delay signals VDM and VDP, and a pair of differential clock signals VCO_CKM and VCO_CKP. The data signals VBM and VBP correspond to the input data signal V in the frequency detector 500 B . The delay signals VDM and VDP correspond to the signal V B delayed by approximately one-quarter time unit D . The clock signals CKM and CKP correspond to the clock signal CK generated by the VCO controlled by the frequency detector 500.

[0040] The DFF modules 611, 612, and 613 may include CML circuits for implementing the sampling functions of the DFFs 511, 512, and 513. Each of the DFF modules 611, 612, and 613 further includes: a differential data input port 621 including terminals DM and DP; a differential clock input port 622 including terminals CKM and CKP; and a differential output port 623 including terminals QM and QP. The data input port 621, the clock input port 622, and the output port 623 are similar to the data input port 114, the clock input port 115, and the output port 116, respectively, and provide a more detailed view of the differential terminals. The DFF modules 611, 612, and 613 are referred to as sampling circuits. The V2I module 630, the NAND module 650, the buffer module 660, the inverter module 670, and the CML-to-CMOS modules 641 and 642 are referred to as control circuits.

[0041] The configurations of the DFF modules 611, 612, and 613 are similar to those of the DFFs 511, 512, and 513 in the frequency detector 500, and they are coupled to each other. The data input ports 621 of the DFF modules 611 and 612 are used to connect to the pair of differential clock signals VCO_CKM and VCO_CKP. The clock input port 622 of the DFF module 611 is used to connect to the pair of differential data signals VBM and VBP. The clock input port 622 of the DFF module 612 is used to connect to the pair of differential delay signals VDM and VDP. The output port 623 of the DFF module 611 generates a pair of differential output signals Q1M and Q1P, which are coupled to the data input port 621 of the DFF module 613. The output port 623 of the DFF module 612 generates a pair of differential output signals Q2M and Q2P, which are coupled to the clock input port 622 of the DFF module 613. The output port 623 of the DFF module 613 generates a pair of differential output signals Q3M and Q3P.

[0042] The CML-to-CMOS modules 641 and 642 include circuitry for converting signals from CML voltage levels to CMOS logic voltage levels. For example, CML may include an output voltage swing lower than CMOS logic. Each of the CML-to-CMOS modules 641 and 642 further includes: a differential input port 645 including terminals VIN_M and VIN_P; and a differential output port 646 including terminals VOUT_M and VOUT_P. The input port 645 receives a CML differential signal, and the output port 646 generates a CMOS rail-to-rail signal converted from the received CML differential signal. The internal circuitry of the CML-to-CMOS modules 641 and 642 is described more fully below. The input port 645 of the CML-to-CMOS module 641 is used to receive signals Q1M and Q1P from the DFF module 611 and generate level-shifted signals Q1P_LS and Q1M_LS at the output port 646. The input port 645 of the CML-to-CMOS module 642 is used to receive signals Q2M and Q2P from the DFF module 612 and generate level-shifted signals Q2P_LS and Q2M_LS. As shown, the connections between the DFF modules 611, 612, and 613 and the CML-to-CMOS modules 641 and 642 are configured such that the positive signal components are connected to the positive terminals and the negative signal components are connected to the negative terminals.

[0043] The NAND module 650 includes circuitry for implementing the NAND operation of the NAND gate 540. The buffer module 660 includes circuitry for buffering or delaying a signal for a period of time, which may be in units of clock cycles. The inverter module 670 includes circuitry for inverting the signal polarity. The NAND module 650 is coupled to the CML-to-CMOS modules 641 and 642 and is used to receive signals Q1P_LS and Q2M_LS as inputs A and B and generate the NAND of signals Q1P_LS and Q2M_LS as output Y. The input and output states of the NAND module 650 are shown in Table 1. The inverter module 670 and the buffer module 660 are coupled to the output of the NAND module 650. The inverter module 670 includes circuitry for inverting the output signal of the NAND module 650 to generate an output signal FONOFF_M. The buffer module 660 includes circuitry for delaying the output signal of the NAND module 650 for a period of time, which is similar to the delay of the inverter module 670. The buffer module 660 generates an output signal FONOFF_P. The output signals FONOFF_M and FONOFF_P are used to form a differential pair to activate or deactivate the V2I module 630.

[0044] The V2I module 630 includes a current source for converting voltage to current. The V2I module 630 further includes: a differential signal adjustment port 631, including terminals ADJM and ADJP; a differential activation port 632, including terminals ONOFFM and ONOFFP; and an output current port 633, denoted as IOUT. The signal adjustment port 631 is used to receive output signals Q3M and Q3P from the output port 623 of the DFF module 613. The activation port 632 is used to receive output signals ONOFFM and ONOFFP from the output terminals of the inverter module 670 and the buffer module 660 respectively. When the ONOFFP signal is at a logic high level, the V2I module 630 generates a current signal at the output port 633, where the amount of current depends on the signals Q3M and Q3P. The current signal is used to drive the current to and from the loop filter to control the frequency of the VCO.

[0045] Figure 7 FIG. 4 is a schematic diagram of an inverter circuit 700 according to an embodiment of the present invention. The inverter module 670 can implement the signal inversion function using the circuit 700. The circuit 700 includes an n-channel metal oxide semiconductor (NMOS) transistor 710 denoted as M1 and a p-channel metal oxide semiconductor (PMOS) transistor 720 denoted as M2. The drains and gates of the NMOS transistor 710 and the PMOS transistor 720 are interconnected. The source of the NMOS transistor 710 is connected to a ground denoted as GND. The source of the PMOS transistor 720 is connected to a supply voltage denoted as V DD The input of the inverter 700, denoted as A, is connected to the gates of the NMOS transistor 710 and the PMOS transistor 720. The output of the inverter circuit 700, denoted as Y, is connected to the drains of the NMOS transistor 710 and the PMOS transistor 720. When the input A is at a low level, the NMOS transistor 710 is turned off and the PMOS transistor 720 is turned on, thereby providing a connection path between the output Y and the V DD rail. Therefore, the output Y is at a logic high level. When the input A is at a high level, the NMOS transistor 710 is turned on and the PMOS transistor 720 is turned off, thereby providing a connection path between the output Y and GND. Therefore, the output Y is at a logic low level.

[0046] Figure 8 FIG. 5 is a schematic diagram of a buffer circuit 800 according to an embodiment of the present invention. The buffer module 600 can implement the buffer function using the circuit 800. The circuit 800 includes two inverter circuits 810 and 820 similar to the inverter circuit 700. The inverter circuit 810 receives the input signal A and generates a reverse signal of the input signal A, denoted as Z. The inverter circuit 820 receives the inverted signal Z and generates a reverse signal of the signal Z, denoted as Y. Therefore, the circuit 800 outputs a delayed copy of the input signal A.

[0047] Figure 9 Schematic diagram of a CML to CMOS level conversion circuit 900 according to an embodiment of the present invention. The CML to CMOS module 650 may implement the level conversion function using the circuit 900. The circuit 900 converts the CML voltage level to the CMOS logic voltage level. The circuit 900 includes two differential logic parts 910 and 920 and an output part 930. The differential logic part 910 includes an NMOS transistor 911 shown as M1 and an NMOS transistor 912 shown as M2. The differential logic part 920 includes a PMOS transistor 913 shown as M3 and a PMOS transistor 914 shown as M4. The gate of the NMOS transistor 911 receives the input voltage VINP, and the gate of the NMOS transistor 912 receives the input voltage VINM. The input voltages VINP and VINM include the CML voltage level. The drain of the NMOS transistor 911 is connected to the drain of the PMOS transistor 913 and the gate of the PMOS transistor 914. The drain of the NMOS transistor 912 is connected to the drain of the PMOS transistor 914 and the gate of the PMOS transistor 913. The sources of the NMOS transistors 911 and 912 are connected to the ground shown as GND. The sources of the PMOS transistors 913 and 914 are connected to the supply voltage shown as V DD which is the CMOS rail voltage. In operation, when VINP is high, VINM is low. Therefore, the NMOS transistor 911 is turned on, and the NMOS transistor 912 is turned off, resulting in VA being at a logic low level. The transition of VA turns on the PMOS transistor 914, thus providing a connection path between VB and V DD rails. When VINP is low, VINM is high. Therefore, the NMOS transistor 911 is turned off, and the NMOS transistor 912 is turned on, resulting in VB being at a logic low level. The transition of VB turns on the PMOS transistor 913, thus providing a connection path between VA and V DD rails.

[0048] The output part 930 includes two inverter circuits 931 and 932 similar to the inverter circuits 700, 810, and 820. The inverter circuit 931 is coupled to the signal VA and generates an inverted signal of the signal VA, shown as VOUTP. The inverter circuit 932 is coupled to the signal VB and generates an inverted signal of the signal VB, shown as VOUTM. The signals VOUTP and VOUTM include voltage levels related to V DD and GND, and this voltage level is the CMOS voltage level.

[0049] Figure 10Schematic diagram of a NAND gate circuit 1000 according to an embodiment of the present invention. The NAND module 650 can use the circuit 1000 to implement the NAND operation. The circuit 1000 includes two NMOS transistors 1011 and 1012 respectively shown as M1 and M2, and two PMOS transistors 1013 and 1014 respectively shown as M3 and M4. The source of the NMOS transistor 1011 is connected to the drain of the NMOS transistor 1012. The source of the NMOS transistor 1012 is connected to the ground shown as GND. The gates of the NMOS transistors 1011 and 1012 are respectively connected to a pair of inputs A and B. The drains of the PMOS transistors 1013 and 1014 are connected to the drain of the NMOS transistor 1011, and the drain of the NMOS transistor 1011 is the output of the NAND circuit 1000, shown as Y. The sources of the PMOS transistors 1013 and 1014 are connected to the power supply voltage shown as V DD . The gates of the PMOS transistors 1014 and 1013 are respectively connected to a pair of inputs A and B. The NMOS transistors 1011 and 1012 act as a pull-down network, where when the inputs A and B are at a low level, the output Y is at a low level. The PMOS transistors 1013 and 1014 act as a pull-up network, where when either input A or B is at a low level, the output Y is at a high level.

[0050] Figure 11 FIG. 1100 is a diagram showing waveforms captured by the jitter-tolerant reference-free frequency detector 500 according to an embodiment of the present invention. In FIG. 1100, the x-axis represents time in certain constant units, and the y-axis represents signal amplitude in volts. FIG. 1100 is generated by implementing a frequency detector according to scheme 600. In FIG. 1100, the solid curve corresponds to the positive differential signal component, and the dotted curve corresponds to the negative differential signal component. Waveform Q 1 1110 shows the signals Q1M and Q1P captured at the output of the DFF module 611. Waveform Q 2 1120 shows the signals Q2M and Q2P captured at the output of the DFF module 612. Waveform Q 3 1130 shows the signals Q3M and Q3P captured at the output of the DFF module 613. Waveform F_ONOFF 1140 shows the signals F_ONOFFM and F_ONOFFP captured at the outputs of the inverter module 670 and the buffer module 660 respectively. Waveform V CTRL 1150 shows the control voltage signal generated by the loop filter controlled by the V2I module 630. The control voltage signal is used to adjust the frequency of the VCO, which generates the clock signals CKM and CKP in scheme 600. As shown, when waveform Q 2When the signal in 1120 switches due to jitter, the solid curve in waveform F_ONOFF 1140 corresponding to signal F_ONOFFP remains at the logic high level instead of switching to the logic low level. Comparing waveform V CTRL 340 with waveform V CTRL 1150, the V in waveform V CTRL 1150 is stable, unlike the V in waveform V CTRL 340 where the V CTRL signal varies. CTRL

[0051] Figure 12 FIG. 1200 is a diagram showing the eye diagram 1210 captured by the jitter - tolerant reference - free frequency detector 500 when experiencing jitter. In FIG. 1200, the x - axis represents time in certain constant units, and the y - axis represents signal amplitude in certain constant units. The eye diagram 1210 corresponds to the retimed data signal of the frequency detector 500 when experiencing jitter. Compared with the eye diagram 410 and the eye diagram 1210, the eye diagram 1210 is open while the eye diagram 410 is closed.

[0052] Figure 13 FIG. 1300 is a flowchart of a method 1300 for performing reference - free frequency detection when experiencing jitter according to an embodiment of the present invention. The method 1300 is adopted by a frequency detector such as the frequency detector 500, and the frequency detector 500 is part of a CDR circuit. The mechanism adopted by the method 1300 is similar to that of the frequency detector 500 and the scheme 600. At step 1310, the clock signal is sampled according to the data signal to generate a first sampled signal. For example, a first D - flip - flop, such as DFFs 111, 112, 113, 511, 512, and 513 or DFF modules 611, 612, and 613, can be used to sample the clock signal. At step 1320, the data signal is delayed for a duration of one - quarter of the time unit to generate a delayed signal. For example, buffers similar to the delay buffers 120 and 520, buffer modules 660, and buffer circuit 800 can be used to delay the data signal. At step 1330, the clock signal is sampled according to the delayed signal to generate a second sampled signal. At step 1340, a NAND operation is performed according to the first sampled signal and the second sampled signal to generate an activation signal. The activation signal is used to activate the charge pump to align the frequency of the clock signal with the frequency of the data signal. For example, a NAND gate, such as NAND gates 540, NAND modules 650, and NAND circuits 700, can be used to perform the NAND operation. To generate the activation signal such that the charge pump is activated only when the first sampled signal is in the logic state 1 and the second sampled signal is in the logic state 0, the NAND gate receives the inverted signal of the second sampled signal and the first sampled signal as inputs. The output of the NAND gate is shown in Table 1 above.

[0053] Although the present invention provides multiple specific embodiments, it should be understood that the disclosed systems and methods may also be embodied in many other specific forms without departing from the spirit or scope of the present invention. The examples of the present invention should be considered illustrative rather than restrictive, and the present invention is not limited to the details given herein. For example, various elements or components may be combined or integrated in another system, or certain features may be omitted or not implemented.

[0054] In addition, without departing from the scope of the present invention, the technologies, systems, subsystems, and methods described and illustrated as discrete or separate in various embodiments may be combined or integrated with other systems, modules, technologies, or methods. Other items shown or discussed as being coupled or directly coupled or communicating with each other may also be indirectly coupled or communicating via some interface, device, or intermediate component in an electrical, mechanical, or other manner. Other variations, substitutions, and alternation examples will be apparent to those skilled in the art and are all within the spirit and scope disclosed herein.

Claims

1. A device, characterized in that, comprising: a first sampling circuit for sampling a clock signal according to a data signal to generate a first sampling signal; a second sampling circuit for sampling the clock signal according to a delay signal to generate a second sampling signal; and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a NAND operation according to the first sampling signal and the second sampling signal to generate an activation signal for activating frequency adjustment of the clock signal; the first sampling signal and the second sampling signal have the same period; the delay signal corresponds to the data signal with a quarter of a time unit delay.

2. The device according to claim 1, characterized in that, the control circuit includes a NAND gate, and the control circuit is further configured to perform the NAND operation by applying an inverted signal of the second sampling signal and the first sampling signal to the NAND gate to generate the activation signal.

3. The device according to claim 2, characterized in that, the data signal, the delay signal, and the clock signal are differential signals including current mode logic (CML) voltage levels; the first sampling circuit includes a first current mode logic to complementary metal oxide semiconductor (CML-to-CMOS) converter for converting the first sampling signal from the CML voltage level to a complementary metal oxide semiconductor (CMOS) logic voltage level to generate a first level conversion signal; the second sampling circuit includes a second CML-to-CMOS converter for converting the second sampling signal from the CML voltage level to the CMOS logic voltage level to generate a second level conversion signal.

4. The device according to claim 3, characterized in that, the control circuit is further configured to perform the NAND operation by applying a positive signal component of the first level conversion signal and a negative signal component of the second level conversion signal to an input of the NAND gate.

5. The device according to claim 3, characterized in that, the control circuit further includes: an inverter coupled to the NAND gate and configured to invert the activation signal generated by the NAND gate to generate a negative differential signal component, wherein the inverter is associated with a delay time; a buffer coupled to the NAND gate and configured to delay the activation signal by the delay time to generate a positive differential signal component; and a charge pump coupled to the inverter and the buffer, wherein the charge pump is configured to activate frequency adjustment of the clock signal according to the positive differential signal component and the negative differential signal component generated from the activation signal.

6. The device according to claim 5, characterized in that, the first CML-to-CMOS converter, the second CML-to-CMOS converter, the NAND gate, the inverter, and the buffer include CMOS logic circuits.

7. The device according to any one of claims 1 to 6, characterized in that, The first sampling circuit and the second sampling circuit include one or more D-type flip-flops (DFFs).

8. The apparatus according to any one of claims 1 to 6, wherein, further comprising a third sampling circuit coupled to the first sampling circuit and the second sampling circuit, wherein the third sampling circuit is configured to sample the first sampling signal according to the second sampling signal to generate a frequency error signal indicating whether to increase or decrease the frequency of the clock signal to match the frequency of the data signal.

9. The apparatus according to any one of claims 1 to 6, wherein, the data signal and the clock signal operate between about 10 gigabits per second (Gbps) and about 100 Gbps.

10. A method, wherein, comprising: sampling a clock signal according to a data signal to generate a first sampling signal; delaying the data signal for a duration of a quarter of a time unit to generate a delayed signal; sampling the clock signal according to the delayed signal to generate a second sampling signal; the first sampling signal and the second sampling signal have the same period; and performing a NAND operation according to the first sampling signal and the second sampling signal to generate an activation signal for activating a charge pump to align the frequency of the clock signal to the frequency of the data signal.

11. The method according to claim 10, wherein, the data signal and the clock signal are differential signals including current mode logic (CML) voltage levels, and the method further comprises: converting the first sampling signal from the CML voltage level to a complementary metal oxide semiconductor (CMOS) logic voltage level through a first level converter to generate a first level conversion signal; and converting the second sampling signal from the CML voltage level to the CMOS logic voltage level through a second level converter to generate a second level conversion signal.

12. The method according to claim 11, wherein, the performing the NAND operation further comprises: applying a positive signal component of the first level conversion signal to a first input of a NAND gate; and applying a negative signal component of the second level conversion signal to a second input of the NAND gate.

13. The method according to claim 11, wherein, further comprising: generating a differential signal from the activation signal by: inverting the activation signal to generate a negative signal component of the differential signal; and delaying the activation signal to generate a positive signal component of the differential signal.

14. The method according to any one of claims 10 to 13, wherein, further comprising: sampling the first sampling signal according to the second sampling signal to generate a frequency error signal for correcting the frequency of the clock signal.

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