Laminated substrate structure and electronic device including the laminated substrate structure

Abstract

A stacked substrate structure and an electronic device including the stacked substrate structure are provided, and the stacked substrate structure includes: a first printed circuit board having a first side and a second side opposite to the first side; a second printed circuit board arranged on the second side of the first printed circuit board and having a first side connected to the second side of the first printed circuit board and a second side opposite to the first side connected to the second side of the first printed circuit board; a reinforcement structure attached to the first side of the second printed circuit board and spaced apart from the second side of the first printed circuit board; and a bottom filling resin arranged between the second side of the first printed circuit board and the first side of the second printed circuit board and covering at least a portion of the reinforcement structure.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0164685 filed on December 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present invention relates to a laminated substrate structure and an electronic device including the laminated substrate structure. Background Art

[0003] According to the increase in the number and integration of I / Os due to the high performance of electronic products, a highly layered and large-sized substrate is required in the substrate. For example, it is necessary to increase the size and number of layers of a flip chip ball grid array (FCBGA) substrate for high-performance semiconductors, and therefore, the problem of increased cost may occur due to increased technical difficulty and reduced yield. Therefore, a technology that can reduce costs while maintaining semiconductor performance is needed. In addition, according to the highly layered and large-sized substrate, the warping characteristics of the substrate have also emerged as an important characteristic. Therefore, a technology that can improve the warping characteristics of the substrate is needed. Summary of the invention

[0004] An aspect of the inventive concept is to provide a stacked substrate structure capable of coping with a high degree of layering and a large size of a substrate and an electronic device including the stacked substrate structure.

[0005] Another aspect of the inventive concept is to provide a stacked substrate structure capable of reducing costs and an electronic device including the stacked substrate structure.

[0006] Another aspect of the inventive concept is to provide a stacked substrate structure capable of easily improving a warpage characteristic and an electronic device including the stacked substrate structure.

[0007] According to an aspect of the present disclosure, printed circuit boards are stacked on printed circuit boards, thereby providing a stacked substrate structure.

[0008] According to another aspect of the present disclosure, in the stacked substrate structure, a lower side of the reinforcement structure is spaced apart from the printed circuit board and an upper side of the reinforcement structure is attached to a lower surface of the printed circuit board, and the reinforcement structure is fixed by an underfill resin.

[0009] According to one aspect of the inventive concept, a stacked substrate structure includes: a first printed circuit board having a first side and a second side opposite to the first side; a second printed circuit board disposed on the second side of the first printed circuit board and having a first side connected to the second side of the first printed circuit board and a second side opposite to the first side connected to the second side of the first printed circuit board; a reinforcement structure attached to the first side of the second printed circuit board and spaced apart from the second side of the first printed circuit board; and an underfill resin disposed between the second side of the first printed circuit board and the first side of the second printed circuit board and covering at least a portion of the reinforcement structure.

[0010] For example, an electronic device includes: a main board; a first printed circuit board, which is arranged on the upper side of the main board; a second printed circuit board, which is arranged on the upper side of the first printed circuit board; an electronic component, which is arranged on the upper side of the second printed circuit board; a reinforcement structure, which is arranged between the first printed circuit board and the second printed circuit board, attached to the lower side of the second printed circuit board, and spaced apart from the first printed circuit board; and a bottom filling resin, which is arranged between the first printed circuit board and the second printed circuit board and covers at least a portion of the reinforcement structure.

[0011] For example, an electronic device includes: a first printed circuit board; a first electrically connecting metal piece, which is arranged on the lower side of the first printed circuit board; a second printed circuit board, which is arranged on the upper side of the first printed circuit board; a second electrically connecting metal piece, which is arranged between the upper side of the first printed circuit board and the lower side of the second printed circuit board, and connects the first printed circuit board and the second printed circuit board to each other; a third electrically connecting metal piece, which is arranged on the upper side of the second printed circuit board; and a reinforcing structure, which is arranged between the first printed circuit board and the second printed circuit board, attached to the lower side of the second printed circuit board, and spaced apart from the first printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0014] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0015] Figure 3 is a schematic cross-sectional view showing an example of a stacked substrate structure;

[0016] Figure 4 It is along Figure 3 A schematic plan view of a stacked substrate structure taken along line II';

[0017] Figure 5 It is shown Figure 3 A schematic cross-sectional view of an example of a first printed circuit board; and

[0018] Figure 6 It is shown Figure 3 Schematic cross-sectional view of an example of a second printed circuit board. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0020] However, the present disclosure may be exemplified in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] Throughout the specification, it will be understood that when an element (such as a layer, region, or wafer (substrate)) is referred to as being "on", "connected to", or "bonded to" another element, the element may be directly "on", "connected to", or "bonded to" the other element, or there may be other elements intervening therebetween. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly bonded to" another element, there may be no elements intervening therebetween. Similar reference numerals refer to similar elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0022] It will be apparent that, although the terms "first," "second," "third," etc., may be used herein to describe various members, components, regions, layers, and / or portions, these members, components, regions, layers, and / or portions should not be limited to these terms. These terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Thus, the first member, first component, first region, first layer, or first portion discussed below may be referred to as a second member, second component, second region, second layer, or second portion without departing from the teachings of the exemplary embodiments.

[0023] For ease of description, spatially relative terms such as "above," "above," "below," and "below" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, the elements described as being "above" or "above" other elements or features will then be positioned as being "below" or "below" the other elements or features. Therefore, the term "above" may include both above and below orientations depending on the particular orientation of the drawing. The device may be otherwise positioned (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0024] The terms used herein describe only specific embodiments, and the present disclosure is not limited thereto. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be further understood that when used in this specification, the terms "include" and / or "comprise" list the existence of stated features, integers, steps, operations, components, elements and / or their groups, but do not exclude the existence or addition of one or more other features, integers, steps, operations, components, elements and / or their groups.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to schematic diagrams showing embodiments of the present disclosure. In the accompanying drawings, for example, variations in the shapes shown may be estimated due to manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown herein, for example, to include shape variations due to manufacturing. The following embodiments may also be composed of one or a combination of them.

[0026] The contents of the present disclosure described below may have various configurations, and only required configurations are presented here, but are not limited thereto.

[0027] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0028] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically or electrically connected to the mainboard 1010. These electronic components may be connected to other components to be described below through various signal lines 1090.

[0029] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters, application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have a package form including the above-mentioned chips or electronic components.

[0030] The network-related components 1030 may include components operating according to protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating according to various other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with each other together with the chip-related component 1020 described above.

[0031] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components in the form of chip components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the chip-related components 1020 or the network-related components 1030 described above.

[0032] The electronic device 1000 includes other electronic components that may or may not be physically connected or electrically connected to the mainboard 1010, depending on the type of the electronic device 1000. A camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. may be provided as examples of other electronic components. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disc (CD), a digital versatile disc (DVD), etc. In addition, other electronic components for various purposes may be included according to the type of the electronic device 1000.

[0033] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0034] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0035] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the electronic components 1120 may be the above-mentioned chip-related components (e.g., semiconductor packages 1121), but are not limited thereto. The semiconductor package 1121 may be a package substrate in the form of a multi-layer printed circuit board, or may have a form in which a semiconductor chip or a passive component is mounted on a surface of a laminated substrate structure including a multi-layer printed circuit board, but is not limited thereto. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0036] Figure 3 is a schematic cross-sectional view showing an example of a stacked substrate structure.

[0037] Figure 4 It is along Figure 3 Schematic plan view of the stacked substrate structure taken along line II'.

[0038] Reference Figure 3 and Figure 4, the laminated substrate structure according to the embodiment includes: a first printed circuit board 100; a second printed circuit board 200 disposed on the first printed circuit board 100; and a reinforcement structure 400 attached to the lower side of the second printed circuit board 200 and spaced apart from the first printed circuit board 100 (e.g., the upper side of the first printed circuit board 100). The laminated substrate structure 500 may further include an underfill resin 450 disposed between the first printed circuit board 100 and the second printed circuit board 200 and covering at least a portion of the reinforcement structure 400. The reinforcement structure 400 is provided for warpage control, and the reinforcement structure 400 may be a stiffener, but is not limited thereto.

[0039] As described above, the laminated substrate structure 500 according to the embodiment may have a stacked structure of the first printed circuit board 100 and the second printed circuit board 200 corresponding to a high degree of stratification and a large size. Therefore, compared with the case where a substrate having a high degree of stratification and a large size is manufactured by only one printed circuit board, the technical difficulty can be reduced, the yield can be increased, and as a result, the cost can be reduced. In addition, the wiring designs of the first printed circuit board 100 and the second printed circuit board 200 are different from each other, and an optimal wiring design can be implemented, and as a result, more excellent performance can be provided.

[0040] In addition, in the laminated substrate structure 500 according to the embodiment, the reinforcement structure 400 is disposed between the first printed circuit board 100 and the second printed circuit board 200, and thus the warpage characteristics can be effectively improved. The reinforcement structure 400 can be introduced in a state of being attached to the lower side of the second printed circuit board 200, and can be spaced apart from the first printed circuit board 100. In this case, the reinforcement structure 400 can be attached to the second printed circuit board 200 in advance, and then the assembly process of the first printed circuit board 100 and the second printed circuit board 200 can be performed. In this regard, the reinforcement structure 400 can be easily introduced into the laminated substrate structure 500 according to the example without problems such as alignment defects.

[0041] In addition, in the laminated substrate structure 500 according to the embodiment, the bottom filling resin 450 covers at least a portion of the reinforcement structure 400. In this regard, the reinforcement structure 400 can be stably fixed. In an embodiment, the bottom filling resin 450 fills at least a portion of the space between the first printed circuit board 100 and the reinforcement structure 400. In this case, the bottom filling resin 450 covers the reinforcement structure 400 in the form of surrounding the side surface and the lower surface of the reinforcement structure 400. In this regard, the reinforcement structure 400 can be more effectively and more stably fixed. The bottom filling resin 450 can also cover at least a portion of each of the plurality of second electrical connection metal pieces 290 and / or the passive components 350 to be described later, and also fix them. The bottom filling resin 450 may include a thermosetting resin such as an epoxy resin, but is not limited thereto. Alternatively, other materials may also be used for the bottom filling resin, as long as the bottom filling resin is disposed between the first printed circuit board 100 and the second printed circuit board 200 so that the reinforcement structure 400, the plurality of second electrical connection metal pieces 290 and / or the passive components 350 are embedded and fixed.

[0042] The electronic component 300 may be disposed on the upper side of the second printed circuit board 200. For example, the stacked substrate structure 500 according to the embodiment may be used as a package substrate. The electronic component 300 may be a known active component and / or a passive component. The electronic component 300 may be a semiconductor chip (for example, a memory chip (such as a volatile memory, a non-volatile memory, a flash memory, etc.), an application processor chip (such as a central processing unit, a graphics processor, a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.) or a logic chip (such as an analog-to-digital converter, an ASIC, etc.)). However, the embodiments of the present disclosure are not limited thereto. The electronic component 300 may be arranged in a package form as needed. In addition, the electronic component 300 may be provided as a plurality of electronic components, and each electronic component may be of the same type or of different types.

[0043] The passive component 350 may be surface mounted below the second printed circuit board 200. The passive component 350 may be electrically connected to the electronic component 300 through internal wiring of the second printed circuit board 200. The passive component 350 may be a known chip inductor or chip capacitor that may be surface mounted. By arranging the passive component 350, the electrical characteristics (e.g., power integrity (PI)) of the electronic component 300 may be improved.

[0044] The first printed circuit board 100 may be mounted on the main board 800 by a plurality of first electrical connection metal parts 190 having a first pitch P1. In addition, the second printed circuit board 200 may be mounted on the first printed circuit board 100 by a plurality of second electrical connection metal parts 290 having a second pitch P2. The plurality of second electrical connection metal parts 290 may be disposed between the upper side of the first printed circuit board 100 and the lower side of the second printed circuit board 200. In addition, the electronic component 300 may be mounted on the second printed circuit board 200 by a third electrical connection metal part 390 having a third pitch P3. The first pitch P1 may be larger than the second pitch P2, and the second pitch P2 may be larger than the third pitch P3. As described above, the laminated substrate structure 500 according to the embodiment may be mounted on the main board 800 of the electronic device such as a smart phone described above. In this case, the first printed circuit board 100 may have a size larger than that of the second printed circuit board 200, while the second printed circuit board 200 may have a size larger than that of the electronic component 300. For example, the first printed circuit board 100 may have a thickness greater than that of the second printed circuit board 200. In addition, the first printed circuit board 100 may have a planar area greater than that of the second printed circuit board 200.

[0045] The first printed circuit board 100 may include a plurality of first pads 122P with a first pitch P1' located below it. In addition, the second printed circuit board 200 may include a plurality of first pads 212P1 with a second pitch P2' located below it. In addition, the second printed circuit board 200 may include a plurality of second pads 212P2 with a third pitch P3' located above it. In addition, the first printed circuit board 100 may include a plurality of second pads 132P located above it, and the plurality of second pads 132P may have the same pitch as the second pitch P2', but is not limited thereto, and there may be a process error due to alignment, etc. The plurality of first pads 122P of the first printed circuit board 100 may be connected to a plurality of first electrical connection metal parts 190, respectively. Each of the plurality of second pads 132P of the first printed circuit board 100 and each of the plurality of first pads 212P1 of the second printed circuit board 200 may be connected to the second electrical connection metal part 290. Each of the plurality of second pads 212P2 of the second printed circuit board 200 may be connected to the third electrical connection metal member 390. Therefore, the first pitch P1' may be larger than the second pitch P2', and the second pitch P2' may be larger than the third pitch P3'. The first pitch P1 and the first pitch P1' are identical to each other, but there may be a process error due to alignment. This relationship may also be applied to the relationship between the second pitch P2 and the second pitch P2' and the relationship between the third pitch P3 and the third pitch P3'.

[0046] The reinforcement structure 400 may be continuously disposed along the edge of the lower side of the second printed circuit board 200. For example, the reinforcement structure 400 may be disposed to continuously surround the plurality of second electrical connection metal parts 290 and / or the passive components 350 along the edge of the lower side of the second printed circuit board 200 at the lower side of the second printed circuit board 200. For example, the reinforcement structure 400 may have a through portion (or may be referred to as a through hole) 400H, and the plurality of second electrical connection metal parts 290 and / or the passive components 350 may be disposed in the through portion 400H. By this arrangement, the size of the reinforcement structure 400 may be sufficiently ensured while minimizing the influence on the arrangement of the plurality of second electrical connection metal parts 290 and / or the passive components 350. In addition, if necessary, the reinforcement structure 400 may be divided into a plurality of units spaced apart from each other by an empty space, and in this case, the through portion 400H may be communicated with each of the empty spaces for dividing the reinforcement structure 400.

[0047] The reinforcement structure 400 may include a metal material and / or a ceramic material as a material. In this case, excellent rigidity maintenance and minimization of the difference in thermal expansion coefficient may be effective in warpage control. In addition, in the case of a metal-based material and / or a ceramic-based material, since the thermal conductivity is excellent compared to a molded resin or an insulating resin according to the prior art, the heat dissipation characteristics can also be improved. In addition, the formation process of the through-portion 400H can be performed using an etching process instead of a laser drilling process, and thus foreign matter defects can be fundamentally removed. As a metal-based material, in addition to ordinary metal materials such as copper (Cu) and aluminum (Al), an alloy with excellent rigidity and thermal conductivity can also be used. In this case, an alloy containing at least iron can be used. For example, an Fe-Ni-based alloy, an Invar alloy, or a Kovar alloy can be used, but is not limited thereto. In addition, in the case of using a ceramic-based material (such as a zirconium oxide (ZrO2)-based material, an aluminum oxide (Al2O3)-based material, a silicon carbide (SiC)-based material, a silicon nitride (Si3N4)-based material, etc.) instead of an alloy, a similar effect can be provided. If necessary, the material can be an insulating material. For example, the material of the reinforcement structure 400 can be a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), or a resin (for example, a prepreg) in which a thermosetting resin or a thermoplastic resin is impregnated in a core material (such as glass fiber) together with an inorganic filler. As an example, the reinforcement structure 400 may have a more excellent rigidity and may have a greater elastic modulus than the insulating material of the buildup layer (described later) of the second printed circuit board 200. The elastic modulus of the reinforcement structure 400 may be larger than each of the elastic modulus of the buildup layer of the first printed circuit board 100 and the elastic modulus of the buildup layer of the second printed circuit board 200.

[0048] The reinforcement structure 400 may be attached to the lower side of the second printed circuit board 200 by an adhesive 410. The adhesive 410 may be, for example, an epoxy resin-based adhesive, a silicone resin-based adhesive, etc., but is not limited thereto. Alternatively, an adhesive formed using various materials may be used as long as the adhesive can attach the reinforcement structure 400 to the second printed circuit board 200 to be fixed.

[0049] Figure 5 It is shown Figure 3 Schematic cross-sectional view of an example of a first printed circuit board.

[0050] Reference Figure 5 , the first printed circuit board 100 according to the embodiment may be a core-type printed circuit board (core PCB). For example, the first printed circuit board 100 according to the embodiment includes: a core layer 110; a first buildup layer 120, which is arranged below the core layer 110; a second buildup layer 130, which is arranged above the core layer; a plurality of first wiring layers 122, which are embedded in the first buildup layer 120; a plurality of second wiring layers 132, which are embedded in the second buildup layer 130; and a through-hole 115, which electrically connects the plurality of first wiring layers 122 and the plurality of second wiring layers 132 while penetrating the core layer 110. The layers of the plurality of first wiring layers 122 vertically adjacent to each other may be electrically connected to each other through the vias that penetrate the plurality of layers of the first buildup layer 120, and the layers of the plurality of second wiring layers 132 vertically adjacent to each other may be electrically connected to each other through the vias that penetrate the plurality of layers of the second buildup layer 130. The first passivation layer 140 may be arranged on the first buildup layer 120. The second passivation layer 150 may be arranged on the second buildup layer 130. The first passivation layer 140 may have a plurality of first openings that expose the first pads 122P, respectively, and the first electrical connection metal members 190 are respectively disposed on the first openings to be connected to the first pads 122P, respectively. The second passivation layer 150 may have a plurality of second openings that expose the second pads 132P, respectively, and the second electrical connection metal members 290 to be described later are respectively disposed on the second openings to be connected to the second pads 132P, respectively. In addition, the first printed circuit board 100 according to the embodiment does not necessarily have to be a core type, but may also be a coreless type.

[0051] The core layer 110 may be a core board (as the center of the first printed circuit board 100 according to the embodiment). For example, an insulating material may be used as the material of the core layer 110. In this case, the insulating material may be a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), or a material including a reinforcing material (such as glass fiber, glass cloth, glass fabric) and / or an inorganic filler and a thermosetting resin or a thermoplastic resin (for example, a copper clad laminate (CCL) or a bare CCL), etc. However, it is not limited thereto, and if necessary, the core layer 110 may be a metal plate or a glass plate, and may be a ceramic plate. If necessary, the material of the core layer 110 may be a liquid crystal polymer (LCP). For the purpose of warpage control, the core layer 110 may be thicker than the thickness of each insulating layer forming the buildup layers 120 and 130. In addition, for the purpose of warpage control, the core layer 110 may have a more excellent rigidity than each insulating layer forming the buildup layers 120 and 130. For example, the core layer 110 may have an elastic modulus greater than the elastic modulus of each insulating layer.

[0052] The buildup layers 120 and 130 may provide an insulating region for the formation of multilayer wiring on both sides based on the core layer 110. Each of the buildup layers 120 and 130 may include a plurality of insulating layers, and the boundaries between the insulating layers may be clear or unclear. The material of the insulating layer may be an insulating material. In this case, each insulating material may be a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), or a material including a reinforcing material (such as glass fiber) and / or an inorganic filler and a thermosetting resin or a thermoplastic resin (such as a prepreg, ABF (Ajinomoto Build-up Film), etc.). If necessary, the material of the insulating layer may be a photosensitive dielectric (PID) material. In addition, the insulating layer may include the same material, or may include different materials.

[0053] The material of the wiring layers 122 and 132 may also be a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. The wiring layers 122 and 132 may be formed using a plating process (e.g., an additive process (AP), a semi-AP (SAP), an improved SAP (MSAP), and a sealing hole (TT), etc.), and as a result, each wiring layer may include a seed layer (as an electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The wiring layers 122 and 132 may perform various functions according to the design of their corresponding layers. For example, the wiring layer may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signal patterns other than a ground pattern, a power pattern, etc., and may include, for example, a data signal pattern, etc. Each pattern may include a line pattern, a plane pattern, and / or a pad pattern. The material of the vias connected to the wiring layers 122 and 132 may be a metal material, and the vias are also formed using a plating process (such as AP, SAP, MSAP, TT, etc.). The vias may also perform various functions according to the design of the corresponding layer. For example, the vias may include wiring vias for signal connection, wiring vias for ground connection, wiring vias for power connection, etc. Each via may be formed by being completely filled with a metal material, or may be formed when a metal material is formed along the wall of the via hole. In addition, all shapes known in the prior art (such as a tapered shape, etc.) may be applied to the vias.

[0054] The through-via 115 can connect the wiring layers 122 and 132 respectively disposed below and above the core layer 110 to each other while penetrating the core layer 110. The material of the through-via 115 can also be a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. Each through-via 115 can also be formed using a plating process (such as AP, SAP, MSAP, TT, etc.), and as a result, each through-via layer can include a seed layer (as an electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The through-via 115 can include a through-via for signal connection, a through-via for ground connection, a through-via for power connection, etc. The through-via 115 can have a cylindrical shape, an hourglass shape, etc. If necessary, an insulating material can be filled in the through-via 115.

[0055] The passivation layers 140 and 150 are additional components that can protect the internal structure of the first printed circuit board 100 according to the embodiment from external physical damage and chemical damage. Each of the passivation layers 140 and 150 may include a thermosetting resin. For example, each of the passivation layers 140 and 150 may be ABF (Ajinomoto buildup film). However, it is not limited thereto, and each of the passivation layers 140 and 150 may be a known solder resist (SR) layer. In addition, if necessary, a PID material may be included in the passivation layers 140 and 150. Each of the passivation layers 140 and 150 may include a plurality of openings. In addition, through the plurality of openings, a surface treatment layer may be formed on the surface of the exposed pads 122P and 132P. The surface treatment layer may be formed using, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating / displacement plating, direct immersion gold (DIG) plating, hot air leveling (HASL), etc. If necessary, each opening may be formed using a plurality of via holes. If necessary, an under bump metallization (UBM) may be provided on each opening to improve reliability.

[0056] The electrical connection metal piece 190 is an additional component that can physically connect and / or electrically connect the first printed circuit board 100 according to the embodiment to the outside. For example, the first printed circuit board 100 according to the embodiment can be mounted on another substrate such as a mainboard of an electronic device through the electrical connection metal piece 190. For example, the first printed circuit board 100 according to the embodiment can be a part or the entirety of a ball grid array (BGA) type package. Each of the electrical connection metal pieces 190 can be disposed on a plurality of openings of the passivation layer 140, and each of the electrical connection metal pieces 290 can be disposed on a plurality of openings of the passivation layer 150. Each of the electrical connection metal pieces 190 can be formed using a metal having a lower melting point than copper (Cu), such as tin (Sn) or an alloy including tin (Sn). For example, each of the electrical connection metal pieces 190 can be formed using solder, but this is only an example, and its material is not limited thereto.

[0057] Each of the electrically connected metal parts 190 may be a pad, a solder ball, a pin, etc. The electrically connected metal parts 190 may be formed into a multilayer structure or a single layer structure. When the electrically connected metal parts include multiple layers, the electrically connected metal parts include a copper column and a solder. When the electrically connected metal parts include a single layer, the electrically connected metal parts include a tin-silver solder. However, the electrically connected metal parts are only examples, and the present disclosure is not limited thereto. The number, spacing, arrangement form, etc. of the electrically connected metal parts 190 are not specifically limited, but can be fully modified by those skilled in the art according to the design details.

[0058] Figure 6 It is shown Figure 3 Schematic cross-sectional view of an example of a second printed circuit board.

[0059] Reference Figure 6 , the second printed circuit board 200 according to the embodiment may be a coreless printed circuit board (coreless PCB). For example, the second printed circuit board 200 according to the embodiment includes a buildup layer 210 and a plurality of wiring layers 222 embedded in the buildup layer 210. The layers vertically adjacent to each other of the plurality of wiring layers 222 may be electrically connected to each other by vias including a plurality of layers penetrating the buildup layer 210. The first passivation layer 240 may be disposed below the buildup layer 210. The second passivation layer 250 may be disposed above the buildup layer 210. The first passivation layer 240 may have a plurality of first openings that expose the first pads 212P1, respectively, and the second electrical connection metal pieces 290 are respectively disposed on the first openings to be connected to the first pads 212P1, respectively. The second passivation layer 250 may have a plurality of second openings that expose the second pads 212P2, respectively, and the third electrical connection metal pieces 390 are respectively disposed on the second openings to be connected to the second pads 212P2, respectively. Furthermore, the second printed circuit board 200 according to the embodiment does not necessarily have to be a coreless type but may also be a core type.

[0060] The buildup layer 210 may provide an insulating region for the formation of multilayer wiring. The buildup layer 210 may include a plurality of insulating layers, and the boundaries between the insulating layers may be clear or unclear. The material of the insulating layer may be an insulating material. In this case, each insulating material may be a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), or a material (such as a prepreg, ABF, etc.) including a reinforcing material (such as glass fiber) and / or an inorganic filler and a thermosetting resin or a thermoplastic resin. If necessary, the material of the insulating layer may be a PID material. In addition, the insulating layer may include the same material, or may include different materials.

[0061] The material of the wiring layer 222 may be a metal material, and in this case, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The wiring layer 222 may be formed using a plating process (e.g., an additive process (AP), a semi-AP (SAP), an improved SAP (MSAP), and a sealing hole (TT), etc.), and as a result, each wiring layer may include a seed layer (as an electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The wiring layer 222 may perform various functions according to the design of the corresponding layer. For example, the wiring layer may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signal patterns other than the ground pattern, the power pattern, etc., and may include, for example, a data signal pattern, etc. Each pattern may include a line pattern, a plane pattern, and / or a pad pattern. The material of the via connected to the wiring layer 222 may be a metal material, and the via is also formed using a plating process (such as, AP, SAP, MSAP, TT, etc.). The via may also perform various functions according to the design of the corresponding layer. For example, the vias may include wiring vias for signal connection, wiring vias for ground connection, wiring vias for power connection, etc. Each via may be formed by being completely filled with a metal material, or may be formed when a metal material is formed along the wall of the via hole. In addition, all shapes known in the prior art (such as a tapered shape, etc.) may be applied to the vias.

[0062] The passivation layers 240 and 250 are additional components that can protect the internal structure of the second printed circuit board 200 according to the embodiment from external physical damage and chemical damage. Each of the passivation layers 240 and 250 may include a thermosetting resin. For example, each of the passivation layers 240 and 250 may be ABF (Ajinomoto buildup film). However, it is not limited thereto, and each of the passivation layers 240 and 250 may be a known SR layer. In addition, if necessary, a PID material may be included in the passivation layers 240 and 250. Each of the passivation layers 240 and 250 may include a plurality of openings. In addition, through the plurality of openings, a surface treatment layer may be formed on the surface of the exposed pads 212P1 and 212P2. The surface treatment layer may be formed by, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / alternative gold plating, DIG plating, HASL, etc. If necessary, each opening may be formed using a plurality of vias. If necessary, a UBM may be provided on each opening to improve reliability.

[0063] The electrical connection metal parts 290 and 390 are additional components that can physically connect and / or electrically connect the second printed circuit board 200 according to the embodiment to the outside. For example, the second printed circuit board 200 according to the embodiment can be mounted on another printed circuit board through the second electrical connection metal part 290. In addition, the electronic component can be mounted on the second printed circuit board 200 according to the embodiment through the third electrical connection metal part 390. For example, the second printed circuit board 200 according to the embodiment can be a part or the whole of a BGA type package. Each of the electrical connection metal parts 290 can be arranged on a plurality of openings of the passivation layer 240, and each of the electrical connection metal parts 390 can be arranged on a plurality of openings of the passivation layer 250. Each of the electrical connection metal parts 290 and 390 can be formed using a metal having a lower melting point than copper (Cu) (e.g., tin (Sn) or an alloy including tin (Sn)). For example, each of the electrical connection metal parts 290 and 390 can be formed using solder, but this is only an example, and its material is not limited thereto.

[0064] Each of the electrically connected metal parts 290 and 390 can be a pad, a solder ball, a pin, etc. The electrically connected metal parts 290 and 390 can be formed into a multi-layer structure or a single-layer structure. When the electrically connected metal part includes multiple layers, the electrically connected metal part includes a copper column and a solder. When the electrically connected metal part includes a single layer, the electrically connected metal part includes a tin-silver solder. However, the electrically connected metal part is only an example, and the present disclosure is not limited thereto. The number, spacing, arrangement form, etc. of the electrically connected metal parts 290 and 390 are not specifically limited, but can be fully modified by those skilled in the art according to the design details.

[0065] As described above, according to example embodiments of the inventive concept, a stacked substrate structure capable of coping with a high degree of layering and a large size of a substrate and an electronic device including the stacked substrate structure may be provided.

[0066] Furthermore, a stacked substrate structure capable of reducing costs and an electronic device including the stacked substrate structure can be provided.

[0067] Furthermore, a laminated substrate structure capable of easily improving warpage characteristics and an electronic device including the laminated substrate structure can be provided.

[0068] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A laminated substrate structure, comprising: a first printed circuit board having a first side and a second side opposite the first side; a second printed circuit board disposed on a second side of the first printed circuit board, the second printed circuit board having a first side connected to the second side of the first printed circuit board, and the second printed circuit board having a second side opposite to the first side of the second printed circuit board; a reinforcement structure attached to an edge of the first side of the second printed circuit board and spaced apart from the second side of the first printed circuit board; and An underfill resin is disposed between the second side of the first printed circuit board and the first side of the second printed circuit board and covers at least a portion of the reinforcement structure and the second printed circuit board, respectively.

2. The laminated substrate structure according to claim 1, further comprising: a plurality of electrical connection metal members disposed between the second side of the first printed circuit board and the first side of the second printed circuit board and connecting the second side of the first printed circuit board to the first side of the second printed circuit board, The bottom filling resin covers at least a portion of each of the plurality of electrical connection metal parts.

3. The laminated substrate structure according to claim 2, further comprising: passive components mounted on the first side of the second printed circuit board, Wherein, the bottom filling resin covers at least a portion of the passive component.

4. The laminated substrate structure according to claim 3, wherein: The reinforcing structure has a through portion, and The plurality of electrical connection metal parts and the passive components are disposed in the through portion.

5. The laminated substrate structure according to claim 1, wherein: The reinforcement structure is disposed continuously along an edge of the first side of the second printed circuit board.

6. The laminated substrate structure according to claim 1, wherein: The reinforcement structure is attached to the first side of the second printed circuit board by an adhesive.

7. The laminated substrate structure according to claim 1, wherein: The underfill resin is disposed in at least a portion of a space between the second side of the first printed circuit board and the reinforcement structure.

8. The laminated substrate structure according to claim 1, wherein: The first printed circuit board is a core type printed circuit board, and The second printed circuit board is a coreless type printed circuit board.

9. The laminated substrate structure according to claim 8, wherein: The first printed circuit board is thicker than the second printed circuit board.

10. The laminated substrate structure according to claim 8, wherein: The first printed circuit board has a larger plane area than the second printed circuit board.

11. The laminated substrate structure according to claim 1, wherein: The first printed circuit board includes first pads having a first pitch on a first side of the first printed circuit board, The second printed circuit board includes second pads having a second pitch on a first side of the second printed circuit board, and The first pitch is greater than the second pitch.

12. The laminated substrate structure according to claim 11, wherein: The second printed circuit board also includes third pads having a third pitch on a second side of the second printed circuit board, and The second pitch is greater than the third pitch.

13. An electronic device comprising: Motherboard; A first printed circuit board, disposed on the upper side of the main board; a second printed circuit board disposed on an upper side of the first printed circuit board; an electronic component disposed on an upper side of the second printed circuit board; a reinforcement structure disposed between the first printed circuit board and the second printed circuit board, attached to an edge of a lower side of the second printed circuit board, and spaced apart from the first printed circuit board; as well as An underfill resin is disposed between the first printed circuit board and the second printed circuit board and covers at least a portion of the reinforcement structure and the second printed circuit board, respectively.

14. The electronic device according to claim 13, wherein: The first printed circuit board is mounted on the main board through a plurality of first electrical connection metal parts having a first pitch. The second printed circuit board is mounted on the first printed circuit board through a plurality of second electrical connection metal members having a second pitch, The electronic component is mounted on the second printed circuit board through a plurality of third electrical connection metal members having a third pitch, The first pitch is larger than the second pitch, and The second pitch is greater than the third pitch.

15. A laminated substrate structure comprising: a first printed circuit board; a first electrical connection metal member, disposed on the lower side of the first printed circuit board; a second printed circuit board disposed on an upper side of the first printed circuit board; a second electrical connection metal member disposed between the upper side of the first printed circuit board and the lower side of the second printed circuit board and connecting the first printed circuit board and the second printed circuit board to each other; a third electrical connection metal member, disposed on the upper side of the second printed circuit board; as well as a reinforcement structure disposed between the first printed circuit board and the second printed circuit board, attached to an edge of a lower side of the second printed circuit board, and spaced apart from the first printed circuit board; An underfill resin is disposed between the first printed circuit board and the second printed circuit board and covers at least a portion of the reinforcement structure and the second printed circuit board, respectively.

16. The laminated substrate structure according to claim 15, wherein: The first printed circuit board is mounted on a main board of the electronic device through the first electrical connection metal member.

17. The laminated substrate structure according to claim 15, wherein: The reinforcement structure includes at least one of metal and ceramic.

18. The laminated substrate structure according to claim 15, wherein: The reinforcing structure has an elastic modulus greater than each of an elastic modulus of a buildup layer of the first printed circuit board and an elastic modulus of a buildup layer of the second printed circuit board.

19. The laminated substrate structure according to claim 15, wherein: The reinforcement structure has a through hole, and each of the second electrical connection metal members is disposed in the through hole.

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