Method and apparatus for adaptive alignment

Abstract

A method for aligning a wafer image with a reference image, comprising: searching for a target reference position on the wafer image to align the wafer image with the reference image; and in response to determining that the target reference position does not exist: defining a current locked position and an area surrounding the current locked position on the wafer image; calculating an alignment score for the current locked position; comparing the alignment score of the current locked position with a stored alignment score of a previously selected position for aligning the wafer image with the reference image; and aligning the wafer image with the reference image based on the comparison.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of U.S. Application No. 62 / 749,566, filed on October 23, 2018, the entire content of which is incorporated herein by reference. Technical Field

[0003] Embodiments consistent with the present disclosure generally relate to alignment methods, and more particularly to alignment methods for defect detection during semiconductor manufacturing operations. Background Art

[0004] During the manufacture of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems using optical microscopes or charged particle (e.g., electron) beam microscopes, such as scanning electron microscopes (SEM), can be employed. As the physical dimensions of IC components continue to shrink, the accuracy and effectiveness of defect detection become increasingly important. However, the imaging resolution and throughput of inspection tools struggle to keep pace with the decreasing feature sizes of IC components. Further improvements to the prior art are needed. Summary of the Invention

[0005] According to some embodiments of the present disclosure, a method for aligning a wafer image with a reference image is provided. The method may include: searching a database for a target reference position for aligning the wafer image with the reference image; and in response to determining that the target reference position does not exist in the database: identifying a current locked position and a region surrounding the current locked position on the wafer image; calculating an alignment score for the current locked position; comparing the alignment score of the current locked position with a stored alignment score of a previously selected position for aligning the wafer image with the reference image; and aligning the wafer image with the reference image based on the comparison.

[0006] In the method, aligning the wafer image with the reference image based on the comparison may further include: in response to determining that the alignment score of the current locked position meets a threshold condition: storing the positioning information and alignment score of the current locked position on the database to facilitate determination of the target reference position; and using the current locked position to align the region surrounding the current locked position with the reference image.

[0007] In the method, when the alignment score of the current locked position is higher than the stored alignment score of a position located within the region surrounding the current locked position, which is a previously selected position for aligning the wafer image with the reference image, the alignment score of the current locked position may meet the threshold condition.

[0008] In this method, aligning the image with the reference image based on comparison may further include: in response to determining that the alignment score at the current locked position does not meet the threshold condition: selecting the highest alignment score among the stored alignment scores; and aligning the region surrounding the current locked position with the reference image using the locked position corresponding to the highest alignment score.

[0009] In this method, the threshold condition may not be met when the alignment score at the current locked position is lower than the stored alignment scores of positions located within the region surrounding the current locked position, and the positions located within the region surrounding the current locked position are positions previously selected for aligning the wafer image with the reference image. The locked position corresponding to the highest alignment score may be a positioning point within the field of view and different from the current locked position. The region surrounding the current locked position may be the field of view or a part of the field of view.

[0010] In this method, the positions previously selected for aligning the wafer image with the reference image may include positions located within the region surrounding the current locked position, which are the first part of the previously selected positions, or may include positions not located within the region surrounding the current locked position, which are the second part of the previously selected positions. The positions previously selected for aligning the wafer image with the reference image include positions located within the region surrounding the current locked position, which are the first part of the previously selected positions, or may include positions not located within the region surrounding the current locked position, which are the second part of the previously selected positions, and may further include: the positions located within the region surrounding the current locked position are the first part of the previously selected positions; and the positions not located within the region surrounding the current locked position are the second part of the previously selected positions. The first part may be one or more positions among the previously selected positions, and the second part may be one or more positions among the previously selected positions. The first part may not be any of the previously selected positions, and the second part may be all of the previously selected positions. The first part may be all of the previously selected positions, and the second part may not be any of the previously selected positions.

[0011] In this method, the dimensions of the region surrounding the current locked position and the dimensions of the region surrounding the target reference position can be in the range from millimeters to nanometers. The current locked position can be defined based on a comparison of the number of features present on different ranges of the wafer. The current locked position can be defined based on a comparison of the number of pattern edges present on different ranges of the wafer. The current locked position can be substantially positioned at the center of the region surrounding the current locked position of the wafer. The determination of the target reference position can further include: identifying the current locked position as the target reference position. The identification of the target reference position can be based on a comparison between the total number of times the position has been selected as a locked position in previous alignments and a threshold number. The threshold number can be 20. The reference image can include a Graphics Data System (GDS). The reference image can be an image of a different wafer.

[0012] According to some embodiments of the present disclosure, an electron beam inspection apparatus is provided, including: a controller having circuitry to cause the electron beam inspection apparatus to perform the following: search for a target reference position in a database; and in response to determining that the target reference position does not exist in the database: define a current locked position and a region surrounding the current locked position on a wafer image; calculate an alignment score for the current locked position; compare the alignment score of the current locked position with a stored alignment score of a position previously selected for aligning the wafer image with a reference image; and align the wafer image with the reference image based on the comparison.

[0013] In this apparatus, aligning the wafer image with the reference image based on the comparison can further include: in response to determining that the alignment score of the current locked position meets a threshold condition: storing the positioning information and the alignment score of the current locked position in the database for facilitating the determination of the target reference position; and using the current locked position to align the region surrounding the current locked position with the reference image.

[0014] In this apparatus, aligning the wafer image with the reference image based on the comparison can further include: in response to determining that the alignment score of the current locked position does not meet the threshold condition: selecting the highest alignment score among the stored alignment scores; and using the locked position corresponding to the highest alignment score to align the region surrounding the current locked position with the reference image.

[0015] According to some embodiments of the present disclosure, a non-transitory computer-readable medium storing instructions is provided, and the instructions can be executed by a controller of a device to cause the device to perform a method including: searching for a target reference position in a database; and in response to determining that the target reference position does not exist in the database: defining a current locked position and a region surrounding the current locked position on a wafer image; calculating an alignment score of the current locked position; comparing the alignment score of the current locked position with a stored alignment score of a previously selected position for aligning the wafer image with a reference image; and aligning the wafer image with the reference image based on the comparison.

[0016] In the non-transitory computer-readable medium, aligning the wafer image with the reference image based on the comparison may further include: in response to determining that the alignment score of the current locked position meets a threshold condition: storing the positioning information and the alignment score of the current locked position on the database to facilitate determining the target reference position; and using the current locked position to align the region surrounding the current locked position with the reference image.

[0017] In the non-transitory computer-readable medium, aligning the wafer image with the reference image based on the comparison may further include: in response to determining that the alignment score of the current locked position does not meet the threshold condition: selecting the highest alignment score from the stored alignment scores; and using the locked position corresponding to the highest alignment score to align the region surrounding the current locked position with the reference image. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A is a schematic scanning electron microscope (SEM) image alignment diagram showing precise alignment, and Figure 1B is a schematic SEM image alignment diagram showing non-precise alignment consistent with some embodiments of the present disclosure.

[0019] Figure 2 is a block diagram of an exemplary alignment system consistent with some embodiments of the present disclosure.

[0020] Figure 3 is a schematic diagram of an exemplary electron beam inspection (EBI) system consistent with some embodiments of the present disclosure.

[0021] Figure 4 is a schematic diagram of an exemplary electron beam tool consistent with some embodiments of the present disclosure, and the electron beam tool can be Figure 3 a part of the exemplary electron beam inspection (EBI) system.

[0022] Figure 5 is a flowchart of an exemplary method indicating aligning an image of a wafer with a reference image consistent with some embodiments of the present disclosure.

[0023] Figure 6 is a flowchart showing a detailed exemplary method for aligning a wafer image with a reference image in accordance with some embodiments of the present disclosure.

[0024] Figure 7 is a flowchart showing a detailed exemplary method for aligning a wafer image with a reference image in accordance with some embodiments of the present disclosure.

[0025] Figure 8 is a flowchart showing a detailed exemplary method for aligning a wafer image with a reference image in accordance with some embodiments of the present disclosure.

[0026] Figure 9 is a schematic diagram showing an SEM image for inspection and a locked position defined on the SEM image in accordance with some embodiments of the present disclosure.

[0027] Figure 10 and Figure 11 is a schematic diagram showing a comparison of the alignment score of the current locked position with the alignment scores of some positions near the current locked position in accordance with some embodiments of the present disclosure. Detailed Description

[0028] Reference will now be made in detail to exemplary embodiments, which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, where like numerals in different drawings represent the same or similar elements unless otherwise noted. The embodiments set forth in the following description of the exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with aspects of the present invention as recited in the appended claims. For example, although some embodiments are described in the context of using an electron beam inspection (EBI) system (e.g., a scanning electron microscope (SEM)) to generate wafer images, the present disclosure is not limited thereto. Other types of inspection systems and image generation systems may be similarly applied.

[0029] The enhanced computing power of an electronic device, while reducing the physical size of the device, can be achieved by significantly increasing the packaging density of circuit components on an IC chip, such as transistors, capacitors, diodes, etc. For example, in a smart phone, an IC chip (the size of a thumbnail) can include over two billion transistors, each transistor being less than 1 / 1000 the size of a human hair. Not surprisingly, semiconductor IC manufacturing is a complex process with hundreds of individual steps. Even an error in one step has the potential to significantly affect the functionality of the final product. Even a "fatal defect" can cause the device to malfunction. The goal of the manufacturing process is to increase the overall yield of the process. For example, for a 50-step process, to achieve a 75% yield, each individual step must have a yield greater than 99.4%, and if the yield of an individual step is 95%, the overall process yield drops to 7%.

[0030] In various steps of the semiconductor manufacturing process, pattern defects may occur on at least one of the wafer, chip, or mask, which may cause the manufactured semiconductor device to fail, thus significantly reducing the yield. As the size of semiconductor devices (along with any defects) continues to become smaller and smaller, identifying defects becomes more challenging and expensive. Currently, engineers in semiconductor manufacturing lines typically spend hours (and sometimes even days) identifying the location points of small defects to minimize their impact on the final product.

[0031] Traditional optical inspection techniques are ineffective in inspecting small defects (e.g., nanoscale defects). Advanced electron beam inspection (EBI) tools, such as scanning electron microscopes (SEM) with high resolution and large depth of focus, have been developed to meet the needs in the semiconductor industry. An important step during defect inspection in EBI tools is to align the wafer image with a reference image (e.g., a Graphics Data System (GDS) file). For example, the SEM image of the wafer can be superimposed on the reference image, and then the position of the wafer image relative to the reference image can be adjusted until the features in the wafer image are substantially matched with the features in the reference image. In this way, the wafer image to be inspected can be mapped to the reference image coordinates, and the defect location points on the wafer image can be identified in the reference image coordinates.

[0032] Although EBI tools play a key role in the detection of small defects in semiconductor wafers, they are sensitive to the alignment accuracy between the wafer image and the reference image. Since the pixel size of the SEM image is small, there is not much room for alignment error. Therefore, alignment accuracy is crucial for EBI tools when inspecting wafers and identifying defects.

[0033] However, alignment is a challenging task, especially when there is a large amount of noise or distortion in the image, or when most of the image has a periodic pattern (e.g., an array pattern where each element looks similar to all other elements, making it difficult to match a specific element in the wafer image with its corresponding element in the reference image). Another inherent challenge in alignment is that it is difficult to have a uniform metric / score threshold to distinguish between precise alignment and imprecise alignment.

[0034] The disclosed embodiments provide an adaptive alignment process that improves alignment accuracy during a defect inspection process. The alignment process generates an alignment score based on selected positioning points on an image or a reference image, and aligns the image with the reference image to generate the alignment score. The alignment score and the selected positioning points can be stored for later reference.

[0035] When the next image is ready for inspection, the alignment process can generate a second alignment score, which can be compared with the previously stored alignment score. If the second alignment score is higher than the stored score, the second alignment score and its corresponding selected positioning points are stored for later reference. This process can continue until all images have been inspected. By consistently updating the storage pool with alignment scores and their corresponding selected positioning points and evaluating whether there are better candidates, the accuracy of alignment is improved.

[0036] In addition, the adaptive alignment process can be performed without manual intervention and can accelerate the inspection process, resulting in higher throughput. Unless otherwise stated, the term "or" as used herein includes all possible combinations, unless it is infeasible. For example, if it is stated that a database can include A or B, then the database can include A, or B, or A and B, unless otherwise specifically stated or infeasible. As a second example, if it is stated that a database can include A, B, or C, then the database can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C, unless otherwise explicitly stated or infeasible.

[0037] Now referring to Figure 1A and Figure 1B , which Figure 1A is a schematic SEM image alignment diagram showing precise alignment, Figure 1B is a schematic SEM image alignment diagram showing imprecise alignment. As Figure 1AAs shown, the wafer image 110 has a hole pattern generated during the semiconductor manufacturing process. The hole pattern in the wafer image 110 has a missing hole defect 102 that needs to be identified. The reference image 120 (which corresponds to the wafer image 110) has a square pattern including a square 104 at the positioning point corresponding to the hole defect 102 on the wafer image. During the alignment process, the wafer image 110 is superimposed on the reference image 120, and then the position of the wafer image 110 relative to the reference image 120 is adjusted such that the hole pattern of the wafer image 110 substantially fits the square pattern in the reference image 120, thereby indicating precise alignment, as shown in the superimposed image 130. In this way, the wafer image 110 is mapped to the reference image coordinates (e.g., the x-y coordinates shown in the figure), and the positioning point of the hole defect 102 on the wafer image 110 can be accurately identified by the position of the square 104 (the superimposed hole defect 102 on the superimposed image 130) in the x-y coordinates.

[0038] Figure 1B Shows an example of non-precise alignment. As Figure 1B shown, the wafer image 140 has a hole pattern generated during the semiconductor manufacturing process. The hole pattern in the wafer image 140 has holes 106. The reference image 150 has a square pattern including a square 108 at the position corresponding to the holes 106. In this exemplary alignment process, the wafer image 140 is superimposed on the reference image 150, but the position of the wafer image 140 relative to the reference image 150 is not adjusted such that the hole pattern of the wafer image 140 substantially fits the square pattern in the reference image 150. More specifically, the square pattern is shifted to the left by an amount of the periodic distance T, as evidenced by the distance T interval between the square 108 and the holes 106 on the superimposed image 160 (if the alignment were precise, the square and the holes should be superimposed). Thus, the defect position on the wafer image 140 cannot be accurately identified in the reference image coordinates (e.g., the x-y coordinates as shown in the figure).

[0039] To help determine whether the alignment is precise, an alignment algorithm can be used to generate an alignment score. The alignment score can be used to indicate the precision of the alignment, where a higher alignment score indicates a more precise alignment. The alignment score can be determined based on the difference in pixel intensity values between the wafer image and the reference image (e.g., the sum of the squared differences in intensity between the wafer image and the reference image). Alternatively, the alignment score can be determined based on the correlation coefficient between the wafer image and the reference image.

[0040] Some alignment score algorithms may not be optimal. For example, Figure 1A and Figure 1BThe alignment shown, even if different, may result in very similar alignment scores. Due to the lack of a unified metric to evaluate the alignment results, it is difficult to control the alignment error, and misalignment leads to a high interference rate in the defect detection results. For example, the interference can be false positive defects, and the interference rate can be expressed as the ratio between the number of false positive defects and the total number of marked defects. In Figure 1B as shown, due to misalignment, hole 106 is not aligned with square 108. As a result, the hole can be marked as a defect when hole 106 is actually not a defect but is caused by the misalignment of the wafer image with the reference image. This is an example of imprecise alignment that produces false positives (i.e., interference). It can be imagined that imprecise alignment can produce a large number of false positives in the detection results, leading to a higher interference rate for a particular image.

[0041] In another example including a given image A and two reference images R1 and R2, defects can be identified by calculating the intensity differences D1 and D2 between image A and the two reference images R1 and R2, i.e., D1 = |A - R1| and D2 = |A - R2|. If image A has a defect, the defect will manifest in the difference calculations D1 and D2. In the case where image A is defect-free and the alignment of image A with reference images R1 and R2 is optimal, the pixel values in the difference calculations D1 and D2 will be zero or close to zero. However, in the case of imprecise alignment, there are many non-zero pixels in the difference calculations D1 and D2, resulting in features on image A being incorrectly marked as defects (i.e., false positives or interference). Since time or computational resources must be spent analyzing these false positives, false positive defects such as these increase the difficulty for an operator or an automatic defect classifier to identify the true defects of interest. Therefore, traditional alignment systems may have difficulty distinguishing imprecise alignment from precise alignment. Accordingly, there is a need for an accurate and adaptive alignment method for defect detection in wafers.

[0042] Now refer to Figure 2 which is a block diagram showing an exemplary alignment system consistent with some embodiments of the present disclosure. As Figure 2 shown, alignment system 200 includes a computer system 202, an inspection system 212, and a reference storage device 210. Computer system 202 also includes a processor 204, a storage medium 206, and a user interface 208. Processor 204 can include multiple processors, and storage medium 206 and reference storage device 210 can be the same single storage medium. Computer system 202 communicates with inspection system 212 and reference storage device 210 via wired communication or wireless communication.

[0043] The computer system 202 may include, but is not limited to, a personal computer, a workstation, a network computer, or any device having one or more processors. The storage medium 206 stores alignment instructions, and the processor 204 is configured (via its circuitry) to execute the alignment instructions to control the alignment process. The processor 204 is configured to build a plurality of alignment knowledge files based on a plurality of alignments of the patch images. A patch image is a small image (e.g., 34×34 pixels) of a portion of a wafer. The plurality of patch images may be generated by the wafer inspection system 212. The processor 204 is configured to process the patch images transmitted from the inspection system 212 and perform the alignment of the patch images of the wafer with the reference images transmitted from the reference storage device 210.

[0044] The user interface 208 includes a display configured to display the alignment image of the wafer, an input device configured to transmit user commands to the computer system 202, etc. The display may be any type of computer output surface and projection mechanism for displaying text and graphic images, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a light emitting diode (LED), a gas plasma, a touch screen, or other image projection technologies for displaying information to a computer user. The input device may be any type of computer hardware device for providing data and control signals from an operator to the computer system 202. The input device may include but is not limited to a keyboard, a mouse, a scanner, a digital camera, a joystick, a trackball, cursor direction keys, a touch screen monitor, or an audio / video commander, etc., for transmitting direction information and command selections to the processor or for controlling the movement of the cursor on the display.

[0045] The reference storage device 210 stores a reference file database accessed by the computer system 202 during the alignment process. In some embodiments, the reference storage device 210 may be a part of the computer system 202. The reference image file for wafer inspection may be manually provided to the computer system 202 by an operator. Alternatively, the reference storage device 210 may be implemented with a processor, and the reference image file may be automatically provided to the computer system 202 by the reference storage device 110. The reference storage device 210 may be a remote server computer configured to store and provide any reference images, or may be cloud storage, etc.

[0046] The inspection system 212 may be any inspection system capable of generating wafer images. The wafer may be a semiconductor wafer substrate, a semiconductor wafer substrate having one or more epitaxial layers or processing films, etc. Embodiments of the present disclosure do not limit the specific type of the wafer inspection system 212, as long as the wafer inspection system can generate wafer images with a resolution high enough to observe critical features (e.g., less than 20 nm) on the wafer, consistent with contemporary semiconductor foundry technologies. In some embodiments of the present disclosure, the inspection system 212 is regardingFigure 3 The described electron beam inspection (EBI) system 304.

[0047] Once the wafer image is acquired by the inspection system 212, the wafer image can be transferred to the computer system 202, where the system can align the wafer image with a reference image (e.g., GDS). The computer system 202 and the reference storage device 210 can be part of the inspection system 212 or remote from the inspection system.

[0048] Now refer to Figure 3 , which is a schematic diagram showing an exemplary electron beam inspection system consistent with some embodiments of the present disclosure. As Figure 3 shown, the electron beam inspection system 300 includes a main chamber 302, a load / lock chamber 304, an electron beam tool 306, and an equipment front end module 308. The electron beam tool 306 is positioned within the main chamber 302. The equipment front end module 308 includes a first load port 308a and a second load port 308b. The equipment front end module 308 may include additional load port(s). The first load port 308a and the second load port 308b receive wafer cassettes that contain wafers (e.g., semiconductor wafers or wafers made of other materials) or samples to be inspected (wafers and samples are hereinafter collectively referred to as "wafers"). One or more robotic arms (not shown) in the equipment front end module 308 transfer the wafers to the load / lock chamber 304. The load / lock chamber 304 is connected to a load / lock vacuum pump system (not shown), which removes gas molecules in the load / lock chamber 304 to reach a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) transfer the wafers from the load / lock chamber 304 to the main chamber 302. The main chamber 302 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules in the main chamber 302 to reach a second pressure below the first pressure. After reaching the second pressure, the wafers are inspected by the electron beam tool 306.

[0049] Now refer to Figure 4 , which is a schematic diagram showing an exemplary electron beam tool consistent with some embodiments of the present disclosure, and the electron beam tool can be Figure 3 part of the exemplary electron beam inspection. Figure 4 Shows exemplary components of the electron beam tool 306 consistent with some embodiments of the present disclosure. As Figure 4As shown, the electron beam tool 306 includes a stage 400 and a wafer holder 402 supported by the stage 400 to hold a wafer 403 to be inspected. The electron beam tool 306 also includes an objective lens assembly 404, an electron detector 406 (which includes an electron sensor surface), an objective aperture 408, a condenser lens 410, a beam limiting aperture 412, a gun aperture 414, an anode 416, and a cathode 418. In some embodiments, the objective lens assembly 404 may include an improved swinging objective retardation immersion lens (SORIL), which includes a pole piece 404a, a control electrode 404b, a deflector 404c, and an excitation coil 404d. The electron beam tool 306 may additionally include an energy dispersive X-ray spectrometer (EDS) detector (not shown) to characterize materials on the wafer.

[0050] By applying a voltage between the anode 416 and the cathode 418, a primary electron beam 420 is emitted from the cathode 418. The primary electron beam 420 passes through the gun aperture 414 and the beam limiting aperture 412, both of which can determine the size of the electron beam entering the condenser lens 410 below the beam limiting aperture 412. Before the primary electron beam enters the objective aperture 408, the condenser lens 410 focuses the primary electron beam 420 to set the size of the electron beam before it enters the objective lens assembly 404. The deflector 404c deflects the primary electron beam 420 to facilitate electron beam scanning on the wafer. For example, during scanning, the deflector 404c can be controlled to sequentially deflect the primary electron beam 420 to different positioning points on the top surface of the wafer 403 at different time points to provide data for image reconstruction of different parts of the wafer 403. In addition, the deflector 404c can also be controlled to deflect the primary electron beam 420 to different sides of the wafer 403 at different time points at a specific positioning point to provide data for stereoscopic image reconstruction of the wafer structure at the positioning point. In addition, in some embodiments, the anode 416 and the cathode 418 can be configured to generate multiple primary electron beams 420, and the electron beam tool 306 can include multiple deflectors 404c to simultaneously project the multiple primary electron beams 420 onto different parts / sides of the wafer to provide data for image reconstruction of different parts of the wafer 203.

[0051] The excitation coil 404d and the pole piece 404a generate a magnetic field that starts at one end of the pole piece 404a and terminates at the other end of the pole piece 404a. A portion of the wafer 403 scanned by the primary electron beam 420 can be immersed in the magnetic field and can be charged, which in turn generates an electric field. Before the impact of the primary electron beam collides with the wafer, the electric field reduces the energy of the impact primary electron beam 420 near the wafer surface. The control electrode 404b, which is electrically isolated from the pole piece 404a, controls the electric field on the wafer to prevent micro-arching of the wafer and ensure proper beam focusing.

[0052] When receiving the primary electron beam 420, a secondary electron beam 422 can be emitted from the portion of the wafer 403. The secondary electron beam 422 can form a beam spot on the surface of the sensor of the electron detector 406. The electron detector 406 can generate a signal (e.g., voltage, current, etc.) representing the intensity of the beam spot and provide the signal to a processing system (not shown). The intensity of the secondary electron beam 422 and the resulting beam spot can vary according to the external or internal structure of the wafer 403. In addition, as described above, the primary electron beam 420 can be projected onto different positioning points on the top surface of the wafer to generate secondary electron beams 422 with different intensities (and the resulting beam spots). Therefore, by mapping the intensity of the beam spot to the positioning points of the wafer 403, the processing system can reconstruct an image reflecting the internal or external structure of the wafer 403. Once the electron beam tool 306 obtains the wafer image, the wafer image can be transmitted to the computer system 402 (as Figure 2 shown), where the computer system can align the wafer image with a reference image (e.g., GDS).

[0053] Now referring to Figure 5 , which is a flowchart indicating an exemplary alignment method consistent with some embodiments of the present disclosure. As Figure 5 shown, in step S501, the wafer to be inspected is loaded onto the wafer inspection system. The wafer inspection system can be an electron beam inspection (EBI) system, for example, the EBI system described with respect to Figure 3 .

[0054] In step S502, optical alignment (global alignment) of the wafer is performed. Since optical alignment is ineffective for detecting small defects (e.g., nanoscale defects) due to low resolution (usually dozens to hundreds of nanometers), in step S503, an EBI tool with higher resolution and larger depth of focus, such as a scanning electron microscope (SEM), is used. More specifically, in step S503, the wafer is imaged using the SEM. The wafer image can be loaded into a computer system (e.g., Figure 2 the computer system 202).

[0055] In step S504, the computer system can acquire a reference image to align with the wafer image. For example, the computer system can acquire the reference image via a storage device on the computer system or via a remote storage device.

[0056] In step S505, the locking positions and the patches surrounding the locking positions are identified to assist in the alignment of the wafer image and the reference image. The locking position refers to the alignment structure on the wafer image or the reference image, and the patch refers to the area surrounding the alignment structure. The computer system uses the locking positions and the patches to lock the determination of the position of the wafer image relative to the reference image. For example, the reference image may be superimposed on the wafer image, and the relative positions of the two images are adjusted until the structures of the reference image and the wafer image are locked in place.

[0057] To perform the locking of the images, for example, the alignment structure of the wafer image (e.g., a specific set of holes on a hole pattern) can be analyzed to determine how the structure interlocks with the alignment structure of the reference image (e.g., a specific set of squares on a square pattern) to provide precise alignment. The choice of the alignment structure can strongly affect whether precise alignment occurs. That is, the more unique the alignment structure, the more likely precise alignment will occur.

[0058] After the locking positions and the patches are selected, in step S506, the alignment of the wafer image with the reference image is performed, which is Figure 6 described in detail.

[0059] Now refer to Figure 6 , which is a flowchart indicating a detailed exemplary method for aligning a wafer image with a reference image consistent with some embodiments of the present disclosure. In Figure 6 , step S601 describes starting the alignment process of the current image of the wafer with the reference image. The current image can be an image captured by an electron beam tool such as an SEM. Step S602 describes searching for a target reference position for alignment on the wafer image. The target reference position can be a position that has been selected multiple times during a previous inspection process or a position that has been confirmed from previous inspection results. The target reference position can be based on one or more unique features (e.g., an aperiodic pattern in a logic region) such that the alignment position can be locked unambiguously. In the absence of such unique features, it is difficult to precisely fit a wafer image having only a periodic pattern to the reference image because each element in the pattern looks similar to all other elements. The target reference position can be identified based on the total number of times a position has been selected as a locking position in previous alignments, for example, by comparing the total number with a predetermined threshold number. The threshold number can be a number defined by the user. In some embodiments, the threshold number is 20.

[0060] Alternatively, the target reference position can be identified based on the inspection results of other wafers manufactured in the same process as the wafer, because wafers manufactured under the same conditions can have similar patterns or features. In response to determining the existence of the target reference position, in step S603, a patch surrounding the target reference position is defined. In this way, the area to be aligned on the wafer image is defined, and in step S604, the alignment of the patch with the reference image is performed using the target reference position. By selecting the target reference position instead of a random position as the locking position, the alignment accuracy is improved. In addition, by starting the alignment process using the target reference position that has been proven to be a reliable reference position in previous alignment processes without searching for and comparing locking positions, the inspection process is accelerated, resulting in higher throughput. On the other hand, in response to determining the non-existence of the target reference position in S602, the method performs operation A as shown in Figure 7 shown.

[0061] Now refer to Figure 7 , which is a flowchart indicating a detailed exemplary method of aligning an image of a wafer with a reference image consistent with some embodiments of the present disclosure. As described above, Figure 7 's method describes a scenario where the target reference position does not exist. For example, the target reference position does not exist on the wafer image because a single locking position has not been selected multiple times in previous inspections, or because the previous inspection results have not been applied to the current image due to a change in inspection conditions, etc. In this case, as shown in Figure 7 , in step S701, a current locking position on the image of the wafer and a patch surrounding the current locking position are defined, and an alignment score of the current locking position is calculated. The current locking position can be defined based on a comparison of the number of random features present in different ranges of the wafer. For example, if a range of the wafer image has more random features than any other range of the wafer image, the current locking position can be defined as a point (e.g., the center point) of this one range. Random features can include features having a unique shape or size that can be easily identified. The unique shape / size makes the possibility of misalignment lower because there may be fewer similar patterns that could be mistaken for the unique pattern. Alternatively, the current locking position can be defined based on a comparison of the number of pattern edges present in different ranges of the wafer. For example, if a range of the wafer image has more pattern edges than any other range of the image, the locking position can be defined as a point (e.g., the center point) of this one range. According to some embodiments, the patch surrounding the current locking position is the current field of view (FOV), such that the alignment of the current FOV is performed based on one locking position (i.e., the current locking position). According to some embodiments, the patch surrounding the current locking position is a part of the current FOV, such that the alignment of the current FOV is performed using multiple locking positions including the current locking position.

[0062] The alignment score of the current locked position can be determined based on the sum of the squared differences in intensity:

[0063] SSD = ∑ i (p i - q i ) 2 (Equation 1)

[0064] where p i and q i represent the pixel intensity values of the wafer image and the reference image, respectively.

[0065] Alternatively, the alignment score of the current locked position can be determined based on the correlation coefficient between the two images:

[0066]

[0067] where p i and q i represent the pixel intensity values of the wafer image and the reference image, respectively, and and represent the average intensity values of the wafer image and the reference image, respectively.

[0068] In Figure 7 , in step S702, the computer system compares the alignment score of the current locked position with the stored alignment scores of positions near the current locked position. The positions near the current locked position can be positions located within a patch surrounding the current locked position and that were previously selected for aligning the wafer image with the reference image. The alignment scores of the positions near the current locked position can be calculated using the formula used in calculating the alignment score of the current locked position.

[0069] In Figure 7 , in step S703, if it is determined that the alignment score of the current locked position satisfies a threshold condition (e.g., as shown, the alignment score of the current locked position is higher than the stored alignment scores of positions near the current locked position), then in step S704, the positioning information and alignment score of the current locked position are stored. For example, as Figure 2 shown, this information can be stored in the storage medium 206. The data within the storage medium can be consistently updated with the alignment score and the corresponding positioning information through an inspection process. The updated stored information can in turn be used at step S702 to select a better candidate locked position. By consistently updating the storage medium with the positioning information and alignment score of the current locked position and consistently checking for the existence of a better candidate locked position, the accuracy of locked position selection is adaptively improved, thereby improving the alignment accuracy.

[0070] After or during the storage in step S704, in step S705, the alignment of the patch surrounding the current locked position with the reference image is performed using the current locked position.

[0071] On the other hand, in response to determining in step S703 that the alignment score of the current locked position does not meet the threshold condition (e.g., as shown in the figure, the alignment score of the current locked position is lower than the stored alignment scores of the positions near the current locked position), the method performs operation B, as Figure 8 shown.

[0072] Now refer to Figure 8 , which is a flowchart indicating an exemplary local alignment method consistent with some embodiments of the present disclosure. As described above, Figure 8 the method in Figure 8 depicts a scenario where the alignment score of the current locked position does not meet the threshold condition (e.g., as shown in the figure, the alignment score of the current locked position is lower than the stored alignment scores of the positions near the current locked position). In this case, as

[0073] Now refer to Figure 9 , which is a schematic diagram showing a wafer image obtained by a scanning electron microscope (SEM) for inspection and the locked positions identified on the SEM image consistent with some embodiments of the present disclosure. As Figure 9 shown, the SEM image 900 of the wafer includes blue polygons representing a plurality of patterns on the wafer. The red crosses indicate the locked positions 902 on the image 900, and the red squares surrounding the red crosses indicate the patches 904 surrounding the locked positions 902 on the image 900.

[0074] In some embodiments of the present disclosure, in Figure 9 , the locked position 902 can be a target reference position, and the target reference position can be a previously determined positioning point surrounded by a region containing features that can be used to align the image of the wafer (e.g., an image obtained by SEM) and the reference image (e.g., an image defined in a GDS dataset, an image of a second wafer, etc.). In Figure 9In the example, the patch 904 is a previously determined area around the locking position 902, which is the target reference position of the example. The features of the wafer can be analyzed to find a set of features similar to those of the patch 904. The more unique the set of features of the patch area, the more likely the set of similar features found on the image of the wafer will be the "correctly" adapted set of features rather than a set of features that are similar but not "correctly" adapted and cause misalignment. When a set of features sufficiently similar to those of the patch 904 is identified on the image of the wafer, the image of the wafer can be aligned with the reference image based on the locking position 902. The target reference position can be identified based on the total number of times a position has been selected as the locking position in previous alignments. Alternatively, the target reference position can be identified based on the inspection results of another wafer manufactured in the same process as the wafer.

[0075] In some embodiments of the present disclosure, in Figure 9 , the locking position 902 can be the current locking position defined on the image 900 of the wafer for aligning the image with the reference image in response to determining that the target reference position does not exist. The patch 904 is the area surrounding the defined current locking position. In this case, the current locking position is used to perform the alignment of the patch 904 with the reference image. Specifically, an alignment score of the current locking position 902 is calculated and compared with the stored alignment scores of the positions near the current locking position 902. The positions near the current locking position can be the positions previously selected for aligning the image with the reference image. If it is determined that the alignment score of the current locking position 902 is higher than the stored alignment scores of the positions near the current locking position 902, the positioning information and the alignment score of the current locking position 902 are stored, and the current locking position 902 is used to perform the alignment of the patch 904 with the reference image. During the inspection, the positioning information and the alignment score of the current locking position are stored immediately, so that the storage pool is updated consistently. The consistently updated storage pool is in turn used to select better candidate locking positions. By consistently updating the storage pool with the positioning information and the alignment score of the current locking position during the inspection and consistently checking for the existence of better candidate locking positions, the accuracy of the selection of the locking position is adaptively improved, and thus the alignment accuracy is improved.

[0076] If the alignment score of the current locking position 902 is lower than the stored alignment scores of the positions near the current locking position 902, the highest alignment score among the stored alignment scores is selected, and the locking position corresponding to the highest alignment score is used to perform the alignment of the patch 904 with the reference image. In this way, the best alignment point(s) on the wafer image are identified, and the area surrounding the best alignment point is selected for alignment.

[0077] In some embodiments of the present disclosure, the size of the region surrounding the current lock position and the size of the region surrounding the target reference position are in the scale of millimeters to nanometers. The current lock position can be defined based on a comparison of the number of random features present on different ranges of the wafer or based on a comparison of the number of pattern edges present on different ranges of the wafer. The current lock position can be positioned at the center of the region surrounding the current lock position of the wafer. Similarly, the target reference position can be positioned at the center of the region surrounding the target reference position. The alignment score of the current lock position and the stored alignment score can be calculated using Equation 1 or Equation 2.

[0078] Now refer to Figure 10 and Figure 11 , which are schematic diagrams showing a comparison of the alignment score of the current lock position and the alignment score of positions near the current lock position consistent with some embodiments of the present disclosure. In Figure 10 and Figure 11 , the vertical axis indicates the alignment score of the current lock position and positions near the current lock position, and the horizontal axis indicates the spacing of positions near the current lock position from the current lock position. In Figure 10 , the alignment scores of positions near the current lock position (in this case, 20 different positions) are lower than the alignment score of the current lock position. Thus, the alignment of the region surrounding the current lock position with the reference image is performed using the current lock position.

[0079] On the other hand, in Figure 11 , the alignment scores of positions near the current lock position (in this case, 20 different positions) are higher than the alignment score of the current lock position. In this case, the position with the highest alignment score among the 20 different positions (denoted as 1102) is selected, and the alignment is performed using the position with the highest alignment score. In this way, for the alignment point, the position with the highest alignment score within the region is selected and thus the alignment accuracy is improved.

[0080] Now return to refer to Figure 2 , the computer system 202 can be a controller of the inspection system 212 (e.g., an electron beam inspection system), and the controller can include circuitry for: searching for the target reference position on the wafer image; and in response to determining that the target reference position does not exist: defining a current lock position and a region surrounding the current lock position on the image of the wafer; calculating the alignment score of the current lock position; comparing the alignment score of the current lock position with the stored alignment score of a previously selected position for aligning the image with the reference image; and aligning the wafer image with the reference image based on the comparison.

[0081] In an inspection system, aligning an image with a reference image based on a comparison may further include: in response to determining that an alignment score at a current locked position is higher than a stored alignment score at a previously selected position for aligning a wafer image with the reference image, storing positioning information and the alignment score at the current locked position, and using the current locked position to align a region surrounding the current locked position with the reference image.

[0082] In an inspection system, aligning an image with a reference image based on a comparison may further include: in response to determining that an alignment score at the current locked position is lower than the alignment score at a previously selected position for aligning the image with the reference image, selecting the highest alignment score from the stored alignment scores, and using the locked position corresponding to the highest alignment score to align a region surrounding the current locked position with the reference image.

[0083] In an inspection system, a controller having circuitry is further configured to: in response to determining the presence of the target reference position, define a region around the target reference position on the wafer, and use the target reference position to align the region around the target reference position with the reference.

[0084] Now return to reference Figure 2 , the storage medium 206 may be a non-transitory computer-readable medium storing an instruction set that may be executed by a controller of the device to cause the device to perform a method that includes: searching for a target reference position on an image of a wafer; and in response to determining the absence of the target reference position: defining a current locked position and a region surrounding the current locked position on the image of the wafer; calculating an alignment score at the current locked position; comparing the alignment score at the current locked position with a stored alignment score at a previously selected position for aligning the wafer image with the reference image; and aligning the image with the reference image based on the comparison.

[0085] In a non-transitory computer-readable medium, aligning the image with a reference image based on a comparison may further include: in response to determining that an alignment score at the current locked position is higher than a stored alignment score at a previously selected position for aligning the image with the reference image, storing positioning information and the alignment score at the current locked position, and using the current locked position to align a region surrounding the current locked position with the reference image.

[0086] In a non-transitory computer-readable medium, aligning the image with a reference image based on a comparison may further include: in response to determining that an alignment score at the current locked position is lower than the alignment score at a previously selected position for aligning the image with the reference image, selecting the highest alignment score from the stored alignment scores, and using the locked position corresponding to the highest alignment score to align a region surrounding the current locked position with the reference image.

[0087] In a non-transitory computer-readable medium, an instruction set executable by a controller of a device may cause the device to further perform: in response to determining the existence of the target reference position, defining an area around the target reference position on the wafer, and aligning the area around the target reference position with the reference image using the target reference position.

[0088] The embodiments may be further described using the following clauses:

[0089] 1. A method for aligning a wafer image with a reference image, comprising:

[0090] Searching a database for a target reference position for aligning the wafer image with the reference image; and

[0091] In response to determining that the target reference position does not exist in the database:

[0092] Identifying a current locked position and an area surrounding the current locked position on the wafer image;

[0093] Calculating an alignment score for the current locked position;

[0094] Comparing the alignment score of the current locked position with a stored alignment score of a previously selected position for aligning the wafer image with the reference image; and

[0095] Aligning the wafer image with the reference image based on the comparison.

[0096] 2. The method according to clause 1, wherein aligning the wafer image with the reference image based on the comparison further comprises:

[0097] In response to determining that the alignment score of the current locked position meets a threshold condition:

[0098] Storing the positioning information and alignment score of the current locked position on the database for facilitating determination of the target reference position; and

[0099] Aligning the area surrounding the current locked position with the reference image using the current locked position.

[0100] 3. The method according to clause 2, wherein the alignment score of the current locked position meets the threshold condition when the alignment score of the current locked position is higher than the stored alignment score of a position located within the area surrounding the current locked position, and the position located within the area surrounding the current locked position is a previously selected position for aligning the wafer image with the reference image.

[0101] 4. The method according to clause 1, wherein aligning the wafer image with the reference image based on the comparison further comprises:

[0102] In response to determining that the alignment score of the current locked position does not meet a threshold condition:

[0103] Select the highest alignment score among the stored alignment scores; and

[0104] Align the area surrounding the current locked position with the reference image using the locked position corresponding to the highest alignment score.

[0105] 5. The method according to clause 4, wherein the threshold condition is not met when the alignment score of the current locked position is lower than the stored alignment scores of positions located within the area surrounding the current locked position, and the positions located within the area surrounding the current locked position are positions previously selected for aligning the wafer image with the reference image.

[0106] 6. The method according to any one of clauses 4 to 5, wherein the locked position corresponding to the highest alignment score is a position within the field of view and different from the current locked position.

[0107] 7. The method according to any one of clauses 1 to 6, wherein the area surrounding the current locked position is the field of view.

[0108] 8. The method according to any one of clauses 1 to 6, wherein the area surrounding the current locked position is a part of the field of view.

[0109] 9. The method according to any one of clauses 1 to 8, wherein the alignment score of the current locked position and the stored alignment scores are determined based on the sum of the squared differences in intensity:

[0110]

[0111] where p i and q i represent the pixel intensity values of the wafer image and the reference image, respectively.

[0112] 10. The method according to any one of clauses 1 to 8, wherein the alignment score of the current locked position and the stored alignment scores are determined based on the correlation coefficient between the two images:

[0113]

[0114] where p i and i represent the pixel intensity values of the wafer image and the reference image, respectively, and and represent the average intensity values of the wafer image and the reference image, respectively.

[0115] 11. The method according to any one of clauses 1 to 10, wherein the size of the region surrounding the current locking position and the size of the region surrounding the target reference position are within the scale from millimeters to nanometers.

[0116] 12. The method according to any one of clauses 1 to 11, wherein the current locking position is defined based on a comparison of the number of features present on different ranges of the wafer.

[0117] 13. The method according to any one of clauses 1 to 11, wherein the current locking position is defined based on a comparison of the number of pattern edges present on different ranges of the wafer.

[0118] 14. The method according to any one of clauses 1 to 13, wherein the current locking position is substantially positioned at the center of the region surrounding the current locking position of the wafer.

[0119] 15. The method according to clause 2, wherein determining the target reference position further comprises: identifying the current locking position as the target reference position.

[0120] 16. The method according to clause 15, wherein the identification of the target reference position is based on a comparison between the total number of times the position has been selected as the locking position in previous alignments and a threshold number.

[0121] 17. The method according to clause 16, wherein the threshold number is 20.

[0122] 18. The method according to any one of clauses 1 to 17, wherein the reference image includes a Graphics Data System (GDS).

[0123] 19. The method according to any one of clauses 1 to 18, wherein the reference image is an image of a different wafer.

[0124] 20. An electron beam inspection apparatus, comprising:

[0125] A controller having circuitry to cause the electron beam inspection apparatus to perform the following:

[0126] Search for a target reference position in a database; and

[0127] In response to determining that the target reference position does not exist in the database:

[0128] Define a current locking position and a region surrounding the current locking position on the wafer image;

[0129] Calculate an alignment score for the current locking position;

[0130] Compare the alignment score of the current locked position with the stored alignment score of a previously selected position for aligning the wafer image with the reference image; and

[0131] Align the wafer image with the reference image based on the comparison.

[0132] 21. The electron beam inspection device according to clause 20, wherein aligning the wafer image with the reference image based on the comparison further includes:

[0133] In response to determining that the alignment score of the current locked position meets a threshold condition:

[0134] Store the positioning information and alignment score of the current locked position in a database to facilitate determination of a target reference position; and

[0135] Use the current locked position to align the area surrounding the current locked position with the reference image.

[0136] 22. The electron beam inspection device according to clause 20, wherein aligning the wafer image with the reference image based on the comparison further includes:

[0137] In response to determining that the alignment score of the current locked position does not meet the threshold condition:

[0138] Select the highest alignment score among the stored alignment scores; and

[0139] Use the locked position corresponding to the highest alignment score to align the area surrounding the current locked position with the reference image.

[0140] 23. A non-transitory computer-readable medium storing a set of instructions executable by a controller of a device to cause the device to perform a method, the method including:

[0141] Search for a target reference position in a database; and

[0142] In response to determining that the target reference position does not exist in the database:

[0143] Define a current locked position and an area surrounding the current locked position on the wafer image;

[0144] Calculate the alignment score of the current locked position;

[0145] Compare the alignment score of the current locked position with the stored alignment scores of previously selected positions for aligning the wafer image with the reference image; and

[0146] Align the wafer image with the reference image based on the comparison.

[0147] 24. The non-transitory computer-readable medium according to clause 23, wherein aligning the wafer image with the reference image based on the comparison further includes:

[0148] In response to determining that the alignment score of the current locked position meets a threshold condition:

[0149] Storing the positioning information and alignment score of the current locked position in a database to facilitate determination of a target reference position; and

[0150] Using the current locked position to align the area surrounding the current locked position with the reference image.

[0151] 25. The non-transitory computer-readable medium according to clause 23, wherein aligning the wafer image with the reference image based on the comparison further includes:

[0152] In response to determining that the alignment score of the current locked position does not meet the threshold condition:

[0153] Selecting the highest alignment score among the stored alignment scores; and

[0154] Using the locked position corresponding to the highest alignment score to align the area surrounding the current locked position with the reference image.

[0155] 26. The method according to clause 1,

[0156] wherein the previously selected positions for aligning the wafer image with the reference image include:

[0157] Positions located within the area surrounding the current locked position, which are the first part of the previously selected positions; or

[0158] Positions not located within the area surrounding the current locked position, which are the second part of the previously selected positions.

[0159] 27. The method according to clause 26,

[0160] wherein the previously selected positions for aligning the wafer image with the reference image include:

[0161] Positions located within the area surrounding the current locked position, which are the first part of the previously selected positions, or

[0162] Positions not located within the area surrounding the current locked position, which are the second part of the previously selected positions,

[0163] further includes:

[0164] A position located within the area surrounding the current locked position, which is the first part of a previously selected position; and

[0165] A position not located within the area surrounding the current locked position, which is the second part of a previously selected position.

[0166] 28. The method according to clause 27, wherein the first part is one or more positions among the previously selected positions, and wherein the second part is one or more positions among the previously selected positions.

[0167] 29. The method according to clause 26, wherein the first part is not any of the previously selected positions, and wherein the second part is all of the previously selected positions.

[0168] 30. The method according to clause 26, wherein the first part is all of the previously selected positions, and wherein the second part is not any of the previously selected positions.

[0169] The example embodiments have been described above with reference to the flowchart illustrations or block diagrams of methods, apparatuses (systems), and computer program products. It will be understood that each block of the flowchart illustrations or block diagrams, and combinations of blocks in the flowchart illustrations or block diagrams, can be implemented by computer program products or instructions on a computer program product. These computer program instructions can be provided to a processor of a computer or other programmable data processing device to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing device create a means for implementing the functions / actions specified in one or more blocks of the flowchart or block diagram.

[0170] These computer program instructions can also be stored in a computer-readable medium, which can direct a hardware processor core of a computer, other programmable data processing device, or other device to operate in a specific manner, such that the instructions stored in the computer-readable medium form a manufacture's product including instructions for implementing the functions / actions specified in one or more blocks of the flowchart or block diagram.

[0171] The computer program instructions can also be loaded onto a computer, other programmable data processing device, or other device, so as to perform a series of operational steps on the computer, other programmable device, or other device to produce a computer-implemented process, thereby providing a process for implementing the functions / actions specified in one or more blocks of the flowchart or block diagram by the instructions executed on the computer or other programmable device.

[0172] Any combination of one or more computer-readable media can be utilized. The computer-readable media can be non-transitory computer-readable storage media. The computer-readable storage media can be, by way of example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage media would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM, EEPROM, or Flash memory), an optical fiber, a cloud storage, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, the computer-readable storage media can be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0173] Any suitable medium can be used to transmit the program code contained on the computer-readable medium, including but not limited to wireless, wired, fiber optic cable, RF, IR, etc., or any suitable combination of the foregoing.

[0174] The computer program code for performing the operations of the exemplary embodiments can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network connection, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0175] The flowcharts and block diagrams in the accompanying drawings illustrate examples of the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code that includes one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, depending on the functionality involved, actually be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order. It will also be noted that each block of the block diagrams or flowchart illustrations, and combinations of blocks in the block diagrams or flowchart illustrations, can be implemented by a system based on dedicated hardware that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0176] It should be understood that the described embodiments are not mutually exclusive, and elements, components, materials, or steps described in connection with one example embodiment may be combined with other embodiments in a suitable manner or eliminated from other embodiments to achieve the desired design objectives.

[0177] References herein to "some embodiments" or "some exemplary embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment. The phrases "an embodiment," "some embodiments," or "some exemplary embodiments" that appear in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily separate or alternative embodiments that are mutually exclusive of other embodiments.

[0178] It should be understood that the steps of the example methods set forth herein need not necessarily be performed in the order described, and the order of such method steps should be understood to be merely exemplary. Similarly, in methods consistent with various embodiments, additional steps may be included in such methods, and certain steps may be omitted or combined.

[0179] As used in this application, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Instead, the use of the word is intended to present concepts in a concrete manner.

[0180] In addition, unless otherwise specified or clearly referred to in the context as being in the singular form, the articles "a" and "an" used in this application and the appended claims should generally be construed to mean "one or more."

[0181] Unless otherwise expressly stated, each numerical value and range should be interpreted as approximate, as if the word "about" or "approximately" preceded the value or values of the range.

[0182] The use of reference signs or reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use should not be construed as limiting the scope of those claims to the embodiments shown in the corresponding drawings.

[0183] Although the elements (if any) in the following method claims are recited in a specific order with corresponding labels, these elements are not necessarily intended to be implemented in that specific order unless the claim recitation otherwise implies a specific order for implementing some or all of these elements.

[0184] It should also be understood that various changes may be made by those skilled in the art to the details, materials, and arrangements of the components described and shown for purposes of explaining the nature of the described embodiments without departing from the scope expressed in the appended claims.

Claims

1. A method for aligning a wafer image with a reference image, wherein the wafer image includes a first alignment structure and the reference image includes a second alignment structure that can interlock with the first alignment structure, the method comprising: Searching a database for a target reference position for aligning the wafer image with the reference image; And In response to determining that the target reference position does not exist in the database: Identifying a current locked position on the wafer image that serves as the first alignment structure and an area surrounding the current locked position; Calculating an alignment score for the current locked position; Comparing the alignment score of the current locked position with a stored alignment score of a previously selected position for aligning the wafer image with the reference image; And Aligning the wafer image with the reference image based on the comparison.

2. The method according to claim 1, wherein aligning the wafer image with the reference image based on the comparison further comprises: In response to determining that the alignment score of the current locked position meets a threshold condition: Storing the positioning information and the alignment score of the current locked position on the database to facilitate determination of the target reference position; And Using the current locked position to align the area surrounding the current locked position with the reference image.

3. The method according to claim 2, wherein the alignment score of the current locked position meets the threshold condition when the alignment score of the current locked position is higher than the stored alignment scores of positions located within the area surrounding the current locked position, and the positions located within the area surrounding the current locked position are previously selected positions for aligning the wafer image with the reference image.

4. The method according to claim 1, wherein aligning the wafer image with the reference image based on the comparison further comprises: In response to determining that the alignment score of the current locked position does not meet the threshold condition: Selecting the highest alignment score from the stored alignment scores; And Using the locked position corresponding to the highest alignment score to align the area surrounding the current locked position with the reference image.

5. The method according to claim 4, wherein the threshold condition is not met when the alignment score of the current locked position is lower than the stored alignment scores of positions located within the area surrounding the current locked position, and the positions located within the area surrounding the current locked position are previously selected positions for aligning the wafer image with the reference image.

6. The method according to claim 4, wherein the locked position corresponding to the highest alignment score is a positioning point within the field of view and different from the current locked position.

7. The method according to claim 1, wherein the area surrounding the current locked position is the field of view.

8. The method according to claim 1, wherein the area surrounding the current locked position is a part of the field of view.

9. The method according to claim 1, wherein the alignment score of the current locked position and the stored alignment score are determined based on the sum of the squared differences in intensity: where p i and q i represent the pixel intensity values of the wafer image and the reference image, respectively.

10. The method according to claim 1, wherein the alignment score of the current locked position and the stored alignment score are determined based on the correlation coefficient between two images: where p i and q i represent the pixel intensity values of the wafer image and the reference image, respectively, and and represent the average intensity values of the wafer image and the reference image, respectively.

11. The method according to claim 1, wherein the size of the region surrounding the current locked position and the size of the region surrounding the target reference position are in the range from millimeters to nanometers.

12. The method according to claim 1, wherein the current locked position is defined based on a comparison of the number of features present on different ranges of the wafer.

13. The method according to claim 1, wherein, The current locked position is defined based on a comparison of the number of pattern edges present on different ranges of the wafer.

14. An electron beam inspection apparatus, comprising: a controller having circuitry to cause the electron beam inspection apparatus to perform the following on a wafer image including a first alignment structure and a reference image including a second alignment structure that can interlock with the first alignment structure: search for a target reference position in a database; and in response to determining that the target reference position does not exist in the database: define a current locked position on the wafer image that serves as the first alignment structure and a region surrounding the current locked position; calculate an alignment score for the current locked position; compare the alignment score of the current locked position with a stored alignment score of a previously selected position for aligning the wafer image with the reference image; and align the wafer image with the reference image based on the comparison.

15. A non-transitory computer-readable medium storing a set of instructions executable by a controller of a device to cause the device to perform a method for aligning a wafer image with a reference image, wherein the wafer image includes a first alignment structure and the reference image includes a second alignment structure that can interlock with the first alignment structure, the method comprising: search for a target reference position in a database; and in response to determining that the target reference position does not exist in the database: define a current locked position on the wafer image that serves as the first alignment structure and a region surrounding the current locked position; calculate an alignment score for the current locked position; compare the alignment score of the current locked position with a stored alignment score of a previously selected position for aligning the wafer image with the reference image; and align the wafer image with the reference image based on the comparison.

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