Display devices and electronic equipment

Abstract

A display device is provided that includes a low-power driver and whose output voltage is boosted by a pixel. The display device includes a source driver whose logic section and amplifier section operate appropriately at the same low voltage. The pixel has the function of holding first data and adding the first data and second data to generate third data, which is then supplied to the display device. Therefore, since the voltage output from the source driver can be boosted by the pixel even when it is low, the display device can be appropriately operated.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, method or manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, more specifically, as an example of the technical field of one embodiment of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, a camera device, a method for operating these devices or a method for manufacturing these devices can be cited.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. In addition, a storage device, a display device, a camera device, and an electronic device may include a semiconductor device. Background Art

[0004] Technology for forming transistors using metal oxides formed on a substrate has attracted attention. For example, Patent Documents 1 and 2 disclose a technology for using transistors using zinc oxide or In-Ga-Zn-based oxides as switching elements of pixels of display devices.

[0005] In addition, Patent Document 3 discloses a memory device having a structure in which a transistor with extremely low off-state current is used for a memory cell.

[0006] [Prior technical literature]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2007-123861

[0009] [Patent Document 2] Japanese Patent Application Publication No. 2007-96055

[0010] [Patent Document 3] Japanese Patent Application Publication No. 2011-119674 Summary of the invention

[0011] Technical problem to be solved by the invention

[0012] The driver that supplies data to the pixels of the display device includes a logic unit and an amplifier unit, and is designed so that the logic unit and the amplifier unit work properly. Generally, the logic unit is designed to be high-speed and have suppressed power consumption, and the amplifier unit is designed to have a high withstand voltage and output a high voltage. Therefore, it is necessary to configure transistors with different structures in one chip, and there are many manufacturing processes, which is one of the reasons for the increase in cost.

[0013] The power supply voltages of the logic unit and the amplifier unit are different, and a circuit that outputs two or more voltages is required. If the voltage output can be made uniform, the power supply circuit can be simplified, thereby achieving low cost. In addition, if the power supply voltage of the amplifier unit can be reduced, the overall power consumption of the driver can be reduced.

[0014] In the pixel circuit, when the display device can be properly operated with a data voltage having a small amplitude, power consumption can be reduced.

[0015] Therefore, one of the purposes of one embodiment of the present invention is to provide a display device having a low-power driver. In addition, one of the purposes of one embodiment of the present invention is to provide a display device having a low-power driver and the output voltage of the driver is increased by a pixel. In addition, one of the purposes of one embodiment of the present invention is to provide a display device capable of supplying a voltage higher than the output voltage of a source driver to a display device. In addition, one of the purposes of one embodiment of the present invention is to provide a display device capable of increasing the brightness of a displayed image.

[0016] In addition, one of the purposes of one embodiment of the present invention is to provide a low-power display device. In addition, one of the purposes of one embodiment of the present invention is to provide a display device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a novel display device, etc. In addition, one of the purposes of one embodiment of the present invention is to provide a driving method for the above-mentioned display device. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, etc.

[0017] Note that the recording of these purposes does not prevent the existence of other purposes. In addition, one mode of the present invention does not need to achieve all of the above purposes. In addition, purposes other than the above can be known and extracted from the description of the specification, drawings, claims, etc.

[0018] Solutions to technical problems

[0019] One embodiment of the present invention relates to a display device including a low power consumption driver.

[0020] One embodiment of the present invention is a display device comprising: a driver circuit; and a pixel circuit, wherein the driver circuit includes a shift register circuit and an amplifier circuit, the pixel circuit has a function of adding first data and second data output from the amplifier circuit to generate third data, and the shift register circuit and the amplifier circuit are supplied with the same power supply voltage.

[0021] The shift register circuit and the amplifier circuit may be electrically connected to the same power supply circuit.

[0022] The power supply voltage supplied to the driver circuit may be 3.3V or less.

[0023] The driver circuit may also include one or more circuits selected from an input interface circuit, a serial-parallel conversion circuit, a latch circuit, a level conversion circuit, PTL (pass transistor logic), a digital-to-analog conversion circuit and a bias generation circuit, and the circuit may be supplied with the same power supply voltage as the shift register circuit and the amplifier circuit.

[0024] Another embodiment of the present invention is a display device, comprising: a driver circuit; and a pixel circuit, wherein the driver circuit includes a shift register circuit and an amplifier circuit, the pixel circuit has a function of adding first data and second data output from the amplifier circuit to generate third data, the shift register circuit includes a first transistor, the amplifier circuit includes a second transistor, and when one of the first transistor and the second transistor includes a region where the thickness of the gate insulating film is a, the other transistor includes a region where the thickness of the gate insulating film is greater than 0.9a and less than 1.1a.

[0025] The driver circuit may also include one or more circuits selected from an input interface circuit, a serial-parallel conversion circuit, a latch circuit, a level conversion circuit, a PTL, a digital-to-analog conversion circuit, and a bias generation circuit, and the transistor included in the circuit may include a region where the thickness of the gate insulating film is greater than 0.9a and less than 1.1a.

[0026] The pixel circuit may include a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a light-emitting device, one of the source and the drain of the third transistor may be electrically connected to one electrode of the first capacitor, the other electrode of the first capacitor may be electrically connected to one of the source and the drain of the fourth transistor, one of the source and the drain of the fourth transistor may be electrically connected to one of the source and the drain of the fifth transistor, one electrode of the first capacitor may be electrically connected to the gate of the sixth transistor, one of the source and the drain of the sixth transistor may be electrically connected to one of the source and the drain of the seventh transistor, one of the source and the drain of the seventh transistor may be electrically connected to one electrode of the light-emitting device, one electrode of the light-emitting device may be electrically connected to one electrode of the second capacitor, and the other electrode of the second capacitor may be electrically connected to the gate of the seventh transistor.

[0027] The pixel circuit may include a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a second capacitor, and a liquid crystal device, one of the source and the drain of the third transistor may be electrically connected to an electrode of the first capacitor, the other electrode of the first capacitor may be electrically connected to one of the source and the drain of the fourth transistor, one of the source and the drain of the fourth transistor may be electrically connected to one of the source and the drain of the fifth transistor, one electrode of the first capacitor may be electrically connected to one electrode of the second capacitor, and one electrode of the second capacitor may be electrically connected to one electrode of the liquid crystal device.

[0028] The other of the source and the drain of the third transistor may also be electrically connected to the other of the source and the drain of the fourth transistor.

[0029] The transistor included in the pixel circuit preferably contains a metal oxide in a channel formation region, and the metal oxide preferably contains In, Zn, M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

[0030] Effects of the Invention

[0031] By using one embodiment of the present invention, a display device having a low-power driver can be provided. In addition, a display device having a low-power driver and in which the output voltage of the driver is increased by a pixel can be provided. In addition, a display device capable of supplying a voltage higher than the output voltage of the source driver to a display device can be provided. In addition, a display device capable of increasing the brightness of a displayed image can be provided.

[0032] In addition, a low-power display device can be provided. In addition, a highly reliable display device can be provided. In addition, a novel display device can be provided. In addition, an operating method of the above display device can be provided. In addition, a novel semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a diagram for explaining a display device.

[0034] Figure 2 A diagram illustrating a pixel circuit.

[0035] FIG. 3A to FIG. 3C A diagram illustrating a pixel circuit.

[0036] Figure 4 A diagram illustrating a pixel circuit.

[0037] Figure 5 is a timing diagram illustrating the operation of the pixel circuit.

[0038] FIG. 6A to FIG. 6C A diagram illustrating a pixel circuit.

[0039] Figure 7 A diagram illustrating a pixel circuit.

[0040] Figure 8 A diagram illustrating a pixel circuit.

[0041] Fig. 9 A diagram illustrating a pixel circuit.

[0042] FIG. 10A to FIG. 10C This is a diagram illustrating pixel layout.

[0043] Fig.11A This is a diagram for explaining a source driver. Fig. 11B , Fig. 11C is a diagram illustrating a transistor.

[0044] Fig. 12A This is a diagram for explaining a source driver. Fig. 12B , Fig. 12C is a diagram illustrating a transistor.

[0045] FIG. 13A to FIG. 13C It is a diagram for explaining a display device.

[0046] Fig.14A , Fig. 14B It is a diagram for explaining a touch screen.

[0047] Fig.15A , Fig. 15B It is a diagram for explaining a display device.

[0048] Fig.16It is a diagram for explaining a display device.

[0049] Fig.17A , Fig. 17B It is a diagram for explaining a display device.

[0050] Fig.18A , Fig.18B It is a diagram for explaining a display device.

[0051] FIG. 19A to FIG. 19E It is a diagram for explaining a display device.

[0052] FIG. 20A1 to FIG. 20C2 is a diagram illustrating a transistor.

[0053] FIG. 21A1 to FIG. 21C2 is a diagram illustrating a transistor.

[0054] FIG. 22A1 to FIG. 22C2 is a diagram illustrating a transistor.

[0055] FIG. 23A1 to FIG. 23C2 is a diagram illustrating a transistor.

[0056] FIG. 24A to FIG. 24F It is a diagram for explaining an electronic device.

[0057] Fig.25A , Fig.25B It is the I D -V G Characteristics diagram.

[0058] Fig.26A A diagram illustrating an EL pixel circuit. Fig.26B It is a timing diagram.

[0059] Fig.27A , Fig.27B This is a diagram illustrating a liquid crystal pixel circuit.

[0060] Fig.28 is a block diagram of a source driver.

[0061] Fig.29A , Fig.29B FIG. 5 is a diagram illustrating simulation results of power consumption of a source driver.

[0062] Fig.30 This is a diagram illustrating the actual measurement results of the power consumption of the panel.

[0063] Fig.31A It is a diagram illustrating the transmittance of a liquid crystal device. Fig.31B It is a diagram for explaining the brightness of a liquid crystal display panel.

[0064] Fig.32A This is a photo of an image displayed by an EL display panel. Fig.32B This is a photo of an image displayed on a liquid crystal display panel. DETAILED DESCRIPTION

[0065] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person of ordinary skill in the art can easily understand the fact that its methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that in the structure of the invention described below, the same figure marks are used in different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. Note that the shading of the same constituent elements is sometimes appropriately omitted or changed in different drawings.

[0066] In addition, even if it is a single element in the circuit diagram, the element may be composed of multiple elements if there is no problem in function. For example, multiple transistors used as switches may be connected in series or in parallel. In addition, capacitors (also called capacitance elements) may be divided and arranged in multiple locations.

[0067] In addition, sometimes a conductor has multiple functions such as wiring, electrode and terminal, and in this specification, multiple names are sometimes used for the same element. In addition, even if the circuit diagram shows that the elements are directly connected, sometimes the elements are actually connected through multiple conductors, and this structure is also included in the category of direct connection in this specification.

[0068] (Implementation Method 1)

[0069] In this embodiment, a display device which is one embodiment of the present invention is described with reference to the drawings.

[0070] One embodiment of the present invention is a display device including a low-power source driver and a pixel having a function of adding data. The source driver has a structure in which a logic unit and an amplifier unit operate appropriately at the same power supply voltage. Since the power supply voltage of the logic unit operating at low power consumption is used as a reference, the voltage that can be output by the amplifier unit becomes smaller, but the power consumption of the source driver as a whole can be suppressed.

[0071] The pixel has a function of holding the first data and a function of adding the first data and the second data to generate the third data and supplying the third data to the display device. Therefore, since the pixel can boost the voltage even if the voltage output from the source driver is low, the display device can be properly operated.

[0072] That is, by combining a source driver with a low power supply voltage and a pixel capable of voltage boosting operation, a display device with extremely low power consumption can be realized.

[0073] Figure 1 1 is a diagram for explaining a display device according to one embodiment of the present invention. The display device includes a pixel array 11, a source driver 20, and a gate driver 30. The pixel array 11 includes pixels 10 arranged in the column direction and the row direction. Note that wiring is shown simply and will be described in detail later.

[0074] The source driver 20 may include a logic unit 21 and an amplifier unit 22. The logic unit 21 and the amplifier unit 22 are electrically connected to a power supply circuit 25. The power supply circuit 25 is not limited to one, but the voltages supplied to the logic unit 21 and the amplifier unit 22 may be equal.

[0075] Note that the source driver 20 and the gate driver 30 may be formed by placing an IC chip externally by a COF (chip on film) method, a COG (chip on glass) method, a TCP (tape carrier package) method, etc. Alternatively, the source driver 20 and the gate driver 30 may be formed on the same substrate as the pixel array 11 using transistors manufactured in the same process as the pixel array 11.

[0076] Figure 1 Although an example in which the gate driver 30 is disposed on one side of the pixel array 11 is shown, two gate drivers 30 may be provided to face each other across the pixel array 11 to divide the drive rows.

[0077] Figure 2 A circuit diagram of a pixel including a light emitting device is shown as a specific example of the pixel 10. The pixel 10 includes a transistor 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a capacitor 106, a capacitor 107, and a light emitting device 108.

[0078] One of the source and the drain of the transistor 101 is electrically connected to one of the electrodes of the capacitor 106. The other electrode of the capacitor 106 is electrically connected to one of the source and the drain of the transistor 102. One of the source and the drain of the transistor 102 is electrically connected to one of the source and the drain of the transistor 103. One of the electrodes of the capacitor 106 is electrically connected to the gate of the transistor 104. One of the source and the drain of the transistor 104 is electrically connected to one of the source and the drain of the transistor 105. One of the source and the drain of the transistor 105 is electrically connected to one of the electrodes of the light emitting device 108. One of the electrodes of the light emitting device 108 is electrically connected to one of the electrodes of the capacitor 107. The other electrode of the capacitor 107 is electrically connected to the gate of the transistor 104.

[0079] Connections between components included in the pixel 10 and various wirings are described. The gate of the transistor 101 is electrically connected to the wiring 125. The gate of the transistor 102 is electrically connected to the wiring 126. The gate of the transistor 103 is electrically connected to the wiring 125. The gate of the transistor 105 is electrically connected to the wiring 127.

[0080] The other of the source and the drain of the transistor 101 is electrically connected to the wiring 121. The other of the source and the drain of the transistor 102 is electrically connected to the wiring 122. The other of the source and the drain of the transistor 103 is electrically connected to the wiring 124. The other of the source and the drain of the transistor 104 is electrically connected to the wiring 123. The other of the source and the drain of the transistor 105 is electrically connected to the wiring 124. The other electrode of the light-emitting device 108 is electrically connected to the wiring 129.

[0081] The wirings 125, 126, and 127 are used as gate lines and can be electrically connected to the gate driver 30 (see Figure 1 ). The wirings 121 and 122 are used as source lines and can be electrically connected to the source driver 20 .

[0082] The wirings 123 and 129 can be used as power supply lines. For example, by supplying a high potential to the wiring 123 and a low potential to the wiring 129, the light emitting device 108 can be operated in a forward bias (emit light).

[0083] The wiring 124 may have a reference potential (V ref ) function. For example, it can be used as a “V ref ” Use 0V, GND potential, etc. Alternatively, you can set a specific potential to “V ref ”.

[0084] Here, a wiring connecting one of the source and drain of the transistor 101, one electrode of the capacitor 106, the other electrode of the capacitor 107, and the gate of the transistor 104 is denoted as a node NM. A wiring connecting one of the source and drain of the transistor 102, the other electrode of the capacitor 106, and one of the source and drain of the transistor 103 is denoted as a node NA.

[0085] The transistor 101 may have a function of writing a potential of the wiring 121 to the node NM. The transistor 102 may have a function of writing a potential of the wiring 122 to the node NA. The transistor 103 may have a function of supplying a reference potential (V ref The transistor 104 may have a function of controlling the current flowing through the light emitting device 108 according to the potential of the node NM. The transistor 105 may have a function of fixing the source potential of the transistor 104 when writing data to the node NM and a function of controlling the operation timing of the light emitting device 108.

[0086] The node NM is connected to the node NA via the capacitor 106. Therefore, when the node NM is in a floating state, the potential change of the node NA can be added by capacitive coupling. The potential of the node NM is described below.

[0087] In the pixel 10, first, the first data (weight: "W") is written to the node NM. At this time, the reference potential "V ref ”, and “WV” is maintained in capacitor 106. ref ". Next, the node NA is placed in a floating state, and the second data (data: "D") is supplied to the node NA.

[0088] At this time, the capacitance value of capacitor 106 is C 106 And the capacitance value of node NM is C NM When the potential of node NM is W+(C 106 / (C 106 +C NM ))×(DV ref ). Here, when using C 106 The value of C becomes larger and does not consider NM When the value of C 106 / (C 106 +C NM ) is close to 1, so the potential of node NM can be regarded as “W+DV ref ”.

[0089] Therefore, when "W" = "D", "V ref ”=0V,C 106 Large enough to be C NM When , the potential of the node NM is close to “2D”. That is, the third data (“2D”) having a potential approximately twice that of the output of the source driver 20 can be generated by the node NM.

[0090] Note that in "V ref ” is “-W” or “-D”, the potential of the node NM can also be made close to “3D”.

[0091] This function allows the source driver 20 to generate a voltage required by the pixel 10 even if the output voltage is small, so that the light-emitting device 108 can be operated appropriately.

[0092] Node NM and node NA are used as holding nodes. By turning on the transistor connected to each node, data can be written to each node. In addition, by making the transistor non-conductive, the data can be kept in each node. By using a transistor with extremely low off-state current as the transistor, leakage current can be suppressed, thereby maintaining the potential of each node for a long time. For example, the transistor preferably uses a transistor containing a metal oxide in the channel formation region (hereinafter, OS transistor).

[0093] Specifically, as any or all of the transistors 101, 102, and 103, an OS transistor is preferably used. In addition, an OS transistor can be used for all transistors included in the pixel 10. In addition, when the operation is performed within the allowable range of the leakage current, a transistor containing Si in the channel formation region (hereinafter referred to as a Si transistor) can be used. In addition, an OS transistor and a Si transistor can be used in combination. As the above-mentioned Si transistor, a transistor containing amorphous silicon, a transistor containing crystalline silicon (microcrystalline silicon, low-temperature polycrystalline silicon, single crystal silicon), etc. can be cited.

[0094] As a semiconductor material for OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, there are oxide semiconductors containing indium, for example, CAAC-OS or CAC-OS mentioned later can be used. CAAC-OS has stable atoms constituting the crystals, and is suitable for transistors that emphasize reliability. CAC-OS exhibits high mobility characteristics and is suitable for transistors that are driven at high speeds.

[0095] Since the semiconductor layer of the OS transistor has a large energy gap, it can exhibit extremely low off-state current characteristics, which are only a few yA / μm (current value per channel width 1μm). Unlike Si transistors, OS transistors have characteristics such as no impact ionization, avalanche breakdown, and short channel effects, so they can form highly reliable circuits. In addition, the electrical characteristic deviation caused by the uneven crystallinity of Si transistors is not easy to occur in OS transistors.

[0096] As a semiconductor layer in the OS transistor, for example, a film represented by "In-M-Zn oxide" containing indium, zinc and M (M is a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium) can be used. Typically, the In-M-Zn oxide can be formed by sputtering. Alternatively, it can also be formed by ALD (Atomic layer deposition) method.

[0097] When forming an In-M-Zn oxide by sputtering, the atomic ratio of the metal element of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. The atomic ratio of the metal element of such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. Note that the atomic ratio of the semiconductor layer to be formed may vary within the range of ±40% of the atomic ratio of the metal element in the above-mentioned sputtering target.

[0098] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, an oxide semiconductor with a carrier density of 1×10 17 / cm 3 Below, preferably 1×10 15 / cm 3 Below, more preferably 1×10 13 / cm 3 Below, more preferably 1×10 11 / cm 3 Below, more preferably less than 1×10 10 / cm 3 and 1×10 -9 / cm 3 The above oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. Since the defect state density of the oxide semiconductor is low, it can be said that the oxide semiconductor has stable characteristics.

[0099] Note that the present invention is not limited to the above description, and an oxide semiconductor having an appropriate composition can be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the desired transistor. In addition, it is preferred to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0100] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the elements of Group 14, oxygen vacancies increase, which makes the semiconductor layer n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×1017 atoms / cm 3 the following.

[0101] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers are generated, which increases the off-state current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration measured by SIMS) is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0102] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, and the carrier density increases, which makes it easy to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (the concentration measured by SIMS) is preferably 5×10 18 atoms / cm 3 the following.

[0103] In addition, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, hydrogen reacts with oxygen bonded to metal atoms to generate water, and thus oxygen vacancies are sometimes formed in the oxide semiconductor. In the case where the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Furthermore, sometimes hydrogen enters the defects in the oxygen vacancies and is used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated due to the bonding of a portion of the hydrogen to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing more hydrogen tend to have normally-on characteristics.

[0104] Defects in which hydrogen enters oxygen vacancies are used as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate the defects. Therefore, in oxide semiconductors, defects are sometimes evaluated based on carrier concentration rather than donor concentration. Therefore, in this specification, etc., sometimes as parameters of oxide semiconductors, instead of donor concentration, carrier concentration assumed to be in a state where no electric field is applied is used. That is, the "carrier concentration" described in this specification, etc. may sometimes be referred to as "donor concentration".

[0105] Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 By using an oxide semiconductor in which impurities such as hydrogen have been sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

[0106] In addition, the semiconductor layer may also have a non-single-crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) with a c-axis orientation, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest defect state density, while the CAAC-OS has the lowest defect state density.

[0107] The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystalline component. Alternatively, the oxide semiconductor film with an amorphous structure has, for example, a completely amorphous structure and no crystalline part.

[0108] In addition, the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a stacked layer structure including two or more of the above regions.

[0109] Hereinafter, the structure of CAC (Cloud-Aligned Composite)-OS which is one embodiment of the non-single-crystal semiconductor layer will be described.

[0110] CAC-OS refers to, for example, a configuration in which elements contained in an oxide semiconductor are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, is also referred to as a mosaic or patch shape.

[0111] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0112] For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, In-Ga-Zn oxide can be referred to as CAC-IGZO in particular) refers to a material divided into indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4 and Z4 are real numbers greater than 0)) etc. to form a mosaic shape, and the mosaic-shaped InO X1 or In X2 Zn Y2 O Z2 A structure uniformly distributed in the film (hereinafter also referred to as a cloud shape).

[0113] In other words, CAC-OS is a GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0114] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is an arbitrary number).

[0115] The crystalline compound has a single crystal structure, a polycrystalline structure or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0116] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to a composition in which nanoparticle-like regions with Ga as the main component are observed in a part of the material composition containing In, Ga, Zn, and O, and nanoparticle-like regions with In as the main component are observed in a part of the material composition, and are irregularly dispersed in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0117] CAC-OS does not include a stacked-layer structure of two or more films having different compositions, for example, a structure consisting of two layers of a film having In as a main component and a film having Ga as a main component.

[0118] Note that sometimes no GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 There are clear boundaries between the regions of the main components.

[0119] In the case where CAC-OS includes one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium instead of gallium, CAC-OS refers to a structure in which nanoparticle-like regions with the metal element as the main component are observed in a part and nanoparticle-like regions with In as the main component are observed in a part and are irregularly dispersed in a mosaic manner.

[0120] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When CAC-OS is formed by sputtering, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used as a film-forming gas. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the film-forming gas during film formation, the better. For example, the flow rate ratio of the oxygen gas is set to be greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0121] CAC-OS has the following characteristics: when measured by the Out-of-plane method using θ / 2θ scanning, which is one of the X-ray diffraction (XRD) measurement methods, no clear peak is observed. In other words, according to the X-ray diffraction measurement, it is known that there is no orientation in the ab plane direction and the c-axis direction in the measurement area.

[0122] In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called a nanobeam), a ring-shaped area with high brightness (ring-shaped area) and multiple bright spots in the ring-shaped area were observed. Therefore, according to the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is not oriented in the plane direction and the cross-sectional direction.

[0123] In addition, for example, in CAC-OS of In-Ga-Zn oxide, it can be confirmed from an EDX mapping image obtained by energy dispersive X-ray spectroscopy (EDX) that there is a GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 A composition in which the main components are unevenly distributed in the area.

[0124] The structure of CAC-OS is different from that of IGZO compounds in which metal elements are evenly distributed, and it has different properties from IGZO compounds. X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 The regions where the main components are present are separated from each other, and the regions where the main components are present are in a mosaic-like structure.

[0125] Here, In X2 Zn Y2 O Z2 or InO X1 The conductivity of the area with GaO as the main component is higher than that of the area with GaO as the main component. X3 In other words, when the carrier flows through the region with In X2 Zn Y2 O Z2 or InO X1 When In is the main component of the region, it exhibits the conductivity of an oxide semiconductor. X2 Zn Y2 O Z2 or InO X1 When the region as the main component is distributed in a cloud-like manner in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0126] On the other hand, GaO X3 The insulation of the area with In as the main component is higher than that of the area with In X2Zn Y2 O Z2 or InO X1 In other words, when GaO X3 When regions with the main components of MgO and the like are distributed in an oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0127] Therefore, when CAC-OS is used in semiconductor devices, the X3 The insulation properties of etc. and the causes of In X2 Zn Y2 O Z2 or InO X1 The complementary effect of conductivity can achieve high on-state current (I on ) and high field effect mobility (μ).

[0128] In addition, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is suitable for use as a constituent material of various semiconductor devices.

[0129] Notice, Figure 2 The circuit structure of the pixel 10 shown is an example. Figure 3A As shown, one electrode of the light-emitting device 108 may also be electrically connected to the wiring 123 , and the other electrode of the light-emitting device 108 may also be electrically connected to one of the source and the drain of the transistor 104 .

[0130] Or, if Figure 3B As shown, a transistor 109 may be provided between one of the source and drain of the transistor 104 and one electrode of the light emitting device 108. By providing the transistor 109, the light emitting timing may be arbitrarily controlled. Figure 3A , Figure 3B The structure shown.

[0131] In addition, if Figure 3C As shown, the wiring 124 connected to the transistor 105 can be electrically connected to the circuit 40. The circuit 40 can have a reference potential (V ref )'s supply source, a function of obtaining the electrical characteristics of the transistor 104, and a function of generating correction data.

[0132] like Figure 4 As shown, a structure may be adopted in which two pixels adjacent to each other in the vertical direction (the direction in which the source lines (wirings 121 and 122) extend) share a gate line (wiring 125). Figure 4 The diagram explains a pixel 10 [n, m] arranged in the n-th row and m-th column (n and m are natural numbers greater than or equal to 1) and a pixel 10 [n+1, m] arranged in the n+1-th row and m-th column.

[0133] The gate of the transistor 102 of the pixel 10 [n, m] is electrically connected to the wiring 125 [n+1]. The wiring 125 [n+1] is electrically connected to the gate of the transistor 101 and the gate of the transistor 103 of the pixel 10 [n+1, m].

[0134] The gate of the transistor 102 of the pixel 10[n+1,m] is electrically connected to the wiring 125[n+2]. Although not shown, the wiring 125[n+2] is electrically connected to the gate of the transistor 101 and the gate of the transistor 103 of the pixel 10[n+2,m].

[0135] In the pixel 10 of one embodiment of the present invention, there are two writing operations of writing the first data (weight) and writing the second data (data). Since the weight and the data are supplied from different source lines, the data writing timing of one pixel can overlap with the weight writing timing of the other pixel in two adjacent pixels in the vertical direction. Therefore, the gate line connected to the gate of the transistor performing these operations can be used in common.

[0136] By using a gate line between two pixels, the number of gate lines in each pixel can be reduced from three to two, which can improve the aperture ratio of the pixel. In addition, the operation of the gate driver can be simplified. In addition, since the gate wiring that needs to be charged and discharged is reduced, power consumption can also be reduced.

[0137] Next, refer to Figure 5 The timing diagram shown illustrates the use of two pixels together Figure 4 The following describes an operation example in which a data potential approximately twice the data potential output from the source driver is supplied to the display device through the operation of the pixel 10.

[0138] In this operation description, "H" indicates a high potential and "L" indicates a low potential. In addition, the weight supplied to the pixel 10[n, m] is recorded as "W1", and the image data is recorded as "D1", and the weight supplied to the pixel 10[n+1, m] is recorded as "W2", and the image data is recorded as "D2". ref "For example, 0 V, GND potential, or a specific potential may be used.

[0139] The wiring 123 is always supplied with a high potential, the wiring 129 is always supplied with a low potential, and the wiring 124 is always supplied with a reference potential (V ref ). Note that there may be periods when these potentials are not supplied if there is no effect on operation.

[0140] Note that detailed changes due to circuit structure, operation timing, etc. are not considered in the potential distribution, coupling, or loss here. In addition, the potential change caused by the capacitive coupling of the capacitor depends on the capacitance ratio of the capacitor and the element connected to it, but for the sake of convenience, the capacitance value of the node NM is assumed to be a sufficiently small value.

[0141] From time T1 to time T2, the wiring 121 is supplied with “W1”.

[0142] At time T1, when the potential of wiring 125[n] is set to "H" and the potential of wiring 127[n] is set to "H", the transistor 103 in pixel [n, m] is turned on and the potential of node NA[n, m] becomes "V ref ". This operation is used to reset the subsequent addition operation (capacitive coupling operation).

[0143] Transistor 101 is turned on, and the potential of wiring 121[m] is written to node NM[n,m]. This operation is the operation of writing the weight of pixel 10[n,m], and the potential "W1" is written to node NM[n,m]. In addition, transistor 105 is turned on, and the source potential of transistor 104 becomes "V ref Therefore, even if the transistor 104 is in the on state, the light emitting device 108 does not emit light.

[0144] From time T2 to time T3, the wiring 121 is supplied with “W2”, and the wiring 122 is supplied with “D1”.

[0145] At time T2, when the potential of wiring 125[n] is set to "L", the potential of wiring 127[n] is set to "H", the potential of wiring 125[n+1] is set to "H", and the potential of wiring 127[n+1] is set to "H", transistor 101 is non-conductive. At this time, "W1" is held in node NM[n,m]. In addition, "W1-V ref ”.

[0146] The transistor 103 is turned off, the transistor 102 is turned on, and the potential of the node NA[n,m] becomes the potential "D1" of the wiring 122[m]. At this time, "(D1-V ref )'" is applied to the node NM[n, m]. This operation is the addition operation of the pixel 10[n, m], and the potential of the node NM[n, m] becomes "W1+(D1-V ref )'". At this time, in "V ref =0, the potential of the node NM[n,m] becomes "W1+D1'".

[0147] At this time, the source potential of transistor 104 is "V ref ”, the source potential of the transistor 104 can be written into the potential “W1+D1′” at the node NM[n,m] in a stable state.

[0148] In the pixel [n+1, m], the transistor 103 is turned on, and the potential of the node NA[n+1, m] becomes “V ref ". This operation is used to reset the subsequent addition operation (capacitive coupling operation).

[0149] Transistor 101 is turned on, and the potential of wiring 121[m] is written to node NM[n+1, m]. This operation is the writing operation of the weight of pixel 10[n+1, m], and the potential "W2" is written to node NM[n+1, m]. In addition, transistor 105 is turned on, and the source potential of transistor 104 becomes "V ref Therefore, even if the transistor 104 is in the on state, the light emitting device 108 does not emit light.

[0150] From time T3 to time T4, the wiring 122 is supplied with “D2”.

[0151] At time T3, when the potential of wiring 127[n] is set to "L", the potential of wiring 125[n+1] is set to "L", the potential of wiring 127[n+1] is set to "H", and the potential of wiring 125[n+2] is set to "H", in pixel 10[n, m], transistor 105 is non-conductive, and current flows from transistor 104 through light-emitting device 108 according to the potential of node NM[n, m], thereby light-emitting device 108 emits light.

[0152] In pixel 10[n+1,m], transistor 103 is non-conductive and transistor 102 is conductive, and the potential of node NA[n+1,m] becomes the potential "D2" of wiring 122[m]. At this time, "(D2-V ref )'" is applied to the node NM[n+1,m]. This operation is the addition operation of the pixel 10[n+1,m], and the potential of the node NM[n+1,m] becomes "W2+(D2-V ref )'". At this time, in "V ref =0, the potential of the node NM[n+1,m] becomes "W2+D2'".

[0153] At this time, the source potential of transistor 104 is "V ref ”, the source potential of the transistor 104 can be written into the potential “W1+D2′” at the node NM[n+1,m] in a stable state.

[0154] At time T4, when the potential of wiring 127[n+1] is set to "L" and the potential of wiring 125[n+2] is set to "L", in pixel 10[n+1, m], transistor 105 is non-conductive, and current flows from transistor 104 through light-emitting device 108 according to the potential of node NM[n+1, m], thereby light-emitting device 108 emits light.

[0155] In the above operation, W1=D1 or W2=D2, when the capacitance of the node NM is sufficiently smaller than the capacitance of the capacitor 106, "W1+D1'" becomes a value close to "2D1", and "W2+D2'" becomes a value close to "2D2". Thus, a data potential approximately twice the data potential output from the source driver can be supplied to the display device.

[0156] So far, the pixel 10 using a light emitting device is described as an example, but a liquid crystal device may also be used. Fig. 6A 1 is a circuit diagram of a pixel 10 using a liquid crystal device as a display device. One electrode of the liquid crystal device 110 is electrically connected to the node NM, and the other electrode of the liquid crystal device 110 is electrically connected to the wiring 130 . In addition, the other electrode of the capacitor 107 is electrically connected to the wiring 131 .

[0157] Note that the wiring 130 and the wiring 131 may be electrically connected. The wirings 130 and 131 have a function of supplying power. For example, the wirings 130 and 131 may supply a reference potential such as GND or 0 V or an arbitrary potential.

[0158] A voltage “V” connected to the other of the source and drain of the transistor 103 is supplied. ref "The wiring is as follows Figure 6B As shown, the wiring 131 can be used. Alternatively, the wiring 130 can also be used.

[0159] like Figure 6C As shown, capacitor 107 can also be omitted. As described above, an OS transistor can be used as a transistor connected to node NM. Since the leakage current of the OS transistor is extremely small, the display can be maintained for a long time even if capacitor 107 used as a storage capacitor is omitted. In addition, regardless of the transistor structure, omitting capacitor 107 is effective in shortening the display period when using high-speed operation such as field sequential driving. By omitting capacitor 107, the aperture ratio can be increased. In addition, the transmittance of the pixel can be increased.

[0160] When using liquid crystal devices, Figure 4 Likewise, two pixels in the vertical direction can share one gate line. Figure 7As shown, when a liquid crystal device is used, one gate line is used between two pixels, and the number of gate lines in each pixel is substantially reduced from two to one. The operation description of applying a potential to the node NM can refer to the operation when a light emitting device is used.

[0161] In addition, in the pixel 10 according to one embodiment of the present invention, Figure 8 As shown, the transistor may also include a back gate. Figure 8 A structure in which the back gate is electrically connected to the front gate is shown, which has the effect of increasing the on-state current. In addition, a structure in which the back gate is electrically connected to a wiring capable of supplying a constant potential can be provided. By adopting this structure, the threshold voltage of the transistor can be controlled.

[0162] In the pixel 10 according to one embodiment of the present invention, Fig. 9 As shown, a structure with one source line may also be adopted. In the pixel 10, since the weight and data are written at different timings, one source line may be used to supply them.

[0163] Fig. 10A , Fig. 10B , Fig. 10C This is an example of a layout diagram of the pixel 10 when a light-emitting device is used as a display device. Fig. 10A This is a diagram for explaining the arrangement and structure of a transistor and a capacitor, and shows a stack of gate wiring, a semiconductor layer (metal oxide layer), and source-drain wiring.

[0164] The transistors 101 to 105 have a top gate type self-aligned structure and include a back gate. The back gate is used as a gate wiring. The capacitors 106 and 107 are composed of a conductive layer formed in the same process as the gate wiring, an insulating layer formed in the same process as the gate insulating film of the back gate, and a conductive layer (conductive metal oxide layer) formed in the same process as the semiconductor layer (metal oxide layer) of the transistor.

[0165] The conductive metal oxide layer can be formed by introducing impurities into the metal oxide layer to increase the carrier concentration, similarly to the source region and drain region of the transistor. Note that the conductive metal oxide layer used as one electrode of the capacitor is prone to resistance deviation and its resistance is not as low as that of the metal layer. Therefore, it is preferred to make the conductive metal oxide layer conductive to the conductive layer formed in the same process as the source-drain wiring formed in an overlapping manner to assist the wiring function.

[0166] Fig. 10B Show Fig. 10A A structure in which a wiring layer (source wiring and power supply line) is provided on the stacked layer. Fig. 10C Show Fig. 10BA structure in which a pixel electrode 111 is provided on a stack. A light-emitting device may include a pixel electrode 111 as one electrode and a light-emitting layer provided between the pixel electrode and a counter common electrode, etc.

[0167] Next, the source driver 20 of one embodiment of the present invention will be described. Fig.11A It is a block diagram illustrating a conventional source driver. Fig. 11B , Fig. 11C It is a diagram illustrating a cross section in the channel length direction of a transistor. The source driver includes a logic section and an amplifier section. Circuits 21_1 to 21_n (n is a natural number of 2 or more) are provided in the logic section 21. Circuits 22_1 to 22_m (m is a natural number of 2 or more) are provided in the amplifier section 22. Note that circuits other than the above may be provided in the source driver.

[0168] As the circuits 21_1 to 21_n, for example, an input interface circuit, a serial-parallel conversion circuit, a shift register circuit, a latch circuit, etc. may be provided.

[0169] As the circuits 22_1 to 22_m, for example, a level conversion circuit, a PTL, an amplifier circuit, etc. may be provided.

[0170] The logic section 21 includes circuits such as a shift register circuit that require high-speed operation. Therefore, as Fig. 11B shown, the thickness (t GI ) of the gate insulating film of the transistor 151 constituting the logic section 21 is a relatively thin thickness a. In addition, as shown in the Pelgrom Plot, since the operation deviation of a transistor with a thin gate insulating film is small, the channel length (L) of the transistor can be a relatively short length c. Therefore, it is possible to operate at a low voltage and the power consumption of the logic section 21 is low.

[0171] On the other hand, the amplifier section 22 includes circuits such as an amplifier circuit that output a relatively high voltage. In order to output a high voltage, it is necessary to increase the gate voltage. Therefore, as Fig. 11C shown, the thickness (t GI ) of the gate insulating film of the transistor 152 constituting the amplifier section 22 needs to be formed of a relatively thick thickness b (a < b) to increase the breakdown voltage. In addition, as shown in the Pelgrom Plot, since the operation deviation of a transistor with a thick gate insulating film is large, the channel length (L) of the transistor needs to be a relatively long length d (c < d) to reduce the output deviation.

[0172] As described above, the structures of the transistors in the logic section 21 and the amplifier section 22 are different. In particular, when transistors with different thicknesses of the gate insulating film are mixed in one chip (or on the same substrate), the manufacturing process increases, which causes an increase in cost.

[0173] In addition, the power supply voltage is different in the logic section and the amplifier section. Fig.11A As shown, for example, the logic unit 21 is connected to a power supply circuit 25a that outputs a low voltage, and the amplifier unit 22 is connected to a power supply circuit 25b that outputs a high voltage. Such a circuit configuration that outputs a plurality of voltages is one of the causes of increased costs.

[0174] Note that although Fig. 11B , Fig. 11C The fin-type transistor formed on the silicon substrate is shown in the figure, but a planar transistor or an SOI-type transistor may also be used. Alternatively, a transistor provided on an insulating substrate and including single crystal silicon or polycrystalline silicon in the channel formation region may also be used. Alternatively, a transistor provided on an insulating substrate and including a metal oxide in the channel formation region may also be used. Even if any of the above transistors are used, the above-mentioned problems exist.

[0175] Fig. 12A is a block diagram illustrating a source driver 20 according to one embodiment of the present invention. Fig. 12B , Fig. 12C 2 is a diagram for explaining a cross section of a transistor in the channel length direction. Fig.11A The conventional source driver shown may also include a logic section 21 , an amplifier section 22 and other circuits.

[0176] The source driver 20 of one embodiment of the present invention is different from the existing source driver in that the amplifier unit 22 is connected to at least a power supply circuit 25a that outputs a low voltage. All circuits included in the source driver 20 may also be connected to the power supply circuit 25a. Alternatively, all circuits included in the source driver 20 may operate at the same low voltage.

[0177] like Fig. 12B , Fig. 12C As shown, transistors used in the amplifier section 22 can also use transistors with thin gate insulating films and short channel lengths, similarly to the logic section 21. Therefore, the power consumption of the amplifier section 22 can be reduced.

[0178] The same transistor can also be used for the digital-to-analog conversion circuit and the bias generation circuit included in the source driver 20. Therefore, the power consumption of the source driver 20 as a whole can be made extremely low.

[0179] Since the gate insulating film having the same thickness is used for the transistors included in the logic unit 21 and the amplifier unit 22, the number of manufacturing steps can be significantly reduced, thereby reducing the manufacturing cost.

[0180] Since the power supply circuit 25b for the amplifier section 22 required in the conventional source driver does not need to be provided, the above-mentioned cause of the cost increase can be eliminated. Note that a plurality of power supply circuits 25a connected to the source driver 20 may be provided.

[0181] It is a great advantage in the manufacturing process that the transistors included in the logic unit 21 and the transistors included in the amplifier unit 22 have the same gate insulating film thickness. Here, the same thickness means the thickness that would result if they were not formed separately.

[0182] When the design rule of the transistor included in the source driver 20 is several nm to several hundred nm, the thickness of the gate insulating film is, for example, several nm to several tens of nm. Or, sometimes less than 1 nm. The degree of this thickness is affected by the unevenness of the substrate on which the gate insulating film is provided, so even if it is manufactured in the same process, a certain deviation occurs. This deviation can be confirmed by cross-sectional TEM observation, etc.

[0183] In consideration of the above, in the source driver 20, when a transistor included in one of the logic unit and the amplifier unit includes a region where the thickness of the gate insulating film is a, and a transistor included in the other includes a region where the thickness of the gate insulating film is 0.8a or more and 1.2a or less, a gate insulating film may be considered as not being formed separately as in one embodiment of the present invention. When a more stable process is used, the transistor included in one of the logic unit and the amplifier unit includes a region where the thickness of the gate insulating film is a, and a transistor included in the other includes a region where the thickness of the gate insulating film is 0.9a or more and 1.1a or less.

[0184] The above describes a source driver 20 of one embodiment of the present invention. The logic unit and amplifier unit included in the source driver 20 can operate at, for example, 3.3V or less. In this way, since the source driver 20 can operate with low power consumption, its output voltage is small, so it is difficult for general pixels to properly operate the display device. By combining the source driver 20 with the pixel 10 described above, a display device with extremely low power consumption can be realized.

[0185] The effect of reducing power consumption is greater when using a high-definition display device with a pixel count of 4K2K, 8K4K or more and a large display unit. The more pixels there are, the more times a frame is written, and the larger the display unit size, the higher the power consumption of charging and discharging the source line, so the low-voltage operation effect is significantly presented.

[0186] This embodiment mode can be implemented in combination with the structures described in other embodiment modes and examples as appropriate.

[0187] (Implementation Method 2)

[0188] This embodiment mode describes a configuration example of a display device using a liquid crystal device and a configuration example of a display device using a light-emitting device. Note that in this embodiment mode, description of components, operations, and functions of the display device described in Embodiment Mode 1 is omitted.

[0189] The display device described in this embodiment can use the pixel described in Embodiment 1. Note that a scanning line driver circuit described below corresponds to a gate driver, and a signal line driver circuit corresponds to a source driver. The source driver described in Embodiment 1 can be used as the signal line driver circuit.

[0190] FIG. 13A to FIG. 13C The structure of a display device to which one embodiment of the present invention can be applied is shown.

[0191] exist Fig.13A In the embodiment, the sealant 4005 is provided so as to surround the display portion 215 provided over the first substrate 4001 , and the display portion 215 is sealed by the sealant 4005 and the second substrate 4006 .

[0192] exist Fig.13A In the embodiment, the scanning line driver circuit 221a, the signal line driver circuit 231a, the signal line driver circuit 232a, and the common line driver circuit 241a all include a plurality of integrated circuits 4042 provided on a printed circuit board 4041. The integrated circuit 4042 is formed of a single crystal semiconductor or a polycrystalline semiconductor. The common line driver circuit 241a has a function of supplying a predetermined potential to the wirings 123, 124, 129, 130, 131, etc. described in Embodiment 1.

[0193] Various signals and potentials are supplied to the scanning line driving circuit 221 a , the common line driving circuit 241 a , the signal line driving circuit 231 a , and the signal line driving circuit 232 a through an FPC (Flexible printed circuit) 4018 .

[0194] The integrated circuit 4042 included in the scan line driver circuit 221a and the common line driver circuit 241a has a function of supplying a selection signal to the display portion 215. The integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a has a function of supplying image data to the display portion 215. The integrated circuit 4042 is mounted in a region different from a region surrounded by the sealant 4005 on the first substrate 4001.

[0195] Note that there is no particular limitation on the connection method of the integrated circuit 4042, and a wire bonding method, a COF method, a COG method, a TCP method, or the like can be used.

[0196] Fig. 13BAn example in which the integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a is mounted by a COG method is shown. Alternatively, by forming part or all of the driver circuit over a substrate on which the display portion 215 is formed, a system-on-panel can be formed.

[0197] Fig. 13B The example in which the scanning line driver circuit 221a and the common line driver circuit 241a are formed over the substrate on which the display portion 215 is formed is shown. By forming the driver circuits at the same time as the pixel circuits in the display portion 215, the number of components can be reduced, thereby improving productivity.

[0198] In addition, Fig. 13B In the embodiment, a sealant 4005 is provided so as to surround a display portion 215, a scan line driver circuit 221a, and a common line driver circuit 241a provided on a first substrate 4001. A second substrate 4006 is provided over the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a. Thus, the display portion 215, the scan line driver circuit 221a, the common line driver circuit 241a, and the display device are sealed together by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0199] Although in Fig. 13B 2 shows an example in which the signal line driver circuit 231a and the signal line driver circuit 232a are separately formed and mounted on the first substrate 4001, but one embodiment of the present invention is not limited to this structure, and a scanning line driver circuit may be separately formed and mounted, or a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed and mounted. Fig. 13C As shown in FIG. 1 , the signal line driver circuit 231 a and the signal line driver circuit 232 a may be formed over the substrate on which the display portion 215 is formed.

[0200] In addition, a display device may include a panel in which a display device is in a sealed state and a module in which an IC including a controller and the like is mounted on the panel.

[0201] In addition, the display portion and the scan line driver circuit provided over the first substrate include a plurality of transistors. As the transistor, the Si transistor or the OS transistor described in Embodiment 1 can be used.

[0202] The structures of the transistors included in the peripheral drive circuit and the transistors included in the pixel circuit of the display unit may be the same or different. The transistors included in the peripheral drive circuit may all have the same structure or may have two or more structures. Similarly, the transistors included in the pixel circuit may all have the same structure or may have two or more structures.

[0203] In addition, an input device 4200 may be provided on the second substrate 4006. FIG. 13A to FIG. 13C The structure shown in which the display device is provided with the input device 4200 can be used as a touch screen.

[0204] The sensing device (also referred to as a sensor element) included in the touch screen of one embodiment of the present invention is not particularly limited. Various sensors that can detect the approach or contact of a detection object such as a finger or a stylus pen can be used as the sensing device.

[0205] As the type of sensor, various types such as electrostatic capacitance type, resistance type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type can be used.

[0206] In this embodiment, a touch screen including an electrostatic capacitive sensing device is taken as an example for description.

[0207] As the electrostatic capacitance type, there are surface type electrostatic capacitance type, projected type electrostatic capacitance type, etc. In addition, as the projected type electrostatic capacitance type, there are self capacitance type, mutual capacitance type, etc. It is preferable to use the mutual capacitance type because multi-point sensing can be performed simultaneously.

[0208] The touch panel of one embodiment of the present invention can have various structures, such as a structure in which a display device and a sensing element manufactured separately are bonded together, a structure in which electrodes constituting a sensing element are provided on one or both of a substrate supporting a display device and a counter substrate.

[0209] Fig.14A and Fig. 14B An example of a touch screen is shown. Fig.14A It is a three-dimensional diagram of the touch screen 4210 . Fig. 14B 4 is a perspective view of the input device 4200. Note that for the sake of clarity, only typical components are shown.

[0210] The touch screen 4210 has a structure in which a display device and a sensing device that are manufactured separately are bonded together.

[0211] The touch screen 4210 includes an input device 4200 and a display device which are overlapped.

[0212] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, a wiring 4237, a wiring 4238, and a wiring 4239. For example, the electrode 4227 may be electrically connected to the wiring 4237 or the wiring 4239. In addition, the electrode 4228 may be electrically connected to the wiring 4238. The FPC 4272b may be electrically connected to the wiring 4237, the wiring 4238, and the wiring 4239, respectively. The FPC 4272b may be provided with an IC 4273b.

[0213] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. When the touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element may be used in addition to a capacitive touch sensor.

[0214] Fig.15A and Fig. 15B yes Fig. 13B A cross-sectional view of the portion indicated by the dashed line N1-N2 in FIG. Fig.15A and Fig. 15B The display device shown includes an electrode 4015, which is electrically connected to a terminal of an FPC 4018 via an anisotropic conductive layer 4019. Fig.15A and Fig. 15B In the embodiment, the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112 , the insulating layer 4111 , and the insulating layer 4110 .

[0215] The electrode 4015 and the first electrode layer 4030 are formed using the same conductive layer, and the wiring 4014 and the source electrode and the drain electrode of the transistor 4010 and the transistor 4011 are formed using the same conductive layer.

[0216] In addition, the display portion 215 and the scan line driver circuit 221a provided over the first substrate 4001 include a plurality of transistors. Fig.15A and Fig. 15B , a transistor 4010 in the display portion 215 and a transistor 4011 in the scan line driver circuit 221a are shown. Fig.15A and Fig. 15B Although bottom-gate transistors are shown as the transistor 4010 and the transistor 4011 , top-gate transistors may also be used.

[0217] exist Fig.15A and Fig. 15B In FIG. 4 , an insulating layer 4112 is provided over the transistor 4010 and the transistor 4011. Fig. 15B In the embodiment, a partition wall 4510 is formed on the insulating layer 4112.

[0218] In addition, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. In addition, the transistor 4010 and the transistor 4011 include an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can function as a back gate electrode.

[0219] in addition, Fig.15A and Fig. 15B The display device shown includes a capacitor 4020. Fig.15A and Fig. 15BIn the example of FIG. 4 , the capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, an insulating layer 4103, and an electrode formed in the same process as the source electrode and the drain electrode. The structure of the capacitor 4020 is not limited to this, and the capacitor 4020 can also be formed using other conductive layers and insulating layers.

[0220] Generally, the capacitance value of a capacitor provided in a pixel portion of a display device is set so as to hold charge for a predetermined period in consideration of leakage current of a transistor arranged in the pixel portion, etc. The capacitance value of a capacitor may be set in consideration of off-state current of a transistor electrically connected to the capacitor, etc.

[0221] The transistor 4010 provided in the display portion 215 is electrically connected to the display device. Fig.15A This is an example of a liquid crystal display device that uses a liquid crystal device as a display device. Fig.15A In the embodiment, a liquid crystal device 4013 as a display device includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 serving as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with the liquid crystal layer 4008 interposed therebetween.

[0222] As the liquid crystal device 4013, a liquid crystal device using various modes can be used. For example, a liquid crystal device using a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS mode, a guest-host mode, or the like can be used.

[0223] In addition, a normally black liquid crystal display device, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode, may be used for the liquid crystal display device shown in this embodiment. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, etc. may be used.

[0224] Liquid crystal devices are elements that use the optical modulation effect of liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by the electric field (horizontal electric field, vertical electric field or tilted electric field) applied to the liquid crystal. As liquid crystals used in liquid crystal devices, thermotropic liquid crystals, low molecular liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, etc. depending on the conditions.

[0225] Although Fig.15A An example of a liquid crystal display device having a liquid crystal device in a vertical electric field mode is shown, but a liquid crystal display device having a liquid crystal device in a horizontal electric field mode can also be used in one mode of the present invention. In the case of a horizontal electric field mode, a liquid crystal presenting a blue phase without an alignment film can also be used. The blue phase is a type of liquid crystal phase, and refers to a phase that appears before the transition from the cholesteric phase to the homogeneous phase when the temperature of the cholesteric liquid crystal is raised. Because the blue phase only appears in a narrow temperature range, a liquid crystal composition in which a chiral agent of more than 5wt% is mixed is used for the liquid crystal layer 4008 to expand the temperature range. Since the liquid crystal composition containing a liquid crystal presenting a blue phase and a chiral agent has a fast response speed and is optically isotropic. In addition, the liquid crystal composition containing a liquid crystal presenting a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. In addition, since there is no need to set an alignment film and no friction treatment is required, electrostatic damage caused by the friction treatment can be prevented, and defects and damages of the liquid crystal display device in the manufacturing process can be reduced.

[0226] The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer and is provided to control the interval (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that a spherical spacer may also be used.

[0227] In addition, as needed, optical components (optical substrates) such as black matrices (light shielding layers), coloring layers (color filters), polarizing components, phase difference components, and anti-reflection components can be appropriately provided. For example, circular polarization using polarizing substrates and phase difference substrates can also be used. In addition, backlights or sidelights can also be used as light sources. As the above-mentioned backlights or sidelights, micro-light emitting diodes (Micro-LEDs) can also be used.

[0228] exist Fig.15A In the display device shown in FIG. 4 , a light shielding layer 4132 , a coloring layer 4131 , and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031 .

[0229] As materials that can be used for the light-shielding layer, carbon black, titanium black, metals, metal oxides, or composite oxides containing a solid solution of multiple metal oxides can be cited. The light-shielding layer can also be a film containing a resin material or a thin film of an inorganic material such as a metal. In addition, a laminated film containing a film of a material for a coloring layer can also be used for the light-shielding layer. For example, a laminated structure can be used in which a film containing a material for a coloring layer that allows light of a certain color to pass through and a film containing a material for a coloring layer that allows light of other colors to pass through. By making the material of the coloring layer and the light-shielding layer the same, in addition to being able to use the same equipment, the process can also be simplified, so it is preferred.

[0230] Examples of materials that can be used for the coloring layer include metal materials, resin materials, and resin materials containing pigments or dyes. The light shielding layer and the coloring layer can be formed by, for example, an inkjet method or the like.

[0231] in addition, Fig.15A and Fig. 15B The display device shown includes an insulating layer 4111 and an insulating layer 4104. Insulating layers that do not easily transmit impurity elements are used as the insulating layer 4111 and the insulating layer 4104. Since the semiconductor layer of the transistor is sandwiched between the insulating layer 4111 and the insulating layer 4104, mixing of impurities from the outside can be prevented.

[0232] In addition, as a display device included in the display device, a light-emitting device can be used. As a light-emitting device, for example, an EL device using electroluminescence can be used. The EL device has a layer (also referred to as an EL layer) containing a light-emitting compound between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL device is generated between a pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, whereby the light-emitting compound contained in the EL layer emits light.

[0233] As the EL device, for example, an organic EL device or an inorganic EL device can be used. Note that an LED (including a micro LED) including a compound semiconductor can also be used as a light-emitting material.

[0234] In an organic EL device, electrons are injected into the EL layer from one electrode and holes are injected into the EL layer from the other electrode by applying a voltage. The light-emitting organic compound forms an excited state by the recombination of these carriers (electrons and holes), and emits light when returning to the ground state from the excited state. Due to this mechanism, this light-emitting device is called a current-excitation light-emitting device.

[0235] In addition to the light-emitting compound, the EL layer may also include substances with high hole injection properties, substances with high hole transport properties, hole blocking materials, substances with high electron transport properties, substances with high electron injection properties, or bipolar substances (substances with high electron transport properties and hole transport properties).

[0236] The EL layer can be formed by a method such as an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, or a coating method.

[0237] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their element structures. Dispersed inorganic EL devices include a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism thereof is donor-acceptor recombination type light-emitting using donor energy level and acceptor energy level. Thin-film inorganic EL devices have a structure in which a light-emitting layer is sandwiched between dielectric layers, and the dielectric layers sandwiching the light-emitting layer are sandwiched between electrodes, and the light-emitting mechanism thereof is localized type light-emitting using inner shell electron transition of metal ions. Note that an organic EL device is used as a light-emitting device for explanation here.

[0238] In order to extract the light, at least one of the pair of electrodes of the light-emitting device can be made transparent. A transistor and a light-emitting device are formed on a substrate, and the light-emitting device can adopt a top emission structure that extracts light from the surface opposite to the substrate; a bottom emission structure that extracts light from the surface on one side of the substrate; and a double-sided emission structure that extracts light from both surfaces.

[0239] Fig. 15B This is an example of a light-emitting display device (also referred to as an "EL display device") using a light-emitting device as a display device. The light-emitting device 4513 used as a display device is electrically connected to the transistor 4010 provided in the display portion 215. Although the light-emitting device 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting device 4513 can be appropriately changed according to the direction of light extraction from the light-emitting device 4513, etc.

[0240] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material. An opening is formed in the first electrode layer 4030, and a side surface of the opening is formed into an inclined surface having a continuous curvature.

[0241] The light-emitting layer 4511 may be formed of a single layer or a stack of a plurality of layers.

[0242] The light emitting device 4513 can emit light of white, red, green, blue, cyan, magenta, yellow, or the like depending on the material constituting the light emitting layer 4511 .

[0243] As a method for realizing color display, there are the following methods: a method of combining a light-emitting device 4513 having a white light-emitting color and a coloring layer; and a method of providing a light-emitting device 4513 having a different light-emitting color in each pixel. The former method has higher productivity than the latter method. On the other hand, in the latter method, a light-emitting color having a higher color purity than that of the former method can be obtained. By making the light-emitting device 4513 have a microcavity structure in the latter method, the color purity can be further improved.

[0244] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. For example, by using quantum dots in the light-emitting layer, they can also be used as a light-emitting material.

[0245] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from invading the light-emitting device 4513, a protective layer may be formed on the second electrode layer 4031 and the partition wall 4510. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon: diamond-like carbon film), etc. may be formed. In addition, a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. In this way, in order not to be exposed to the outside air, it is preferable to use a protective film (adhesive film, ultraviolet curing resin film, etc.) with high airtightness and little degassing, and a covering material for packaging (encapsulation).

[0246] As filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet curing resin or thermosetting resin may be used, for example, PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate), etc. Filler 4514 may also contain a desiccant.

[0247] As the sealant 4005, a glass material such as glass frit, a curable resin such as a two-liquid mixed resin that cures at room temperature, a light-curable resin, a thermosetting resin, or other resin material can be used. The sealant 4005 may contain a desiccant.

[0248] In addition, as required, an optical film such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a phase difference plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately arranged on the light emitting surface of the light emitting device. In addition, an anti-reflection film may be arranged on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment may be performed, which is a treatment to reduce reflected glare by utilizing the surface concavity and convexity to diffuse reflected light.

[0249] By providing a light emitting device with a microcavity structure, light with high color purity can be extracted. In addition, by combining a microcavity structure with a color filter, reflected glare can be reduced, thereby improving the visibility of the image.

[0250] Regarding the first electrode layer and the second electrode layer (also called pixel electrode layer, common electrode layer, opposing electrode layer, etc.) that apply voltage to the display device, their transmittance and reflectivity can be selected according to the direction of light extraction, the location where the electrode layer is set, and the pattern structure of the electrode layer.

[0251] As the first electrode layer 4030 and the second electrode layer 4031, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can be used.

[0252] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), their alloys, and their nitrides.

[0253] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also called a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer composed of two or more of aniline, pyrrole and thiophene or its derivatives can be cited.

[0254] Furthermore, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably formed using a nonlinear element.

[0255] Note that Fig.16 As shown in FIG. 1 , a stacked structure having a region where transistors and capacitors overlap in the height direction may also be used. For example, by arranging the transistors 4011 and 4022 constituting the driving circuit in an overlapping manner, a display device with a narrow frame can be realized. In addition, by arranging the transistors 4010, 4023, and 4020 constituting the pixel circuit in a manner that partially includes the overlapping region, the aperture ratio and the resolution can be improved. In addition, in Fig.16 Shown in Fig.15A The example of the liquid crystal display device using the stacked structure shown in FIG. Fig. 15B The EL display device shown.

[0256] In addition, in the pixel circuit, using a conductive film with high light transmittance to visible light as an electrode and wiring can increase the light transmittance in the pixel, thereby substantially increasing the aperture ratio. In addition, since the semiconductor layer is also light-transmissive when an OS transistor is used, the aperture ratio is further increased. This is also effective when the transistor does not adopt a stacked structure.

[0257] Furthermore, a liquid crystal display device and a light-emitting device may be combined to form a display device.

[0258] The light emitting device is arranged on the opposite side of the display surface or at the end of the display surface. The light emitting device has the function of supplying light to the display device. The light emitting device is called a backlight.

[0259] Here, the light-emitting device may include a plate-shaped or film-shaped light-guiding portion (also called a light-guiding plate), and a plurality of light-emitting devices that present light of different colors. By arranging the light-emitting device near the side of the light-guiding portion, light can be emitted from the side of the light-guiding portion to the inside. The light-guiding portion includes a mechanism for changing the light path (also called a light extraction mechanism), whereby the light-emitting device can uniformly irradiate light to the pixel portion of the display panel. Alternatively, a structure in which the light-emitting device is arranged directly under the pixel without providing a light-guiding portion may be adopted.

[0260] The light emitting device preferably includes light emitting devices of three colors: red (R), green (G), and blue (B). Furthermore, it may also include a light emitting device of white (W). As these light emitting devices, light emitting diodes (LEDs) are preferably used.

[0261] Furthermore, the light-emitting device is preferably a light-emitting device with extremely high color purity, the full width at half maximum (FWHM) of the emission spectrum of which is 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and further preferably 20 nm or less. Note that the full width at half maximum of the emission spectrum is as small as possible, for example, it can be 1 nm or more. Thus, when performing color display, a vivid display with high color reproducibility can be performed.

[0262] In addition, the red light-emitting device preferably uses an element whose peak wavelength of the emission spectrum is within the range of 625nm to 650nm. In addition, the green light-emitting device preferably uses an element whose peak wavelength of the emission spectrum is within the range of 515nm to 540nm. The blue light-emitting device preferably uses an element whose peak wavelength of the emission spectrum is within the range of 445nm to 470nm.

[0263] The display device sequentially flashes the light emitting devices of three colors and drives the pixels synchronously, and can display colors by using the additive color mixing method. This driving method can also be called field sequential driving.

[0264] Field sequential driving can display bright color images. In addition, smooth dynamic images can be displayed. In addition, by using the above-mentioned driving method, since a pixel does not need to be composed of multiple sub-pixels of different colors, the effective reflection area of ​​a pixel (also called effective display area, aperture ratio) can be expanded, and a bright display can be performed. Furthermore, since a color filter does not need to be set in the pixel, the transmittance of the pixel can also be improved, and a brighter display can be performed. In addition, the manufacturing process can be simplified, thereby reducing the manufacturing cost.

[0265] Fig.17A , Fig. 17B 4001 is an example of a cross-sectional schematic diagram of a display device capable of field sequential driving. A backlight unit capable of emitting light of each RGB color is provided on one side of the first substrate 4001 of the display device. Note that in field sequential driving, since the light emission of each RGB color is divided into time to display the color, a color filter is not required.

[0266] Fig.17A The backlight unit 4340a shown has a structure in which a plurality of light emitting devices 4342 are arranged directly below the pixel via a diffusion plate 4352. The diffusion plate 4352 has a function of diffusing the light emitted from the light emitting device 4342 to the first substrate 4001 side to make the brightness within the display portion uniform. A polarizing plate may be arranged between the light emitting device 4342 and the diffusion plate 4352 as required. In addition, the diffusion plate 4352 may not be arranged if not required. In addition, the light shielding layer 4132 may be omitted.

[0267] The backlight unit 4340a can realize bright display because it can mount more light emitting devices 4342. In addition, since a light guide plate is not required, there is an advantage that the light efficiency of the light emitting device 4342 is not easily lost. Note that a lens 4344 for light diffusion can also be provided in the light emitting device 4342 as needed.

[0268] Fig. 17B The backlight unit 4340b shown has a structure in which a light guide plate 4341 is provided directly below a pixel via a diffuser plate 4352. A plurality of light emitting devices 4342 are provided at the end of the light guide plate 4341. The light guide plate 4341 has a concavo-convex shape on the side opposite to the diffuser plate 4352, so that the guided light can be scattered by the concavo-convex shape and emitted in the direction of the diffuser plate 4352.

[0269] The light emitting device 4342 may be fixed to the printed circuit board 4347. Fig. 17B RGB light emitting devices 4342 are shown overlapping each other, but RGB light emitting devices 4342 may be arranged in the depth direction. In addition, a reflective layer 4348 that reflects visible light may be provided on the side of the light guide plate 4341 opposite to the light emitting device 4342.

[0270] Since the backlight unit 4340b can reduce the light emitting device 4342, a low-cost and thin backlight unit can be implemented.

[0271] As the liquid crystal device, a light scattering liquid crystal device can also be used. As the light scattering liquid crystal device, it is preferred to use a composite material element containing liquid crystal and polymer. For example, a polymer dispersed liquid crystal device can be used. Alternatively, a polymer network liquid crystal (PNLC (Polymer Network Liquid Crystal)) element can also be used.

[0272] The light scattering type liquid crystal device has a structure in which a liquid crystal portion is provided in a three-dimensional network structure of a resin portion sandwiched between a pair of electrodes. As a material for the liquid crystal portion, for example, a nematic liquid crystal can be used. In addition, as the resin portion, a photocurable resin can be used. The photocurable resin can use, for example, a monofunctional monomer such as acrylate, methacrylate, etc.; a multifunctional monomer such as diacrylate, triacrylate, dimethacrylate, trimethacrylate, etc.; or a polymerizable compound mixed with the above substances.

[0273] Light-scattering liquid crystal devices utilize the anisotropy of the refractive index of the liquid crystal material to display by transmitting or scattering light. In addition, the resin portion may also have anisotropy of the refractive index. When the liquid crystal molecules are arranged in a certain direction according to the voltage applied to the light-scattering liquid crystal device, a direction in which the difference in the refractive index between the liquid crystal portion and the resin portion becomes smaller is generated, and the light incident along this direction is transmitted without being scattered in the liquid crystal portion. Therefore, the light-scattering liquid crystal device is viewed as a transparent state from this direction. On the other hand, when the liquid crystal molecules are randomly arranged according to the applied voltage, the difference in the refractive index between the liquid crystal portion and the resin portion does not change much, so the incident light is scattered in the liquid crystal portion. Therefore, the light-scattering liquid crystal device becomes an opaque state regardless of the viewing direction.

[0274] Fig.18A Yes Fig.17A The liquid crystal device 4013 of the display device is replaced with a light scattering liquid crystal device 4016. The light scattering liquid crystal device 4016 includes a composite layer 4009 having a liquid crystal portion and a resin portion, a first electrode layer 4030, and a second electrode layer 4031. Fig.17A Similarly, when the light scattering liquid crystal element 4016 is used, an alignment film and a polarizing plate are not required. Note that the spacer 4035 in the drawing is spherical in shape, but may be columnar.

[0275] Fig.18B Show that Fig. 17B The liquid crystal device 4013 of the display device is replaced with a light scattering liquid crystal device 4016. Fig.18B The structure shown is preferably a structure that operates in a mode in which light is transmitted when no voltage is applied to the light scattering type liquid crystal device 4016 and light is scattered when voltage is applied. By adopting this structure, a transparent display device can be used in a normal state (non-display state). In this case, color display can be performed when the light is scattered.

[0276] FIG. 19A to FIG. 19E Show Fig.18B A variation of the display device shown in FIG. FIG. 19A to FIG. 19E In order to make it easier to understand, we use Fig.18B The diagram shows a part of the components and omits other components.

[0277] Fig.19A The structure in which the first substrate 4001 is used as a light guide plate is shown. A concave-convex shape may also be provided on the outer surface of the first substrate 4001. In this structure, a light guide plate does not need to be provided separately, so the manufacturing cost can be reduced. In addition, since light attenuation caused by the light guide plate does not occur, the light emitted by the light emitting device 4342 can be efficiently used.

[0278] Fig.19BThe structure of light incident from the vicinity of the end of the composite layer 4009 is shown. Light can be emitted to the outside from the light scattering type liquid crystal device by utilizing total reflection at the interface between the composite layer 4009 and the second substrate 4006 and at the interface between the composite layer 4009 and the first substrate 4001. A material having a larger refractive index than the first substrate 4001 and the second substrate 4006 is used as the resin portion of the composite layer 4009.

[0279] Note that the light emitting device 4342 is not only provided on one side of the display device, but also Fig.19C As shown, it can also be arranged on two opposite sides. Furthermore, it can also be arranged on three sides or four sides. By arranging the light emitting device 4342 on multiple sides, light attenuation can be compensated, and it can also correspond to a large-area display device.

[0280] Fig.19D The structure in which light emitted from the light emitting device 4342 is guided to the display device via the mirror 4345 is shown. With this structure, since light can be easily guided to the display device at a certain angle, total reflected light can be efficiently obtained.

[0281] Fig.19E The structure of the layer 4003 and the layer 4004 stacked on the composite layer 4009 is shown. One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other can be formed of an inorganic film, a cover film or a thin film of an organic resin, etc. A material having a larger refractive index than that of the layer 4004 is used as the resin portion of the composite layer 4009. In addition, a material having a larger refractive index than that of the layer 4003 is used as the layer 4004.

[0282] A first interface is formed between the composite layer 4009 and the layer 4004, and a second interface is formed between the layer 4004 and the layer 4003. With this structure, light that is not totally reflected at the first interface but passes through is totally reflected at the second interface and can return to the composite layer 4009. Therefore, the light emitted by the light emitting device 4342 can be efficiently utilized.

[0283] Notice, Fig.18B and FIG. 19A to FIG. 19E The structures can be combined with each other.

[0284] This embodiment mode can be implemented in combination with the structures described in other embodiment modes and examples as appropriate.

[0285] (Implementation 3)

[0286] In this embodiment, examples of transistors that can be used instead of the transistors described in the above embodiments are described with reference to drawings.

[0287] The display device of one embodiment of the present invention can be manufactured using various types of transistors such as bottom-gate transistors and top-gate transistors, so that the semiconductor layer material or transistor structure used can be easily replaced in accordance with existing production lines.

[0288] [Bottom-gate transistor]

[0289] Fig.20A1 FIG. 8 is a cross-sectional view of a channel protection transistor 810, which is one of the bottom-gate transistors, in the channel length direction. Fig.20A1 In the embodiment, the transistor 810 is formed on a substrate 771. In addition, the transistor 810 includes an electrode 746 on the substrate 771 via an insulating layer 772. In addition, the semiconductor layer 742 is included on the electrode 746 via an insulating layer 726. The electrode 746 can be used as a gate electrode. The insulating layer 726 can be used as a gate insulating layer.

[0290] In addition, an insulating layer 741 is included on the channel formation region of the semiconductor layer 742. In addition, an electrode 744a and an electrode 744b are included on the insulating layer 726 in a manner of contacting a portion of the semiconductor layer 742. The electrode 744a can be used as one of the source electrode and the drain electrode. The electrode 744b can be used as the other of the source electrode and the drain electrode. A portion of the electrode 744a and a portion of the electrode 744b are formed on the insulating layer 741.

[0291] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 on the channel formation region, the semiconductor layer 742 can be prevented from being exposed when the electrodes 744a and 744b are formed. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrodes 744a and 744b are formed. According to one embodiment of the present invention, a transistor with good electrical characteristics can be realized.

[0292] In addition, the transistor 810 includes an insulating layer 728 over the electrode 744 a , the electrode 744 b , and the insulating layer 741 , and includes an insulating layer 729 over the insulating layer 728 .

[0293] When an oxide semiconductor is used for the semiconductor layer 742, it is preferable to use a material that can remove oxygen from a portion of the semiconductor layer 742 to generate oxygen vacancies for at least the portion of the electrode 744a and the electrode 744b that is in contact with the semiconductor layer 742. The carrier concentration in the region where the oxygen vacancies are generated in the semiconductor layer 742 increases, and the region is converted to n-type and becomes an n-type region (n + region). Therefore, the region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, an example of a material that can remove oxygen from the semiconductor layer 742 to generate oxygen vacancies can be tungsten, titanium, or the like.

[0294] By forming the source region and the drain region in the semiconductor layer 742, the contact resistance between the electrode 744a and the electrode 744b and the semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor such as field effect mobility and threshold voltage can be improved.

[0295] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer used as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer used as an n-type semiconductor or a p-type semiconductor can be used as a source region or a drain region of a transistor.

[0296] The insulating layer 729 is preferably formed using a material having a function of preventing impurities from being diffused into the transistor from the outside or reducing diffusion of impurities. Alternatively, the insulating layer 729 may be omitted as necessary.

[0297] Fig.20A2 The transistor 811 shown in the figure is different from the transistor 810 in that an electrode 723 which can function as a back gate electrode is included over the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746.

[0298] Generally speaking, the back gate electrode is formed using a conductive layer and is arranged in a manner that the channel forming region of the semiconductor layer is clamped by the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be equal to that of the gate electrode, or it can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0299] The electrode 746 and the electrode 723 can both be used as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can all be used as gate insulating layers. Alternatively, the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

[0300] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as a "gate electrode", the electrode 746 is referred to as a "back gate electrode". In addition, when the electrode 723 is used as a "gate electrode", the transistor 811 can be regarded as a top gate transistor. In addition, one of the electrode 746 and the electrode 723 is sometimes referred to as a "first gate electrode", and the other is sometimes referred to as a "second gate electrode".

[0301] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween and setting the potentials of the electrode 746 and the electrode 723 to be the same, the region through which the carriers flow in the semiconductor layer 742 is further expanded in the film thickness direction, so that the amount of carrier movement increases. As a result, the on-state current of the transistor 811 increases, and the field effect mobility also increases.

[0302] Therefore, transistor 811 is a transistor having a large on-state current relative to the occupied area. That is, the occupied area of ​​transistor 811 can be reduced relative to the required on-state current. According to one embodiment of the present invention, the occupied area of ​​the transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device with high integration can be realized.

[0303] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, they have a function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity, etc.). In addition, when the back gate electrode is formed larger than the semiconductor layer so as to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0304] In addition, by forming the back gate electrode using a light-shielding conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side, thereby preventing light degradation of the semiconductor layer and preventing degradation of electrical characteristics such as threshold voltage drift of the transistor.

[0305] According to one embodiment of the present invention, a transistor with high reliability can be realized. In addition, a semiconductor device with high reliability can be realized.

[0306] Fig.20B1 is with Fig.20A1 A cross-sectional view of a channel length direction of a channel protection transistor 820 having a different structure. The transistor 820 has a structure substantially the same as that of the transistor 810, except that the insulating layer 741 covers the end of the semiconductor layer 742. In an opening formed by selectively removing a portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744a. In addition, in another opening formed by selectively removing a portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744b. The region of the insulating layer 741 overlapping the channel formation region can be used as a channel protection layer.

[0307] Figure 20B2 The transistor 821 shown is different from the transistor 820 in that an electrode 723 which can be used as a back gate electrode is included on the insulating layer 729 .

[0308] By providing the insulating layer 741, exposure of the semiconductor layer 742 generated when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, the semiconductor layer 742 can be prevented from being thinned when the electrode 744a and the electrode 744b are formed.

[0309] In addition, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 of the transistor 820 and the transistor 821 are longer than those of the transistor 810 and the transistor 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with good electrical characteristics can be provided.

[0310] Fig.20C1 8 is a cross-sectional view of a channel length direction of a channel-etched transistor 825, which is one of the bottom-gate transistors. In the transistor 825, the electrode 744a and the electrode 744b are formed without using the insulating layer 741. Therefore, a portion of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed is sometimes etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be improved.

[0311] Fig.20C2 The transistor 826 shown is different from the transistor 825 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729 .

[0312] FIG. 21A1 to FIG. 21C2 810 , 811 , 820 , 821 , 825 , and 826 are cross-sectional views in the channel width direction, respectively.

[0313] exist Fig.21B2 and Fig.21C2 In the structure shown, the gate electrode and the back gate electrode are connected to each other, so that the gate electrode and the back gate electrode have the same potential. In addition, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0314] In the channel width direction, the length of the gate electrode and the back gate electrode is greater than that of the semiconductor layer 742 , and the entire semiconductor layer 742 is covered by the gate electrode and the back gate electrode with the insulating layers 726 , 741 , 728 , and 729 interposed therebetween.

[0315] With this structure, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric field of the gate electrode and the back gate electrode.

[0316] A device structure of a transistor such as the transistor 821 and the transistor 826 in which the semiconductor layer 742 forming a channel formation region is electrically surrounded by an electric field between a gate electrode and a back gate electrode can be called a surrounded channel (S-channel) structure.

[0317] By adopting the S-channel structure, an electric field for causing channel formation can be effectively applied to the semiconductor layer 742 using one or both of the gate electrode and the back gate electrode, thereby improving the current driving capability of the transistor, thereby obtaining a higher on-state current characteristic. In addition, since the on-state current can be increased, the transistor can be miniaturized. In addition, by adopting the S-channel structure, the mechanical strength of the transistor can be improved.

[0318] [Top-gate transistor]

[0319] Fig.22A1 The transistor 842 shown is a top-gate transistor. The electrode 744 a and the electrode 744 b are electrically connected to the semiconductor layer 742 through openings formed in the insulating layer 728 and the insulating layer 729 .

[0320] In addition, a portion of the insulating layer 726 that does not overlap with the electrode 746 is removed, and impurities are introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, thereby forming an impurity region in the semiconductor layer 742 in a self-aligned manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration of the region of the semiconductor layer 742 into which the impurities are introduced through the insulating layer 726 is lower than the impurity concentration of the region into which the impurities are not introduced through the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that overlaps with the insulating layer 726 and does not overlap with the electrode 746.

[0321] Fig.22A2 The transistor 843 shown is different from the transistor 842 in that it includes an electrode 723. The transistor 843 includes an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 via an insulating layer 772. The electrode 723 can be used as a back gate electrode.

[0322] In addition, if Fig.22B1 The transistor 844 and Fig.22B2 As in the transistor 845 shown in FIG. 8 , the insulating layer 726 in the region not overlapping with the electrode 746 may be completely removed. Fig.22C1 The transistor 846 and Fig.22C2As in the transistor 847 shown in the figure, the insulating layer 726 does not need to be removed.

[0323] In transistors 842 to 847, after forming electrode 746, impurities may be introduced into semiconductor layer 742 using electrode 746 as a mask, thereby forming an impurity region in semiconductor layer 742 in a self-aligned manner. According to one embodiment of the present invention, a transistor with good electrical characteristics can be realized. In addition, according to one embodiment of the present invention, a semiconductor device with high integration can be realized.

[0324] FIG. 23A1 to FIG. 23C2 It is a cross-sectional view of transistors 842 , 843 , 844 , 845 , 846 , and 847 in the channel width direction.

[0325] The transistor 843, the transistor 845, and the transistor 847 have the above-mentioned S-channel structure. However, the present invention is not limited to this, and the transistor 843, the transistor 845, and the transistor 847 may not have the S-channel structure.

[0326] This embodiment mode can be implemented in combination with the structures described in other embodiment modes and examples as appropriate.

[0327] (Implementation 4)

[0328] Electronic devices that can use the display device of one embodiment of the present invention include display devices, personal computers, image storage devices and image reproduction devices with recording media, mobile phones, game consoles including portable game consoles, portable data terminals, electronic book readers, photographing devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), and vending machines, etc. Specific examples of these electronic devices are shown in FIG24 .

[0329] Fig.24A The digital camera includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display portion 965, operation keys 966, a zoom button 968, a lens 969, and the like. By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed.

[0330] Fig. 24B This is a portable data terminal including a housing 911, a display unit 912, a speaker 913, an operation button 914, a camera 919, and the like. Data can be input or output by utilizing the touch screen function of the display unit 912. By using the display device of one embodiment of the present invention for the display unit 912, various images can be displayed.

[0331] Fig.24C The mobile phone includes a housing 951, a display unit 952, an operation button 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, and the like. The mobile phone includes a touch sensor in the display unit 952. All operations such as making a call or inputting text can be performed by touching the display unit 952 with a finger or a stylus pen. In addition, the housing 951 and the display unit 952 are flexible and can be used in a bent manner as shown in the figure. By using a display device of one embodiment of the present invention for the display unit 952, various images can be displayed.

[0332] Fig.24D The video camera includes a first housing 901, a second housing 902, a display unit 903, operation keys 904, a lens 905, a connection unit 906, a speaker 907, and the like. The operation keys 904 and the lens 905 are provided in the first housing 901, and the display unit 903 is provided in the second housing 902. By using the display device of one embodiment of the present invention for the display unit 903, various images can be displayed.

[0333] Fig.24E The television set includes a housing 971, a display portion 973, operation buttons 974, a speaker 975, a communication connection terminal 976, and a photoelectric sensor 977. The display portion 973 is provided with a touch sensor to enable input operations. By using the display device of one embodiment of the present invention for the display portion 973, various images can be displayed.

[0334] Fig.24F The digital signage includes a large display unit 922. The digital signage includes, for example, a large display unit 922 mounted on a side surface of a pillar 921. By using the display device of one embodiment of the present invention for the display unit 922, a high-quality display can be performed.

[0335] This embodiment mode can be implemented in combination with the structures described in other embodiment modes and examples as appropriate.

[0336] [Example]

[0337] In this embodiment, test production results of a transistor and a display device according to one embodiment of the present invention are described.

[0338] <Transistor Characteristics>

[0339] Fig.25A The I of the OS transistor (W / L=3 μm / 6 μm) manufactured in the same process as the manufacturing process of the display device is shown. D -V G Characteristics (Vds = 0.1V, 10V). In addition, Fig.25BShows the I-V characteristics of the OS transistor (W / L = 6μm / 2μm). D -V G characteristics (V ds = 0.1V, 10V). The transistor characteristics are normally off, and the off-state current is a value below the measurement lower limit of the measuring instrument. The OS transistor exhibits the same level of current capability as a general low-temperature polycrystalline silicon (LTPS) transistor when the channel length is 2μm or less.

[0340] <EL pixel circuit>

[0341] Fig.26A Shows the circuit diagram of a pixel using a light-emitting device as a display element. A storage circuit composed of one transistor (M4) and one capacitor (CW) is provided in the pixel circuit. The entire pixel circuit has a structure including five transistors (M1 to M5), two capacitors (CW, CS), and a light-emitting device (OLED). In addition, all transistors are provided with a back gate electrically connected to the front gate. The components included in the pixel circuit are electrically connected to at least one of the gate lines (GL1 to GL3), source lines (SL, SLW), power supply lines (ANODE, CATHODE), and reference potential line (V0). In addition, the pixel circuit includes node A and node B connected to several components. For detailed content, refer to Figure 2 the description of

[0342] Since the OS transistor has an extremely small leakage current characteristic, it can have the function of a storage circuit composed of one transistor and one capacitor. Therefore, compared with the case of using LTPS transistors, fewer components can be used to assemble the storage circuit in the pixel. In addition, this storage circuit can hold an analog value.

[0343] Next, a method of driving according to the timing diagram shown in Fig.26B will be briefly described. The period of writing the weight (V w ) and the period of writing the display data (V data ) are different timings. Note that n shown in the timing diagram represents the number of rows of pixels, and n is a natural number of 1 or more.

[0344] <Writing of the weight (V w )

[0345] First, the gate line GL1 is set to a high potential to turn on the transistors M4 and M5, and node A is written with the reference potential V0 supplied from the reference potential line (V0). In addition, node B is written with the potential (V w ) supplied to the source line SLW.

[0346] <Display data(V data )'s write>

[0347] Next, the gate line GL1 is set to a low potential, the gate line GL2 is set to a high potential, and the potential (V data ). At this time, the voltage V g For (C w (V w -V0)+C s (V w -V0)+C w ·V data ) / (C w +C s ). Note that C w is the capacitance value of capacitor CW, C s is the capacitance value of capacitor CS.

[0348] Here, when V0 = 0V, V g =V w +(C w / (C w +C s ))·V data Therefore, at V w >(C s / (C w +C s ))·V data When , a voltage greater than the output of the source driver can be applied to the pixel.

[0349] <Liquid crystal pixel circuit>

[0350] Fig.27A A circuit diagram of a pixel using a liquid crystal device as a display element is shown. In the pixel circuit, a storage circuit consisting of a transistor (M4) and a capacitor (CW) is provided, similarly to the EL pixel circuit. The pixel circuit as a whole includes two transistors (M1, M4), two capacitors (CW, CS), and a liquid crystal device (LC). In addition, all transistors are provided with a back gate electrically connected to the front gate. The components included in the pixel circuit are electrically connected to at least one of the gate lines (GL1, GL2), the source lines (SL, SLW), and the reference potential lines (TCOM, CSCOM). In addition, the pixel circuit includes node A and node B connected to several components. For details, please refer to Fig. 6A Note that the same reference numerals are used for the same components as those of the EL pixel circuit.

[0351] Next, a driving method of the above-mentioned liquid crystal pixel circuit is briefly described.

[0352] <Weight(V w )'s write>

[0353] First, the gate lines GL1 and GL2 are set to high potential, the transistors M1 and M4 are turned on, and the potential supplied to the source line SL (reference potential V r ). In addition, node B is written with the potential (V w ).

[0354] <Display data(V data )'s write>

[0355] Next, the gate line GL1 is set to a low potential, the gate line GL2 is set to a high potential, only M4 is made non-conductive, and the potential (V data At this time, due to the capacitive coupling of capacitor CW, the potential of node B is (C w (V w -V r )+(C s +C lc )·(V w -V r )+C w ·V data ) / (C w +C s +C lc ). Note that C lc is the capacitance value of the liquid crystal device LC.

[0356] The potential of node B also depends on C w and (C s +C lc ) ratio, this formula can be used to obtain the ratio V data That is, it is possible to data A large potential is applied to the liquid crystal device LC.

[0357] <Source Driver>

[0358] When the above effect is utilized, the voltage V g When a maximum voltage of 5V is required, the output voltage of the source driver can be less than 5V. g It also depends on the capacitance ratio of the capacitor CW to the capacitor CS, and the output voltage of the source driver is sufficient at, for example, 3.3 V.

[0359] In the liquid crystal pixel circuit, when a maximum voltage of 5 V is required at node B, the output voltage of the source driver can be a value less than 5 V. The voltage of node B also depends on the capacitance ratio of capacitor CW to capacitor CS + liquid crystal device LC, and the output voltage of the source driver is sufficient, for example, 3.3 V.

[0360] This effect contributes to the reduction of the upper limit of the withstand voltage of the amplifier circuit included in the source driver. By using the above-mentioned EL pixel circuit, the amplifier circuit of the source driver does not need to be composed of a technology with a withstand voltage of 5V, but can be composed of a technology with a withstand voltage of 3.3V. In addition, by using the above-mentioned liquid crystal pixel circuit, the amplifier circuit of the source driver does not need to be composed of a technology with a withstand voltage of more than 10V, but can be composed of a technology with a withstand voltage of less than 10V.

[0361] The source driver has Fig.28 The structure of the block diagram shown is simulated to estimate the power consumption of each block assuming 5V technology and 3.3V technology. The assumed panel is a smartphone-sized panel with 1080×1920 pixels. Note that Smartspice from Silvaco was used for the simulation.

[0362] Note that the operating conditions of the panel assume a case where 30% of the display portion is rewritten. Also, assume a case where the structure of the logic portion of the source driver and the like is common and only the transistor size of the amplifier circuit is changed.

[0363] Fig.29A The estimated comparison results of the power consumption of the source driver for the EL pixel circuit are shown. The pixel circuit A is assumed to be a conventional pixel circuit (transistor × 3 + capacitor × 1, Fig.26A The power consumption of the source driver including the amplifier circuit of 5V technology is shown. Pixel circuit B is assumed to be a pixel circuit of one embodiment of the present invention described above (transistor × 5 + capacitor × 2, Fig.26A ), showing the power consumption of the source driver including the amplifier circuit of 3.3V technology.

[0364] like Fig.29A As shown, by using pixel circuit B and using a source driver with appropriate technology, power consumption can be greatly reduced. The reason for greatly reducing power consumption is that low voltage technology can be used in the amplifier circuit that accounts for most of the power consumption of the source driver. In addition, the power consumption of the level conversion circuit depends on the power supply voltage. Therefore, by using a pixel circuit of one embodiment of the present invention, the power consumption of the source driver can be reduced.

[0365] Fig.29BShows the estimated comparison results of the power consumption of the source driver for the liquid crystal pixel circuit. Pixel circuit C shows the power consumption assuming the existing pixel circuit (1 transistor + 1 capacitor, the structure not including transistor M1 and capacitor CW in Fig.27A and the source driver. In addition, pixel circuit D shows the power consumption assuming the pixel circuit of one embodiment of the present invention and the source driver of appropriate technology. Note that as pixel circuit D, the pixel circuit shown in Fig.27B which can operate with lower power consumption is used (3 transistors + 2 capacitors). From the results shown in Fig.29B , it can be seen that, similar to the results of the source driver for the EL pixel circuit, by using the pixel circuit of one embodiment of the present invention, the power consumption of the source driver can be reduced.

[0366] Fig.26A The pixel circuit shown in Fig.26A corresponds to the above pixel circuit B (5 transistors + 2 capacitors) and can also operate as pixel circuit A (3 transistors + 1 capacitor). Here, the results of actually measuring the power consumption when operating as pixel circuit A (A mode) and when operating as pixel circuit B (B mode) for a trial-produced panel including the pixel circuit shown in

[0367] are described. Note that 5V technology is used in the source driver.

[0368] Fig.30 Shows the comparison results of the power consumption when displaying each image. The power consumption is the value obtained by adding the power consumption of the light-emitting device, the power consumption of the source driver, and the power consumption of the gate driver. At this time, as described above, the power consumption of the light-emitting device in both A mode and B mode is the same. Although the power consumption of the gate driver is higher in B mode where there is one more driven gate line, it is one digit lower than the power consumption of the source driver, so the influence on the comparison result of the power consumption is very small.

[0369] It can be said that the difference in power consumption for each display is substantially the difference in the power consumption of the source driver, and it can be seen that the power consumption can be reduced by operating in B mode. That is, it is confirmed that: the pixel circuit of one embodiment of the present invention can operate with lower power consumption compared to the existing pixel circuit.

[0370] <EL Display Panel>

[0371] Table 1 shows the specifications of the trial-produced EL display panel. The gate driver uses an OS transistor and is provided on the same substrate as the pixel circuit. The light-emitting device uses a white tandem organic EL device and adopts a method of achieving colorization through color filters. Fig.32AThe display results of the prototype EL display panel are shown.

[0372] [Table 1]

[0373] Specification Diagonal size 4.68 inches Resolution 720×1280 Pixel size 84μm×84μm Pixel density 302ppi Opening rate 43.7％ Pixel arrangement RGB Strip Color Mode White tandem OLED + color filter Light extraction method Top Launch Source Driver COG Gate Driver built-in

[0374] <Liquid Crystal Display Panel>

[0375] The following is a trial production of a liquid crystal display panel with the specifications shown in Table 2. The gate driver uses an OS transistor and is set on the same substrate as the pixel circuit. The source driver uses an IC chip that can output -4V to +4V. FFS mode liquid crystal materials such as Fig.31A The saturation voltage is 10 V. Since this voltage is higher than the output voltage of the source driver, the liquid crystal device cannot be saturated in the existing pixel circuit.

[0376] [Table 2]

[0377] Specification Diagonal size 10.2 inches Resolution 720×1920 Pixel size 126μm×126μm Pixel density 201ppi Opening rate 46.2％ liquid crystal FFS mode Source Driver COG Gate Driver built-in

[0378] Fig.31B The relationship between the voltage applied to the liquid crystal device and the brightness of the panel is shown in the figure. The results of comparing the existing pixel circuit X and the pixel circuit Y of one embodiment of the present invention are shown. It is confirmed that the voltage higher than the output of the source driver can be applied to the liquid crystal device through the boost function of the pixel circuit Y of one embodiment of the present invention. Fig.32B The display results of the trial-produced liquid crystal display panel are shown. Since a sufficient voltage can be applied to the liquid crystal device even when a low-output source driver is used, a high-brightness display can be performed.

[0379] By utilizing the extremely small off-state leakage characteristics of the OS transistor, an organic EL display panel and a liquid crystal display panel with a memory circuit installed in the pixel were trial-produced. It was confirmed that by maintaining the weight in the memory, a voltage higher than the output of the source driver can be generated in the pixel, so the output voltage of the source driver can be reduced. In addition, it is estimated that this effect can reduce the withstand voltage of the transistor constituting the source driver and reduce the power consumption of the source driver.

[0380] The pixel circuit of one embodiment of the present invention can be composed of only OS transistors. In addition, there is no special manufacturing process and the number of masks does not increase. In addition, compared with the manufacturing process of LTPS transistors, the manufacturing process of OS transistors can reduce the number of masks, so it is preferable to use OS transistors for display panels in terms of manufacturing processes.

[0381] [Explanation of symbols]

[0382] 10: Pixel, 11: Pixel array, 20: Source driver, 21: Logic unit, 21_n: Circuit, 21_1: Circuit, 22: Amplifier unit, 22_m: Circuit, 22_1: Circuit, 25: Power supply circuit, 25a: Power supply circuit, 25b: Power supply circuit, 30: Gate driver, 40: Circuit, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Capacitor, 107: Capacitor, 108: Light emitting device, 109: Transistor, 110: Liquid crystal device, 111: Pixel electrode, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 127: Wiring, 129: Wiring, 130: Wiring, 131: Wiring, 151: Transistor, 152: Transistor, 215: Display unit, 221a: Scanning line driver circuit, 231a: Signal line driver circuit, 232a: Signal line driver circuit, 241a: Common line driver circuit, 723: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 771: Substrate, 772: Insulating layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Crystal tube, 844: transistor, 845: transistor, 846: transistor, 847: transistor, 901: housing, 902: housing, 903: display unit, 904: operation key, 905: lens, 906: connection unit, 907: speaker, 911: housing, 912: display unit, 913: speaker, 914: operation button, 919: camera, 921: pillar, 922: display unit, 951: housing, 952: display unit, 953: operation button, 954: external connection port, 955: speaker, 956: microphone, 957: camera, 961: housing, 962: shutter button, 963: microphone, 965: display unit, 966: operation key, 967: speaker , 968: zoom button, 969: lens, 971: housing, 973: display unit, 974: operation button, 975: speaker, 976: communication connection terminal, 977: optical sensor, 4001: substrate, 4003: layer, 4004: layer, 4005: sealant, 4006: substrate, 4008: liquid crystal layer, 4009: composite layer, 4010: transistor, 4011: transistor, 4013: liquid crystal device, 4014: wiring, 4015: electrode, 4016: light scattering type liquid crystal device, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020: capacitor, 4021: electrode, 4022: transistor, 4023: transistor,4030: electrode layer, 4031: electrode layer, 4032: insulating layer, 4033: insulating layer, 4035: spacer, 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: insulating layer, 4104: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: coloring layer, 4132: light shielding layer, 4133: insulating layer, 4200: input device, 4210: touch screen, 4227: electrode, 4228 : electrode, 4237: wiring, 4238: wiring, 4239: wiring, 4263: substrate, 4272b: FPC, 4273b: IC, 4340a: backlight unit, 4340b: backlight unit, 4341: light guide plate, 4342: light emitting device, 4344: lens, 4345: mirror, 4347: printed circuit board, 4348: reflection layer, 4352: diffusion plate, 4510: partition wall, 4511: light emitting layer, 4513: light emitting device, 4514: filler,

Claims

1. A display device, comprising: Driver circuit; as well as Pixel circuit, Wherein, the driver circuit includes a shift register circuit and an amplifier circuit, The pixel circuit is configured to generate third data by adding first data and second data output from the amplifier circuit, The shift register circuit and the amplifier circuit are each supplied with the same power supply voltage, The pixel circuit includes a first transistor, a second transistor, a third transistor and a first capacitor; One of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor; The other electrode of the first capacitor is electrically connected to one of the source and the drain of the second transistor; The one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; The gate of the first transistor and the gate of the third transistor are electrically connected to a first gate line, Furthermore, a gate of the second transistor is electrically connected to a second gate line.

2. The display device according to claim 1, The shift register circuit and the amplifier circuit are electrically connected to the same power supply circuit.

3. The display device according to claim 1, The power supply voltage supplied to the driver circuit is 3.3V or less.

4. The display device according to claim 1, The driver circuit further includes one or more circuits selected from an input interface circuit, a serial-to-parallel conversion circuit, a latch circuit, a level conversion circuit, a PTL, a digital-to-analog conversion circuit, and a bias generation circuit. And the one or more circuits are supplied with the same power supply voltage as the power supply voltage used for the shift register circuit and the amplifier circuit.

5. A display device, comprising: Driver circuit; as well as Pixel circuit, Wherein, the driver circuit includes a shift register circuit and an amplifier circuit, The pixel circuit is configured to generate third data by adding first data and second data output from the amplifier circuit, The shift register circuit comprises a first transistor, The amplifier circuit comprises a second transistor, When one of the first transistor and the second transistor includes a first region whose gate insulating film has a thickness of a, the other of the first transistor and the second transistor includes a second region whose gate insulating film has a thickness of 0.9a or more and 1.1a or less, The pixel circuit includes a third transistor, a fourth transistor, a fifth transistor and a first capacitor, One of the source and the drain of the third transistor is electrically connected to one electrode of the first capacitor; The other electrode of the first capacitor is electrically connected to one of the source and the drain of the fourth transistor and one of the source and the drain of the fifth transistor; The gate of the third transistor and the gate of the fifth transistor are electrically connected to the first gate line, Furthermore, a gate of the fourth transistor is electrically connected to the second gate line.

6. The display device according to claim 5, The driver circuit further includes one or more circuits selected from an input interface circuit, a serial-to-parallel conversion circuit, a latch circuit, a level conversion circuit, a PTL, a digital-to-analog conversion circuit, and a bias generation circuit. And the transistor included in the one or more circuits includes a gate insulating film with a thickness of 0.9 Å to 1.1 Å.

7. The display device according to claim 5, wherein the pixel circuit further comprises: a sixth transistor; The seventh transistor; a second capacitor; as well as Light emitting device, wherein the gate of the sixth transistor is electrically connected to the one electrode of the first capacitor and the one electrode of the second capacitor, The one of the source and the drain of the fifth transistor is electrically connected to the other electrode of the first capacitor, One of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor, The one of the source and the drain of the seventh transistor is electrically connected to an electrode of the light emitting device, The one electrode of the light emitting device is electrically connected to the other electrode of the second capacitor, Furthermore, the other electrode of the second capacitor is electrically connected to the one of the source and the drain of the sixth transistor and the one of the source and the drain of the seventh transistor.

8. The display device according to claim 5, wherein the pixel circuit further comprises: a second capacitor; as well as Liquid crystal devices, wherein the one of the source and the drain of the fifth transistor is electrically connected to the other electrode of the first capacitor, the other electrode of the first capacitor is electrically connected to the one of the source and the drain of the fourth transistor, The one of the source and the drain of the fourth transistor is electrically connected to the one of the source and the drain of the fifth transistor, The one electrode of the first capacitor is electrically connected to one electrode of the second capacitor, Furthermore, the one electrode of the second capacitor is electrically connected to one electrode of the liquid crystal device.

9. The display device according to claim 7 or 8, The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.

10. The display device according to any one of claims 5, 7 and 8, Each of the transistors included in the pixel circuit includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, M, Furthermore, M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf.

11. The display device according to any one of claims 5 to 8, further comprising a power supply circuit, in, The power supply circuit provides power supply voltage to the shift register circuit and the amplifier circuit. And the shift register circuit and the amplifier circuit are supplied with the same power supply voltage.

12. An electronic device comprising: The display device according to claim 1 or 5; as well as camera.

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