Network switch ASIC and optical transceiver assembly

Abstract

The present invention relates to a switch system comprising one or more optical transceiver assemblies (14) connected to a switch ASIC (29).

Description

Summary of the invention

[0001] Exemplary embodiments of the present invention relate to a high-bandwidth switch ASIC in a network server. The switch ASIC and the optical transceiver assembly are placed on a high-speed substrate so that the electrical connections are very short for minimal signal distortion. TSVs in the transceiver chip separate the optical interface from the electrical interface in order to avoid wire bonding and provide an efficient heat dissipation concept. TSVs and pluggable optical connectors allow for reflow solderable assembly of the transceiver socket. Due to the compactness of the transceiver socket and the pluggable optical connector, the optical fiber extends horizontally from the transceiver assembly, which allows the heat sink to be placed above the transceiver assembly. The pluggable optical connector contains a stack of silicon chips so that heat can be dissipated from the transceiver chip very efficiently. The laser can be externally connected to the transceiver chip from an external source outside the high-speed substrate. The switch ASIC can be connected to the same heat sink.

[0002] Definition of terms

[0003] • Network switch, which is a term used by those skilled in the art to describe a computer networking device that connects devices on a computer network together by using packet switching to receive, process, and forward data to a destination device.

[0004] Switch ASIC (Application Specific Integrated Circuit), a term used by those skilled in the art to describe semiconductor chips typically deployed in network switches that connect devices on a computer network together by using packet switching to receive, process, and forward data to a destination device.

[0005] High-speed substrate, a term used by those skilled in the art to describe signal-carrying materials and designs where the integrity of the signal is not severely impacted by the physical characteristics of the board, such as layout, packaging, layer stack-up, interconnects, etc.

[0006] • Switch co-packaging, a term used by those skilled in the art to describe the assembly of a switch ASIC and an additional semiconductor chip placed on a common high-speed substrate to enable chip-to-chip communications with high signal integrity and low power consumption.

[0007] • Optical transceiver assembly, which is a term used to describe a system for connecting one or an array of optical signal paths, such as optical fibers, with optical coupling elements in a photonic integrated circuit.

[0008] EPIC: Electronic Photonic Integrated Circuit (EPIC)

[0009] • Optical transceiver, which is a term used by those skilled in the art for transmitters and receivers that convert electrical data signals into optical signals and vice versa.

[0010] TSV with metal pads, which is a term used by those skilled in the art to describe through silicon vias, connecting lines to conductor trace connections or metal pads located below the bottom surface of the transceiver chip substrate, where the connecting lines extend from electronic or optoelectronic components through through holes in the substrate to conductor trace connections or metal pads located below the back side of the substrate.

[0011] - Optical wavelength multiplexer, which is a term used by those skilled in the art to describe a device that multiplexes many optical carrier signals onto a single optical signal path such as an optical fiber or waveguide by using different wavelengths.

[0012] Optical wavelength demultiplexer, which is a term used by those skilled in the art to describe a device that demultiplexes an optical input signal from a single optical signal path such as an optical fiber or waveguide containing multiple optical carrier signals using different wavelengths into multiple optical signal paths each containing one optical carrier signal.

[0013] - Wavelength Division Multiplexing (WDM), which is a term used by those skilled in the art to describe the technique of multiplexing many optical carrier signals onto a common signal path such as an optical fiber or waveguide by using different wavelengths.

[0014] • Time Division Multiplexing (TDM), a term used by those skilled in the art to describe a method of sending and receiving independent signals over a common signal path so that each signal appears on the line only a fraction of the time in an alternating pattern.

[0015] Polarization Division Multiplexing (PDM), which is a term used by those skilled in the art to describe a method for multiplexing signals carried on electromagnetic waves, allowing two channels of information to be sent on the same carrier frequency using waves in two orthogonal polarization states.

[0016] • Optical fiber array, which is a term used by those skilled in the art to describe an array of optical fibers grouped into parallel bundles or ribbons through the use of an encapsulating cable coating.

[0017] • Multi-core optical fiber, which is a term used by those skilled in the art to describe an optical fiber containing more than one optical fiber core.

[0018] • Thermal interface material, a term used by those skilled in the art to describe materials used in the interface of assembled components in order to achieve good thermal conductivity.

[0019] Ball grid array, a term used by those skilled in the art to describe a type of surface mount package for integrated circuits. A regular array of solder balls creates solderable connections on the bottom surface of the PCB.

[0020] • Transfer moulding, a term used by those skilled in the art to describe the manufacturing process of forcing the casting material into a mould in order to achieve sealing of the components in a co-package.

[0021] • Lens array chip, which is a term used by those skilled in the art to describe an array of lenses etched on a silicon substrate.

[0022] • Through-hole, which is a term used by those skilled in the art to describe a hole etched through a substrate.

[0023] • Motherboard, which is a term used by those skilled in the art to describe a large printed circuit board that holds and allows communication between many of the key electronic components of the system and provides connectors for other peripherals.

[0024] · Pluggable optical connector, which is a term used to describe an optical interface component that includes a fiber mount for securing an optical fiber, and a mirrored facet on the fiber termination side.

[0025] • Optical transceiver chips, electronic photonic integrated circuits (EPICs) that include transceiver functionality for converting electrical signals into optical signals and vice versa.

[0026] An exemplary embodiment of the present invention is directed to a switch packaging configuration that includes one or more (e.g., all) of the following features:

[0027] -16 optical transceiver assemblies are connected to a 51.2Tbit / s switch ASIC, with 4 optical transceiver assemblies on each side of the switch ASIC (see picture). In this case:

[0028] - There are 32 transmitter and 32 receiver input and output channels between an optical transceiver assembly and the switch ASIC, with a net data rate of 100Gbit / s per channel. The aggregate data throughput of an optical transceiver assembly is 3.2Tbit / s.

[0029] The following variants AC of the above embodiment are considered advantageous:

[0030] -A) In parallel arrangement (all channels coupled in different fibers): 16 optical transceiver assemblies contain 16 pluggable optical connectors (one for each). Each pluggable optical connector contains preferably 72 fibers (32 receiver fibers, 32 transmitter fibers, and 8 fibers for external laser input to the EPIC). The aggregate fiber count of the switch package is 1152 fibers. This arrangement supports standards like IEEE400GBASE-DR4 (one fiber per channel)

[0031] -B) An arrangement with an optical multiplexer (e.g. 4:1) and an optical demultiplexer (e.g. 1:4), for example integrated in pluggable optical connectors (Figure). Each pluggable optical connector contains preferably 24 fibers (8 receiver fibers, 8 transmitter fibers, and 8 fibers for external laser input to the EPIC). The aggregate fiber count of the switch package is 384 fibers. This arrangement supports standards like IEEE 400GBASE-FR4.

[0032] - Arrangements A) and B) can be arranged in such a way that they can be used with the same transceiver socket of the transceiver assembly. In this case, swapping of the pluggable optical connectors is required. -> It would be advantageous for a configurable switch package and / or switch system to be able to change between the two arrangements by swapping only the optical connectors, the fiber optic cable assembly and the external laser source.

[0033] -C) An arrangement of multi-core optical fibers attached to a pluggable optical connector. The pluggable optical connector utilizes a beam forming arrangement (mirrors, lenses, ...) to couple N light beams of the multi-core optical fiber into a transceiver chip. Utilizing such a multi-core optical fiber arrangement, the number of optical fibers of each pluggable optical connector and the aggregate fiber count of the switch package are reduced by, for example, 1 / N. N light beams from at least one multi-core optical fiber are deflected by mirror facets in the pluggable optical connector and directed to a lens array or an array of lens arrays in lens array chip 1 and lens array chip 2. A single lens as part of a lens array is arranged to match the pattern of multiple cores inside the multi-core optical fiber. After passing through the lens array chip 2, the light from each core is directed to a separate grating coupler in the EPIC chip.

[0034] Another exemplary embodiment of the present invention relates to a switch system having optical input and output interfaces and electrical switch functionality and may include one or more of the following features:

[0035] • One (or more) switch ASICs with an array of one (or more) optical transceiver components.

[0036] • Co-packaging on high-speed substrates with a ball grid array or land grid array on the bottom.

[0037] · RF high-speed lines between the switch ASIC and the transceiver components are routed within the high-speed substrate.

[0038] • DC and controls are connected to the mainboard via a ball grid array or land grid array interface.

[0039] • The switch ASIC is soldered on the top surface of the high-speed substrate in a flip-chip configuration.

[0040] The electrical interfaces on the transceiver chip are routed through through-silicon vias (TSVs) to metal pads on the bottom surface of the transceiver chip.

[0041] The lens array chip 2 is placed on top of the transceiver chip.

[0042] • The optical fiber array is mounted inside the pluggable optical connector and extends horizontally away from the transceiver assembly.

[0043] Pluggable optical connector.

[0044] • The transceiver assembly can be reflow soldered to contact the electrical interface when the pluggable optical connector is unplugged.

[0045] • Pluggable optical connectors and transceiver sockets are primarily composed of silicon. The preferred materials for the stacked sheets are bulk silicon, silicon-on-insulator (SOI), or SiO2 glass.

[0046] • One or more heat sinks are mounted on the transceiver assembly to hold the pluggable optical connector in place and dissipate heat.

[0047] The laser radiation is supplied to the transceiver assembly by an additional optical fiber in a pluggable optical connector.

[0048] The input interface for external laser radiation into the transceiver chip is polarization-independent.

[0049] The optical coupling element is a grating coupler in the transceiver chip that receives the laser light at an angle of 3°-25° relative to the surface of the transceiver chip.

[0050] The optical coupling element in the transceiver chip is a grating coupler.

[0051] • Demultiplexing / multiplexing functionality is integrated in pluggable optical connectors. This can be achieved by arrayed waveguide gratings implemented in planar photoconductive circuits using silicon, SOI or glass.

[0052] • Guide pins are used to align the pluggable optical connector to the transceiver receptacle in the horizontal plane and provide mechanical stability.

[0053] • The demultiplexing / multiplexing functionality of the pluggable optical connectors can also be integrated in the fiber optic assembly (separate from the stack of pluggable optical connectors).

[0054] High-speed electrical connections are differential lines.

[0055] Wavelength Division Multiplexing (WDM), Time Division Multiplexing (TDM) and Polarization Division Multiplexing (PDM) can be used for multiplexing. WDM, TDM and PDM are not mutually exclusive.

[0056] One or several switch ASICs (silicon chips) with high aggregate data throughput (data rate), e.g. 51.2 Tbit / s

[0057] A switch ASIC is an electrical switch with electrical input and output interfaces

[0058] For example, 512 transmitter output channels and 512 receiver output channels

[0059] For example, the net data rate per channel is 100 Gbit / s using the PAM-4 modulation format.

[0060] • One or more heat sinks are part of the switch co-package and dissipate heat from the switch co-package.

[0061] Multi-core optical fiber is used to combine multiple transmission channels in one optical fiber.

[0062] • Ability to implement different modulation formats in the transceiver components, such as NRZ, PAM-N, especially PAM-4, QPSK or DP-QPSK.

[0063] Many electrical input signals are combined into one optical fiber with the help of Nyquist pulses. The modulation sidebands of one Nyquist channel are arranged in time so that the center of each transmitted symbol is located at the intersection of the other Nyquist channels. On the receiver side, a local oscillator is used in combination with a balanced receiver system to retrieve each Nyquist channel.

[0064] Further exemplary embodiments of the present invention relate to:

[0065] 1) An arrangement comprising one or more transceiver components that convert electrical high-speed data signals from one or more switch ASICs into optical high-speed data signals and couple these optical signals into optical waveguides (e.g., optical fibers) and vice versa. The transceiver components may include a layer system. The layer system may include one or more of the following features:

[0066] o The optical transceiver chip is preferably implemented as an electronic photonic integrated circuit (EPIC) comprising TSVs with pads on the bottom surface of the EPIC chip as an electrical interface and grating couplers on the top surface of the EPIC chip as an optical interface to other layers of the transceiver components.

[0067] o beam forming layers, which may contain lenses or lens arrays etched into the layer material,

[0068] o pluggable interface including mechanical guide pins inside the layer assembly,

[0069] o optical imaging designed so that the light beam is expanded and collimated to achieve loose alignment tolerances between the pluggable optical connector and the transceiver receptacle,

[0070] οFiber interface layer in pluggable optical connectors: V-shaped grooves are used to align and fix the optical fiber; anisotropically etched mirror facets reflect the light beam toward the transceiver chip.

[0071] The arrangement and / or layer system preferably comprises one or more of the following features:

[0072] - All layers of the transceiver assembly are preferably based on a silicon substrate as base material. This results in the same thermal expansion coefficient and high thermal conductivity. Both are advantageous due to high power dissipation in the EPIC and high temperatures in the switch co-package,

[0073] - the transceiver assembly is preferably soldered to a high-speed substrate,

[0074] - pluggable optical connectors facilitate the lower part of the transceiver assembly, i.e. the transceiver socket, to be solderable (the optical fiber in the pluggable optical connector is not resistant to soldering temperatures),

[0075] - For example, 32 transmitter and 32 receiver input and output channels per transceiver component,

[0076] - The transceiver assembly preferably has an external laser input via a fiber optic interface

[0077] o The external laser input is preferably polarization independent through a special arrangement in the EPIC transceiver chip.

[0078] and / or

[0079] 2) A fiber optic cable assembly containing a fiber optic bundle that optically connects the pluggable optical connector of the transceiver assembly to the outside world, such as through a connector in the housing of a network switch system.

[0080] In a parallel arrangement, the fiber optic cable assembly preferably contains 72 optical fibers. On the side connected to the pluggable optical connector, all optical fibers are arranged in a row. The optical fibers of the cable have a diameter of, for example, 80 μm and are fixed in the pluggable optical connector at a spacing of, for example, 82 μm. On the side connected to the fiber optic cable, the fiber bundles in the cable are arranged in, for example, 4 rows and 18 columns. This helps to provide a reasonable bending radius on both axes. On the side connected to the front panel of the network switch system, the four lines of the cable are divided into four fan-out cables terminated by, for example, 4 connectors in the housing of the network switch system. Each of the four fan-out cables transmits an 800Gbit / s optical data stream and additionally light from one or several external lasers (in 2 of the 18 optical fibers) to a connector in the housing of the network switch system.

[0081] Another exemplary embodiment of the present invention is directed to a switch system in which 16 transceiver tiles are arranged on four sides of an ASIC chip, four on each side to handle incoming and outgoing data traffic.

[0082] An optical transceiver has optical input and output interfaces and electrical input and output interfaces and may include one or more of the following features:

[0083] • One (or more) switch ASICs with an array of one (or more) optical transceiver components.

[0084] • The optical transceiver assembly is located on a main high-speed substrate that is mechanically and electrically connected to the high-speed substrate that carries the ASIC chip.

[0085] The optical transceiver chip is located next to the digital signal processing chip on the same main high-speed substrate.

[0086] • The main high-speed substrate is connected to the high-speed substrate carrying the ASIC via a ball grid array or land grid array interface.

[0087] The main high-speed substrate including the optical transceiver package ("tile") has a width of 7-10 mm and a length of 20-40 mm

[0088] The transceiver chip possesses one or more (e.g., all) of the following features:

[0089] Modulator Driver and Modulator,

[0090] Photodetectors and transimpedance amplifiers

[0091] Light monitoring and control functionality,

[0092] SPI or I to the DSP chip, to the external laser source, to the host board and / or to the central communication unit 2 C communication.

[0093] The transceiver chip includes one or more (e.g. all) of the typical monitoring and diagnostic functionalities, which are:

[0094] - Loopback on line and network side.

[0095] -Connection to DSP according to IEEE Standard 1149.1.

[0096] - Detect and signal a LOS event at the receiver optical input.

[0097] -Monitor the average power and frequency response of the optical signal and modulator output.

[0098] - Check the lock status of the DSP on both the transmitter and receiver.

[0099] - Internal voltage monitor.

[0100] -Internal temperature sensor.

[0101] - Generation of interrupt signals.

[0102] • The pluggable optical connector is implemented with two separate structures of alignment features, one structure for coarse alignment and the other structure for fine alignment.

[0103] • Fine alignment features are implemented in the silicon layer stack. Coarse alignment features are implemented by structures in the housing of the transceiver chip and the package around the optical connector.

[0104] Two fine alignment features of the pluggable optical connector include self-alignment features. Such a self-alignment feature can be a pocket in the surface of the chip that holds the ball so that half of the ball is a recess.

[0105] • A fiber ribbon or array is permanently attached to the transceiver package ("pigtail").

[0106] Fiber arrays or ribbons extend horizontally from the transceiver package

[0107] • The optical fiber array or optical fiber ribbon has a pitch between 80 μm and 255 μm.

[0108] • Wavelength division multiplexing is achieved by discrete optical components like membrane filters to selectively pass wavelengths into different channels.

[0109] • Wavelength division multiplexing is achieved by planar photoconductor circuits (PLC) to selectively transfer wavelengths into different channels.

[0110] Wavelength division multiplexing is implemented in the fiber optic connection from the transceiver chip to the front panel of the device.

[0111] The fiber array terminates at the front panel of the switch device.

[0112] The fiber array consists of two different fiber ribbons, one for input and output traffic and the other for external lasers that provide laser light to the transceiver chip.

[0113] The fiber connection between the external laser source and the transceiver chip is realized by polarization-maintaining (PM) fiber.

[0114] The transceiver package has two different fiber connections, one connected to the signal stream and the other connected to the external laser source.

[0115] The functional building blocks of the transmitter and the functional building blocks of the receiver are organized to form rectangular sub-units. The sub-units are then patterned linearly or two-dimensionally onto the transceiver chip. This allows for a very modular design of the chip.

[0116] Preferably, an equal and even number of optical transceiver assemblies are arranged on each side in the plane of the switch ASIC, and each group of optical transceiver assemblies on each side is electrically and mechanically connected to a common second high-speed substrate. The electrical and mechanical connections of each of the second high-speed substrates to the high-speed substrate are implemented by a flexible high-speed substrate. This arrangement reduces the overall size of the high-speed substrate and thus helps to relax the mechanical stress caused on the corresponding substrate due to the placement and related thermal expansion of the connection to the host board or heat sink. In addition, the high-speed substrate carrying the switch ASIC and the corresponding second high-speed substrate carrying the transceiver assembly are more effectively thermally decoupled from each other, thereby reducing the temperature of the transceiver assembly. The flexible high-speed substrate is preferably implemented as a flexible flat cable.

[0117] When a digital signal processing chip (DSP) is located next to a transceiver chip on the same main high-speed substrate, the distance from the DSP to the switch ASIC is preferably less than the distance from the transceiver chip to the switch ASIC in order to reduce the thermal impact of the switch ASIC on the transceiver chip, and this achieves lower temperatures in the transceiver chip. Another advantage is that the electrical connection length between the switch ASIC and the DSP is shorter in order to improve signal integrity.

[0118] Each of the features mentioned above in context with any exemplary embodiment or variant can be combined with any other feature of the same exemplary embodiment or variant. In addition, each of the features mentioned above in context with any exemplary embodiment or variant can be combined with any other feature of any other exemplary embodiment or any other variant. BRIEF DESCRIPTION OF THE DRAWINGS

[0119] In order to easily understand the manner in which the above and other advantages of the present invention are obtained, specific embodiments of the present invention are illustrated in the accompanying drawings. Figure 1-16 The drawings depict only typical embodiments of the invention by way of illustration and therefore should not be considered limiting its scope.

[0120] exist Figure 1-16 In the drawings, the reference numerals refer to the following elements:

[0121] 1: Optical transceiver chip (2 layers)

[0122] 2: Main high-speed substrate

[0123] 3: Digital signal processing chip

[0124] 4: Rough alignment feature (feed hole)

[0125] 5: Rough alignment feature (guide pins)

[0126] 6: Fine alignment features (feed holes)

[0127] 7: Fine alignment features (guide pins)

[0128] 8: Fiber optic mounting parts

[0129] 9: Radiator

[0130] 10: Optical fiber ribbon

[0131] 11: Ball grid array (between the optical transceiver chip and the main high-speed substrate)

[0132] 12: Ball grid array (on the bottom of the high-speed substrate)

[0133] 13: Lens on the optical transceiver chip

[0134] 14: Transceiver components

[0135] 15: Wavelength Multiplexer

[0136] 16: Second optical fiber ribbon

[0137] 17: Connector for input and output signals (to be connected at the front panel)

[0138] 18: Polarization-maintaining optical fiber ribbon (for laser radiation)

[0139] 19: Connector for input of external laser source

[0140] 20a: Guide pin

[0141] 20b: Through hole

[0142] 21: Anti-reflective coating

[0143] 22: Thermal interface materials

[0144] 23: Pluggable optical connector

[0145] 24: Switch motherboard

[0146] 25: Transceiver socket

[0147] 26: Mirror Facets

[0148] 27: UV curing adhesive

[0149] 28: Layer stack with transceiver chip

[0150] 29: Switch ASIC (Application Specific Integrated Circuit)

[0151] 30: Second high-speed substrate

[0152] 31: Spherical top transfer mold

[0153] 32: Lenses in optical connectors

[0154] 33: Cover for fiber optic mounting

[0155] 34: High speed substrate

[0156] 35: Front panel

[0157] 36: Flexible high-speed substrate

[0158] 37: Lens array chip 1

[0159] 38: Lens array chip 2

[0160] 39: Transceiver assembly transfer mold DETAILED DESCRIPTION

[0161] In an exemplary embodiment of the present invention, the transceiver chip 1 is connected via a ball grid array 11 (see, for example, Fig.12 and Fig.13 ) is mounted on the main high-speed substrate 2. Next to the transceiver chip 1, the digital signal processing chip 3 is mounted on the same main high-speed substrate 2. The main high-speed substrate 2 is connected to the high-speed substrate 34 via the second ball grid array 12 (see Fig.10 ). High speed substrate 34 (see Fig.10 ) also carries the switch ASIC 29.

[0162] Fig.12 The upper part of the optical connector is formed, and the optical connector includes a fiber mounting part 8, which holds the optical fiber ribbon 10, a rough alignment feature (shown here as a guide pin 5) and a fine alignment feature (shown here as a guide pin 7). Their counterparts are the feed holes 4 that provide the rough alignment feature in the housing of the transceiver chip 1 and the digital signal processing chip 3, and the feed holes 6 that provide the fine alignment feature in the layer stack of the transceiver chip 1.

[0163] Fig.12 The bottom of the optical connector - i.e., the transceiver chip 1, the digital signal processing chip 3, the housing of the transceiver chip 1 and the digital signal processing chip 3, and the main high-speed substrate 2 - forms a socket that is configured to receive the coarse alignment features (guide pins 5) and fine alignment features (guide pins 7) of the upper optical connector.

[0164] The feed hole 4 can be as follows Fig.13 Shown extending into the main high-speed substrate 2.

[0165] Fig.13 Also depicted is a lens 13 for beam shaping located on the top surface of the transceiver chip 1. Alternatively, the lens 13 for beam shaping may be as shown in FIG. Figure 1 and Figure 2 It is shown in the housing of the transceiver chip 1. Figure 1 and Figure 2 Another exemplary embodiment of a pluggable optical connector 23 and a receptacle 25 is depicted.

[0166] exist Figure 1 and Figure 2 In the embodiment of FIG. 1 , the transceiver chip 1 is mounted directly on a high-speed substrate 34 that also carries the switch ASIC 29 .

[0167] The switch ASIC 29 is preferably connected to a plurality of optical transceiver assemblies 14, preferably four optical transceiver assemblies 14 as shown. Each transceiver assembly 14 preferably includes one transceiver chip 1, a main high-speed substrate 2, a set of coarse and fine alignment features on the sockets 5 and 7, respectively, and on the socket sides 4 and 6, respectively, a DSP chip 3, and a fiber optic mount 8 to which a fiber optic ribbon 10 is permanently attached.

[0168] In the case of n (n>1) optical transceiver assemblies 14, the transceiver assemblies 14 are preferably arranged according to a rotational symmetry of order n relative to the switch ASIC 29, also referred to as n-fold rotational symmetry or n-th order discrete rotational symmetry. In the case of sixteen optical transceiver assemblies 14, the optical transceiver assemblies 14 are preferably arranged according to a four-fold rotational symmetry as shown (see, e.g. Fig.10 ).

[0169] In the above drawings and description, multiple embodiments of the present invention are disclosed. The applicant would like to emphasize that each feature of each embodiment can be combined with or added to any other embodiment in order to modify the corresponding embodiment and create additional embodiments. These additional embodiments form part of the present disclosure, and therefore, the applicant can submit additional patent claims for these additional embodiments at a later stage of the examination.

[0170] In addition, the applicant would like to emphasize that each feature of each of the following dependent claims can be combined with any of the present independent claims and with any other (one or more) dependent claims in the present dependent claims (regardless of the present claim structure). Therefore, the applicant can direct additional patent claims to other claim combinations at a later stage of the examination.

Claims

1. A switch system, comprising: an optical transceiver assembly connected to a switch ASIC, The digital signal processing chip of the optical transceiver assembly is located next to the transceiver chip on the main high-speed substrate. wherein the primary high-speed substrate is electrically and mechanically connected to a second high-speed substrate; wherein the switch ASIC is electrically and mechanically connected to the second high-speed substrate; Wherein, the distance from the digital signal processing chip to the switch ASIC is shorter than the distance from the transceiver chip to the switch ASIC; wherein the pluggable optical connector of the optical transceiver assembly comprises a first heat sink, wherein the first heat sink is integral with the pluggable optical connector and is movable together with the pluggable optical connector; wherein the heat sink comprises an overlapping portion, wherein when the pluggable optical connector is inserted, the overlapping portion overlaps both the digital signal processing chip and the transceiver chip; Wherein, when the pluggable optical connector is plugged into a transceiver socket, the digital signal processing chip and the transceiver chip are sandwiched between the first heat sink of the pluggable optical connector and the main high-speed substrate.

2. The switch system according to claim 1, wherein: The switch ASIC exchanges electrical signals, wherein the optical transceiver assembly comprises a layer stack, and Wherein, the layer stack comprises the following: The transceiver chip, a plurality of beam forming layers, wherein each layer of the plurality of beam forming layers comprises a lens or lens array etched into the layer material and configured to form a beam, A pluggable optical interface comprising mechanical guide pins within the layer stack, and An optical imaging system that expands and collimates the light beam.

3. The switch system according to claim 2, in, The digital signal processing chip is located between the switch ASIC and the transceiver chip, and Wherein, the transceiver chip is located between the digital signal processing chip and the optical fiber ribbon.

4. The switch system according to claim 1, wherein: A second heat sink is located on top of the transceiver assembly.

5. The switch system according to claim 4, wherein: When the pluggable optical connector is plugged into the transceiver socket, the first heat sink is located above both the digital signal processing chip and the transceiver chip.

6. The switch system according to claim 4, wherein: The first heat sink is configured to hold the pluggable optical connector in place and dissipate heat.

7. The switch system according to claim 1, wherein: The pluggable optical connector includes a stack of silicon chips that are configured such that heat can be dissipated very efficiently from the transceiver chip.

8. The switch system according to claim 1, wherein: The switch ASIC is configured to switch electrical signals.

9. The switch system according to claim 1, wherein: The main high-speed substrate is electrically and mechanically connected to the second high-speed substrate via a ball grid array or a land grid array on the bottom of the main high-speed substrate.

10. The switch system according to claim 1, wherein: The main high-speed substrate is rectangular and has a size in the range of 7-10 mm by 20-40 mm.

11. The switch system according to claim 1, wherein: The optical transceiver assembly includes eight optical transceiver assemblies, and four optical transceiver assemblies are arranged on each side of the switch ASIC and are located in the same plane as the switch ASIC.

12. The switch system according to claim 1, wherein: The optical transceiver assembly includes one alignment feature for coarse alignment and a second alignment feature for fine alignment.

13. The switch system according to claim 12, wherein: The second alignment feature is implemented in a layer stack of one or both of the pluggable optical connector and the transceiver receptacle.

14. The switch system according to claim 1, wherein: The main high-speed substrate is a circuit board.

15. The switch system according to claim 1, wherein: The pluggable optical connector comprises silicon.

16. The switch system according to claim 1, wherein: The first heat sink of the pluggable optical connector includes silicon.

17. A switch system, comprising: Optical transceiver components, wherein the optical transceiver assembly is connected to a switch ASIC, wherein the switch ASIC exchanges electrical signals; wherein the optical transceiver assembly comprises a layer stack; and Wherein, the layer stack comprises: Transceiver chip, beam forming layers, each layer of which comprises a lens or array of lenses etched into the layer material and configured to form a beam, A pluggable optical interface comprising mechanical guide pins, and an optical imaging system for expanding and collimating the light beam; The digital signal processing chip of the optical transceiver assembly is located next to the transceiver chip on the main high-speed substrate. wherein the primary high-speed substrate is electrically and mechanically connected to a second high-speed substrate; wherein the switch ASIC is electrically and mechanically connected to the second high-speed substrate; Wherein, the distance from the digital signal processing chip to the switch ASIC is shorter than the distance from the transceiver chip to the switch ASIC; wherein the pluggable optical connector of the optical transceiver assembly comprises a first heat sink, wherein the first heat sink is integral with the pluggable optical connector and is movable together with the pluggable optical connector; and wherein the heat sink comprises an overlapping portion, and when the pluggable optical connector is inserted, the overlapping portion overlaps both the digital signal processing chip and the transceiver chip; Wherein, when the pluggable optical connector is plugged into a transceiver socket, the digital signal processing chip and the transceiver chip are sandwiched between the first heat sink of the pluggable optical connector and the main high-speed substrate.

18. The switch system according to claim 17, wherein: The digital signal processing chip is located between the switch ASIC and the transceiver chip, and Wherein, the transceiver chip is located between the digital signal processing chip and the optical fiber ribbon.

19. The switch system according to claim 17, wherein: A second heat sink is located on top of the transceiver assembly.

20. The switch system according to claim 19, wherein: When the pluggable optical connector is plugged into the transceiver socket, the first heat sink is located above both the digital signal processing chip and the transceiver chip.

21. The switch system according to claim 19, wherein: The first heat sink is configured to hold the pluggable optical connector in place and dissipate heat.

22. The switch system according to claim 17, wherein: The pluggable optical connector includes a stack of silicon chips that are configured such that heat can be dissipated very efficiently from the transceiver chip.

23. The switch system according to claim 17, wherein: The main high-speed substrate is electrically and mechanically connected to the second high-speed substrate via a ball grid array or a land grid array on the bottom of the main high-speed substrate.

24. The switch system according to claim 17, wherein: The optical transceiver assembly includes eight optical transceiver assemblies, and four optical transceiver assemblies are arranged on each side of the switch ASIC and are located in the same plane as the switch ASIC.

25. The switch system according to claim 24, wherein: The optical transceiver assembly includes one alignment feature for coarse alignment and a second alignment feature for fine alignment.

26. The switch system according to claim 17, wherein: The main high-speed substrate is a circuit board.

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