Ultra-low power consumption multichannel high-speed signal synchronous acquisition and emission system suitable for satellite communication

Abstract

The invention relates to an ultra-low power consumption multichannel high-speed signal synchronous acquisition and emission system suitable for satellite communication. The system comprises an acquisition and emission board card which mainly comprises a plurality of radio frequency transceivers, an optical module, a clock unit, an FPGA (Field Programmable Gate Array) 1 processor and the like; the clock unit comprises a clock chip, a clock Buffer and the like; the optical module is used for receiving data, sending the data to an FPGA (Field Programmable Gate Array) 1 for processing, then sending the data to a transmitting channel of the radio frequency transceiver through a JESD204B interface for interpolation filtering, QEC (Quadrature Error Correction) calibration and refreshing, and then performing up-conversion to output an I / Q analog modulation signal; a receiving channel of the radio frequency transceiver receives an I / Q analog signal, the I / Q analog signal is sampled after low-pass filtering, the sampled data is sent to the FPGA1 for processing through the JESD204B interface after QEC calibration, and then the data is forwarded through the optical module. The system can realize ultra-low power consumption and reduce the weight of the whole machine.

Description

Technical Field

[0001] The present application relates to the field of satellite communication technology, and in particular to an ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system suitable for satellite communication. Background Art

[0002] With the advent of the digital age, people's demand for communication has shown a concentrated explosive growth. From the initial voice calls to today's high-definition video, virtual reality (VR), intelligent driving and other application scenarios with extremely high requirements for network communication. Traditional ground communication networks are facing unprecedented challenges. Ground communication networks mainly rely on multiple ground base stations for regional signal coverage, but in remote mountainous areas, vast oceans, deserts and other areas with complex geographical environments or sparse populations, laying base stations is not only extremely difficult to build, but also costly, and it is difficult to achieve comprehensive and effective coverage. At the same time, with the advent of the era of the Internet of Everything, a large number of devices need to access the network, causing the number of connections to grow exponentially, and the access capacity of traditional networks is gradually stretched. Moreover, in high-speed mobile scenarios such as high-speed rail and airplanes, traditional networks are also difficult to perfectly meet users' demand for high-speed and stable switching of the network. Against this background, satellite communication has gradually entered the public's field of vision. It combines the high-speed, low-latency, and large-connection characteristics of mobile Internet with the wide coverage advantages of satellite communication. Using satellites in different orbits such as geosynchronous orbit satellites, medium and low orbit satellites to form a constellation, global communication signal coverage without dead ends is achieved. Whether it is a scientific expedition team in a remote area, a ship sailing on the ocean, or an explorer in the mountains and forests, they can all enjoy smooth network services with the help of satellite communications, truly breaking the geographical restrictions. Satellite communications have outlined a new blueprint for the future development of communications, which is expected to reshape the global communications landscape and promote leapfrog development in various industries. In the future, the field of satellite communications will also develop in the direction of multiple-input multiple-output systems (MIMO), modularization, and high data throughput, and realize multi-channel signal reception and transmission by using multiple transmitting and receiving antenna arrays respectively. Based on this, multi-channel RF transmission and reception synchronization technology has become one of the key technical indicators for the realization of the system, but in practice, due to the differences between the receiving or transmitting channels, it is easy to produce aperture effects, resulting in problems such as beam gain attenuation and deviation from the expected direction path.

[0003] At the same time, considering that aerospace products such as satellites have extremely strict requirements on weight and power consumption, in the field of medium and low orbit satellite communications, multi-input and output systems are limited by power consumption, weight and structural size, and modular design is often used in design. Each module receives and sends RF signals through the same antenna array. In the field of communications, conventional solutions can process signals through RF direct acquisition architecture, but this implementation idea has strict requirements on the sampling rate, power bandwidth and other indicators of ADC and DAC. Even if the RF signal is processed through up and down conversion modules, the performance index requirements of ADC and DAC devices in the baseband data processing part can be effectively reduced, but at the same time, the weight and power consumption of the whole machine will be increased, which is not conducive to the light weight and ultra-low power consumption characteristics of satellite communications. Considering that when multiple antenna arrays are working at the same time, the power-on cycle and clock lock time difference between each board are also key factors restricting synchronization performance. Summary of the invention

[0004] Based on this, it is necessary to provide an ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system suitable for satellite communications that can achieve ultra-low power consumption and reduce the weight of the entire machine in response to the above technical problems.

[0005] An ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system suitable for satellite communication, the system comprises an acquisition and transmission board; the acquisition and transmission board comprises multiple radio frequency transceivers, an optical module, a clock unit and FPGA1; the clock unit comprises a clock chip and a clock buffer; The optical module is used to receive data and send it to FPGA1 for processing to generate I / Q digital signals, which are then sent to the transmitting channel of the RF transceiver through the JESD204B interface for QEC calibration, interpolation filtering, and refresh before up-conversion and output of I / Q modulated signals. The receiving channel of the RF transceiver receives the I / Q analog signal, performs low-pass filtering, sampling and extraction, performs QEC calibration on the sampled data, and sends it to FPGA1 for processing through the JESD204B interface, and then forwards the data through the optical module; The RF transceiver uses a single clock chip to perform VCO multiplication and then frequency division output. The RF transceiver's transmit and receive local oscillator receives the two-channel clock output by the clock chip and then passes through the two clock buffers in the later stage to each RF transceiver as the input clock of the transmit and receive local oscillator. The RF transceiver's transmit and receive local oscillator has its own PLL to multiply the frequency to the corresponding frequency point to shift the signal. At the same time, the GT Bank data processing clock of FPGA1 receives two clock signals and divides them into four through two clock buffers, and then gives them to the GT bank corresponding to each JSED204B interface to realize synchronous transmission and reception of digital signals.

[0006] The above-mentioned ultra-low power multi-channel high-speed signal synchronous acquisition and transmission system is suitable for satellite communication. This application uses the JESD204B interface of the RF transceiver to achieve the synchronization performance of the receiving and transmitting channels within the board, and receives the external homologous clock to achieve synchronization between the boards, solving the impact of the power-on cycle difference and clock skew of each board. The selected single-chip RF transceiver has 8 transceiver channels, and the up and down conversion modules are integrated internally. The power consumption of the RF transceiver is greatly reduced by reducing the sampling rate after the down-conversion processing at the receiving end and reducing the channel data rate by interpolation filtering at the output end. 4 chips can form 32 transceiver RF channels, which reduces the design complexity of the clock tree and is easier to implement, and also reduces the weight of the whole machine. In addition, at the receiving end, the sampling rate is reduced by down-conversion processing; at the output end, the channel data rate is reduced by interpolation filtering. This series of operations greatly reduces the power consumption. At the same time, a first-level clock tree architecture is adopted, and a single clock chip performs VCO multiplication and frequency division output. Compared with the multi-level clock tree architecture, this architecture avoids the phase ambiguity or frequency deviation problems caused by the internal phase detector of the multi-level clock chip, and simplifies the design. At the same time, it reduces the number of clock chips used, reduces the cost and power consumption, and receives the 2-channel clock output by the clock chip in the RF transceiver's transceiver local oscillator, and then gives it to each RF transceiver as the input clock of the transceiver local oscillator through the 2 clock buffers in the later stage; the GT Bank data processing clock of FPGA1 receives the 2-channel clock signal and divides it into four through the 2 clock buffers, and then gives it to the FPGA1 GT Bank corresponding to each JSED204B interface. Through this clock distribution method, the synchronous acquisition and transmission of signals is guaranteed, while unnecessary clock lines and buffer devices are reduced, and power consumption and weight are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of a framework of an ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system suitable for satellite communication in one embodiment; Figure 2 is a schematic diagram of a clock unit in one embodiment; Figure 3 The present invention is a flow chart of an implementation method of an ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system applicable to satellite communications in one embodiment. DETAILED DESCRIPTION

[0008] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0009] In one embodiment, Figure 1As shown, an ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system suitable for satellite communication is provided, including an acquisition and transmission board; the acquisition and transmission board includes multiple RF transceivers, optical modules, clock units and FPGA1; the clock unit includes a clock chip and a clock buffer.

[0010] The optical module is used to receive data and send it to FPGA1 for processing to generate I / Q digital signals, which are then sent to the transmit channel of the RF transceiver through the JESD204B interface for QEC calibration. After that, the data is interpolated and filtered, refreshed, and up-converted to output I / Q modulated signals.

[0011] The receiving channel of the RF transceiver receives the I / Q analog signal for low-pass filtering, sampling and extraction, and performs QEC calibration on the sampled data, and then sends it to FPGA1 for processing through the JESD204B interface, and then forwards the data through the optical module.

[0012] The RF transceiver uses a single clock chip to perform VCO multiplication and then frequency division output. The RF transceiver's transmit and receive local oscillator receives the two-channel clock output by the clock chip and then passes through the two clock buffers in the later stage to each RF transceiver as the input clock of the transmit and receive local oscillator. The RF transceiver's transmit and receive local oscillator has its own PLL to multiply the frequency to the corresponding frequency point to shift the signal. At the same time, the GT Bank data processing clock of FPGA1 receives two clock signals and divides them into four through two clock buffers, and then gives them to the GT bank corresponding to each JSED204B interface to realize synchronous transmission and reception of digital signals.

[0013] The above is applicable to satellite communication ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system, such as Figure 1 As shown in the figure, a single acquisition and transmission board has 4 RF transceivers to form 32 parallel IF signal acquisition channels and 32 parallel IF signal transmission channels. Each acquisition and transmission board has an 8-transmitter 8-receiver, single-channel transmission rate of 10Gbps transceiver integrated optical module, which is used to forward the data that needs to be sampled by the RF transceiver and receive the data that needs to be refreshed.

[0014] The receiving channel of the RF transceiver on the acquisition and transmission board receives the I / Q analog signal, samples it after low-pass filtering, performs QEC calibration on the sampled data, and then sends it to FPGA1 for processing through the JESD204B interface, and then forwards the data through the optical module.

[0015] The data received by the optical module of the acquisition and transmission board is sent to FPGA1 for processing to generate I / Q digital signals, and then sent to the transmission channel of the RF transceiver through the JESD204B interface for QEC calibration, interpolation filtering, refresh, and then up-conversion to output I / Q modulated signals.

[0016] The four RF transceivers on a single acquisition and transmission module board can be multiplied by a single clock chip and then divided for output. The two-channel clock output by the RF transceiver's transceiver local oscillator receiving clock chip is then given to each RF transceiver as the input clock of the transceiver local oscillator through the two clock buffers at the later stage. The RF transceiver's transceiver local oscillator has its own PLL that can multiply the frequency to the corresponding frequency point to move the signal. At the same time, the GT Bank data processing clock of FPGA1 receives two clock signals and is divided into four by two clock buffers and then given to the GT bank corresponding to each JSED204B interface.

[0017] The clock chip uses a clock chip with an internally integrated dual phase-locked loop architecture. The VCO multiplies the frequency to the required clock and then distributes it to the RF transceiver. The first-stage phase-locked loop has an extremely narrow loop bandwidth, which is used to remove clock jitter and suppress the high-frequency phase noise of the input clock. The working loop of PLL2 is wider, which is used to fan out high-frequency clocks and improve far-end phase noise. The SYNC pin of the clock chip is connected to FPGA0 to trigger the clock chip output clock for phase synchronization after power-on stabilization, and can also be triggered through the SPI interface of the clock chip; when multiple acquisition and transmission boards are synchronized between boards, the system external control unit needs to give each FPGA0 a trigger signal to trigger the phase synchronization of each transceiver channel.

[0018] like Figure 2 As shown in the figure, the clock unit is composed of a single clock chip plus four clock buffers. The clock chip outputs four master clocks and four auxiliary clocks as the device clocks and reference clocks of the RF transceiver. At the same time, the clock chip outputs two master clocks and two auxiliary clocks. Each clock passes through a clock buffer and is given to each GT Bank of FPGA1 or the local oscillator input interface of each RF transceiver. Finally, the clock chip outputs one master clock and one auxiliary clock to the JESD204B IP core of FPGA1 for use. The SYNC pin and SPI interface of the clock chip are connected to FPGA0 to solve the phase ambiguity or frequency deviation problem caused by the clock output during the power-on process. The specific implementation measures of the clock unit are as follows: the system input differential clock 122.88MHz is sent to the CLKIN0 differential port of the first-level clock chip to enter PLL1 as the system master clock of the JESD204B clock network, and the clock channel is selected through the switch inside the chip. A 128.88MHz voltage-controlled temperature-compensated crystal oscillator (VC-TCXO) single-ended output is selected and connected to OSC_INP as the input of the clock local oscillator receiving module. At the same time, the voltage-controlled pin VC of the VC-TCXO is connected to the CP_OUT pin of PLL1. By adjusting the voltage-controlled voltage, the frequency deviation of the temperature-compensated crystal oscillator output clock in the full temperature range is adjusted to calibrate the clock and improve the phase noise capability.

[0019] In this implementation scheme, each acquisition and transmission board contains 4 RF transceivers, each of which has 8 receiving channels and 8 transmitting channels. The receiving channel ADC can receive I / Q analog signals and send them to FPGA1 for processing after low-pass filtering, sampling, DC calibration and QEC calibration. When the amount of data exceeds the upper limit of the JESD204B LANE rate, the LANE rate can be reduced by the internal extraction filter. The transmitting channel receives the I / Q digital signal processed by FPGA1, QEC calibration, and data refresh to output the I / Q modulated signal. At the same time, the internal interpolation filter can further reduce the number or rate of LANE usage of the JESD204B link, thereby reducing the power consumption of the RF transceiver. The 8 receiving channels of each RF transceiver receive analog signals for sampling and then encode, scramble, and serialize the data and send them to FPGA1 for processing. FPGA1 also receives optical module data, performs orthogonal modulation and other processing on the data, and then sends it to the 8 transmitting channels of each RF transceiver to perform QEC calibration, interpolation filtering, and refresh the digital signal before output.

[0020] The phase synchronization of the RF transceiver channel is achieved by dynamically compensating the phase difference of each channel and aligning the channel with its own elastic buffer by using a JESD204B interface protocol chip. Based on this, the present application provides a practical design idea, which can greatly reduce the power consumption of a single board while reducing the weight. At the same time, a simpler clock tree design is adopted to avoid the occasional phase ambiguity or phase offset caused by the discreteness of the internal phase detector and loop filter parameters of the clock chip due to the high complexity of the clock tree. Based on the premise of ultra-low power consumption, light weight and inter-board synchronization feasibility, the present application proposes to use the JESD204B interface of the RF transceiver to achieve the synchronization performance of the receiving and transmitting channels within the board, and at the same time receive the external homologous clock and trigger signal to achieve synchronization between the boards, solving the influence of the power-on cycle difference and clock skew of each board. The selected single-chip RF transceiver has 8 transceiver channels, and the up and down frequency conversion module is integrated internally. The sampling rate is reduced after the down-conversion processing at the receiving end and the channel data rate is reduced by interpolation filtering at the output end, thereby greatly reducing the system power consumption. 4 chips can form 32 RF channel transceivers, which reduces the design complexity of the clock tree and makes it easier to implement, and also reduces the weight of the whole machine. The technical indicators of the selected RF transceivers are analyzed, and the technical indicators of RF transceiver are further optimized without affecting the synchronization performance. Finally, the power consumption of a single RF transceiver channel can be as low as 0.3W. Compared with the RF direct acquisition architecture, the weight and power consumption of the whole machine have been greatly improved, which is very suitable for the field of satellite communications.

[0021] In one of the embodiments, the clock unit mainly includes a single clock chip and 4 clock buffers; the clock chip outputs 4 main clocks and 4 auxiliary clocks as the device clock and reference clock of the RF transceiver, and at the same time, the clock chip outputs 2 main clocks and 2 auxiliary clocks. Each clock passes through a clock buffer and is given to each GT Bank of FPGA1 or each RF transceiver local oscillator input interface. Finally, the clock chip outputs 1 main clock and 1 auxiliary clock to the JESD204B IP core of FPGA1 for use.

[0022] In one of the embodiments, the clock synchronization process of the receiving channel of the RF transceiver is as follows: the clock chip simultaneously provides the device clock DCLK and the accompanying reference clock SYSREF signal to the transmitting end of the receiving channel and the receiving end of FPGA1, and the device clock DCLK is divided to obtain the frame clock and the multi-frame clock LMFC, wherein the LMFC aligns the frame data by capturing the edge of the SYSREF signal; the SYSREF signal and the device clock must meet the timing requirements, and the edge of the SYSREF is captured by the falling edge or rising edge of the device clock to complete the leading edge alignment of the frame and LMFC, and the data in the elastic buffer is released with reference to the aligned LMFC edge.

[0023] In a specific embodiment, the SYSREF signal and the device clock must meet the timing requirements, and the edge of SYSREF is captured by the falling edge or rising edge of the device clock to complete the front edge alignment of the frame and LMFC, and the data in the elastic buffer is released with the aligned LMFC edge as a reference. Here, if the SYSREF signal and the device clock timing do not meet the setup and hold time requirements, the channel delay can be adjusted separately through the clock chip, with the minimum adjustment step accuracy of 1.5ps and the maximum adjustable range of 630ps.

[0024] In one of the embodiments, the code group synchronization process of the receiving channel of the RF transceiver is as follows: after the clock synchronization is completed, FPGA1 pulls down the SYNC_IN synchronization signals of multiple RF transceivers at the same time after performing an AND operation, and the device clock of the RF transceiver captures the synchronization signal and pulls it down, and then starts sending the K28.5 character after a delay of a period of time on the next LMFC clock edge; the FPGA1 receiving end uses clock recovery technology to parse out four consecutive K28.5s in the aligned data stream and then pulls up the synchronization signal, indicating that the CGS process synchronization is completed; the device clock of the RF transceiver transmitting end captures the synchronization signal and pulls it up, and stops sending the K28.5 character at the rising edge of LMFC, and the FPGA1 end will use the first non-K28.5 character detected as the start frame of the next frame to complete the frame synchronization operation.

[0025] In one embodiment, the initial channel synchronization process of the receiving channel of the RF transceiver is as follows: after CGS synchronization, the next step is to perform the initial channel synchronization process. The main function of ILAS is to align all receiving channels on the link, verify the link configuration parameters and determine the position of the frame and multi-frame boundaries in the data stream of the receiver. The ILAS sequence is sent at the next LMFC clock edge after the code group synchronization is completed. The sequence length of ILAS is composed of 4 multi-frames or more multi-frame lengths; the first, third and fourth multi-frames start with the character / R / and end with the character / A / , and the second multi-frame contains the character / R / and the character / Q / . The data after the character / Q / is the link configuration parameter. The FPGA1 receiving end compares the link configuration parameters in the second multi-frame sent by the transmitting end of the receiving channel. If they are consistent, it means that the link parameter verification has passed, and if they are wrong, the link establishment fails.

[0026] The transmitter will start sending user data after the last character / A / of the last ILAS multiframe is sent.

[0027] In one embodiment, the link alignment process of the receiving channel of the RF transceiver: the sending and receiving of the ILAS sequence has specific timing requirements, and the sending end of all receiving channels outputs ILAS multi-frame data based on the LMFC edge. Each chip is affected by factors such as different power-on cycle changes and PCB routing delays of each analog channel, resulting in differences in the time when the data of each channel arrives at the receiving end in different power-on cycles. After the receiving end of the receiving channel detects the / R / character, the data after the / R / character is stored in the elastic buffer to ensure that the last arrival time of the data of different channels is before the next LMFC clock edge arrives, and the data of all channels can complete the alignment operation and start data output, wherein the deterministic delay length cannot exceed one LMFC clock cycle, otherwise the phase relationship between the device clock and SYSREF is readjusted so that the SYSREF edge is within the valid clock window to meet the setup time and hold time requirements of the two. The receiving buffer delay directly determines the buffer depth, ranging from 1 to K frames (a multi-frame length) length, which is used to absorb the variable delay in the link. The more multi-frames, the greater the allowed variable delay.

[0028] In a specific embodiment, the multi-channel synchronous JESD204B link establishment process of the DAC unit of the transmitting channel of the RF transceiver is similar to that of the ADC unit of the receiving channel, and will not be described in detail.

[0029] In one of the embodiments, the phase consistency measurement between each receiving channel is performed by selecting one channel as the reference, and the remaining 31 channels are compared with the reference channel to calculate the phase difference. The excitation of the receiving channel uses an RF source to output a sine wave of known frequency, which is then input to each analog channel through a two-stage cascaded power divider and an RF cable of equal length. FPGA0 controls the link establishment process and data sampling process of the receiving channel through the data interface interacting with FPGA1 and exports a section of user data sampled in the FPGA1 Buffer to the host computer. The host computer tool performs FFT calculation on the sampled data and extracts the phase information of each channel to calculate the phase difference between the reference channel and the channel to be tested. In the early test, when it was found that there was occasional asynchronization between the phase difference between the channels during different power-on processes, the timing relationship between the clock and SYSREF signal of the corresponding RF transceiver device can be fine-tuned, and the minimum adjustable step is 1.5ps. After the adjustment is completed, the relevant registers of the clock chip are reconfigured, and the system is repeatedly powered on and off for stress testing to observe whether the phase difference between the channel to be tested and the reference channel is kept within the error range during different power-on processes to determine whether each receiving channel meets the synchronization requirements. In this implementation case, the phase difference of the 32 receiving channels measured by the host computer during different power-on processes is always within 1°, which has excellent synchronization performance. The step adjustment accuracy of 1.5ps can further optimize the synchronization performance.

[0030] The phase consistency measurement process of each transmitting channel is similar to that of the receiving channel. The transmitting channel performs QEC calibration, DC calibration, interpolation filtering, and refresh on the I / Q data sent by FPGA1, and then up-converts the output to obtain an intermediate frequency analog sinusoidal signal. One of the I channel and Q channel is selected as the reference to calculate the phase difference of other I channels and Q channels. The test method of the phase consistency of the analog signal can be carried out through a multi-channel high-speed oscilloscope or Labview instrument equipment, but conventional test equipment cannot complete 32 channel tests at one time. Due to the limitation of the measuring instrument channel, the channels to be tested need to be continuously replaced until all channels are polled and measured. This application performs loopback testing through 32 stable and synchronized receiving channels, which can greatly reduce the difficulty of the test work. The disadvantage is that the phase difference accuracy will be limited by the synchronization consistency index of the receiving channel. In this implementation case, the phase difference of the 32 transmitting channels is measured to be within 3° through the loopback of 32 stable and synchronized receiving channels. At the same time, the clock chip supports 1.5ps step accuracy to further improve the synchronization performance of the transmitting channel.

[0031] In one embodiment, a method for implementing an ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system applicable to satellite communication is as follows: Figure 3 shown.

[0032] For the traditional LVDS data interface, realizing multi-channel synchronization not only makes the PCB layout and routing complex, which increases the difficulty of FPGA data splicing or processing, but also has defects such as high power consumption and complex clock tree design compared to the RF direct acquisition architecture solution. This application uses a zero-IF architecture RF transceiver with a JESD204B synchronization protocol interface to design a 32-channel transceiver system. The elastic buffer of subclass 1 in the JESD204B protocol can effectively solve the problem of synchronous transmission of the receiving channel and the transmitting channel in a high-speed link, and uses a first-level clock tree architecture to distribute the JESD204B clock of each device to achieve the synchronization of receiving channel signal sampling and the phase synchronization of the transmitting channel signal output of multiple RF transceivers on the board, and the clock synchronization signal can be used to achieve inter-board synchronization between multiple boards, which can be applied to satellite communications, digital phased arrays and other fields.

[0033] The synchronization process is divided into two points. The first point is the synchronous sampling of data. Here, it mainly relies on the SYSREF generated by the dedicated clock chip to realize the synchronization of the sampling moments of multiple RF transceivers during the power-on and power-off process, that is, the synchronization of the sampling moment strongly depends on the edge alignment of the reference signal SYSREF given to each RF transceiver; the second point is the synchronous transmission and reception of data. The determinism and repeatability of the link delay are the guarantee for realizing link channel alignment, synchronizing internal frames and multi-frames, and aligning the local LMFC phase of the transmitter and receiver. Here, the elastic buffer provided by the JESD204B protocol can be used to realize the alignment operation of multi-channel data during transmission. The phase difference between channels is dynamically compensated by each power-on, which greatly reduces the strict equal length requirements of the high-speed interface differential pairs. In addition, the lower the frequency of the intermediate frequency carrier signal, the smaller the error introduced by cables, PCB routing, etc., and the better the synchronization performance. Based on this, this application adopts an RF transceiver with a zero intermediate frequency architecture, and moves the intermediate frequency carrier signal to zero frequency for processing through the internal local oscillator. In the absence of a carrier signal, the phase synchronization performance is better.

[0034] The first-level clock tree architecture is relatively easy to achieve intra-board synchronization, avoiding phase ambiguity or frequency deviation problems caused by internal phase detectors in multi-level clock chips. However, for application fields such as satellite communications and digital phased arrays, multiple modules are often required to work together, and the requirements for inter-board synchronization will gradually increase. Inter-board synchronization not only requires the same source working clock to be distributed to each single-board clock chip, but also requires a separate trigger signal to be given to the FPGA0 of each acquisition and transmission board to control FPGA1 to indicate the working status of each stage of the RF transceiver, and at the same time align the data transmission and reception time and export it to the host computer for phase calculation and analysis. Considering the consistency of each functional module, if multiple acquisition and transmission boards need to achieve inter-board signal transmission and reception synchronization, a separate clock board needs to be designed to achieve clock distribution. The clock chip of each acquisition and transmission board receives 1 working clock and 1 accompanying clock output by the clock board as input and SYNC synchronization trigger signal. The clock chip on the board uses the SYNC synchronous pulse trigger signal to ensure that the SYSREF signal given to each RF transceiver is strictly edge-aligned, and the edge of the SYSREF signal is captured by the DCLK clock to achieve sampling time alignment, and the frame and multi-frame clocks are aligned at the same time. The clock can be recovered at the receiving end to parse serial data. The SYSREF signal routing length of each device is strictly equal and is about 200mil longer than the DCLK routing length, ensuring that the establishment and hold time of the SYSREF signal is completed within one clock cycle of the DCLK. The slightly longer routing is mainly to meet the SYSREF hold time requirements. When the timing requirements are not met, it can be fine-tuned through the clock chip, with a step accuracy of 1.5ps and a maximum adjustable step of 630ps. The JESD204B interface elastic buffer performs multiple channel data alignment operations through the aligned LMFC, and the receiving end recovers and sequences the sampled data. In order to solve the phase ambiguity problem caused by the phase-locked loop (PLL) during different power-on cycles, the selected clock chip can support the external synchronization trigger signal SYNC or SPI trigger mechanism to ensure that the sampling time of each channel is aligned during different power-on processes. The routing delay of each clock fan-out channel can be adjusted independently to meet the sampling and holding time requirements of the RF transceiver and avoid timing criticality problems. This application realizes the design of a 32-transceiver integrated ultra-low power multi-channel phase synchronous data acquisition and transmission system.

[0035] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. An ultra-low power consumption multi-channel high-speed signal synchronous acquisition and transmission system suitable for satellite communication, characterized in that: The system includes an acquisition and transmission board; the acquisition and transmission board includes multiple RF transceivers, an optical module, a clock unit and FPGA1; the clock unit includes a clock chip and a clock buffer; The optical module is used to receive data and send it to FPGA1 for processing to generate I / Q digital signals, and then send it to the transmission channel of the RF transceiver through the JESD204B interface for QEC calibration, interpolation filtering, refreshing, and then up-conversion to output I / Q modulated signals; The receiving channel of the RF transceiver receives the I / Q analog signal, performs low-pass filtering, sampling and extraction, performs QEC calibration on the sampled data, and then sends it to FPGA1 for processing through the JESD204B interface, and then forwards the data through the optical module; The RF transceiver performs VCO multiplication and frequency division output through a single clock chip. The 2-channel follow-up clock output by the RF transceiver's transceiver local oscillator receiving clock chip is then given to each RF transceiver as the input clock of the transceiver local oscillator through 2 clock buffers at the subsequent stage. The transceiver local oscillator of the RF transceiver has its own PLL frequency multiplication to the corresponding frequency point to shift the signal. At the same time, the GT Bank data processing clock of the FPGA1 receives 2 clock signals and divides them into four through 2 clock buffers, and then gives them to the GT bank corresponding to each JSED204B interface to realize synchronous transmission and reception of digital signals.

2. The system according to claim 1, characterized in that The clock unit mainly includes a single clock chip and 4 clock buffers; the clock chip outputs 4 master clocks and 4 auxiliary clocks as the device clock and reference clock of the RF transceiver. At the same time, the clock chip outputs 2 master clocks and 2 auxiliary clocks. Each clock passes through a clock buffer and is given to each GT Bank of FPGA1 or each RF transceiver local oscillator input interface. Finally, the clock chip outputs 1 master clock and 1 auxiliary clock to the JESD204B IP core of FPGA1 for use.

3. The system according to claim 1, characterized in that The clock chip is a clock chip with an internally integrated dual phase-locked loop architecture. The VCO multiplies the frequency to the required clock and then distributes it to the RF transceiver. The first-stage phase-locked loop has an extremely narrow loop bandwidth, which is used to eliminate clock jitter and suppress the high-frequency phase noise of the input clock. The working loop of PLL2 is wider, which is used to fan out high-frequency clocks and improve far-end phase noise. The SYNC pin or SPI interface of the clock chip is connected to FPGA0 to trigger the clock chip output clock for phase synchronization after power-on stability. When multiple acquisition and transmission boards are synchronized between boards, the system external control unit needs to give each FPGA0 a trigger signal to trigger the phase synchronization of each transceiver channel.

4. The system according to claim 1, characterized in that The RF transceiver includes 8 receiving channels and 8 transmitting channels. The receiving channel ADC receives the I / Q analog signal, performs low-pass filtering and sampling, performs DC calibration and QEC calibration on it, and sends it to FPGA1 for processing. When the data volume exceeds the upper limit of the JESD204B LANE rate, the LANE rate is reduced through the internal extraction filter; the transmitting channel receives the I / Q digital signal processed by FPGA1, QEC calibration and data refresh, and then outputs the I / Q analog modulated signal.

5. The system according to claim 4, characterized in that The synchronization process of the receiving channel of the RF transceiver is as follows: the clock chip provides the device clock DCLK and the accompanying reference clock SYSREF signal to the transmitting end of the receiving channel and the receiving end of FPGA1 at the same time. The device clock DCLK is processed by frequency division to obtain the frame clock and the multi-frame clock LMFC, wherein the LMFC performs frame data alignment by capturing the edge of the SYSREF signal; the SYSREF signal and the device clock must meet the timing requirements, and the edge of the SYSREF is captured by the falling edge or rising edge of the device clock to complete the front edge alignment of the frame and LMFC, and the data in the elastic buffer is released with the aligned LMFC edge as a reference.

6. The system according to claim 5, characterized in that The code group synchronization process of the receiving channel of the RF transceiver is as follows: FPGA1 pulls down the SYNC_IN synchronization signals of multiple RF transceivers at the same time after performing an AND operation, and the device clock of the RF transceiver captures the synchronization signal and pulls it down, and then starts to send the K28.5 character after a delay of a period of time on the next LMFC clock edge; the receiving end of FPGA1 uses clock recovery technology to parse four consecutive K28.5 in the aligned data stream and then pulls up the synchronization signal, indicating that the CGS process synchronization is completed; After the device clock at the transmitting end of the RF transceiver captures the synchronization signal and is pulled high, it stops sending the K28.5 character at the rising edge of LMFC. The FPGA1 end uses the first non-K28.5 character detected as the starting frame of the next frame to complete the frame synchronization operation.

7. The system according to claim 5, characterized in that The initial channel synchronization process of the receiving channel of the RF transceiver is as follows: the ILAS sequence is sent starting from the next LMFC clock edge after the code group synchronization is completed, and the sequence length of the ILAS is composed of 4 multi-frames or more multi-frame lengths; the first, third and fourth multi-frames start with the character / R / and end with the character / A / , and the second multi-frame contains the character / R / and the character / Q / , and the data after the character / Q / is the link configuration parameter. The FPGA1 receiving end compares the link configuration parameters in the second multi-frame sent by the transmitting end of the receiving channel. If they are consistent, it means that the link parameter verification has passed, and if there is an error, the link establishment fails.

8. The system according to claim 5, characterized in that The link alignment process of the receiving channel of the RF transceiver is as follows: after the receiving end of the receiving channel detects the / R / character, the data following the / R / character is stored in an elastic buffer to ensure that the data of different channels finally arrives before the next LMFC clock edge arrives, and the data of all channels can complete the alignment operation and start data output, wherein the deterministic delay length cannot exceed one LMFC clock cycle, otherwise the phase relationship between the device clock and SYSREF is readjusted so that the SYSREF edge is within the valid clock window, meeting the setup time and hold time requirements of the two.

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