Solid-state imaging device and electronic equipment

Abstract

A solid-state imaging device according to an embodiment of the present invention includes a mode switching switch portion that electrically connects a first signal path to a photoelectric conversion portion and electrically disconnects a second signal path from the photoelectric conversion portion in a first mode, and electrically connects both the first and second signal paths to the photoelectric conversion portion in a second mode. A first substrate and a second substrate are stacked on each other, the first substrate having at least the photoelectric conversion portion formed therein, and the second substrate having at least the second amplifying transistor formed therein.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device and electronic equipment. Background Art

[0002] Solid-state imaging devices are used in, for example, imaging devices such as digital cameras and video cameras, or electronic devices such as portable terminal devices with imaging functions. Examples of solid-state imaging devices include complementary metal oxide semiconductor (CMOS) image sensors that read charge accumulated in photodiodes, which are photoelectric conversion elements, via metal oxide semiconductor (MOS) transistors.

[0003] CMOS image sensors are expected to have high sensitivity so that they can capture imaging signals even during periods of low illumination. Furthermore, to increase the dynamic range, it is desirable that the photodiodes be less susceptible to saturation. However, there is a trade-off between high sensitivity and the resistance of the photodiodes to saturation, making it difficult to expand the dynamic range while maintaining high sensitivity. For example, Patent Document 1 discloses a method in which a floating diffusion with a small capacitance and a floating diffusion with a large capacitance are provided, with the floating diffusion with the small capacitance being connected to the photodiode during periods of low illumination and the floating diffusion with the large capacitance being connected to the photodiode during periods of high illumination.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2003-134396 Summary of the Invention

[0007] However, when the invention described in Patent Document 1 is applied to high-definition applications, there is a problem: it is difficult to secure sufficient space for two floating diffusions. Therefore, it is desirable to provide a solid-state imaging device that can achieve both high sensitivity and a high dynamic range even in high-definition applications, and an electronic device including the same.

[0008] A solid-state imaging device according to a first aspect of the present invention includes: a photoelectric converter; a first signal path including a first floating diffusion and a first amplifier transistor; and a second signal path including a second floating diffusion and a second amplifier transistor. The solid-state imaging device also includes a mode switching section. In a first mode, the mode switching section electrically connects the first signal path to the photoelectric converter and electrically disconnects the second signal path from the photoelectric converter, and in a second mode, the mode switching section electrically connects both the first and second signal paths to the photoelectric converter. The solid-state imaging device also includes a first substrate and a second substrate. The first substrate includes at least the photoelectric converter, the first floating diffusion, the first amplifier transistor, the second floating diffusion, the second amplifier transistor, and the photoelectric converter among the mode switching switch section. The second substrate is stacked on the first substrate. The second substrate includes at least the photoelectric converter, the first floating diffusion, the first amplifier transistor, the second floating diffusion, the second amplifier transistor, and the second amplifier transistor among the mode switching switch section.

[0009] An electronic device according to a first aspect of the present invention includes: a solid-state imaging device that outputs a pixel signal corresponding to incident light; and a signal processing circuit that processes the pixel signal. The solid-state imaging device provided in the electronic device has a configuration similar to that of the solid-state imaging device according to the first aspect of the present invention.

[0010] A solid-state imaging device according to a second aspect of the present invention includes: a photoelectric converter; a first signal path including a first floating diffusion and a first amplifier transistor; and a second signal path including a second floating diffusion and a second amplifier transistor. The solid-state imaging device also includes a mode switching portion. In a first mode, the mode switching portion electrically connects the first signal path to the photoelectric converter and electrically disconnects the second signal path from the photoelectric converter, and in a second mode, the mode switching portion electrically connects both the first and second signal paths to the photoelectric converter. The solid-state imaging device also includes a first substrate, a second substrate, and a third substrate. The photoelectric converter and the first floating diffusion are formed on the first substrate. The second substrate is stacked on the first substrate. The first amplifier transistor, the second floating diffusion, and the mode switching portion are formed on the second substrate. The third substrate is stacked on the second substrate. The second amplifier transistor is formed on the third substrate.

[0011] An electronic device according to a second aspect of the present invention includes: a solid-state imaging device that outputs a pixel signal corresponding to incident light; and a signal processing circuit that processes the pixel signal. The solid-state imaging device provided in the electronic device has a configuration similar to that of the solid-state imaging device according to the second aspect of the present invention.

[0012] In the solid-state imaging device and electronic device according to the first aspect of the present invention, as well as the solid-state imaging device and electronic device according to the second aspect of the present invention, the amplifier transistor to be used is selected according to the mode. This can expand the dynamic range while maintaining high sensitivity. In addition, in the solid-state imaging device and electronic device according to the first aspect of the present invention, as well as the solid-state imaging device and electronic device according to the second aspect of the present invention, at least the amplifier transistor is formed on a substrate different from the substrate on which the photoelectric conversion unit is formed. This makes it possible to ensure sufficient space for the floating diffusion unit and the amplifier transistor even in high-definition solid-state imaging devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a schematic configuration of a solid-state image pickup device according to an embodiment of the present invention is illustrated.

[0014] Figure 2 Pictured Figure 1 Example of a sensor pixel and readout circuit.

[0015] Figure 3 Pictured Figure 1 An example of a cross-sectional configuration of a solid-state imaging device in the vertical direction.

[0016] Figure 4 Pictured Figure 1 An example of a cross-sectional configuration of a solid-state imaging device in the horizontal direction.

[0017] Figure 5 Pictured Figure 1 An example of a cross-sectional configuration of a solid-state imaging device in the horizontal direction.

[0018] Figure 6 The diagram shows when Figure 4 The cross-sectional structure and Figure 5 An example of a structure when the cross-sectional structures of are superimposed on each other.

[0019] Figure 7 Pictured Figure 1 A modified example of the horizontal cross-sectional structure of the solid-state imaging device.

[0020] Figure 8A Pictured Figure 1 An example of a method for manufacturing a solid-state imaging device.

[0021] Figure 8BIt is a successor Figure 8A Illustration of the subsequent manufacturing process.

[0022] Figure 8C It is a successor Figure 8B Illustration of the subsequent manufacturing process.

[0023] Figure 8D It is a successor Figure 8C Illustration of the subsequent manufacturing process.

[0024] Figure 8E It is a successor Figure 8D Illustration of the subsequent manufacturing process.

[0025] Figure 8F It is a successor Figure 8E Illustration of the subsequent manufacturing process.

[0026] Figure 8G It is a successor Figure 8F Illustration of the subsequent manufacturing process.

[0027] Figure 9 Pictured Figure 1 Modifications of the sensor pixel and readout circuit.

[0028] Figure 10 Pictured Figure 4 A modified example of the cross-sectional structure.

[0029] Figure 11 Pictured Figure 5 A modified example of the cross-sectional structure.

[0030] Figure 12 Pictured Figure 7 A modified example of the cross-sectional structure.

[0031] Figure 13 Pictured Figure 1 Modifications of the sensor pixel and readout circuit.

[0032] Figure 14 Pictured Figure 1 Modifications of the sensor pixel and readout circuit.

[0033] Figure 15 Pictured Figure 1 Modifications of the sensor pixel and readout circuit.

[0034] Figure 16 Pictured Figure 1 Modifications of the sensor pixel and readout circuit.

[0035] Figure 17 Pictured Figure 1 Modifications of the sensor pixel and readout circuit.

[0036] Figure 18 Pictured Figure 1 A modified example of the vertical cross-sectional structure of the solid-state imaging device.

[0037] Figure 19 Pictured Figure 1 A modified example of the vertical cross-sectional structure of the solid-state imaging device.

[0038] Figure 20 The figure shows a modified example of the connection pattern between the plurality of readout circuits and the plurality of vertical signal lines.

[0039] Figure 21 The diagram shows Figure 15 A modified example of the horizontal cross-sectional structure of the solid-state imaging device having the structure shown in FIG.

[0040] Figure 22 The diagram shows Figure 15 A modified example of the horizontal cross-sectional structure of the solid-state imaging device having the structure shown in FIG.

[0041] Figure 23 A modification of the cross-sectional configuration in the vertical direction of any of the solid-state imaging devices according to the aforementioned embodiment and its modification is illustrated.

[0042] Figure 24 The diagram shows Figure 15 、 Figure 21 、 Figure 22 and Figure 23 A modified example of the cross-sectional structure in the horizontal direction of any solid-state imaging device among the solid-state imaging devices having the structure described above.

[0043] Figure 25 The diagram shows Figure 15 、 Figure 21 、 Figure 22 and Figure 23 A modified example of the cross-sectional structure in the horizontal direction of any solid-state imaging device among the solid-state imaging devices having the structure described above.

[0044] Figure 26 The diagram shows Figure 15 、 Figure 21 、 Figure 22 and Figures 23 to 25 A modified example of the cross-sectional structure in the horizontal direction of any solid-state imaging device among the solid-state imaging devices having the structure described above.

[0045] Figure 27 The diagram shows Figure 15 、 Figure 21 、 Figure 22 and Figures 23 to 26A modified example of the cross-sectional structure in the horizontal direction of any solid-state imaging device among the solid-state imaging devices having the structure described above.

[0046] Figure 28 An example of a circuit configuration of an image pickup device provided with any one of the solid-state image pickup devices according to the aforementioned embodiments and their modifications is illustrated.

[0047] Figure 29 Pictured Figure 28 An example of a configuration in which a solid-state imaging device is stacked with three substrates.

[0048] Figure 30 An example of logic circuits formed separately in a substrate including sensor pixels and a substrate including a readout circuit is illustrated.

[0049] Figure 31 An example in which the logic circuit is formed in the third substrate is illustrated.

[0050] Figure 32 An example of a schematic configuration of an imaging system including any one of the solid-state imaging devices according to the aforementioned embodiments and their modifications is illustrated.

[0051] Figure 33 Pictured Figure 32 An example of a camera program in a camera system.

[0052] Figure 34 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0053] Figure 35 It is an auxiliary explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0054] Figure 36 is a view showing an example of a schematic configuration of an endoscopic surgery system.

[0055] Figure 37 : is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU: Camera Control Unit). DETAILED DESCRIPTION

[0056] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the description will be given in the following order.

[0057] 1. Example (Solid-State Imaging Device) Figures 1 to 8G

[0058] 2. Modification (Solid-State Imaging Device) Figures 9 to 31

[0059] 3. Application Example (Camera System) Figure 32 and Figure 33

[0060] 4. Practical Application Examples

[0061] Practical application examples of mobile objects... Figure 34 and Figure 35

[0062] Practical application examples of endoscopic surgery systems... Figure 36 and Figure 37

[0063] <1. Example>

[0064] [structure]

[0065] A solid-state imaging device 1 according to an embodiment of the present invention will be described. The solid-state imaging device 1 is, for example, a backside-illuminated image sensor including a complementary metal oxide semiconductor (CMOS) image sensor. The solid-state imaging device 1 receives light from a subject and performs photoelectric conversion to generate an image signal, thereby capturing an image. The solid-state imaging device 1 outputs a pixel signal corresponding to the incident light.

[0066] A backside-illuminated image sensor is an image sensor constructed such that a photoelectric conversion unit, such as a photodiode, is provided between a light-receiving surface on which light from the subject is incident and a wiring layer, which includes wiring, such as a transistor, for driving each pixel. Note that the present invention is not limited to application to CMOS image sensors.

[0067] Figure 1 The diagram illustrates an example of a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present invention. The solid-state imaging device 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The solid-state imaging device 1 is a three-dimensional imaging device in which the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30) are attached together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0068] The first substrate 10 includes a pixel region 13 in which a plurality of sensor pixels 12 performing photoelectric conversion are arranged in a matrix. The pixel region 13 is formed on a semiconductor substrate 11. The second substrate 20 includes a plurality of readout circuits 22 that output pixel signals based on the charge output from the sensor pixels 12. For example, the plurality of readout circuits 22 are formed on a semiconductor substrate 21, and the plurality of readout circuits 22 are assigned one-to-one to each sensor pixel 12. The second substrate 20 includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 includes a logic circuit 32 that processes the pixel signals. The logic circuit 32 is formed on the semiconductor substrate 31. For example, the logic circuit 32 includes a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs the output voltage Vout of each sensor pixel 12 to the outside.

[0069] The vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12, for example, in units of rows. The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on the pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 performs, for example, CDS processing to extract the signal level of the pixel signal and stores pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35 sequentially outputs the pixel data stored in the column signal processing circuit 34 to the outside, for example. The system control circuit 36 ​​controls the driving of each block within the logic circuit 32 (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35).

[0070] Figure 2 An example of the circuit configuration of the sensor pixel 12 and the readout circuit 22 is shown. Figure 2 The case shown is one in which one readout circuit 22 is assigned to one sensor pixel 12 .

[0071] Each sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TRG electrically connected to the photodiode PD, and two floating diffusions FD1 and FD2 that temporarily hold charge output from the photodiode PD via the transfer transistor TRG. The photodiode PD corresponds to a specific example of a "photoelectric converter" in the present invention. The floating diffusion FD1 corresponds to a specific example of a "first floating diffusion" in the present invention. The floating diffusion FD2 corresponds to a specific example of a "second floating diffusion" in the present invention.

[0072] The photodiode PD performs photoelectric conversion, thereby generating a charge corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TRG, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground GND). The drain of the transfer transistor TRG is electrically connected to the floating diffusion FD1, and the gate of the transfer transistor TRG is electrically connected to the pixel drive line 23. The transfer transistor TRG is, for example, an NMOS (Metal Oxide Semiconductor) transistor.

[0073] Each sensor pixel 12 also includes, for example, a switching transistor FDG that switches between two floating diffusions FD1 and FD2. The switching transistor FDG corresponds to a specific example of a "mode switching switch" in the present invention. The switching transistor FDG is, for example, an NMOS transistor. The source of the switching transistor FDG is the floating diffusion FD1, and the source of the switching transistor FDG is electrically connected to the drain of the transfer transistor TRG. The drain of the switching transistor FDG is the floating diffusion FD2, and the drain of the switching transistor FDG is electrically connected to the source of the reset transistor RST, which will be described later.

[0074] The readout circuit 22 includes, for example, a reset transistor RST, two amplifier transistors AMP1 and AMP2, and two select transistors SEL1 and SEL2. The amplifier transistor AMP1 corresponds to a specific example of the "first amplifier transistor" of the present invention. The amplifier transistor AMP2 corresponds to a specific example of the "second amplifier transistor" of the present invention. The reset transistor RST, the amplifier transistors AMP1 and AMP2, and the select transistors SEL1 and SEL2 are each, for example, NMOS transistors.

[0075] The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD2, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drains of the two amplifier transistors AMP1 and AMP2. The gate of the reset transistor RST is electrically connected to the pixel drive line 23 (see Figure 1 ). The source of the amplifier transistor AMP1 is electrically connected to the drain of the selection transistor SEL1, and the gate of the amplifier transistor AMP1 is electrically connected to the floating diffusion portion FD1. The source of the selection transistor SEL1 (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL1 is electrically connected to the pixel drive line 23 (see Figure 1). The source of the amplifier transistor AMP2 is electrically connected to the drain of the selection transistor SEL2, and the gate of the amplifier transistor AMP2 is electrically connected to the floating diffusion portion FD2. The source of the selection transistor SEL2 (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL2 is electrically connected to the pixel drive line 23 (see Figure 1 ).

[0076] The readout circuit 22 is provided with a signal path P1 including a floating diffusion FD1 and an amplifier transistor AMP1, and a signal path P2 including a floating diffusion FD2 and an amplifier transistor AMP2. Signal path P1 corresponds to a specific example of the "first signal path" of the present invention. Signal path P2 corresponds to a specific example of the "second signal path" of the present invention. One end of each of signal paths P1 and P2 is electrically connected to the vertical signal line 24, the other end of signal path P1 is electrically connected to the floating diffusion FD1, and the other end of signal path P2 is electrically connected to the floating diffusion FD2. Therefore, when the switching transistor FDG is on, signal paths P1 and P2 are connected in parallel. Furthermore, regardless of whether the switching transistor FDG is on or off, signal path P1 is electrically connected to the transfer transistor TRG. Simultaneously, when the switching transistor FDG is on, signal path P2 is electrically connected to the transfer transistor TRG. However, when the switching transistor FDG is off, signal path P2 is electrically isolated from the transfer transistor TRG. In other words, when the switching transistor FDG is off, no current flows into signal path P2.

[0077] When the transfer transistor TRG enters the on state, the transfer transistor TRG transfers the charge of the photodiode PD to the floating diffusion FD1 or the floating diffusion FD2. Figure 3 As shown, the gate of the transfer transistor TRG (transfer gate TG) extends from the top surface of the semiconductor substrate 11 to a depth that penetrates the p-well layer 42 and reaches the PD 41 .

[0078] Reset transistor RST resets the potential of each floating diffusion FD1 and FD2 to a predetermined potential. When reset transistor RST turns on, the potential of each floating diffusion FD1 and FD2 is reset to the potential of power supply line VDD. Select transistors SEL1 and SEL2 each control the output timing of pixel signals from readout circuit 22.

[0079] Amplifier transistor AMP1 generates a pixel signal with a voltage corresponding to the level of charge held in floating diffusion FD1. Amplifier transistor AMP2 generates a pixel signal with a voltage corresponding to the level of charge held in floating diffusion FD2. Amplifier transistors AMP1 and AMP2 form a source-follower amplifier and output a pixel signal with a voltage corresponding to the level of charge generated in photodiode PD. When select transistor SEL1 is turned on, amplifier transistor AMP1 amplifies the potential of floating diffusion FD1 and outputs a voltage corresponding to this potential to column signal processing circuit 34 via vertical signal line 24. When select transistor SEL2 is turned on, amplifier transistor AMP2 amplifies the potential of floating diffusion FD2 and outputs a voltage corresponding to this potential to column signal processing circuit 34 via vertical signal line 24.

[0080] When switching the conversion efficiency, the switching transistor FDG is used. Generally, when photographing in a dark place, the pixel signal is small. When performing charge-voltage conversion based on Q=CV, if the capacitance of the floating diffusion FD1 (FD capacitance C) is large, the value V when converted to voltage using the amplifier transistor is small. At the same time, in a bright place, the pixel signal becomes larger; therefore, unless the FD capacitance C is large, it is impossible for the floating diffusion FD1 to fully receive the charge of the photodiode PD. In addition, the FD capacitance C needs to be large so that the value V when converted to voltage using the amplifier transistor is not too large (i.e., small). Taking these circumstances into account, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, thereby increasing the entire FD capacitance C. At the same time, when the switching transistor FDG is turned off, the entire FD capacitance C becomes smaller. In this way, by switching the switching transistor FDG on / off, the FD capacitance C can be changed, so that the conversion efficiency can be switched.

[0081] The switching transistor FDG switches the FD capacitor C between the time of the high-sensitivity low-illuminance mode (first mode) and the time of the low-sensitivity high-illuminance mode (second mode). Specifically, in the first mode, the switching transistor FDG enters the cut-off state so that the FD capacitor C is relatively small, and in the second mode, the switching transistor FDG enters the on state so that the FD capacitor C is relatively large. The switching transistor FDG, the reset transistor RST, the amplifier transistors AMP1 and AMP2, and the selection transistors SEL1 and SEL2 are, for example, NMOS transistors. Under the control of the vertical drive circuit 33, in the first mode, the switching transistor FDG electrically connects the signal path P1 to the photodiode PD and electrically separates the signal path P2 from the photodiode PD, and in the second mode, the switching transistor FDG electrically connects both the signal path P1 and the signal path P2 to the photodiode PD. Specifically, the switching transistor FDG enters the cut-off state in the first mode and enters the on state in the second mode.

[0082] Figure 3 An example of a cross-sectional configuration of the solid-state imaging device 1 in the vertical direction is illustrated. Figure 3 The cross-sectional configuration of the solid-state imaging device 1 at a position facing the sensor pixels 12 is illustrated. The solid-state imaging device 1 has a configuration in which a first substrate 10, a second substrate 20, and a third substrate 30 are stacked in this order. The solid-state imaging device 1 also includes a color filter 40 and a light-receiving lens 50 located on the back side of the first substrate 10. The color filter 40 and the light-receiving lens 50 are provided, for example, one for each sensor pixel 12. In other words, the solid-state imaging device 1 is a back-illuminated imaging device.

[0083] The first substrate 10 has a structure in which an insulating layer 46 is stacked on the semiconductor substrate 11. The first substrate 10 includes the insulating layer 46 as part of the interlayer insulating film 51. The insulating layer 46 is provided in the gap between the semiconductor substrate 11 and the semiconductor substrate 21. The semiconductor substrate 11 is constructed of a silicon substrate. The semiconductor substrate 11 includes, for example, a p-well layer 42 located in and near a portion of the top surface, and includes a PD 41 located in another region (a region deeper than the p-well layer 42) having a conductivity type different from that of the p-well layer 42. The p-well layer 42 has, for example, a p-type conductivity type. The PD 41 has a conductivity type different from that of the p-well layer 42, and for example, has an n-type conductivity type. The semiconductor substrate 11 includes floating diffusions FD1 and FD2 located within the p-well layer 42, having a conductivity type different from that of the p-well layer 42.

[0084] The first substrate 10 includes a photodiode PD, a transfer transistor TRG, a switching transistor FDG, and floating diffusions FD1 and FD2 for each sensor pixel 12. The first substrate 10 has a structure in which the photodiode PD, the transfer transistor TRG, the switching transistor FDG, and the floating diffusions FD1 and FD2 are arranged on the top surface of the semiconductor substrate 11. The first substrate 10 includes an element isolation portion 43 that isolates the sensor pixels 12 from each other. The element isolation portion 43 is formed to extend along the normal direction (thickness direction) of the semiconductor substrate 11. The element isolation portion 43 is provided between two adjacent sensor pixels 12. The element isolation portion 43 electrically isolates the adjacent sensor pixels 12 from each other. The element isolation portion 43 is constructed of, for example, silicon oxide. The element isolation portion 43, for example, penetrates the semiconductor substrate 11.

[0085] The first substrate 10 also includes, for example, a p-well layer 44, which is located on the side of the element isolation portion 43 and in contact with the surface on the photodiode PD side. The p-well layer 44 has a conductivity type different from that of the photodiode PD, for example, a p-type conductivity type. The first substrate 10 also includes, for example, a fixed charge film 45 in contact with the back surface of the semiconductor substrate 11. To suppress dark current generated by the interface state of the semiconductor substrate 11 on the light-receiving surface side, the fixed charge film 45 includes a negative fixed charge. The fixed charge film 45 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for such insulating films include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. The electric field induced by the fixed charge film 45 forms a hole accumulation layer at the interface on the light-receiving surface side of the semiconductor substrate 11. This hole accumulation layer suppresses the generation of electrons from this interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. For example, the color filter 40 is provided in contact with the fixed charge film 45 and is located at a position opposite the sensor pixels 12 across the fixed charge film 45. The light receiving lens 50 is provided, for example, in contact with the color filter 40 , and is provided at a position opposing the sensor pixel 12 via the color filter 40 and the fixed charge film 45 .

[0086] The second substrate 20 has a structure in which an insulating layer 52 is stacked on the semiconductor substrate 21. The second substrate 20 includes the insulating layer 52 as part of the interlayer insulating film 51. The insulating layer 52 is provided in the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is constructed of a silicon substrate. The second substrate 20 includes, for example, one readout circuit 22 for each sensor pixel 12. The second substrate 20 has a structure in which the readout circuit 22 is provided on the top surface of the semiconductor substrate 21. The second substrate 20 is attached to the first substrate 10, with the back surface of the semiconductor substrate 21 facing the top surface of the semiconductor substrate 11. In other words, the second substrate 20 is attached to the first substrate 10 in a back-to-face manner. The second substrate 20 also includes an insulating layer 53 that penetrates the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The second substrate 20 includes the insulating layer 53 as part of the interlayer insulating film 51. The insulating layer 53 is provided to cover the side surfaces of the through-wiring 54 described later.

[0087] The stacked body including the first substrate 10 and the second substrate 20 includes an interlayer insulating film 51 and a plurality of through-wirings 54 provided within the interlayer insulating film 51. The plurality of through-wirings 54 extend along the normal direction of the semiconductor substrate 21 and are provided to penetrate the interlayer insulating film 51, including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other via the plurality of through-wirings 54. For example, two through-wirings 54 are electrically connected to the floating diffusions FD1 and FD2 and to a connection wiring 55 described later.

[0088] The second substrate 20 includes, for example, a plurality of connection portions 59 located within the insulating layer 52, and the plurality of connection portions 59 are electrically connected to the readout circuit 22 and the semiconductor substrate 21. The second substrate 20 also includes, for example, a wiring layer 56 located on the insulating layer 52. The wiring layer 56 includes, for example, an insulating layer 57 and a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 provided within the insulating layer 57. The wiring layer 56 also includes, for example, a plurality of connection wirings 55 located within the insulating layer 57. The plurality of connection wirings 55 are electrically connected to the through wirings 54 electrically connected to the floating diffusions FD1 and FD2, respectively, and are electrically connected to the readout circuit 22. For example, the floating diffusion FD1 and the gate of the amplifier transistor AMP1 are electrically connected to each other through the connection wirings 55 and the through wirings 54. Furthermore, for example, the floating diffusion FD2 and the gate of the amplifier transistor AMP2 are electrically connected to each other through the connection wirings 55 and the through wirings 54.

[0089] The wiring layer 56 further includes, for example, a plurality of pad electrodes 58 located within the insulating layer 57. Each pad electrode 58 is formed, for example, of Cu (copper). Each pad electrode 58 is exposed on the top surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and for attaching the second substrate 20 and the third substrate 30 together. The plurality of pad electrodes 58 are provided, for example, in a one-to-one manner for each pixel drive line 23 and each vertical signal line 24.

[0090] The third substrate 30, for example, has a structure in which an interlayer insulating film 61 is stacked on a semiconductor substrate 31. The third substrate 30 is attached to the second substrate 20 in a face-to-face manner. Therefore, when describing the structure within the third substrate 30, the vertical relationship to be described is opposite to the vertical direction in the figure. The semiconductor substrate 31 is constructed from a silicon substrate. The third substrate 30 has a structure in which the logic circuit 32 is disposed on the top surface of the semiconductor substrate 31. The third substrate 30 also includes, for example, a wiring layer 62 disposed on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and a plurality of pad electrodes 64 disposed within the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is formed, for example, from Cu (copper). Each pad electrode 64 is exposed on the top surface of the wiring layer 62. Each pad electrode 64 serves to electrically connect the second substrate 20 and the third substrate 30 and to attach the second substrate 20 and the third substrate 30 together. The second substrate 20 and the third substrate 30 are electrically connected to each other through the bonding between the pad electrodes 58 and 64. That is, the gate of the transfer transistor TRG (transfer gate TG) is electrically connected to the logic circuit 32 via, for example, the through wiring 54, the connection wiring 55, the connection portion 59, and the pad electrodes 58 and 64. The third substrate 30 is attached to the second substrate 20, and the top surface of the semiconductor substrate 31 is opposed to the top surface side of the semiconductor substrate 21. That is, the third substrate 30 is attached to the second substrate 20 in a face-to-face manner.

[0091] The first substrate 10 and the second substrate 20 are electrically connected to each other via a through-wiring 54. Furthermore, the second substrate 20 and the third substrate 30 are electrically connected to each other via a bond between pad electrodes 58 and 64. Here, the width of the through-wiring 54 is narrower than the width of the bond between pad electrodes 58 and 64. In other words, the cross-sectional area of ​​the through-wiring 54 is smaller than the cross-sectional area of ​​the bond between pad electrodes 58 and 64. Therefore, the through-wiring 54 does not hinder the higher integration density of the sensor pixels 12 within the first substrate 10. Furthermore, the readout circuit 22 is formed in the second substrate 20, and the logic circuit 32 is formed in the third substrate 30. This allows the structure for electrically connecting the second and third substrates 20 and 30 to have a lower density than the structure for electrically connecting the first and second substrates 10 and 20. Therefore, the bond between pad electrodes 58 and 64 can be used as the structure for electrically connecting the second and third substrates 20 and 30.

[0092] Figure 4 and Figure 5 An example of a cross-sectional configuration of the solid-state imaging device 1 in the horizontal direction is respectively illustrated. Figure 4 An example of the top surface configuration of the semiconductor substrate 11 is illustrated, and Figure 5 An example of the top surface configuration of the semiconductor substrate 21 is shown. Figure 6 The diagram shows Figure 4 The structure shown and Figure 5 The configurations shown are examples of stacked configurations. The transfer transistor TRG, the switching transistor FDG, and the floating diffusions FD1 and FD2 are provided on the top surface of the semiconductor substrate 11. That is, the transfer transistor TRG, the switching transistor FDG, and the floating diffusions FD1 and FD2 are provided in the first substrate 10. Simultaneously, for example, the reset transistor RST, the amplifying transistors AMP1 and AMP2, and the select transistors SEL1 and SEL2 are provided on the top surface of the semiconductor substrate 21. That is, the reset transistor RST, the amplifying transistors AMP1 and AMP2, and the select transistors SEL1 and SEL2 are provided in the second substrate 20.

[0093] At this time, for example, Figure 6 As shown, when Figure 4 The structure shown and Figure 5 When the structures shown are superimposed on each other, an overlapping region α exists. As can be understood from the above, in the solid-state imaging device 1, the overlapping region α allows for a reduction in size compared to a case where the transfer transistor TRG, the switching transistor FDG, the floating diffusions FD1 and FD2, the reset transistor RST, the amplifier transistors AMP1 and AMP2, and the select transistors SEL1 and SEL2 are provided in a common substrate.

[0094] Incidentally, the L lengths b1 and b2 of the amplifier transistors AMP1 and AMP2 are, for example, equal to each other. Meanwhile, regarding the W lengths of the amplifier transistors AMP1 and AMP2, for example, the W length a2 of the amplifier transistor AMP2 is greater than the W length a1 of the amplifier transistor AMP1. The W length a2 of the amplifier transistor AMP2 is, for example, two or three times the W length a1 of the amplifier transistor AMP1. When the switching transistor FDG is turned on, the W length of the amplifier transistor serving as the readout circuit 22 is the sum of the W length a1 of the amplifier transistor AMP1 and the W length a2 of the amplifier transistor AMP2. Therefore, by switching the switching transistor FDG on and off, the W length of the amplifier transistor serving as the readout circuit 22 can be tripled or quadrupled, for example.

[0095] Note that Figure 7 As shown, a plurality of amplifier transistors AMP2 may be provided for the readout circuit 22. In this case, the W length a2 of each amplifier transistor AMP2 may be equal to the W length a1 of the amplifier transistor AMP1, or may be greater than the W length a1 of the amplifier transistor AMP1.

[0096] [Manufacturing method]

[0097] Next, a method of manufacturing the solid-state image pickup device 1 is described. Figures 8A to 8G An example of a manufacturing process of the solid-state imaging device 1 is respectively illustrated.

[0098] First, a p-well layer 42, an element isolation portion 43, and a p-well layer 44 are formed in the semiconductor substrate 11. Next, a photodiode PD, a transfer transistor TRG, a switching transistor FDG, and floating diffusion portions FD1 and FD2 are formed on the semiconductor substrate 11. Figure 8A ). This allows the sensor pixels 12 to be formed on the semiconductor substrate 11. At this time, as the electrode material for the sensor pixels 12, it is preferable not to use a material with low heat resistance such as CoSi2 and NiSi manufactured by a salicide process. Instead, it is preferable to use a material with high heat resistance as the electrode material for the sensor pixels 12. Examples of materials with high heat resistance include polycrystalline silicon. Thereafter, an insulating layer 46 ( Figure 8A ). In this way, the first substrate 10 is formed.

[0099] Next, the semiconductor substrate 21 is attached to the first substrate 10 (insulating layer 46) ( Figure 8BAt this point, the semiconductor substrate 21 is thinned as necessary. In this case, the thickness of the semiconductor substrate 21 is set to the film thickness required to form the readout circuit 22. The thickness of the semiconductor substrate 21 is typically approximately several hundred nanometers (nm). However, depending on the concept of the readout circuit 22, a fully depleted (FD) type can also be used; in this case, the thickness of the semiconductor substrate 21 can also range from several nm to several μm.

[0100] Next, an insulating layer 53 ( Figure 8C For example, the insulating layer 53 is formed at a position opposite to the floating diffusion portions FD1 and FD2. For example, a slit is formed in the semiconductor substrate 21 so as to penetrate the semiconductor substrate 21 and separate the semiconductor substrate 21 into a plurality of blocks of the semiconductor substrate 21. Thereafter, the insulating layer 53 is formed so as to fill the slit. Thereafter, the readout circuit 22 (including the amplifier transistors AMP1 and AMP2 and the selection transistors SEL1 and SEL2) is formed in each block of the semiconductor substrate 21. Figure 8D At this time, when a metal material with high heat resistance is used as the electrode material of the sensor pixel 12, the gate insulating film of the readout circuit 22 can be formed by thermal oxidation. In addition, the electrode of each transistor included in the readout circuit 22 can contain silicide. After forming the sensor pixel 12, the readout circuit 22 is formed. Therefore, the surface of the impurity diffusion region that contacts the source electrode and drain electrode of each transistor included in the readout circuit 22 can be made of silicide with low heat resistance.

[0101] Next, an insulating layer 52 is formed on the semiconductor substrate 21. In this way, an interlayer insulating film 51 including the insulating layers 46, 52, and 53 is formed. Subsequently, through holes 51A, 51B, 51C, and 51D are formed in the interlayer insulating film 51 ( Figure 8E Specifically, through holes 51C and 51D are formed through the insulating layer 52 at a position of the insulating layer 52 that is part of the interlayer insulating film 51 and faces the readout circuit 22 (for example, the amplifier transistors AMP1 and AMP2). Furthermore, through holes 51A and 51B are formed through the interlayer insulating film 51 at a position of the interlayer insulating film 51 that is opposite to the floating diffusions FD1 and FD2 (that is, at a position facing the insulating layer 53).

[0102] Next, by embedding a conductive material in the through holes 51A, 51B, 51C, and 51D, the through wiring 54 is allowed to be formed in the through holes 51A and 51B and the connection portion 59 is allowed to be formed in the through holes 51C and 51D ( Figure 8F ). In addition, a connection wiring 55 ( Figure 8F ). Thereafter, a wiring layer 56 including pad electrodes 58 is formed on the insulating layer 52. In this way, the second substrate 20 is formed.

[0103] Next, the second substrate 20 is attached to the third substrate 30 on which the logic circuit 32 and the wiring layer 62 are formed, and the top surface of the semiconductor substrate 21 is opposed to the top surface side of the semiconductor substrate 31 ( Figure 8G At this time, the pad electrode 58 of the second substrate 20 and the pad electrode 64 of the third substrate 30 are bonded to each other, thereby electrically connecting the second substrate 20 and the third substrate 30 to each other. In this way, the solid-state imaging device 1 is manufactured.

[0104] [Effect]

[0105] Next, the effects of the solid-state image pickup device 1 according to the present embodiment will be described.

[0106] It is desirable that a CMOS image sensor have high sensitivity so that an imaging signal can be acquired even during low illumination. In addition, in order to increase the dynamic range, it is desirable that the photodiode is not easily saturated. However, there is a trade-off between high sensitivity and the difficulty in saturating the photodiode, so it is difficult to expand the dynamic range while maintaining high sensitivity. Therefore, for example, the above-mentioned patent document 1 discloses that a floating diffusion portion with a small capacitance and a floating diffusion portion with a large capacitance are provided, and the floating diffusion portion with a small capacitance is connected to the photodiode during low illumination, while the floating diffusion portion with a large capacitance is connected to the photodiode during high illumination. In the case of applying the invention described in patent document 1 to high-definition applications, there is a problem that it is difficult to ensure sufficient space to provide the two floating diffusion portions.

[0107] At the same time, in this embodiment, the amplifier transistors AMP1 and AMP2 to be used are selected according to the mode. This can expand the dynamic range while maintaining high sensitivity. In addition, in this embodiment, at least the amplifier transistors AMP1 and AMP2 are formed in a second substrate 20 that is different from the first substrate 10 on which the photodiode PD is formed. Specifically, the photodiode PD, the transfer transistor TRG, the floating diffusions FD1 and FD2, and the switching transistor FDG are formed in the first substrate 10, and the reset transistor RST, the amplifier transistors AMP1 and AMP2, and the selection transistors SEL1 and SEL2 are formed in the second substrate 20. This ensures sufficient space for arranging the floating diffusions FD1 and FD2 and the amplifier transistors AMP1 and AMP2, even when the solid-state imaging device 1 has high resolution. As a result, both high sensitivity and a high dynamic range can be achieved even in high-resolution applications.

[0108] Furthermore, in the present embodiment, in the case where the electrode of each transistor included in the readout circuit 22 contains silicide, it is possible to reduce the parasitic resistance of each transistor included in the readout circuit 22. As a result, noise reduction can be achieved.

[0109] It should be noted that in this embodiment, the vertical drive circuit 33 can change the drive current according to the size of the amplifier transistors AMP1 and AMP2, which are switched by the switching transistor FDG under the control of the system control circuit 36. In this case, the drive current per unit amplifier transistor can be prevented from being reduced, thereby suppressing the degradation of noise characteristics.

[0110] <2. Modifications>

[0111] Hereinafter, a modification of the solid-state image pickup device 1 according to the aforementioned embodiment is described.

[0112] [[Variant A]]

[0113] Figure 9 The diagram illustrates a modification of the circuit configuration of the sensor pixel 12 and readout circuit 22 of the solid-state imaging device 1 according to the aforementioned embodiment. In this modification, the photodiode PD, transfer transistor TRG, floating diffusions FD1 and FD2, switch transistor FDG, amplifier transistor AMP1, and select transistor SEL1 are formed in the first substrate 10. Simultaneously, the reset transistor RST, amplifier transistor AMP2, and select transistor SEL2 are formed in the second substrate 20. Even in this case, similar to the aforementioned embodiment, sufficient space can be secured for arranging the floating diffusions FD1 and FD2 and amplifier transistors AMP1 and AMP2. As a result, both high sensitivity and a high dynamic range can be achieved, even in high-definition applications.

[0114] Figure 10 The diagram shows Figure 9 An example of the top surface configuration of the semiconductor substrate 11 in the solid-state imaging device 1 of the configuration shown. Figure 11 and Figure 12 The diagrams show Figure 9 An example of the top surface structure of the semiconductor substrate 21 in the solid-state imaging device 1 of the structure shown in FIG. In this modification, for example, Figure 10 As shown, the photodiode PD, the transfer transistor TRG, the floating diffusions FD1 and FD2, the switch transistor FDG, the amplifier transistor AMP1, and the selection transistor SEL1 can be accommodated in a smaller area. Figure 11 and Figure 12As shown, the reset transistor RST, the amplifier transistor AMP2, and the selection transistor SEL2 can be accommodated in a smaller area. In this way, while reducing the occupied area in this way, the solid-state imaging device 1 can be miniaturized.

[0115] [[Variant B]]

[0116] Figure 13 The diagram illustrates a modification of the circuit configuration of the sensor pixels 12 and the readout circuit 22 of the solid-state imaging device 1 according to the aforementioned embodiment. In this modification, two sensor pixels 12 (12A and 12B) share one readout circuit 22. Here, the term "share" means that the outputs of the two sensor pixels 12 (12A and 12B) are commonly input to the readout circuit 22. In this case, the one readout circuit 22 is formed in a region of the semiconductor substrate 21 that faces the two sensor pixels 12. Therefore, compared to the aforementioned embodiment, the area for forming the one readout circuit 22 can be expanded to twice, thereby ensuring sufficient space for providing the floating diffusion portions FD1 and FD2 and the amplifier transistors AMP1 and AMP2. As a result, both high sensitivity and high dynamic range can be achieved even in high-definition applications.

[0117] [[Variant C]]

[0118] Figure 14 The diagram illustrates a modified circuit configuration of the sensor pixel 12 and readout circuit 22 of the solid-state imaging device 1 according to Modification B described above. In this modification, the photodiode PD and transfer transistor TRG are formed in the first substrate 10. Simultaneously, the floating diffusions FD1 and FD2, two switching transistors FDG, amplifier transistors AMP1 and AMP2, and select transistors SEL1 and SEL2 are formed in the second substrate 20. Even in this case, similar to Modification B described above, sufficient space can be secured for the floating diffusions FD1 and FD2 and amplifier transistors AMP1 and AMP2. As a result, both high sensitivity and a high dynamic range can be achieved, even in high-definition applications.

[0119] [[Variant D]]

[0120] Figure 15The diagram illustrates a modified example of the circuit configuration of the sensor pixels 12 and readout circuit 22 of the solid-state imaging device 1 according to the aforementioned Modification B. In this modification, four sensor pixels 12 (12A, 12B, 12C, and 12D) share a single readout circuit 22. In this case, the single readout circuit 22 is formed in a region of the second substrate 20 facing the four sensor pixels 12. Consequently, the area for forming the single readout circuit 22 can be quadrupled compared to the aforementioned embodiment, ensuring ample space for arranging the floating diffusions FD1 and FD2 and the amplifier transistors AMP1 and AMP2. As a result, both high sensitivity and a high dynamic range can be achieved even in high-definition applications.

[0121] [[Variant E]]

[0122] Figure 16 The diagram illustrates a modified example of the circuit configuration of the sensor pixels 12 and readout circuit 22 of the solid-state imaging device 1 according to Modification C described above. In this modification, four sensor pixels 12 (12A, 12B, 12C, and 12D) share a single readout circuit 22. In this case, the single readout circuit 22 is formed in a region of the second substrate 20 facing the four sensor pixels 12. Consequently, the area for forming the single readout circuit 22 can be quadrupled compared to the previously described embodiment, ensuring ample space for arranging the floating diffusions FD1 and FD2 and the amplifier transistors AMP1 and AMP2. As a result, both high sensitivity and a high dynamic range can be achieved even in high-definition applications.

[0123] [[Variant F]]

[0124] Figure 17 The diagram illustrates a modification of the circuit configuration of the sensor pixel 12 and readout circuit 22 of the solid-state imaging device 1 according to the aforementioned embodiment. In this modification, a switching transistor FDGa having the same configuration as the switching transistor FDG is provided in the location where the switching transistor FDG is provided, and a switching transistor FDGb is further provided in the middle of the wiring that connects the floating diffusion FD1 and the gate of the amplifier transistor AMP1. The switching transistors FDGa and FDGb are each, for example, an NMOS transistor.

[0125] Furthermore, in this variation, the FD capacitor C is switched between the time of the high-sensitivity, low-illuminance mode (first mode) and the time of the low-sensitivity, high-illuminance mode (second mode). Specifically, under the control of the system control circuit 36, in the first mode, the vertical drive circuit 33 electrically connects the signal path P1 to the photodiode PD and electrically disconnects the signal path P2 from the photodiode PD. Under the control of the system control circuit 36, in the second mode, the vertical drive circuit 33 electrically connects both the signal path P1 and the signal path P2 to the photodiode PD. For example, in the first mode, the vertical drive circuit 33 turns the switching transistor FDGa off and turns the switching transistor FDGb on. Furthermore, in the second mode, for example, the vertical drive circuit 33 turns the switching transistor FDGa on and also turns the switching transistor FDGb on. By constructing in this manner, similar to the aforementioned embodiment, both high sensitivity and high dynamic range can be achieved even in high-definition applications.

[0126] In this modification, two sensor pixels 12 can share one readout circuit 22. In this modification, four sensor pixels 12 can share one readout circuit 22. In this case, similar to the aforementioned modifications B to E, both high sensitivity and high dynamic range can be achieved even in high-definition applications.

[0127] [[Variant G]]

[0128] Figure 18 A modified example of the cross-sectional configuration of the solid-state imaging device 1 according to any of the aforementioned embodiments and their modified examples is shown. In this modified example, two photodiodes PD are provided for each light-receiving lens 50, and the two photodiodes PD are isolated from each other by an element isolation unit 43. Hereinafter, the two photodiodes PD provided corresponding to the light-receiving lens 50 will be referred to as photodiodes PDa and PDb.

[0129] In this modified example, floating diffusions FD1 are provided on a one-to-one basis for each of the photodiodes PDa and PDb. At the same time, a single switching transistor FDG is allocated to each of the photodiodes PDa and PDb. Therefore, the floating diffusion FD1 provided for the photodiode PDa and the floating diffusion FD1 provided for the photodiode PDb are electrically connected to each other via a connection wiring 49 provided within the insulating layer 46.

[0130] Furthermore, in this modified example, the photodiodes PDa and PDb, two transfer transistors TRG, two floating diffusions FD1, one floating diffusion FD2, the switch transistor FDG, the amplifier transistor AMP1, and the select transistor SEL1 are formed in the first substrate 10. Simultaneously, the reset transistor RST, the amplifier transistor AMP2, and the select transistor SEL2 are formed in the second substrate 20. Even in this case, similar to the aforementioned embodiment, sufficient space can be secured for arranging the floating diffusions FD1 and FD2 and the amplifier transistors AMP1 and AMP2. As a result, both high sensitivity and a high dynamic range can be achieved, even in high-definition applications.

[0131] [[Variant H]]

[0132] Figure 19 The figure shows a modified example of the cross-sectional structure of the solid-state imaging device 1 according to the aforementioned modification G. In this modification, a floating diffusion FD1 is provided on a one-to-one basis for each of the photodiodes PDa and PDb. At the same time, a single switching transistor FDG is allocated to each of the photodiodes PDa and PDb. Therefore, the floating diffusion FD1 provided for the photodiode PDa and the floating diffusion FD1 provided for the photodiode PDb are electrically connected to each other via a connection wiring 55 provided within the insulating layer 52. The floating diffusion FD1 provided for the photodiode PDa and the floating diffusion FD1 provided for the photodiode PDb are connected to the gates of the switching transistor FDG and the amplifier transistor AMP1 via the connection wiring 55 and the through wiring 54.

[0133] In this modification, the second substrate 20 includes two semiconductor substrates 21 and 26. The semiconductor substrate 26 is stacked on the semiconductor substrate 21 with an interlayer insulating film 51 (insulating layer 52) interposed therebetween. The semiconductor substrate 26 is provided between the interlayer insulating film 51 (insulating layer 52) and the insulating layer 57. The semiconductor substrate 26 has an opening, and a portion of the insulating layer 57 (hereinafter referred to as "insulating layer 28") is provided in the opening. A through-wiring 54 penetrates the insulating layer 28. The through-wiring 54 penetrating the insulating layer 28 electrically connects the floating diffusion portion FD2 and the gate of the amplifier transistor AMP2 to each other via the connection wiring 55 and other through-wiring 54.

[0134] In this modification, the photodiodes PDa and PDb and the two floating diffusions FD1 are formed in the first substrate 10, the amplifier transistor AMP1, the floating diffusion FD2, and the switching transistor FDG are formed in the semiconductor substrate 21 of the second substrate 20, and the amplifier transistor AMP2 is formed in the semiconductor substrate 26 of the second substrate 20. Even in this case, similar to the previous embodiment, sufficient space can be secured for arranging the floating diffusions FD1 and FD2 and the amplifier transistors AMP1 and AMP2. As a result, both high sensitivity and a high dynamic range can be achieved even in high-definition applications.

[0135] In this modification, the electrodes of each transistor formed in semiconductor substrates 21 and 26 may contain silicide. In this case, each transistor formed in semiconductor substrates 21 and 26 is formed after forming sensor pixels 12. Therefore, silicide, which has low heat resistance, can be used for the surface of the impurity diffusion region in contact with the source electrode and drain electrode of each transistor included in readout circuit 22.

[0136] [[Variation 1]]

[0137] Figure 20 The figure shows an example of a connection pattern between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. In the aforementioned embodiment and its modified example, when a plurality of readout circuits 22 are arranged side by side along the direction in which the vertical signal lines 24 extend (for example, the column direction), the plurality of vertical signal lines 24 can be allocated to the respective readout circuits 22 in a one-to-one manner. For example, Figure 20 As shown, when four readout circuits 22 are arranged side by side along the direction in which the vertical signal lines 24 extend (eg, the column direction), the four vertical signal lines 24 can be allocated to the respective readout circuits 22 in a one-to-one manner.

[0138] [Variation J]

[0139] Figure 21 and Figure 22 For example, the diagrams respectively show Figure 15 A modified example of the horizontal cross-sectional structure of the solid-state imaging device 1 is shown. Figure 21 and Figure 22 The upper figures in show examples of cross-sectional configurations of the first substrate 10 in the solid-state imaging device 1 having the configuration of Modification D, respectively. Figure 21 and Figure 22 The upper figures of FIG. 1 respectively illustrate the first substrate 10 and the second substrate 20 of the solid-state imaging device 1 having the structure of the modification D. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec1. Figure 21 and Figure 22In the upper cross-sectional views of each of the figures, the figures illustrating examples of the front surface configuration of the semiconductor substrate 11 are superimposed on each other, and the insulating layer 46 is omitted. Figure 21 and Figure 22 The lower drawings of show examples of cross-sectional configurations of the second substrate 20 in the solid-state imaging device 1 having the configuration of Modification D, respectively. Figure 21 and Figure 22 The following figures illustrate the second substrate 20 and the second substrate 21 of the solid-state imaging device 1 having the structure of the modification D. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec2. It should be noted that Figure 21 and Figure 22 In the lower cross-sectional view of , the views illustrating examples of the front surface configuration of the semiconductor substrate 21 and the insulating layer 53 are superimposed on each other, and the insulating layer 52 is omitted. Figure 21 A configuration in which two groups of 2×2 four sensor pixels 12 are arranged along the second direction H is illustrated. Figure 22 A configuration in which four groups of 2×2 of four sensor pixels 12 are arranged along the first direction V and the second direction H is illustrated.

[0140] The stacked body including the first substrate 10 and the second substrate 20 includes through wirings 67 and 68 provided in the interlayer insulating film 51. The stacked body includes one through wiring 67 and one through wiring 68 for each sensor pixel 12. Each of the through wirings 67 and 68 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate a position including the insulating layer 53 of the interlayer insulating film 51. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through wirings 67 and 68. Specifically, the through wiring 67 is electrically connected to the p-well layer 42 of the semiconductor substrate 11 and is electrically connected to the wiring within the second substrate 20. The through wiring 68 is electrically connected to the transfer gate TG and is electrically connected to the pixel drive line 23. As Figure 21 and Figure 22 As shown, the plurality of through wirings 54, the plurality of through wirings 68, and the plurality of through wirings 67 are arranged in the plane of the first substrate 10 along the first direction V ( Figure 21 The vertical direction and Figure 22 (horizontally in the middle) are arranged side by side in a strip shape. Figure 21 and Figure 22The example illustrates a case where multiple through-wirings 54, multiple through-wirings 68, and multiple through-wirings 67 are arranged side by side in two rows along a first direction V. The first direction V is parallel to one of the two arrangement directions (e.g., the row direction and the column direction) of the multiple sensor pixels 12 arranged in a matrix (e.g., the column direction). In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, with the element isolation portion 43 interposed therebetween. In the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG are arranged so as to surround the four floating diffusions FD, and the four transfer gates TG form, for example, a ring shape.

[0141] The insulating layer 53 is constructed from a plurality of blocks extending along a first direction V. The semiconductor substrate 21 extends along the first direction V and is constructed from a plurality of island-shaped blocks 21A arranged side by side in a second direction H orthogonal to the first direction V, with the insulating layer 53 interposed therebetween. Each block 21A includes, for example, multiple sets of reset transistors RST, amplifier transistors AMP, and select transistors SEL. The single readout circuit 22 shared by the four sensor pixels 12 is constructed, for example, from the reset transistor RST, amplifier transistor AMP, and select transistor SEL within the region facing the four sensor pixels 12. The single readout circuit 22 shared by the four sensor pixels 12 is constructed, for example, from the amplifier transistor AMP within the block 21A adjacent to the left of the insulating layer 53 and from the reset transistor RST and select transistor SEL within the block 21A adjacent to the right of the insulating layer 53.

[0142] [Variant K]

[0143] Figure 23 A modified example of a vertical cross-sectional configuration of the solid-state imaging device 1 according to any of the aforementioned embodiments and their modified examples is illustrated. In this modified example, electrical connection between the second substrate 20 and the third substrate 30 is formed in an area facing the peripheral region 14 of the first substrate 10. The peripheral region 14 corresponds to the photo frame region of the first substrate 10 and is provided around the pixel region 13. In this modified example, the second substrate 20 includes a plurality of pad electrodes 58 located in an area facing the peripheral region 14, and the third substrate 30 includes a plurality of pad electrodes 64 located in an area facing the peripheral region 14. The second substrate 20 and the third substrate 30 are electrically connected to each other through bonding between the pad electrodes 58 and 64 provided in the area facing the peripheral region 14.

[0144] In this manner, in this modified example, the second substrate 20 and the third substrate 30 are electrically connected to each other via the bonding between the pad electrodes 58 and 64 provided in the region facing the peripheral region 14. This reduces the possibility of inhibiting miniaturization of the area per pixel, compared to a case where the pad electrodes 58 and 64 are bonded to each other in the region facing the pixel region 13. Consequently, a solid-state imaging device 1 having a chip size equivalent to that of existing chips and having a three-layer structure that does not inhibit miniaturization of the area per pixel can be provided.

[0145] [Variation L]

[0146] Figure 24 and Figure 25 Modifications of the cross-sectional configuration of the solid-state imaging device 1 in the horizontal direction according to any one of Modifications D, J, and K are respectively illustrated. Figure 24 and Figure 25 The upper figures in each illustrate a modification of the cross-sectional configuration of the first substrate 10 in the solid-state imaging device 1 having a configuration of any one of modifications D, J, and K. Figure 24 and Figure 25 The upper figures of FIG. 1 and FIG. 2 illustrate the first substrate 10 and the first substrate 10 of the solid-state imaging device 1 having the configuration of any one of Modifications D, J, and K, respectively. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec1. Figure 24 and Figure 25 In the upper figure of , figures illustrating examples of the front surface configuration of the semiconductor substrate 11 are superimposed on each other, and the insulating layer 46 is omitted. Figure 24 and Figure 25 The lower drawings of show modifications of the cross-sectional configuration of the second substrate 20 in the solid-state imaging device 1 having the configuration of any one of modifications D, J, and K, respectively. Figure 24 and Figure 25 The following figures illustrate the second substrate 20 of the solid-state imaging device 1 having the configuration of any one of Modifications D, J, and K. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec2. It should be noted that Figure 24 and Figure 25 In the lower cross-sectional view of , the views illustrating examples of the front surface configuration of the semiconductor substrate 21 and the insulating layer 53 are superimposed on each other, and the insulating layer 52 is omitted.

[0147] like Figure 24 and Figure 25 As shown, a plurality of through wirings 54, a plurality of through wirings 68 and a plurality of through wirings 67 (a plurality of points arranged in a matrix in the figure) are arranged in the plane of the first substrate 10 along the first direction V ( Figure 24 and Figure 25 (horizontally in the middle) are arranged side by side in a strip shape. Figure 24 and Figure 25 The example illustrates a case where the plurality of through-wirings 54, the plurality of through-wirings 68, and the plurality of through-wirings 67 are arranged side by side in two rows along the first direction V. In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, with the element isolation portion 43 interposed therebetween. In the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, and TG4) are arranged to surround the four floating diffusions FD, and the four transfer gates TG form, for example, a ring shape.

[0148] The insulating layer 53 is constructed from a plurality of blocks extending in a first direction V. The semiconductor substrate 21 extends in the first direction V and is constructed from a plurality of island-shaped blocks 21A arranged side by side in a second direction H perpendicular to the first direction V, with the insulating layer 53 interposed therebetween. Each block 21A includes, for example, a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL. The single readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite the four sensor pixels 12, but is instead arranged offset in the second direction H.

[0149] exist Figure 24 In the embodiment, one readout circuit 22 shared by four sensor pixels 12 is configured by a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL located in a region of the second substrate 20 that is offset in the second direction H from a region facing the four sensor pixels 12. For example, one readout circuit 22 shared by four sensor pixels 12 is configured by the amplifier transistor AMP, the reset transistor RST, and the select transistor SEL within one block 21A.

[0150] exist Figure 25 In the embodiment, one readout circuit 22 shared by four sensor pixels 12 is configured by a reset transistor RST, an amplifier transistor AMP, a selection transistor SEL, and a switch transistor FDG located in a region of the second substrate 20 that is offset in the second direction H from a region facing the four sensor pixels 12. For example, one readout circuit 22 shared by four sensor pixels 12 is configured by the amplifier transistor AMP, the reset transistor RST, the selection transistor SEL, and the switch transistor FDG within one block 21A.

[0151] In this modified example, the single readout circuit 22 shared by the four sensor pixels 12 is not arranged directly opposite the four sensor pixels 12, but is instead arranged offset in the second direction H from the position directly opposite the four sensor pixels 12. In this case, the wiring can be shortened, or the wiring can be omitted and a common impurity region can be used to construct the source of the amplifier transistor AMP and the drain of the select transistor SEL. As a result, the size of the readout circuit 22 can be reduced, or the size of other locations within the readout circuit 22 can be increased.

[0152] [Variation M]

[0153] Figure 26 A modified example of the cross-sectional configuration in the horizontal direction of the solid-state imaging device 1 according to any one of the modified examples D, J, K, and L is illustrated. Figure 26 The upper drawing in shows an example of a cross-sectional configuration of the first substrate 10 in the solid-state image pickup device 1 having a configuration of any one of Modifications D, J, K, and L. FIG. Figure 26 The upper figure of the figure illustrates the first substrate 10 of the solid-state imaging device 1 having the configuration of any one of the modified examples D, J, K and L. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec1. Figure 26 In the upper cross-sectional view of , the views illustrating an example of the front surface configuration of the semiconductor substrate 11 are superimposed on each other, and the insulating layer 46 is omitted. Figure 26 The lower drawing of shows an example of a cross-sectional configuration of the second substrate 20 in the solid-state image pickup device 1 having a configuration of any one of Modifications D, J, K, and L. FIG. Figure 26 The following figure illustrates the second substrate 20 of the solid-state imaging device 1 having the configuration of any one of the modified examples D, J, K, and L. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec2. It should be noted that Figure 26 In the lower cross-sectional view of , the views illustrating examples of the front surface configuration of the semiconductor substrate 21 and the insulating layer 53 are superimposed on each other, and the insulating layer 52 is omitted. Figure 26 A configuration in which two groups of 2×2 four sensor pixels 12 are arranged along the second direction H is illustrated.

[0154] In this variation, the semiconductor substrate 21 is constructed from a plurality of island-shaped blocks 21A arranged side by side in a first direction V and a second direction H with an insulating layer 53 interposed therebetween. Each block 21A includes, for example, a set of a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL. In this case, the insulating layer 53 can suppress crosstalk between adjacent readout circuits 22, thereby suppressing image quality degradation caused by reduced resolution and color mixing in the reproduced image.

[0155] [Variant N]

[0156] Figure 27 A modified example of the cross-sectional configuration in the horizontal direction of the solid-state imaging device 1 according to any one of the modified examples D, J, K, L, and M is illustrated. Figure 27 The upper drawing in shows an example of a cross-sectional configuration of the first substrate 10 in the solid-state image pickup device 1 having a configuration of any one of Modifications D, J, K, L, and M. Figure 27The upper figure of the figure illustrates the first substrate 10 of the solid-state imaging device 1 having the configuration of any one of the modified examples D, J, K, L, and M. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec1. Figure 27 In the upper cross-sectional view of , the views illustrating an example of the front surface configuration of the semiconductor substrate 11 are superimposed on each other, and the insulating layer 46 is omitted. Figure 27 The lower drawing of shows an example of a cross-sectional configuration of the second substrate 20 in the solid-state image pickup device 1 having a configuration of any one of Modifications D, J, K, L, and M. FIG. Figure 27 The following figure illustrates the second substrate 20 of the solid-state imaging device 1 having the configuration of any one of the modified examples D, J, K, L, and M. Figure 3 The cross-section structure of the position corresponding to the cross-section Sec2. It should be noted that Figure 27 In the lower cross-sectional view of , the views illustrating examples of the front surface configuration of the semiconductor substrate 21 and the insulating layer 53 are superimposed on each other, and the insulating layer 52 is omitted. Figure 27 A configuration in which two groups of 2×2 four sensor pixels 12 are arranged along the second direction H is illustrated.

[0157] In this variation, the single readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite the four sensor pixels 12, but rather offset in the first direction V. Similar to Variation F, in this variation, the semiconductor substrate 21 is further constructed from a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H, with an insulating layer 53 interposed therebetween. Each block 21A includes, for example, a set of a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL. In this variation, multiple through-wirings 67 and multiple through-wirings 54 are also arranged in the second direction H. Specifically, the multiple through-wirings 67 are provided between the four through-wirings 54 that share a particular readout circuit 22 and the four through-wirings 54 that share another readout circuit 22 adjacent to the particular readout circuit 22 in the second direction H. In this case, the insulating layer 53 and the through-wirings 67 can suppress crosstalk between adjacent readout circuits 22, thereby suppressing image quality degradation due to reduced resolution and color mixing in the reproduced image.

[0158] [Variant O]

[0159] Figure 28 An example of a circuit configuration of a solid-state imaging device 1 according to any of the aforementioned embodiments and its modified examples is illustrated. The solid-state imaging device 1 according to the present modified example is a CMOS image sensor in which a column-parallel ADC is mounted.

[0160] like Figure 28As shown, in addition to the pixel area 13, the solid-state imaging device 1 according to the present variant is constructed to also include a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37 and a system control circuit 36. In the pixel area 13, a plurality of sensor pixels 12 each including a photoelectric conversion element are arranged two-dimensionally in a matrix manner (matrix shape).

[0161] In this system configuration, based on the main clock MCK, the system control circuit 36 ​​generates a clock signal or control signal, etc. that serves as an operating reference for the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., and provides the clock signal or control signal, etc. to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0162] Furthermore, a vertical drive circuit 33 is formed in the first substrate 10 together with each sensor pixel 12 of the pixel region 13, and the vertical drive circuit 33 is further formed in the second substrate 20 in which the readout circuit 22 is formed. A column signal processing circuit 34, a reference voltage supply section 38, a horizontal drive circuit 35, horizontal output lines 37, and a system control circuit 36 ​​are formed in the third substrate 30.

[0163] Although not shown here, the sensor pixel 12 may have a configuration that includes, in addition to the photodiode PD, a transfer transistor TRG that transfers charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Furthermore, although not shown here, the readout circuit 22 may have a three-transistor configuration that includes, for example, a reset transistor RST that controls the potential of the floating diffusion FD, an amplifier transistor AMP that outputs a signal corresponding to the potential of the floating diffusion FD, and a select transistor SEL for selecting a pixel.

[0164] In pixel region 13, sensor pixels 12 are arranged two-dimensionally. For this pixel arrangement of m rows and n columns, pixel drive lines 23 are connected for each row, and vertical signal lines 24 are connected for each column. One end of each of the plurality of pixel drive lines 23 is connected to the corresponding row output terminals of a vertical drive circuit 33. Vertical drive circuit 33 is constructed using a shift register or the like, and controls row addresses and row scanning for pixel region 13 via the plurality of pixel drive lines 23.

[0165] The column signal processing circuit 34 includes, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column (i.e., each vertical signal line 24) of the pixel area 13, and converts the analog signals output from the sensor pixels 12 of the pixel area 13 for each column into digital signals for output.

[0166] The reference voltage supply section 38 includes, for example, a DAC (Digital-to-Analog Converter) 38A as a means for generating a reference voltage Vref having a so-called ramp waveform, the level of which changes in a sloping manner over time. Note that the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0167] Under the control of the control signal CS1 supplied from the system control circuit 36 ​​, the DAC 38A generates a ramp waveform reference voltage Vref based on the clock CK supplied from the system control circuit 36 ​​to supply the generated reference voltage Vref to the ADCs 34 - 1 to 34 - m of the column signal processing circuit 34 .

[0168] It should be noted that each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to each of the normal frame rate mode and the high-speed frame rate mode in a progressive scan system for reading information from all sensor pixels 12. The high-speed frame rate mode sets the exposure time of the sensor pixels 12 to 1 / N compared to the time in the normal frame rate mode to increase the frame rate to N times, for example, twice. Switching between the operating modes is performed by control signals CS2 and CS3 supplied from the system control circuit 36. Instruction information for switching between the normal frame rate mode and the high-speed frame rate mode is supplied to the system control circuit 36 ​​from an external system controller (not shown).

[0169] All ADCs 34-1 to 34-m have the same configuration; description will be given here with reference to an example of ADC 34-m. ADC 34-m is configured to include a comparator 34A, an up / down counter (referred to as U / DCNT in the figure) 34B as a counting means, a transmission switch 34C, and a memory 34D.

[0170] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 of the n-th column of the pixel area 13 and the reference voltage Vref of the ramp waveform supplied from the reference voltage supply section 38 with each other. For example, when the reference voltage Vref is larger than the signal voltage Vx, the output Vco becomes an “H” level, whereas when the reference voltage Vref is equal to or smaller than the signal voltage Vx, the output Vco becomes an “L” level.

[0171] The up / down counter 34B is an asynchronous counter. Under the control of the control signal CS2 provided from the system control circuit 36, the up / down counter 34B and the DAC 38A are provided with the clock CK from the system control circuit 36 ​​at the same time, and the up / down counter 34B performs down (DOWN) counting or up (UP) counting in synchronization with the clock CK, thereby measuring the comparison period of the comparator 34A from the start to the end of the comparison operation.

[0172] Specifically, in the normal frame rate mode, when a reading operation of a signal from one sensor pixel 12 is performed, a count-down operation is performed during the first reading operation to measure the comparison time during the first reading, and an count-up operation is performed during the second reading operation to measure the comparison time during the second reading.

[0173] At the same time, in the high-speed frame rate mode, while the counting result of the sensor pixels 12 of a certain row is maintained as it is, then, with respect to the sensor pixels 12 of the next row, the counting is decremented at the first reading operation based on the previous counting result, thereby measuring the comparison time at the first reading, and the counting is incremented at the second reading operation, thereby measuring the comparison time at the second reading.

[0174] Under the control of the control signal CS3 provided from the system control circuit 36, in the normal frame rate mode, the transfer switch 34C enters an on (closed) state when the up / down counter 34B completes the counting operation on a certain row of sensor pixels 12, so as to transfer the counting result of the up / down counter 34B to the memory 34D.

[0175] At the same time, for example, at a high-speed frame rate of N=2, when the up / down counter 34B completes the counting operation of the sensor pixels 12 in a certain row, it remains in a disconnected (open) state, and then, when the up / down counter 34B completes the counting operation of the sensor pixels 12 in the next row, it obtains an on state to transfer the counting results of the up / down counter 34B for the two vertical pixels to the memory 34D.

[0176] In this way, analog signals supplied from the respective sensor pixels 12 of the pixel area 13 for each column via the vertical signal line 24 are converted into N-bit digital signals by respective operations of the comparators 34A and up / down counters 34B in the ADCs 34-1 to 34-m, and stored in the memory 34D.

[0177] The horizontal drive circuit 35 is constructed by a shift register or the like, and controls column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, N-bit digital signals that have been AD-converted in the respective ADCs 34-1 to 34-m are sequentially read to a horizontal output line 37 and output as imaging data via the horizontal output line 37.

[0178] Note that, although not particularly illustrated because it has no direct relation to the present invention, circuits for performing various types of signal processing on image pickup data to be output via the horizontal output line 37 may be provided in addition to the above components.

[0179] In the solid-state image pickup device 1 equipped with a column-parallel ADC according to the present modification having the above-described configuration, the count result of the up / down counter 34B can be selectively transferred to the memory 34D via the transfer switch 34C. This makes it possible to control the counting operation of the up / down counter 34B and the reading operation of the count result of the up / down counter 34B to the horizontal output line 37 independently of each other.

[0180] [Variation P]

[0181] Figure 29 Pictured Figure 28 This embodiment illustrates an example of a solid-state imaging device 1 having a stacked structure of three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). In this variation, a pixel region 13 including multiple sensor pixels 12 is formed in the central portion of the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13. Furthermore, a readout circuit region 15 including multiple readout circuits 22 is formed in the central portion of the second substrate 20, and the vertical drive circuit 33 is formed around the readout circuit region 15. A column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, horizontal output lines 37, and a reference voltage supply unit 38 are formed in the third substrate 30. Similar to the aforementioned embodiment and its variations, this eliminates the increase in chip size and the suppression of miniaturization of the area per pixel caused by the structure in which the substrates are electrically connected. As a result, a solid-state imaging device 1 having a chip size equivalent to that of existing chips and a three-layer structure that does not suppress miniaturization of the area per pixel can be provided. Note that the vertical driving circuit 33 may be formed only in the first substrate 10 , or may be formed only in the second substrate 20 .

[0182] [Variant Q]

[0183] Figure 30FIG shows a modified example of the cross-sectional configuration of the solid-state imaging device 1 according to any one of the aforementioned embodiments and their modified examples. In the aforementioned embodiments and their modified examples, the third substrate 30 may be omitted, and for example, Figure 30 As shown, logic circuit 32 disposed in third substrate 30 can be formed in first substrate 10 and second substrate 20, respectively. In this case, circuit 32A of logic circuit 32 disposed on first substrate 10 includes a transistor having a gate structure comprising a stack of a metal gate electrode and a high-k dielectric film containing a material capable of withstanding high-temperature processes (e.g., high-k). Simultaneously, circuit 32B disposed on second substrate 20 includes a low-resistance region 27 formed on the front surface of the impurity diffusion region in contact with the source and drain electrodes. Low-resistance region 27 contains a silicide, such as CoSi2 or NiSi, formed using a self-aligned silicide (SASI) process. Low-resistance region 27 containing silicide is formed from a compound of semiconductor substrate material and metal. This allows high-temperature processes, such as thermal oxidation, to be used when forming sensor pixels 12. Furthermore, in circuit 32B of logic circuit 32 disposed on second substrate 20, the placement of low-resistance region 27 containing silicide on the front surface of the impurity diffusion region in contact with the source and drain electrodes reduces contact resistance. As a result, the speed of arithmetic operations in the logic circuit 32 can be increased.

[0184] Figure 31 The figure illustrates a modified example of the cross-sectional structure of a solid-state imaging device 1 according to any of the aforementioned embodiments and their modifications. In the logic circuit 32 provided on the third substrate 30 according to the aforementioned embodiments and their modifications, a low-resistance region 39 containing silicide, such as CoSi2 or NiSi, formed using a self-aligned silicide process can be formed on the front surface of the impurity diffusion region in contact with the source and drain electrodes. This enables the use of high-temperature processes such as thermal oxidation when forming the sensor pixels 12. Furthermore, in the logic circuit 32, by providing the low-resistance region 39 containing silicide on the front surface of the impurity diffusion region in contact with the source and drain electrodes, contact resistance can be reduced. As a result, the speed of arithmetic operations in the logic circuit 32 can be increased.

[0185] Note that in the aforementioned embodiments and their variations, the conductivity types may be reversed. For example, in the descriptions of the aforementioned embodiments and their variations, p-type may be understood as n-type, and n-type may be understood as p-type. Even in this case, similar effects to those of the aforementioned embodiments and their variations can be achieved.

[0186] <3. Application Examples>

[0187] Figure 32 An example of a schematic configuration of an image pickup system 2 including the solid-state image pickup device 1 according to any of the aforementioned embodiments and their modified examples is illustrated.

[0188] The imaging system 2 is, for example, an electronic device including a solid-state imaging device such as a digital camera or video camera, or a portable terminal device such as a smartphone or tablet terminal. The imaging system 2 includes, for example, the solid-state imaging device 1 according to any of the aforementioned embodiments and their modifications, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the solid-state imaging device 1 according to any of the aforementioned embodiments and their modifications, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to one another via a bus 147.

[0189] The solid-state imaging device 1 according to any of the aforementioned embodiments and their variations outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes the signal (image data) output from the solid-state imaging device 1 according to any of the aforementioned embodiments and their variations. The frame memory 142 temporarily stores the image data processed by the DSP circuit 141 in units of frames. The display unit 143 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, and displays moving images or still images captured by the solid-state imaging device 1 according to any of the aforementioned embodiments and their variations. The storage unit 144 records the image data of the moving images or still images captured by the solid-state imaging device 1 according to any of the aforementioned embodiments and their variations in a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation commands for various functions of the imaging system 2 in response to user operations. The power supply unit 146 appropriately supplies various types of power for operation to the solid-state imaging device 1, DSP circuit 141, frame memory 142, display unit 143, storage unit 144 and operation unit 145 according to any of the aforementioned embodiments and their modifications as supply targets.

[0190] Next, an imaging procedure in the imaging system 2 is described.

[0191] Figure 33 The following diagram illustrates an example of a flowchart of an imaging operation in the imaging system 2. The user instructs the start of imaging by operating the operating unit 145 (step S101). The operating unit 145 then transmits the imaging command to the solid-state imaging device 1 (step S102). Upon receiving the imaging command, the solid-state imaging device 1 (specifically, the system control circuit 36) executes imaging using a predetermined imaging method (step S103).

[0192] The solid-state imaging device 1 outputs image data obtained through imaging to the DSP circuit 141. As used herein, image data refers to data for all pixels generated from pixel signals based on the charge temporarily held in the floating diffusion FD. The DSP circuit 141 performs predetermined signal processing (e.g., noise reduction) based on the image data input from the solid-state imaging device 1 (step S104). The DSP circuit 141 causes the frame memory 142 to store the image data that has undergone the predetermined signal processing, and the frame memory 142 causes the storage unit 144 to store the image data (step S105). In this manner, imaging is performed by the imaging system 2.

[0193] In this application example, the solid-state imaging device 1 according to any of the aforementioned embodiments and their modifications is applied to an imaging system 2. This enables the solid-state imaging device 1 to be miniaturized or have higher resolution, thereby providing a miniaturized or high-resolution imaging system 2.

[0194] <4. Practical Application Examples>

[0195] [Actual Application Example 1]

[0196] The technology according to the embodiments of the present invention (the present technology) can be applied to various products. For example, the technology according to the embodiments of the present invention can be implemented in the form of a device that can be installed on any type of mobile object. Non-limiting examples of mobile objects include automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, any personal mobile device, aircraft, unmanned aerial vehicles (UAVs), ships, and robots.

[0197] Figure 34 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present invention can be applied.

[0198] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 34 In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0199] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for the following devices: a drive force generating device, such as an internal combustion engine or a drive motor, for generating vehicle drive force; a drive force transmission mechanism for transmitting drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating vehicle braking force.

[0200] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as the headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0201] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receive the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, or text on the road, or can detect the distance to such objects.

[0202] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0203] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 for detecting the driver's condition. For example, the driver status detection unit 12041 includes a camera for capturing the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0204] Based on information about the exterior or interior of the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, the microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of the Advanced Driver Assistance System (ADAS), such as collision avoidance or impact mitigation, vehicle-to-vehicle distance-based following driving, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane departure warning.

[0205] In addition, based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform collaborative control aimed at automatic driving, etc. by controlling the driving force generating device, steering mechanism or braking device, etc. Automatic driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0206] Furthermore, based on information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, by controlling the headlights to switch from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform cooperative control aimed at preventing glare.

[0207] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can notify the occupants of the vehicle or the outside of the vehicle of the information in a visual or auditory manner. Figure 34 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are illustrated as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0208] Figure 35 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0209] exist Figure 35 , the camera unit 12031 includes camera units 12101 , 12102 , 12103 , 12104 and 12105 .

[0210] Camera units 12101, 12102, 12103, 12104, and 12105 are, for example, located on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper portion of the windshield inside the vehicle. Camera unit 12101 located on the front nose and camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily capture images of the front of vehicle 12100. Camera units 12102 and 12103 located on the side mirrors primarily capture images of the sides of vehicle 12100. Camera unit 12104 located on the rear bumper or rear door primarily captures images of the rear of vehicle 12100. Camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily detects preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0211] By the way, Figure 35 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located on the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 viewed from above is obtained.

[0212] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0213] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114, as well as the temporal variation of that distance (relative speed to vehicle 12100). This allows microcomputer 12051 to specifically extract the closest three-dimensional object as the preceding vehicle, specifically one that is located in the path of vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the same direction as vehicle 12100. Furthermore, microcomputer 12051 can pre-set the distance to be maintained in front of the preceding vehicle and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control). This enables cooperative control, such as automated driving, that allows the vehicle to travel autonomously without relying on driver input.

[0214] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data on three-dimensional objects into three-dimensional object data for two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or greater than a set value, indicating a collision possibility, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or display unit 12062 and initiates forced deceleration or evasive steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0215] At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the object's outline to determine whether the pedestrian is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a rectangular outline superimposed on the identified pedestrian for emphasis. The audio / video output unit 12052 may also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0216] An example of a mobile object control system to which the technology according to an embodiment of the present invention can be applied has been described above. The technology according to an embodiment of the present invention can be applied to the imaging unit 12031 among the components configured above. Specifically, the solid-state imaging device 1 according to any of the aforementioned embodiments and their variations can be applied to the imaging unit 12031. By applying the technology according to an embodiment of the present invention to the imaging unit 12031, a high-definition captured image with less noise can be obtained, thereby enabling high-precision control using the captured image in the mobile object control system.

[0217] [Actual Application Example 2]

[0218] Figure 36: is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the embodiment of the present invention (the present technology) can be applied.

[0219] exist Figure 36 , a surgeon (physician) 11131 is shown performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices used for endoscopic surgery are installed.

[0220] Endoscope 11100 includes: a barrel 11101 having a region of a predetermined length from a distal end to be inserted into a body cavity of a patient 11132; and a camera 11102 connected to the proximal end of barrel 11101. In the illustrated example, endoscope 11100 is shown as a rigid endoscope having a hard barrel 11101. However, endoscope 11100 may alternatively include a flexible endoscope having a flexible barrel 11101.

[0221] The lens barrel 11101 has an opening at its distal end, in which an objective lens is mounted. A light source device 11203 is connected to the endoscope 11100 so that light generated by the light source device 11203 is introduced to the distal end of the lens barrel 11101 through a light guide extending inside the lens barrel 11101, and the light is irradiated toward an observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 can be a forward-looking endoscope, or can be an oblique-looking endoscope or a side-looking endoscope.

[0222] The optical system and imaging element are arranged within the camera head 11102, so that reflected light from the observation target (observation light) is focused onto the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the CCU 11201.

[0223] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102 and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0224] Under the control of the CCU 11201 , the display device 11202 displays thereon an image based on the image signal that has been image-processed by the CCU 11201 .

[0225] The light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light to the endoscope 11100 when imaging the surgical area.

[0226] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information or commands to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input commands to change the imaging conditions of the endoscope 11100 (such as the type of irradiation light, magnification, or focal length).

[0227] The treatment tool control device 11205 controls the driving of the energy device 11112 for purposes such as tissue cauterization or cutting, or blood vessel sealing. To ensure the field of view of the endoscope 11100 and the surgeon's working space, the pneumoperitoneum device 11206 feeds gas into the patient's 11132 body cavity via the pneumoperitoneum tube 11111 to inflate the cavity. The recorder 11207 is a device capable of recording various surgical information. The printer 11208 is a device capable of printing various surgical information in various formats, such as text, images, or graphics.

[0228] It should be noted that the light source device 11203 that supplies irradiation light to the endoscope 11100 when imaging the surgical area may include a white light source, which includes, for example, an LED, a laser light source, or a combination of the two. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, the light source device 11203 can adjust the white balance of the captured image because it is possible to control the output intensity and output timing with high precision for various colors (various wavelengths). In addition, in this case, if the laser beams from the respective RGB laser light sources are irradiated on the observation target in a time-division manner and the drive of the imaging element of the camera 11102 is controlled in a manner synchronized with the irradiation timing, it is also possible to capture images corresponding to the R, G, and B colors, respectively, in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0229] In addition, the light source device 11203 can be controlled in such a manner that the intensity of the light to be output is changed at each predetermined time. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0230] In addition, the light source device 11203 can be configured to supply light of a predetermined wavelength band prepared for special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue to irradiate narrowband light compared to the irradiation light (i.e., white light) during ordinary observation, it is possible to perform narrowband observation (narrowband imaging) in which predetermined tissues such as blood vessels in the surface portion of the mucous membrane are imaged with high contrast. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image based on fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence from body tissue can be observed by irradiating excitation light onto the body tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating excitation light corresponding to the fluorescence wavelength of the reagent onto the body tissue. The light source device 11203 can be configured to supply such narrowband light and / or excitation light suitable for special light observation as described above.

[0231] Figure 37 It shows Figure 36 A block diagram of an example of the functional configuration of the camera 11102 and CCU 11201 is shown.

[0232] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 to communicate with each other.

[0233] The lens unit 11401 is an optical system that is provided at a connection position with the lens barrel 11101. Observation light obtained from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0234] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). In the case where the imaging unit 11402 is constructed as a multi-board type imaging unit, for example, the imaging element generates image signals corresponding to the corresponding R, G and B, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be constructed to have a pair of imaging elements to respectively obtain an image signal for the left eye and an image signal for the right eye prepared for three-dimensional (3D) display. If a 3D display is performed, the surgeon 11131 can understand the depth of the living tissue in the surgical area more accurately. It should be noted that in the case where the imaging unit 11402 is constructed as a multi-board type imaging unit, a plurality of systems of lens units 11401 are arranged in a manner corresponding to the respective imaging elements.

[0235] In addition, the imaging unit 11402 does not have to be provided on the camera head 11102. For example, the imaging unit 11402 can be provided inside the lens barrel 11101 immediately behind the objective lens.

[0236] The drive unit 11403 includes an actuator and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the camera unit 11402 can be appropriately adjusted.

[0237] The communication unit 11404 includes a communication device to transmit and receive various information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the imaging unit 11402 to the CCU 11201 as RAW data via the transmission cable 11400.

[0238] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, such as information specifying a frame rate for capturing an image, information specifying an exposure value during imaging, and / or information specifying a magnification and focus of a captured image.

[0239] Note that imaging conditions such as the frame rate, exposure value, magnification, or focus may be specified by the user or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE: Auto Exposure) function, an automatic focus (AF: Auto Focus) function, and an automatic white balance (AWB: Auto White Balance) function may be incorporated into the endoscope 11100.

[0240] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0241] The communication unit 11411 includes a communication device to transmit and receive various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera 11102 through the transmission cable 11400.

[0242] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0243] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data transmitted thereto from the camera 11102 .

[0244] The control unit 11413 performs various controls related to the endoscope 11100 capturing images of the surgical area, etc. and displaying images obtained by capturing images of the surgical area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0245] Furthermore, the control unit 11413 controls the display device 11202 to display a captured image of the surgical area, etc., based on the image signal processed by the image processing unit 11412. The control unit 11413 can then use various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can detect the shape and color of the edges of objects included in the captured image to identify surgical tools such as forceps, specific living areas, bleeding, and mist generated by the energy device 11112. When controlling the display device 11202 to display the captured image, the control unit 11413 can utilize the recognition results to display various surgical support information superimposed on the image of the surgical area. Displaying this superimposed surgical support information and presenting it to the surgeon 11131 can reduce the burden on the surgeon 11131, allowing the surgeon 11131 to confidently perform the surgery.

[0246] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable prepared for electric signal communication, an optical fiber prepared for optical communication, or a composite cable prepared for both electric and optical communication.

[0247] Here, although in the illustrated example, communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0248] An example of an endoscopic surgical system to which the technology according to an embodiment of the present invention can be applied has been described above. For example, the technology according to an embodiment of the present invention can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100 in the above-described configuration. By applying the technology according to an embodiment of the present invention to the imaging unit 11402, the imaging unit 11402 can be miniaturized or have higher resolution, thereby providing a miniaturized or high-resolution endoscope 11100.

[0249] Although the present invention has been described above with reference to the embodiments and their variations, applicable examples, and practical application examples, the present invention is not limited to the aforementioned embodiments and the like, but various variations are possible. It should be noted that the effects described herein are merely illustrative. The effects of the present invention are not limited to those described herein. The present invention may have other effects in addition to those described herein.

[0250] Furthermore, the present invention may also have the following configurations.

[0251] (1) A solid-state imaging device comprising:

[0252] Photoelectric conversion unit;

[0253] a first signal path including a first floating diffusion and a first amplifying transistor;

[0254] a second signal path including a second floating diffusion and a second amplifying transistor;

[0255] a mode switching switch portion, wherein in a first mode, the mode switching switch portion electrically connects the first signal path to the photoelectric conversion portion and electrically disconnects the second signal path from the photoelectric conversion portion, and in a second mode, the mode switching switch portion electrically connects both the first signal path and the second signal path to the photoelectric conversion portion;

[0256] a first substrate in which at least the photoelectric conversion portion among the photoelectric conversion portion, the first floating diffusion portion, the first amplifying transistor, the second floating diffusion portion, the second amplifying transistor, and the mode switching switch portion is formed; and

[0257] A second substrate is stacked on the first substrate, and in the second substrate, at least the photoelectric conversion unit, the first floating diffusion unit, the first amplifying transistor, the second floating diffusion unit, the second amplifying transistor and the second amplifying transistor among the mode switching switch unit are formed.

[0258] (2) The solid-state imaging device according to (1), wherein

[0259] The photoelectric conversion portion, the first floating diffusion portion, the second floating diffusion portion, and the mode switching portion are formed in the first substrate, and

[0260] The first amplifying transistor and the second amplifying transistor are formed in the second substrate.

[0261] (3) The solid-state imaging device according to (1), wherein

[0262] The photoelectric conversion portion, the first floating diffusion portion, the first amplifying transistor, the second floating diffusion portion, and the mode switching switch portion are formed in the first substrate, and

[0263] The second amplifying transistor is formed in the second substrate.

[0264] (4) The solid-state imaging device according to (1), wherein

[0265] The photoelectric conversion portion is formed in the first substrate, and

[0266] The first floating diffusion, the first amplifying transistor, the second floating diffusion, the second amplifying transistor, and the mode switching switch section are formed in the second substrate.

[0267] (5) The solid-state imaging device according to any one of (1) to (4), wherein an electrode of the transistor formed in the second substrate contains silicide.

[0268] (6) The solid-state imaging device according to any one of (1) to (5), further comprising a drive circuit that changes a drive current according to the size of a transistor switched by switching of the mode switching switch section.

[0269] (7) A solid-state imaging device comprising:

[0270] Photoelectric conversion unit;

[0271] a first signal path including a first floating diffusion and a first amplifying transistor;

[0272] a second signal path including a second floating diffusion and a second amplifying transistor;

[0273] a mode switching switch portion, wherein in a first mode, the mode switching switch portion electrically connects the first signal path to the photoelectric conversion portion and electrically disconnects the second signal path from the photoelectric conversion portion, and in a second mode, the mode switching switch portion electrically connects both the first signal path and the second signal path to the photoelectric conversion portion;

[0274] a first substrate in which the photoelectric conversion portion and the first floating diffusion portion are formed;

[0275] a second substrate stacked on the first substrate and in which the first amplifying transistor, the second floating diffusion, and the mode switching switch section are formed; and

[0276] a third substrate stacked on the second substrate and in which the second amplifying transistor is formed.

[0277] (8) The solid-state imaging device according to (7), wherein an electrode of each transistor formed in the second substrate and the third substrate contains silicide.

[0278] (9) An electronic device comprising:

[0279] a solid-state imaging device that outputs a pixel signal corresponding to incident light; and

[0280] a signal processing circuit, wherein the signal processing circuit processes the pixel signal,

[0281] The solid-state imaging device comprises:

[0282] Photoelectric conversion unit;

[0283] a first signal path including a first floating diffusion and a first amplifying transistor;

[0284] a second signal path including a second floating diffusion and a second amplifying transistor;

[0285] a mode switching switch portion, wherein in a first mode, the mode switching switch portion electrically connects the first signal path to the photoelectric conversion portion and electrically disconnects the second signal path from the photoelectric conversion portion, and in a second mode, the mode switching switch portion electrically connects both the first signal path and the second signal path to the photoelectric conversion portion;

[0286] a first substrate in which at least the photoelectric conversion portion among the photoelectric conversion portion, the first floating diffusion portion, the first amplifying transistor, the second floating diffusion portion, the second amplifying transistor, and the mode switching switch portion is formed; and

[0287] A second substrate is stacked on the first substrate, and in the second substrate, at least the photoelectric conversion unit, the first floating diffusion unit, the first amplifying transistor, the second floating diffusion unit, the second amplifying transistor and the second amplifying transistor among the mode switching switch unit are formed.

[0288] (10) An electronic device comprising:

[0289] a solid-state imaging device that outputs a pixel signal corresponding to incident light; and

[0290] a signal processing circuit, wherein the signal processing circuit processes the pixel signal,

[0291] The solid-state imaging device comprises:

[0292] Photoelectric conversion unit;

[0293] a first signal path including a first floating diffusion and a first amplifying transistor;

[0294] a second signal path including a second floating diffusion and a second amplifying transistor;

[0295] a mode switching switch portion, wherein in a first mode, the mode switching switch portion electrically connects the first signal path to the photoelectric conversion portion and electrically disconnects the second signal path from the photoelectric conversion portion, and in a second mode, the mode switching switch portion electrically connects both the first signal path and the second signal path to the photoelectric conversion portion;

[0296] a first substrate in which the photoelectric conversion portion and the first floating diffusion portion are formed;

[0297] a second substrate stacked on the first substrate and in which the first amplifying transistor, the second floating diffusion, and the mode switching switch section are formed; and

[0298] a third substrate stacked on the second substrate and in which the second amplifying transistor is formed.

[0299] According to the solid-state imaging device and electronic device of the first aspect of the present invention and the solid-state imaging device and electronic device of the second aspect of the present invention, the amplifier transistor to be used is selected according to the mode, and at least the amplifier transistor is formed on a substrate different from the substrate on which the photoelectric conversion portion is formed. Therefore, even in high-definition applications, both high sensitivity and high dynamic range can be achieved. It should be noted that the effects of this technology are not necessarily limited to the effects described herein, and any of the effects described herein can be achieved.

[0300] This application claims the benefit of Japanese Patent Application No. JP2018-213147 filed with the Japan Patent Office on November 13, 2018, and the entire contents of that Japanese Patent Application are hereby incorporated by reference.

[0301] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors, as long as these modifications, combinations, sub-combinations and alterations are within the scope of the appended claims or their equivalents.

Claims

1. A solid-state imaging device comprising: Photoelectric conversion unit; a first signal path including a first floating diffusion and a first amplifying transistor; a second signal path including a second floating diffusion and a second amplifying transistor; a mode switching switch portion, wherein in a first mode, the mode switching switch portion electrically connects the first signal path to the photoelectric conversion portion and electrically disconnects the second signal path from the photoelectric conversion portion, and in a second mode, the mode switching switch portion electrically connects both the first signal path and the second signal path to the photoelectric conversion portion; a first substrate in which the photoelectric conversion portion, the first floating diffusion portion, the second floating diffusion portion, and the mode switching portion are formed; as well as a second substrate stacked on the first substrate, and in which the first amplifying transistor and the second amplifying transistor are formed, When viewed in the stacking direction of the first substrate and the second substrate, a first region of the first substrate where the first floating diffusion, the second floating diffusion, and the mode switching portion are formed overlaps with a second region of the second substrate where the first amplifying transistor and the second amplifying transistor are formed. wherein the length of the first amplifying transistor is equal to the length of the second amplifying transistor, and the width of the second amplifying transistor is greater than the width of the first amplifying transistor, and The solid-state imaging device further includes a drive circuit that changes a drive current in accordance with the size of a transistor switched by switching of the mode switching switch section.

2. The solid-state imaging device according to claim 1, wherein An electrode of the transistor formed in the second substrate contains silicide.

3. The solid-state imaging device according to claim 1 , further comprising: A third substrate is stacked on the second substrate.

4. The solid-state imaging device according to claim 3, wherein An electrode of the transistor formed in the third substrate contains silicide.

5. An electronic device comprising: The solid-state imaging device according to any one of claims 1 to 4, wherein the solid-state imaging device outputs a pixel signal corresponding to incident light; and A signal processing circuit processes the pixel signal.

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