Bit-cell delay monitor based on ring oscillator

Abstract

Various implementations described herein refer to an integrated circuit having a row of bit cells linked in series to operate as a ring oscillator. Each bit cell in the row of bit cells has a plurality of transistors independent of additional transistors to form a ring oscillator. The plurality of transistors of each bit cell in the row of bit cells are arranged to function as inverters.

Description

[0001] Cross-references to related patent applications

[0002] This non-provisional patent application is related to a patent application entitled “SENSOR FOR PERFORMANCE VARIATION OF MEMORY READ AND WRITE CHARACTERISTICS” filed on November 7, 2018, with patent application number US16 / 183660, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to ring oscillator configurations in integrated circuits, and more particularly, to detecting bit cell delay characteristics for adaptive scaling of voltage, memory internal margining, and / or auxiliary settings. Background Art

[0004] This section is intended to provide information relevant to understanding the various technologies described herein. As the title of this section implies, this is a discussion of related art and should in no way be considered prior art. Generally speaking, related art may or may not be considered prior art. Therefore, it should be understood that any statement in this section should be understood in this sense and is not intended to be any admission of prior art.

[0005] Generally speaking, low leakage memory is an important feature for some Internet of Things (IoT) and embedded applications. This demand has led to ultra-low leakage (ULL) memory bit cells being provided by foundries in various related technologies. In order to minimize leakage, some conventional bit cell transistors use high threshold voltage devices, which can result in significant limitations on speed performance. Therefore, for IoT and embedded designs, the memory path can limit speed performance and therefore drive the use of more leaky high-speed transistors in logic to partially compensate for slow memory. Summary of the invention

[0006] The present invention provides an integrated circuit comprising a row of bit cells, the bit cells in the row of bit cells being linked together in series to operate as a ring oscillator, wherein each bit cell in the row of bit cells has a plurality of transistors arranged to function as an inverter, and wherein the plurality of transistors of each bit cell comprises an input transfer gate transistor and an output transfer gate transistor, the input transfer gate transistor and the output transfer gate transistor being bypassed by shorting the source terminal and the drain terminal of the input transfer gate transistor and shorting the source terminal and the drain terminal of the output transfer gate transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The specific implementations of various technologies are described herein with reference to the accompanying drawings. However, it should be understood that the accompanying drawings only illustrate various specific implementations described herein and are not intended to limit the implementation of the various technologies described herein.

[0008] Figures 1A to 1D Schematic diagrams of various bit cell circuits according to implementations described herein are shown.

[0009] FIG. 2A to FIG. 2B Schematic diagrams of various bit cell chain circuits according to implementations described herein are shown.

[0010] FIG. 3A to FIG. 3C A schematic diagram of a bit cell chain circuit with weak pull-ups according to implementations described herein is shown.

[0011] FIG. 4A to FIG. 4C A schematic diagram of a bit cell chain circuit with weak pull-down according to implementations described herein is shown.

[0012] FIG. 5A to FIG. 5D A schematic diagram of a bit cell chain circuit with weak pull-ups and weak pull-downs according to implementations described herein is shown.

[0013] Figure 6 A placed bit cell chain layout with configurable pull-up and pull-down behavior is shown according to a specific implementation described herein. DETAILED DESCRIPTION

[0014] Various specific implementations described herein relate to a ring oscillator configuration that detects bit cell delay characteristics for adaptive scaling of voltage, memory internal margins, and / or auxiliary settings. For example, various schemes and techniques described herein relate to configuring (or adjusting) a bit cell array to form a ring oscillator that is capable of determining a bit cell skew (including, for example, SF and FS process skew), which is used to analyze and evaluate bit cell performance and stability. In addition, the ring oscillator configuration can be used in a control loop scheme for a memory in a system using adaptive voltage scaling. In addition, the frequency and related frequency ratios between different types of ring oscillator configurations can be designed to provide information about the global skew of the bit cell transistor. This idea can also be used to determine the minimum safe supply voltage to perform read and write operations in a control loop for adaptive voltage scaling. In order to utilize adaptive voltage scaling (AVS) for memory, in addition to the skew of logic, a delay monitor can be used to provide information about the skew of the bit cell. One way to collect skew information is by measuring the frequency of a ring oscillator that is capable of detecting the skew between different types of switching devices within a memory bit cell. The ring oscillator can also operate as a delay chain without using a ring connection. This subject matter and various other features of the ring oscillator will be described in greater detail below.

[0015] Now refer to FIG. 1A to FIG. 5D Various implementations of multi-input logic circuits are described in more detail.

[0016] Figures 1A to 1D Schematic diagrams of various bit cell circuits according to specific implementations described herein are shown. Specifically, Figure 1A Schematic diagram 100A showing a 6T bit cell circuit 102, Figure 1B Schematic diagram 100B showing a 6T bit cell inverter circuit 112, Figure 1C A schematic diagram 100C is shown of a 6T bit cell inverter circuit 122, and Figure 1D A schematic diagram 100D of a 6T bit cell inverter circuit 132 is shown.

[0017] like Figure 1AAs shown, the 6T bit cell 102 may refer to a standard memory cell having some number (N) of transistors (T), such as, for example, 6 transistors (6T). The 6T bit cell 102 may be configured to store at least one data bit value (e.g., associated with storing logic 0 or 1). The 6T bit cell 102 may be referred to as a static random access memory (SRAM) cell, and thus the 6T bit cell 102 may be implemented as a multi-transistor SRAM cell. In some cases, various other types of SRAM cells may be used, such as, for example, 4T, 8T, 10T or more transistors (T) per bit. Generally speaking, an SRAM bit cell may be characterized as having at least two inverters coupled or configured back-to-back to form a latch that will hold data as long as power is applied to the power supply terminal. There may be any number of access devices, and the memory may support multiple single-track or dual-track bit lines. The unified application of this design is how to transform two inverters configured as a latch into a single inverter function. This concept will be explained by discussing the application to a standard 6T (transistor) SRAM bit cell. However, it is understood that it is applicable to any static RAM bit cell. In addition, as shown, the 6T bit cell 102 may include metal oxide semiconductor (MOS) transistors (M1, M2, M3, M4, M5, M6), which may include a combination of N-type MOS (NMOS) transistors and P-type MOS (PMOS) transistors. In this case, the 6T bit cell 102 may include 4 NMOS transistors (M1, M3, M5, M6) and 2 PMOS transistors (M2, M4), which are arranged to provide a latching function using back-to-back inverters (such as, for example, a first inverter (M3, M4) and a second inverter (M1, M2) which may be referred to as a feedback inverter). In this case, the first inverter (M3, M4) may be coupled between a voltage source (Vdd) and a ground (Vss, Gnd), and the second inverter (M1, M2) is also coupled between a voltage source (Vdd) and a ground (Vss, Gnd). In addition, the gates of transistors (M1, M2) are coupled to node Q, and the gates of transistors (M3, M4) are coupled to node QB. In addition, as shown, transistors (M5, M6) are arranged to operate as transfer gate transistors. In this case, transistor (M6) is coupled between node Q and a first bit line (BL) at node (n1), and transistor (M5) is coupled between node QB and a second bit line (BLB) at node (n2), wherein the second bit line (BLB) is complementary to the first bit line (BL). In addition, the gates of transistors (M5, M6) are coupled to a word line (WL), and transistors (M5, M6) are activated using a word line signal from the word line (WL).

[0018] like Figure 1B As shown, the 6T bit cell inverter 112 may have Figure 1A 102, except that the 6T bit cell inverter 112 may be arranged to have a modified (or changed) node connection. For example, the 6T bit cell inverter 112 may include a 6T bit cell that has been modified (or changed) to be used as an inverter. In this case, as shown in the figure, the second inverter (M1, M2) or the feedback inverter can be decoupled from the voltage source (Vdd) and the ground (Vss, Gnd), for example, by an open circuit formed between the transistor (M2) and the voltage source (Vdd) and / or another open circuit formed between the transistor (M1) and the ground (Vss, Gnd). In this case, as shown in the figure, this decoupling of the second inverter (M1, M2) or the feedback inverter from the voltage source (Vdd) and the ground (Vss, Gnd) is used to disable the second inverter (M1, M2). In some cases, the term "disable" may refer to disabling the operation (or function) of the second inverter (M1, M2), or rendering the second inverter (M1, M2) inoperable as an inverter. Additionally, in some cases, the transfer gate transistor (M5, M6) may be bypassed by shorting the source and drain. In some cases, the term "bypass" may refer to disabling the effective use of the transfer gate transistor (M5, M6) because the source and drain are shorted together and the gate of the transfer gate transistor (M5, M6) is thus disabled. Thus, during operation of the 6T bit cell inverter 112, with the second inverter (M1, M2) disabled and the transfer gate transistor (M5, M6) bypassed, the first inverter (M3, M4) inverts the signal passed from node n2 and provides an inverted signal at node n1 via node Q.

[0019] like Figure 1C As shown, the 6T bit cell inverter 122 may have Figure 1A The 6T bit cell 102 is similar to the layout in FIG. 1 , except that the 6T bit cell inverter 122 may be arranged to have a different Figure 1B The modified (or changed) node connections of the 6T bit cell inverter in FIG. Figure 1CThe 6T bit cell inverter 122 may include a 6T bit cell that has been modified (or changed) to function as an inverter, wherein the second inverter (M1, M2) or feedback inverter may be decoupled from node QB (no connection at node QB), wherein the coupling formed at node QB no longer exists. In this case, as shown, the transistor (M2) may be coupled to a voltage source (Vdd), and the transistor (M1) may be coupled to ground (Vss, Gnd). Further, in this case, as shown, this decoupling of the second inverter (M1, M2) or feedback inverter from node QB is used to disable the second inverter (M1, M2). Additionally, in some cases, the transfer gate transistors (M5, M6) may be bypassed by shorting the source and drain. Thus, in Figure 1C During operation of the 6T bit cell inverter 122, with the second inverter (M1, M2) disabled and the pass gate transistor (M5, M6) bypassed, the first inverter (M3, M4) inverts the signal passed from node n2 and provides an inverted signal at node n1 via node Q.

[0020] like Figure 1D As shown, the 6T bit cell inverter 132 may have Figure 1A The 6T bit cell 102 is similar to the layout in FIG. 1 , except that the 6T bit cell inverter 132 may be arranged to have Figure 1B to Figure 1C A combination of modified (or changed) node connections. For example, the 6T bit cell inverter 132 may include a 6T bit cell that has been modified (or changed) to function as an inverter so that the second inverter (M1, M2) is decoupled from the voltage source (Vdd) and ground (Vss, Gnd) and is also decoupled from the node QB (no connection at the node QB). In this case, as shown in the figure, such decoupling of the second inverter (M1, M2) from the voltage source (Vdd) and ground (Vss, Gnd) will disable the second inverter (M1, M2) in the absence of a connection at the node QB. In addition, in some cases, the transfer gate transistor (M5, M6) can be bypassed by shorting the source and drain. Thus, during operation of the 6T bit cell inverter 132, with the second inverter (M1, M2) disabled and the pass gate transistors (M5, M6) bypassed, the first inverter (M3, M4) inverts the signal passed from node n2 and provides an inverted signal at node n1 via node Q.

[0021] FIG. 2A to FIG. 2B 2 shows a schematic diagram of a bit cell chain circuit 202 according to a specific implementation described herein. Specifically, Figure 2A A schematic diagram 200A showing a first portion of a bit cell chain circuit 202 is shown, and Figure 2BAnother schematic diagram 200B shows a second portion of the bit cell chain circuit 202. In some implementations, the bit cell chain circuit 202 can be referred to as a bit cell inverter chain.

[0022] like FIG. 2A to FIG. 2B As shown, the combination of the first portion and the second portion of the bit cell inverter chain 202 provides a multi-6T bit cell inverter chain arranged to function as a ring oscillator. In some cases, the bit cell inverter chain 202 includes a row of bit cells (112A, 112B, ..., 112N) linked together in series to operate as a ring oscillator. Each bit cell in the row of bit cells (112A, 112B, ..., 112N) may have multiple transistors (M1, M2, ..., M6) that are independent of additional transistors to form a ring oscillator. The term "independent" may be defined as one or more or all of the transistors used to form the ring oscillator are bit cell transistors and their electrical characteristics are unchanged compared to transistors in a bit cell used for data storage purposes, such as Figure 1A In addition, the plurality of transistors (M1, M2, ..., M6) of each bit cell in the bit cell row (112A, 112B, ..., 112N) are arranged to function as inverters, such as, for example Figures 1B to 1D Furthermore, each bit cell in the bit cell row (112A, 112B, ..., 112N) may be implemented with a static random access memory (SRAM) bit cell, such as, for example, a standard SRAM bit cell.

[0023] In some cases, each bit cell in the bit cell row (112A, 112B, ..., 112N) may refer to a standard bit cell (or memory cell), and the plurality of transistors (M1, M2, ..., M6) of each bit cell may be implemented with a predetermined number of transistors. Figures 1B to 1D As described, a first number of transistors (e.g., M3, M4) of the plurality of transistors (M1, M2, ..., M6) of each bit cell may be arranged to function as inverters, and a second number of transistors (e.g., M1, M2) of the plurality of transistors (M1, M2, ..., M6) may be disabled, and in addition, a third number of transistors (e.g., M5, M6) may be bypassed. In addition, the first number of transistors (M3, M4) and the second number of transistors (M1, M2) of the plurality of transistors (M1, M2, ..., M6) of each bit cell may be arranged as back-to-back inverters, wherein one of the inverters (e.g., M1, M2) is disabled, thereby disabling the latching function of each bit cell.

[0024] In some implementations, the effective electrical characteristics of the plurality of transistors (M1, M2, ..., M6) of each bit cell remain unchanged, and the effective electrical characteristics maintain the driving strength of each transistor in the plurality of transistors (M1, M2, ..., M6) unchanged. In some cases, the driving strength of each transistor may refer to its current carrying capacity and threshold voltage. In some cases, the front-end layer of each transistor remains unchanged, thereby maintaining the driving strength unchanged. In addition, in some cases, each front-end layer attempts to modify only the connectivity of the transistors in the circuit while maintaining the transistor strength or current carrying capacity unchanged. In addition, in some cases, the back-end layer (e.g., a layer higher than the contact) may modify or attempt to modify only the connectivity of the transistors in the circuit while maintaining the transistor strength or current carrying capacity unchanged. Since the disabled or bypassed devices and / or wires can increase the capacitance, they can still contribute to the timing characteristics of the bit cell inverter (112A, 112B, ..., 112N). Furthermore, the ring oscillator configuration may be adapted from a bit cell for data storage purposes by modifying conductive connections within each bit cell in the bit cell row (112A, 112B, . . . , 112N) to detect bit cell delay characteristics of the bit cell row (112A, 112B, . . . , 112N).

[0025] In various cases, the bit cell row (112A, 112B, ..., 112N) includes an odd number of bit cells to form a ring oscillator, for example, wherein the output (OUT) of the last bit cell (112N) is coupled to the input (IN) of the first bit cell (112A) so as to cause the bit cell row (112A, 112B, ..., 112N) to operate as a ring oscillator. In this case, the signal provided from the output (OUT) of the last bit cell (112N) to the input (IN) of the first bit cell (112A) may be referred to as a feedback signal (FB). Additionally, in some cases, the bit cell row (112A, 112B, ..., 112N) may form part of an odd number of inverting stages to form a ring oscillator, wherein the output of the last inverting stage is coupled to the input of the first inverting stage so as to cause the bit cell row to operate as a ring oscillator. Alternative implementations may cause one of the inverting stages or the inversion to be an enable function that starts the ring oscillator function. This inversion stage used for the enable function can be in the same row as the other bit cells, or it can be just outside the bit cell area and in a peripheral circuit in line with the bit cell row. The inversion stage can have the feedback signal FB from the last inversion bit cell structure as one of the inputs. In addition, in some cases, each bit cell in the bit cell row (112A, 112B, ..., 112N) arranged to operate as an inverter has an input coupled to a bit line (e.g., BL) and an output coupled to another bit line (e.g., BLB) that is complementary to the bit line (e.g., BL).

[0026] In some specific implementations, as described above with reference to Figure 1B As described, the plurality of transistors (M1, M2, ..., M6) of each bit cell in the bit cell row (112A, 112B, ..., 112N) may include a first pair of transistors (M3, M4) and a second pair of transistors (M1, M2). In this case, the second pair of transistors (M1, M2) may be disabled by cutting off the second pair of transistors (M1, M2) from a voltage source (Vdd) and ground (Vss, Gnd) to make them inoperable, and the first pair of transistors (M3, M4) may be adapted to operate as an inverter. In other specific implementations, as described above with reference to Figure 1C As described, the multiple transistors (M1, M2, ..., M6) of each bit cell in the bit cell row (112A, 112B, ..., 112N) may include a first pair of transistors (M3, M4) and a second pair of transistors (M1, M2), wherein the second pair of transistors (M1, M2) may be disabled to be inoperable by cutting off the output node (QB) of the second pair of transistors (M1, M2) from the gates of the first pair of transistors (M3, M4), and the first pair of transistors (M3, M4) may be adapted to operate as inverters.

[0027] Furthermore, in some implementations, the plurality of transistors (M1, M2, ..., M6) of each bit cell in the bit cell row (112A, 112B, ..., 112N) include one or more transmission gate transistors (M5, M6) that are bypassed so as not to operate as transmission gates. Additionally, in this case, the one or more transmission gate transistors (M5, M6) may be bypassed by shorting the source terminal and the drain terminal of the one or more transmission gate transistors (M5, M6). In some cases, as described in more detail herein, the bit cell row (112A, 112B, ..., 112N) may include a plurality of bit cell rows coupled in parallel.

[0028] FIG. 3A to FIG. 3C 302 according to a specific implementation described herein. Specifically, Figure 3A A schematic diagram 300A shows a first portion of a bit cell chain circuit 302 having a weak pull-up configuration, and Figure 3B Another schematic diagram 300B of a second portion of a bit cell chain circuit 302 with a weak pull-up configuration is shown. Figure 3C A bit cell chain circuit 302 using a power switch (M7) is shown. The bit cell chain circuit 302 may be referred to as a bit cell inverter chain with a weak pull-up circuit.

[0029] like FIG. 3A to FIG. 3B As shown, the combination of the first portion and the second portion of the bit cell inverter chain 302 provides a multi-6T bit cell inverter chain arranged in a first row (row_1) that is arranged to function as a ring oscillator with a weak pull-up circuit arranged in a second row (row_2). The first bit cell row (112A-1, 112B-1, ..., 112N-1) of row_1 may be arranged to operate as a ring oscillator, and the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) of row_1 are arranged to function as inverters. Additionally, the second bit cell row (112A-2, 112B-2, ..., 112N-2) of row_2 may be coupled in parallel to the first bit cell row (112A-1, 112B-1, ..., 112N-1), and the second bit cell row (112A-2, 112B-2, ..., 112N-2) is arranged to provide a pull-down circuit for the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1). The pull-down circuit in row_2 is coupled in parallel with the inverter circuit in row_1, such that the combined circuit of row_1 and row_2 functions as a weak pull-up circuit. As such, each bit cell in the second bit cell row (112A-2, 112B-2, ..., 112N-2) is arranged to provide a pull-down circuit for each corresponding bit cell in the first bit cell row (112A-1, 112B-1, ..., 112N-1), wherein the net result of the combined circuits provides a weak pull-up configuration.

[0030] In some implementations, the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_1 is similar in scope, functionality, and operation to the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_2. FIG. 2A to FIG. 2B The multi-6T bit cell inverter chain 202 as a ring oscillator is similar. FIG. 2A to FIG. 2B As described in the first bit cell row (112A-1, 112B-1, ..., 112N-1), the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) include a plurality of transistors (M1, M2, ..., M6), wherein a first number of transistors (M3, M4) of the plurality of transistors (M1, M2, ..., M6) are arranged to function as inverters. In addition, a second number of transistors (M1, M2, ..., M6) of the plurality of transistors (M1, M2, ..., M6) are disabled, and in some cases, a third number of transistors (M5, M6) of the plurality of transistors (M1, M2, ..., M6) may be bypassed.

[0031] Additionally, in some implementations, the bit cells in the second bit cell row (112A-2, 112B-2, ..., 112N-2) include a p-type transistor (PMOS) and an n-type transistor (NMOS). In some cases, the switching of the p-type transistors (PMOS: M2, M4) in the bit cells of the second bit cell row (112A-2, 112B-2, ..., 112N-2) can be disabled, for example, as shown without being connected to a voltage source (Vdd). In this case, the PMOS transistors (M2, M4) can be decoupled from the voltage source (Vdd) and the NMOS transistor (M1) can also be decoupled from ground (Vss, Gnd). Additionally, in this case, the NMOS transistor (M3) remains coupled to ground (Vss, Gnd) to provide a pull-down circuit when IN2 of row_2 is enabled (or activated). Additionally, the bit cells in the second bit cell row (112A-2, 112B-2, . . . , 112N-2) may include power switches (eg, Figure 3C For example, Figure 3C As shown, at least one power switch transistor (M7) may be used to enable (or activate) the pull-down circuit in row_2 using another enable signal (EN2), wherein the local ground Vss2 may be coupled to ground (Vss, Gnd) through M7.

[0032] Furthermore, in some implementations, the first bit cell row (112A-1, 112B-1, ..., 112N-1) may include a plurality of first bit cell rows, and the second bit cell row (112A-2, 112B-2, ..., 112N-2) may include a plurality of second bit cell rows coupled in parallel with the plurality of first bit cell rows. In this case, the plurality of parallel pull-down circuits may be adjusted to achieve an effective increase in the effective pull-down strength of the first bit cell row (112A-1, 112B-1, ..., 112N-1) by adding second pull-down transistors (M3) in the second bit cell row (112A-2, 112B-2, ..., 112N-2) of similar strength to the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1). In some cases, the effective increase in the effective pull-down strength may refer to an effective doubling (e.g., 2X) of the effective pull-down strength. In other cases, adding additional rows may further increase the pull-down strength.

[0033] FIG. 4A to FIG. 4C 4 shows a schematic diagram of a bit cell chain circuit with a weak pull-down 402 according to a specific implementation described herein. Specifically, Figure 4A A schematic diagram 400A shows a first portion of a bit cell chain circuit 402 having a weak pull-down configuration, and Figure 4B Another schematic diagram 400B of a second portion of a bit cell chain circuit 402 having a weak pull-down configuration is shown. Figure 4C A bit cell chain circuit 402 using a power switch (M8) is shown. The bit cell chain circuit 402 may be referred to as a bit cell inverter chain with a weak pull-down circuit.

[0034] like FIG. 4A to FIG. 4B As shown, the combination of the first portion and the second portion of the bit cell inverter chain 402 provides a multi-6T bit cell inverter chain disposed in a first row (row_1) that is arranged to function as a ring oscillator with a weak pull-down circuit disposed in a second row (row_2). The first bit cell row (112A-1, 112B-1, ..., 112N-1) of row_1 may be arranged to operate as a ring oscillator, and the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) of row_1 are arranged to function as inverters. Additionally, the second bit cell row (112A-2, 112B-2, ..., 112N-2) of row_2 may be coupled in parallel to the first bit cell row (112A-1, 112B-1, ..., 112N-1), and the second bit cell row (112A-2, 112B-2, ..., 112N-2) is arranged to provide a pull-up circuit for the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1). The pull-up circuit in row_2 is coupled in parallel with the inverter circuit in row_1, such that the combined circuit of row_1 and row_2 functions as a weak pull-down circuit. Thus, each bit cell in the second bit cell row (112A-2, 112B-2, ..., 112N-2) is arranged to provide a pull-up circuit for each corresponding bit cell in the first bit cell row (112A-1, 112B-1, ..., 112N-1), wherein the net result of the combined circuits provides a weak pull-down configuration.

[0035] In some implementations, the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_1 is similar in scope, functionality, and operation to the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_2. FIG. 2A to FIG. 2B The multi-6T bit cell inverter chain 202 as a ring oscillator is similar. FIG. 2A to FIG. 2BAs described in the first bit cell row (112A-1, 112B-1, ..., 112N-1), the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) include a plurality of transistors (M1, M2, ..., M6), wherein a first number of transistors (M3, M4) in the plurality of transistors (M1, M2, ..., M6) are arranged to function as inverters. In addition, a second number of transistors (M1, M2, ..., M6) in the plurality of transistors (M1, M2, ..., M6) are disabled, and in some cases, a third number of transistors (M5, M6) in the plurality of transistors (M1, M2, ..., M6) may be bypassed.

[0036] Additionally, in some implementations, the bit cells in the second bit cell row (112A-2, 112B-2, ..., 112N-2) include a p-type transistor (PMOS) and an n-type transistor (NMOS). In some cases, the switching of the n-type transistors (NMOS: M1, M3) in the bit cells of the second bit cell row (112A-2, 112B-2, ..., 112N-2) can be disabled, for example, as shown without connection to ground (Vss, Gnd). In this case, the NMOS transistors (M1, M3) can be decoupled from ground (Vss, Gnd) and the PMOS transistor (M2) can also be decoupled from the voltage source (Vdd). Additionally, in this case, the PMOS transistor (M4) remains coupled to the voltage source (Vdd) to provide a pull-up circuit when IN2 of row_2 is enabled (or activated). In addition, the bit cells in the second bit cell row (112A-2, 112B-2, ..., 112N-2) may include a power switch (PMOS M8) that is enabled to selectively activate the pull-up circuit in row_2. For example, the enable circuit may be similar to Figure 3C The enabling circuit shown in FIG. Figure 4C As shown, at least one power switch transistor M8 may be used as a power switch to enable (or activate) the pull-up circuit in row_2 using another enable signal (EN3), wherein the local power supply Vdd2 may be coupled to Vdd through M8.

[0037] Furthermore, in some implementations, the first bit cell row (112A-1, 112B-1, ..., 112N-1) may include a plurality of first bit cell rows, and the second bit cell row (112A-2, 112B-2, ..., 112N-2) may include a plurality of second bit cell rows coupled in parallel with the plurality of first bit cell rows. In this case, the plurality of parallel pull-up circuits may be adjusted to achieve an effective increase in the effective pull-up strength of the first bit cell row (112A-1, 112B-1, ..., 112N-1) by adding the second pull-up transistors (M4) in the second bit cell row (112A-2, 112B-2, ..., 112N-2) of similar strength to the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1). In some cases, the effective increase in the effective pull-up strength may refer to an effective doubling (e.g., 2X) of the effective pull-up strength.

[0038] FIG. 5A to FIG. 5D Schematic diagram of a bit cell chain circuit with weak pull-up and weak pull-down according to some specific implementations described herein. Specifically, Figure 5A Schematic diagram 500A showing a first portion of a bit cell chain circuit 502, Figure 5B Another schematic diagram 500B showing a second portion of a bit cell chain circuit 502, Figure 5C Another schematic diagram 500C shows a third portion of the bit cell chain circuit 502, and Figure 5D Another schematic diagram 500D is shown of a fourth portion of the bit cell chain circuit 502. In some implementations, the bit cell chain circuit 502 can be configured as a bit cell inverter chain with weak pull-up circuits and weak pull-down circuits.

[0039] like FIG. 5A to FIG. 5DAs shown, the combination of the first portion, the second portion, the third portion, and the fourth portion of the bit cell inverter chain 502 provides a multi-6T bit cell inverter chain arranged in a first row (row_1), the multi-6T bit cell inverter chain being arranged to operate as a ring oscillator, wherein a weak pull-up circuit is arranged in a second row (row_2), and a weak pull-down circuit is arranged in a third row (row_3). The first bit cell row (112A-1, 112B-1, ..., 112N-1) of row_1 can be arranged to operate as a ring oscillator, and the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) of row_1 are arranged to function as inverters. The second bit cell row (112A-2, 112B-2, ..., 112N-2) of row_2 can be coupled in parallel to the first bit cell row (112A-1, 112B-1, ..., 112N-1), and the second bit cell row (112A-2, 112B-2, ..., 112N-2) is arranged to selectively provide a pull-down circuit for the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1). The third bit cell row (112A-3, 112B-3, ..., 112N-3) of row_3 may be coupled in parallel to the first bit cell row (112A-1, 112B-1, ..., 112N-1) and the second bit cell row (112A-2, 112B-2, ..., 112N-2), and the third bit cell row (112A-3, 112B-3, ..., 112N-3) is arranged to selectively provide a pull-up circuit for the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1). In some specific implementations, as Figure 5B As shown (similar to Figure 3C ), the pull-down circuit of row_2 can be selectively enabled by activating the power switch M7 (eg, NMOS) using the enable signal (EN2), and also as Figure 5D As shown (similar to Figure 4C ), the pull-up circuit of row_3 can be selectively enabled using an enable signal (EN3) by activating a power switch M8 (eg, PMOS).

[0040] In some implementations, the pull-down circuit in row_2 is coupled in parallel with the inverter circuit in row_1 such that the combined circuit of row_1 and row_2 functions as a weak pull-up circuit. In this way, each bit cell in the second bit cell row (112A-2, 112B-2, ..., 112N-2) is arranged to selectively provide a pull-down circuit for each corresponding bit cell in the first bit cell row (112A-1, 112B-1, ..., 112N-1), wherein the net result of the combined circuit provides a weak pull-up oscillator configuration.

[0041] Additionally, in some implementations, the pull-up circuit in row_3 is coupled in parallel with the inverter circuit in row_1 such that the combined circuit of row_1 and row_3 functions as a weak pull-down circuit. Thus, each bit cell in the third bit cell row (112A-3, 112B-3, ..., 112N-3) is arranged to selectively provide a pull-up circuit for each corresponding bit cell in the first bit cell row (112A-1, 112B-1, ..., 112N-1), wherein the net result of the combined circuits provides a weak pull-down oscillator configuration.

[0042] In some implementations, the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_1 is similar in scope, functionality, and operation to the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_2. FIG. 2A to FIG. 2B , 112N-2) includes a PMOS and an NMOS, wherein the switching of the PMOS transistors (M2, M4) in the bit cells of the second bit cell row (112A-2, 112B-2, ..., 112N-2) can be disabled, for example, as shown without being connected to a voltage source (Vdd). In addition, the bit cells in the third bit cell row (112A-3, 112B-3, ..., 112N-3) include a PMOS and an NMOS, wherein the switching of the NMOS transistors (M1, M3) in the bit cells of the third bit cell row (112A-3, 112B-3, ..., 112N-3) can be disabled, for example, as shown without being connected to a ground (Vss, Gnd).

[0043] As described above, the bit cells in the second bit cell row (112A-2, 112B-2, ..., 112N-2) may include at least one pull-down transistor (M3) that is enabled to selectively activate the pull-down circuit in row_2. Additionally, as described above, the bit cells in the third bit cell row (112A-3, 112B-3, ..., 112N-3) may include at least one pull-up transistor (M4) that is enabled to selectively activate the pull-up circuit in row_3. In some cases, the first bit cell row (112A-1, 112B-1, ..., 112N-1) may include a plurality of first bit cell rows, the second bit cell row (112A-2, 112B-2, ..., 112N-2) may include a plurality of second bit cell rows coupled in parallel with the plurality of first bit cell rows, and the third bit cell row (112A-3, 112B-3, ..., 112N-3) may include a plurality of third bit cell rows coupled in parallel with the plurality of first bit cell rows and the plurality of second bit cell rows. In this case, the parallel pull-down circuits in row_2 may be adjusted to achieve an effective increase in the effective pull-down strength of the first bit cell row (112A-1, 112B-1, ..., 112N-1) by adding the second pull-down transistor (M3) in the second bit cell row (112A-2, 112B-2, ..., 112N-2) of similar strength to the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1). In addition, the parallel pull-down circuits in row_3 may be adjusted to achieve an effective increase in the effective pull-down strength of the first bit cell row (112A-1, 112B-1, ..., 112N-1) by adding the third pull-down transistor (M4) in the third bit cell row (112A-3, 112B-3, ..., 112N-3) of similar strength to the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1).

[0044] In some cases, a power switch M7 (NMOS) external to the inverter chain allows enabling the row with a connection to M3 to activate the pull-down circuit. In addition, in some cases, a power switch M8 (PMOS) external to the inverter chain allows enabling the row with a connection to M4 to activate the pull-up circuit.

[0045] refer to FIG. 5A to FIG. 5B, the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_1 are arranged to operate (or function) as inverters, so the chain of bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_1 operates (or functions) as a ring oscillator. In row_2, the source of each pull-up transistor (M2, M4) is decoupled from the source (Vdd), which means that the bit cells in the second bit cell row (112A-2, 112B-2, ..., 112N-2) can only be pulled down, but not pulled up. Therefore, the ring modified (or changed) in this way has a weak pull-up and a strong pull-down, and therefore, the ring frequency is more sensitive to the weaker pull-up PMOS transistor (M4). In row_3, the source of each pull-down transistor (M1, M3) is decoupled (or disconnected) from ground (Vss, Gnd), which means that the bit cells in the third bit cell row (112A-3, 112B-3, ..., 112N-3) can only be pulled up, but not pulled down. Therefore, the ring modified (or changed) in this way has a weak pull-down and a strong pull-up, and therefore, the ring frequency is more sensitive to the weaker pull-down NMOS transistor (M3).

[0046] In some specific implementations, FIG. 5A to FIG. 5D Will FIG. 3A to FIG. 3B and FIG. 4A to FIG. 4B into a single configuration. The first row (Row_1) is arranged as a ring oscillator with Vdd and ground (Vss, Gnd) connections on all bit cells. The second row (Row_2) is arranged to have a pull-down configuration, i.e., so as to provide an overall weak pull-up configuration without an internal connection to Vdd. The third row (Row_3) is arranged to have a pull-up configuration, i.e., so as to provide an overall weak pull-down configuration without an internal connection to ground (Vss, Gnd). In addition, in some cases, if the source-drain short is removed, the pass gate transistors (M5, M6) in Row_1, Row_2, and Row_3 can be used to replace the power switches M7 and M8 to enable all rows with corresponding gate enable signals (EN, EN_WUP, and EN_WDN). This circuit scheme provides a compact layout for testing as a bit cell ring oscillator together with a weak pull-up configuration and / or a weak pull-down configuration. Therefore, in some cases, a RAM monitor designed in this manner can be integrated with a ring oscillator for supervising logic devices in an AVS. Additionally, a RAM monitor can provide information about the global skew of multiple RAM instances.

[0047] In some implementations, the bit cells in the first bit cell row (112A-1, 112B-1, ..., 112N-1) in row_1 can be omitted. In this case, at least one row with a pull-down configuration and at least one row with a pull-up configuration can replace the function of the inverter of row_1. Figure 6 A placed bit cell chain layout 600 with configurable pull-up and pull-down behavior along with a power switch 602 is shown according to a specific implementation described herein. For example, Figure 6 The combined and configurable pull-up and pull-down arrangements are shown, along with the power switches (PS2, PSN) in the row to enable them.

[0048] Figure 6 Shown according to FIG. 5A to FIG. 5D A fully arranged bit cell oscillator in which the first bit cell row arranged to operate (or function) as an inverter has been omitted. The columns within this arrangement form the stages (or delay chains) of the oscillator. The rows are configured to pull down or pull up, respectively. The cell placement is the same as that used to form a memory array for storage purposes using mirrored adjacent bit cells. The connections to Vdd and Vss are typically arranged to run within a row or column or vice versa. In order to enable the inverting stage for the ring or delay chain, at least one pull down row must be connected to Vss. Figure 6 The case where Vss runs in the row direction and is shared between adjacent bit cells is shown. In this case, the Vdd connection is shared within the array and the Vss connection can be enabled for pairs of rows. The selection of enabled rows controls the overall balance of pull-down and pull-up strengths of the inverting stages formed in each column of the array. It should be understood that any source running in the row direction can be used to select the relative strengths and therefore the stage delays providing pull-up or pull-down to the sensitivity of the transistor.

[0049] In addition, reference Figure 6 , the placement of the array forming the bit cell oscillator is the same as the bit cell array for data storage purposes, whereby one or more or all of the modifications provide additional connections to bypass or provide removal of connections to disable the functionality of certain transistors of the bit cell. These modifications can be made in process layers that do not affect the electrical characteristics of the transistors within the bit cell. The process layers that form the transistor devices and determine their electrical characteristics, commonly referred to as the front end layers (FEOL), are the same for the modified bit cells described herein and the bit cells for data storage purposes. The FEOL typically includes all CMOS process layers up to the contact level. The layer that can provide the connection modifications of the bit cell outlined above can be the interconnect level above the contacts, typically metal and vias.

[0050] In some specific implementations, such as Figure 6As shown, the first bit cell row (row_1) can be arranged to operate as a pull-up circuit, and the second bit cell row (row_2) can be coupled in parallel with the first bit cell row. In this case, the second bit cell row (row_2) can be arranged to provide a pull-down circuit for the bit cells in the first bit cell row so as to form a ring oscillator. In addition, the third bit cell row (row_N) can be coupled in parallel with the second bit cell row (row_2), and the third bit cell row (row_N) can be arranged to operate as a ring oscillator. In this case, the bit cells in the first bit cell row (row_1) and the second bit cell row (row_2) can be arranged to be used as inverters, whereby row one can only provide the pull-up function of the inverter, and row two can provide the pull-down function of the inverter. In addition, the first bit cell row (row_1) and the second bit cell row (row_2) can include multiple bit cell rows, and at least one of the power supply (VDD) and the ground (VSS) can be coupled to the multiple bit cell rows using one or more enable switches. Furthermore, in some cases, logic gates (eg, NAND gate (A1)) may be used to selectively enable the entire structure 602 or specific components of the structure 602, such as one or more rows of the structure 602 (eg, row_1, row_2, . . . , row_N).

[0051] Various implementations of integrated circuits are described herein. The integrated circuit may include a row of bit cells linked in series to operate as a ring oscillator. Each bit cell in the row of bit cells may have a plurality of transistors independent of additional transistors to form a ring oscillator. The plurality of transistors of each bit cell in the row of bit cells are arranged to function as inverters.

[0052] Various implementations of integrated circuits are described herein. The integrated circuit may include a first bit cell row arranged to operate as a ring oscillator, and the bit cells in the first bit cell row may be arranged to function as inverters. The integrated circuit may include a second bit cell row coupled in parallel to the first bit cell row, and the second bit cell row may be arranged to provide a pull-down circuit for the bit cells in the first bit cell row.

[0053] Various implementations of integrated circuits are described herein. The integrated circuit may include a first bit cell row arranged to operate as a ring oscillator, and the bit cells in the first bit cell row may be arranged to function as inverters. The integrated circuit may include a second bit cell row coupled in parallel to the first bit cell row, and the second bit cell row may be arranged to provide pull-up circuits for the bit cells in the first bit cell row.

[0054] It is contemplated that the subject matter of the claims is not limited to the specific implementations and illustrations provided herein, but rather includes modifications of those specific implementations according to the claims, including portions of specific implementations and combinations of elements of different specific implementations. It should be understood that in the development of any such specific implementation, as in any engineering or design project, many specific implementation-specific decisions should be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary between different specific implementations. In addition, it should be understood that such development work may be complex and time consuming, but is nevertheless a routine task of design, manufacture, and production for a person of ordinary skill having the benefit of this disclosure.

[0055] Reference has been made in detail to various specific implementations, examples of which are shown in the accompanying drawings and diagrams. In the following specific description, many specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other cases, well-known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the details of the embodiments.

[0056] It should also be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The first element and the second element are both elements, but they are not considered to be the same element.

[0057] The terms used in the description of the disclosure provided herein are for the purpose of describing a specific implementation, and are not intended to limit the disclosure provided herein. As used in the disclosure provided herein and the description of the appended claims, the singular forms "one", "a kind of" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. As used herein, the term "and / or" refers to and encompasses any and all possible combinations of one or more of the associated listed items. When used in this specification, the terms "include", "comprise" and / or "contain" specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups.

[0058] As used herein, the term "if" may be interpreted to mean "when" or "at" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined that..." or "if [the condition or event] is detected" may be interpreted to mean "upon determining..." or "in response to determining..." or "upon detecting [the condition or event]," or "in response to detecting [the condition or event]," depending on the context. The terms "up" and "down"; "upper" and "lower"; "upwardly" and "downwardly"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in conjunction with some specific implementations of the various techniques described herein.

[0059] While the foregoing is directed to specific implementations of the various techniques described herein, other and additional implementations are contemplated based on the disclosure herein, which may be determined by the appended claims.

[0060] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as exemplary forms of implementing the claims.

Claims

1. An integrated circuit, comprising: a row of bit cells, the bit cells in the row of bit cells being linked together in series to operate as a ring oscillator, wherein each bit cell in the row of bit cells has a plurality of transistors arranged to function as an inverter, and The plurality of transistors of each bit cell include an input transfer gate transistor and an output transfer gate transistor, the input transfer gate transistor and the output transfer gate transistor being bypassed by shorting the source terminal and the drain terminal of the input transfer gate transistor and shorting the source terminal and the drain terminal of the output transfer gate transistor.

2. The integrated circuit of claim 1, wherein each bit cell in the bit cell row is a standard bit cell, and wherein the plurality of transistors of each bit cell is implemented with a predetermined number of transistors.

3. The integrated circuit of claim 1 , wherein a first number of the plurality of transistors of each bit cell are arranged to function as the inverter, and wherein a second number of the plurality of transistors are disabled, and wherein a third number of the plurality of transistors are bypassed.

4. The integrated circuit of claim 3 , wherein the first number of transistors and the second number of transistors of the plurality of transistors of each bit cell are arranged as back-to-back inverters, wherein one of the back-to-back inverters is disabled so as to disable a latching function of each bit cell.

5. The integrated circuit of claim 1, wherein an effective electrical characteristic of the plurality of transistors of each bit cell remains unchanged, and wherein the effective electrical characteristic maintains a strength of each transistor of the plurality of transistors unchanged.

6. The integrated circuit of claim 1, wherein the ring oscillator is configured to detect a bit cell delay characteristic of the row of bit cells by modifying a conductive connection within each bit cell in the row of bit cells.

7. The integrated circuit of claim 1 , wherein the row of bit cells forms part of an odd number of inversion stages to form the ring oscillator, wherein the output of a last inversion stage is coupled to the input of a first inversion stage to cause the row of bit cells to operate as the ring oscillator.

8. The integrated circuit of claim 1, wherein each bit cell in the row of bit cells arranged to operate as the inverter has an input coupled to a bit line and an output coupled to another bit line complementary to the bit line.

9. The integrated circuit of claim 1 , wherein the plurality of transistors of each bit cell in the row of bit cells comprises a first pair of transistors and a second pair of transistors, and wherein the second pair of transistors are disabled so as to be inoperable by disconnecting output nodes of the second pair of transistors from gates of the first pair of transistors, and wherein the first pair of transistors are adapted to operate as the inverter.

10. The integrated circuit of claim 1, wherein the bit cell row comprises a plurality of bit cell rows coupled in parallel.

11. The integrated circuit of claim 1, wherein each bit cell in the bit cell row is implemented using a static random access memory (SRAM) bit cell.

12. The integrated circuit of claim 1 , wherein the plurality of transistors of each bit cell in the row of bit cells comprises a first pair of transistors and a second pair of transistors, and wherein the first pair of transistors are disabled so as to be inoperable by being disconnected from a voltage source and ground, and wherein the second pair of transistors are adapted to operate as the inverter.

13. The integrated circuit of claim 1 , wherein the bit cell rows include a first bit cell row, and wherein the integrated circuit further includes a second bit cell row coupled in parallel with the first bit cell row, and wherein each bit cell in the second bit cell row is arranged to provide a pull-down circuit for each corresponding bit cell in the first bit cell row.

14. The integrated circuit of claim 13, wherein the first bit cell row comprises a plurality of first bit cell rows, and wherein the second bit cell row comprises a plurality of second bit cell rows coupled in parallel with the first bit cell row.

15. The integrated circuit of claim 1 , wherein the bit cell rows include a first bit cell row, and wherein the integrated circuit further includes a second bit cell row coupled in parallel with the first bit cell row, and wherein each bit cell in the second bit cell row is arranged to provide a pull-up circuit for each corresponding bit cell in the first bit cell row.

16. The integrated circuit of claim 15, wherein the first bit cell row comprises a plurality of first bit cell rows, and wherein the second bit cell row comprises a plurality of second bit cell rows coupled in parallel with the first bit cell row.

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