Bit error rate balancing method and device, reading method and device

Abstract

The present invention provides a bit error rate balancing method and device, and a reading method and device. In an embodiment of the present invention, a first-level encoding is performed on part of the original data to obtain j first code words. A two-level encoding method is used for other original data: after the first-level encoding process, J‑j second code words are obtained, and a modification operation is performed on the data of the J‑j page logical page corresponding to the first bit unit group in the J‑j second code words and the j first code words to balance the bit error rate of each logical page. After performing the modification operation, the first bit unit group is modified into the second bit unit group, and the distribution state combinations of the G bit units in the first bit unit group and the second bit unit group correspond to the first distribution state combination set and the second distribution state combination set, respectively. Compared with the distribution state combinations in the first distribution state combination set, the distribution state combinations in the second distribution state combination set can balance the bit error rate of each logical page to a certain extent.

Description

Technical Field

[0001] The present invention relates to the technical field of non-volatile memory, and in particular to a bit error rate balancing method and device, and a reading method and device. Background Art

[0002] NAND flash is a non-volatile storage architecture used in SSDs and memory cards.

[0003] A typical NAND flash memory consists of multiple blocks, each of which consists of multiple physical pages. Each page corresponds to a word line (WL) and consists of multiple storage units (the smallest storage granularity). The physical page is the unit of reading and writing, which means that writing or reading data to or from the NAND flash memory must be done in pages.

[0004] Among them, TLC NAND flash memory is a type of NAND. A storage unit of TLC NAND can store 3 bits, and these 3 bits belong to different logical pages: upper page, middle page, and lower page. That is, one physical page corresponds to three virtual pages.

[0005] The 3-bit Gray code has multiple distribution states (E to P7) as shown in Table 1 below.

[0006] E P1 P2 P3 P4 P5 P6 P7 Lower page 1 0 0 0 0 1 1 1 Middle page 1 1 0 0 1 1 0 0 Upper page 1 1 1 0 0 0 0 1

[0007] Table 1

[0008] Before writing data to a physical page, the original data is encoded and stored. When the bit error rate of any page of data in the Upper Page, Middle Page, or Lower Page reaches the upper limit of the error correction capability, the data in the Upper Page, Middle Page, or Lower Page needs to be read out for error correction, and then re-encoded and written after error correction.

[0009] The error rates of the Upper Page, Middle Page, and Lower Page are unbalanced. Figure 1 When the Upper Page reaches the error correction limit, when the Upper page bit error rate rises to the error correction capacity limit, it is necessary to perform read error correction and then write operations. At this time, the bit error rates of the Middle page and the Lower Page are still low, and the error correction capacity is wasted. Summary of the invention

[0010] In view of this, embodiments of the present invention provide a bit error rate balancing method and device, and a reading method and device to achieve balancing of the bit error rates of different logical pages.

[0011] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0012] A bit error rate balancing method, comprising:

[0013] Get J blocks of raw data; J is the total number of logical pages;

[0014] Using a first preset encoding algorithm to encode j blocks of original data, to obtain j first codewords; the j blocks of original data correspond to j logical pages in a first logical page group; wherein j is a positive integer less than J; and the length of the first codeword is L;

[0015] The Jj blocks of original data are encoded using a second preset encoding algorithm to obtain Jj second code words; the Jj blocks of original data correspond to the Jj logical pages in the second logical page group; the length of the second code word is S; S is less than L; the first S bits of data of the j first code words and the Jj second code words correspond to data of the same storage unit as a bit unit; each bit unit includes J bits of data;

[0016] According to the distribution state of the bit unit, a first bit unit group is determined; the first bit unit group includes: G bit units corresponding to G consecutive storage units on the same channel, and the distribution state combination of the G bit units is a distribution state combination in the first distribution state combination set; G is a natural number;

[0017] A modification operation is performed on the data of the Jj page logical page in the first bit unit group to balance the bit error rate of each logical page, and Jj third code words are obtained; wherein, after performing the modification operation, the first bit unit group is modified into a second bit unit group; and the distribution state combination of the G bit units in the second bit unit group is a distribution state combination in a second distribution state combination set;

[0018] The Jj third code words are encoded using a third preset encoding algorithm to obtain Jj fourth code words; the length of the fourth code words is L;

[0019] The j first code words and Jj fourth code words are written into a nonvolatile memory.

[0020] A reading method for reading data written by the above method;

[0021] The reading method comprises:

[0022] Acquire J blocks of data corresponding to each logical page in the nonvolatile memory, where J is the total number of logical pages;

[0023] Based on a universal log-likelihood probability LLR value, decoding and error correction processing are performed on j blocks of data corresponding to j logical pages in the first logical page group using a decoding algorithm corresponding to the first preset encoding algorithm to obtain the j blocks of original data;

[0024] Based on the common LLR value, decode and correct the Jj block data corresponding to the Jj page logical page in the second logical page group using a decoding algorithm corresponding to the third preset encoding algorithm to obtain the Jj third code words;

[0025] Predicting the bit positions of the data changed by performing the modification operation in the Jj third codewords; the predicted bit positions are unreliable bit positions, and the other bit positions are reliable bit positions;

[0026] Set the LLR value of the unreliable bit position to 0;

[0027] The LLR value corresponding to the reliable bit position with data value 1 is -10, and the LLR value corresponding to the reliable bit position with data value 0 is 10;

[0028] Based on the LLR value of each bit position, a decoding algorithm corresponding to the second preset encoding algorithm is used to decode and error correct the Jj third code words to obtain Jj blocks of original data.

[0029] A bit error rate balancing device, comprising:

[0030] A first acquisition unit is used to acquire J blocks of original data, where J is the total number of logical pages;

[0031] The first encoding unit is used for:

[0032] Using a first preset encoding algorithm to encode j blocks of original data, to obtain j first codewords; the j blocks of original data correspond to j logical pages in a first logical page group; wherein j is a positive integer less than J; and the length of the first codeword is L;

[0033] The second encoding unit is used for:

[0034] The Jj blocks of original data are encoded using a second preset encoding algorithm to obtain Jj second codewords; the Jj blocks of original data correspond to the Jj logical pages in the second logical page group; the length of the second codeword is S; S is less than L; the first S bits of data of the j first codewords and the S bits of data of the Jj second codewords, data corresponding to the same storage unit is a bit unit; each bit unit includes J bits of data;

[0035] According to the distribution state of the bit unit, a first bit unit group is determined; the first bit unit group includes: G bit units corresponding to G consecutive storage units on the same channel, and the distribution state combination of the G bit units is a distribution state combination in the first distribution state combination set; G is a natural number;

[0036] A modification operation is performed on the data of the Jj page logical page in the first bit unit group to balance the bit error rate of each logical page, and Jj third code words are obtained; wherein, after performing the modification operation, the first bit unit group is modified into a second bit unit group; and the distribution state combination of the G bit units in the second bit unit group is a distribution state combination in a second distribution state combination set;

[0037] The Jj third code words are encoded using a third preset encoding algorithm to obtain Jj fourth code words; the length of the fourth code words is L;

[0038] The j first code words and Jj fourth code words are written into a nonvolatile memory.

[0039] A reading device for reading data written by the above method;

[0040] The reading device comprises:

[0041] The second acquisition unit is used for:

[0042] Acquire J blocks of data in the non-volatile memory, where J is the total number of logical pages;

[0043] The first decoding unit is used for:

[0044] Based on a universal log-likelihood probability LLR value, decoding and error correction processing are performed on j blocks of data corresponding to j logical pages in the first logical page group using a decoding algorithm corresponding to the first preset encoding algorithm to obtain the j blocks of original data;

[0045] The second decoding unit is used for:

[0046] Based on the universal log-likelihood probability LLR value, the Jj block data corresponding to the Jj page logical page in the second logical page group is decoded and error corrected by using a decoding algorithm corresponding to the third preset encoding algorithm to obtain the Jj third codewords;

[0047] Predicting the bit positions of the data changed by performing the modification operation in the Jj third codewords; the predicted bit positions are unreliable bit positions, and the other bit positions are reliable bit positions;

[0048] Set the LLR value of the unreliable bit position to 0;

[0049] The LLR value corresponding to the reliable bit position with data value 1 is -10, and the LLR value corresponding to the reliable bit position with data value 0 is 10;

[0050] Based on the LLR value of each bit, a decoding algorithm corresponding to the second preset encoding algorithm is used to decode and error correct the Jj third code words to obtain Jj blocks of original data.

[0051] It can be seen that in the embodiment of the present invention, a part of the original data is first-level encoded to obtain j first code words. A two-level encoding method is used for other original data: after the first-level encoding process, Jj second code words are obtained, and a modification operation is performed on the data of the Jj page logical page corresponding to the first bit unit group in the Jj second code words and the j first code words to balance the bit error rate of each logical page. After performing the modification operation, the first bit unit group is modified to the second bit unit group, and the distribution state combination of the G bit units in the second bit unit group is the distribution state combination in the second distribution state combination set, and the distribution state combination of the G bit units in the first bit unit group is the distribution state combination in the first distribution state combination set. Compared with the distribution state combination in the first distribution state combination set, the distribution state combination in the second distribution state combination set can balance the bit error rate of each logical page to a certain extent, thereby delaying the occurrence time of the read-out error correction and re-write operation.

[0052] It should be noted that the present invention introduces a third code word by modifying the error on the basis of the second code word, and encodes it again to obtain the fourth code word. As time goes by, other errors may occur in the bits of the fourth code word. When reading data, other errors will be corrected after the first decoding of the Jj block data corresponding to the Jj page logical page, and Jj third code words will be obtained.

[0053] Decoding is an error correction process based on LLR values. In the third codeword, there are no other errors except the modification error, so the bit position where the modification error is located can be predicted and regarded as an unreliable position, and the other bit positions can be regarded as reliable bit positions. Because there are no errors in other bit positions, their LLR values ​​can be set to 10 or -10, and the LLR values ​​of unreliable bit positions can be set to 0.

[0054] In the second decoding process, the general LLR value is no longer used for error correction processing, but error correction is performed based on the LLR value set as above, so as to achieve a more accurate error correction effect and correct the modification error introduced by the embodiment of the present invention during encoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1This is a schematic diagram of bit error rate imbalance;

[0056] Figure 2a A schematic diagram of the lateral diffusion effect provided by an embodiment of the present invention;

[0057] Figure 2b A schematic diagram of the mutual influence between storage units provided in an embodiment of the present invention;

[0058] Figure 2c A schematic diagram of the structure of a solid-state drive provided by an embodiment of the present invention;

[0059] Figure 3a , Figure 4a An exemplary process of a bit error rate balancing method provided by an embodiment of the present invention;

[0060] Figure 3b , Figure 4b An exemplary process of a reading method provided by an embodiment of the present invention;

[0061] Figure 3c A schematic diagram of a confidence interval provided by an embodiment of the present invention;

[0062] Figure 5 A schematic diagram of the structure of a bit error rate balancing device provided by an embodiment of the present invention;

[0063] Figure 6 A schematic diagram of the structure of a reading device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0064] NAND flash memory is divided into SLC (Single-Level Cell) NAND flash memory, MLC (Double-Level Cell) NAND flash memory and TLC (Triple-Level Cell) NAND flash memory.

[0065] A storage unit of TLC NAND can store 3 bits, and these 3 bits belong to different logical pages: upper page, middle page, and lower page. That is, one physical page corresponds to three virtual pages.

[0066] See also Figure 2a TLC NAND flash memory adopts a "shared charge storage layer (Share Silicon)" structure, which simplifies the process while bringing about a lateral diffusion (Lateral spreading) effect: if data is written to a block, then for the storage cells corresponding to adjacent word lines (Word Line) on the same channel, if the stored charge difference is large, it will cause an obvious lateral diffusion effect, and then cause a significant increase in the bit error rate of the corresponding storage cell.

[0067] Taking the P6 state as an example, Figure 2b The bit error rate of adjacent word lines in the same channel is shown in the state of E to P7. It can be seen that if the information stored in the adjacent WL is E, the bit error rate of P6 is obviously much higher than that of the adjacent WL when the information stored is P7.

[0068] See also Figure 2b According to statistics, when WL(n) (word line n) stores the P6 state, if the information stored in WL(n+1) is the E state, the bit error rate of P6 is much higher than the bit error rate of the adjacent P7 state. At the same time, because of the programming order (programming starts from WL(0)), WL(n+1) has a greater impact on WL(n) than WL(n-1).

[0069] Since the threshold distribution of the high state (such as the P7 state) will be more severely broadened and drift faster during the storage process due to the lateral diffusion effect and longitudinal decoupling, the overlap between the high state distribution states will be more serious. If the Gray code encoding method in Table 1 is used for data writing, the errors caused by the overlap of the P7 and P6 states are borne by the Upper Page, and the errors caused by the overlap of the P6 and P5 states are borne by the Middle Page. The errors caused by these high states are often more than the errors caused by the overlap of other states, resulting in different error growth rates of the three logical pages in the TLC, which in turn leads to an imbalance in the bit error rate between logical pages.

[0070] In order to solve the above problem, the present invention provides a bit error rate balancing method and device to achieve balancing of the bit error rates of different logical pages.

[0071] See also Figure 2c The above-mentioned device may specifically be an ECC (Error Checking and Correcting) module in a solid state drive (Solid State Disk or Solid State Drive, referred to as SSD), or a controller (including an ECC module and a read-write controller) in an SSD.

[0072] The data to be written into NAND from the PC (personal computer) will be processed by the ECC module and then written into NAND by the read / write controller. When data needs to be read, the read / write controller can read the data from NAND, hand it over to the ECC module for decoding, and then provide it to the PC.

[0073] Figure 3a An exemplary process of the above-mentioned bit error rate balancing method is shown, which may include:

[0074] S0: Get J blocks of original data.

[0075] J is the total number of logical pages, which is a positive integer. Taking SLC as an example, J=1, taking MLC as an example, J=2, and taking TLC as an example, J=3. The length of each block of original data is K.

[0076] S1: Use a first preset encoding algorithm to encode j blocks of original data to obtain j first code words.

[0077] When encoding, it is encoded separately according to logical pages.

[0078] The j blocks of original data in this step correspond to the j logical pages in the first logical page group (where j is a positive integer less than J).

[0079] The first preset coding algorithm may be a BCH (Bose-Chaudhuri-Hocquenghem) coding algorithm, an LDPC (low-density parity-check, LDPC) coding algorithm, or the like.

[0080] In one example, the LDPC (9872, 8192) encoding algorithm may be used for encoding.

[0081] It should be noted that, in LDPC (9872, 8192), 9872 is the codeword length, that is, L; 8192 is the length of the data information in the codeword; the LDPC (9872, 8192) check information length is 1680.

[0082] The length K of the data block mentioned above is equal to the length of the data information supported by the coding algorithm. If LDPC (9872, 8192) is used, the value of K is 8192.

[0083] S2: Use a second preset encoding algorithm to encode Jj blocks of original data to obtain Jj second code words.

[0084] Steps S1 and S2 are executed in parallel.

[0085] The original data of block Jj corresponds to the logical page Jj in the second logical page group. This article will later introduce how to determine the first logical page group and the second logical page group.

[0086] The length of the second codeword is S, which is smaller than the length L of the first codeword.

[0087] In one example, an LDPC (8962, 8192) encoding algorithm may be used for encoding, and S=8962.

[0088] The first 8962 bits of the j first code words and the Jj second code words can be observed, a total of 8962*J bits.

[0089] Among these 8962*J bits, the data corresponding to the same storage unit is a bit unit, and each bit unit includes J bits of data.

[0090] The J bits of data correspond to a distribution state, and the J bits in a bit unit belong to J logical pages respectively.

[0091] For TLC NAND flash memory, J=3, that is, a bit unit includes 3 bits belonging to different logical pages: Upper Page, Middle Page and Lower Page. The number of bits contained in a bit unit is exactly the storage capacity of a TLC NAND storage unit.

[0092] In the TLC mode, the Gray code distribution states (E to P7) of 3 bits of a bit unit are shown in Table 2 below.

[0093] E P1 P2 P3 P4 P5 P6 P7 Lower page 1 0 0 0 0 1 1 1 Middle page 1 1 0 0 1 1 0 0 Upper page 1 1 1 0 0 0 0 1

[0094] Table 2

[0095] The second code word may be represented by DP1.

[0096] S3: Determine a first bit unit group according to the distribution state of the bit units.

[0097] The first bit unit group includes: G bit units corresponding to G consecutive storage units located on the same channel, and the distribution state combination corresponding to the G consecutive bit units matches the first distribution state combination set.

[0098] G is a positive integer. Taking G=3 as an example, each first bit unit group includes three bit units corresponding to three consecutive storage units located on the same channel, and the distribution state combination corresponding to these three bit units is a distribution state combination in the first distribution state combination set.

[0099] by Figure 2a For example, the memory cells corresponding to the word lines WL(n+3), WL(n+2), and WL(n+1) on the same channel can constitute a memory cell group, and the bit cell group corresponding to the memory cell group can be called cell group n+2; the memory cells corresponding to the word lines WL(n+2), WL(n+1), and WL(n) on the same channel can constitute a memory cell group, and the bit cell group corresponding to the memory cell group can be called cell group n+1; similarly, the memory cells corresponding to the word lines WL(n+1), WL(n), and WL(n-1) on the same channel can also constitute a memory cell group, and the bit cell group corresponding to the memory cell group can be called cell group n.

[0100] Assuming that the distribution state combination corresponding to the unit group n is a distribution state combination in the first distribution state combination set, then the unit group n is the first bit unit group.

[0101] This article will introduce the first distribution state combination set in detail later.

[0102] S4: performing a modification operation on the data of the first bit unit group corresponding to the Jj-page logical page to balance the bit error rate of each logical page, and obtaining Jj third code words.

[0103] From the perspective of the bit unit group, after the modification, the first bit unit group (such as the aforementioned unit group n) is modified into the second bit unit group, and the distribution state combination corresponding to the second bit unit group is the distribution state combination in the second distribution state combination set. The second distribution state combination set will be described in detail later in this article.

[0104] From the codeword perspective, the data corresponding to the Jj page logical page is actually the data in the Jj second codewords. Therefore, this step is to modify the data in the Jj second codewords to obtain Jj third codewords. The third codeword can be represented by DalgPalg.

[0105] S5: Encode the Jj third code words using a third preset encoding algorithm to obtain Jj fourth code words.

[0106] The fourth code word can be represented by DalgPalgP2, and the length of the fourth code word is L, which is the same as the first code word.

[0107] The second preset coding algorithm may be a BCH coding algorithm, an LDPC coding algorithm, or the like.

[0108] In an example, the third preset coding algorithm may specifically be LDPC (9872, 8962).

[0109] S6: Write the j first code words and Jj fourth code words into the non-volatile memory.

[0110] The first codeword and the fourth codeword have the same length and will be written into the NAND flash memory together. They can be written in the existing writing method, which will not be described in detail here.

[0111] Step S5 can be performed by Figure 2c The read-write controller in is executed.

[0112] That is, in this embodiment, some original data blocks are encoded once, and some original data blocks are encoded twice, and the data are modified during the encoding process.

[0113] For the corresponding Figure 3b, after storing the third codeword into the non-volatile memory, the written data can be read in the following manner:

[0114] S7: Acquire J blocks of data corresponding to each logical page in the nonvolatile memory.

[0115] If the length of the first code word and the fourth code word is 9872, the length of the acquired data may be 9872*J.

[0116] It should be noted that as time goes by, other errors will occur in the bits of the codeword, so the data obtained is not the same as when it was stored. alg P′ alg P'2 represents the fourth code word in which an error occurs. The same is true for the first code word.

[0117] S8: Based on a common LLR (log-likelihood probability) value, the j blocks of data corresponding to the j logical pages in the first logical page group are decoded and error corrected using a decoding algorithm corresponding to the aforementioned first preset encoding algorithm to obtain j blocks of original data.

[0118] During the encoding process, the original data corresponding to the first logical page group is encoded using a first preset encoding algorithm. Therefore, in this step, the data corresponding to the first logical page group is decoded and error corrected using a corresponding decoding algorithm to obtain j blocks of original data.

[0119] Now let’s briefly introduce LLR.

[0120] LLR reflects confidence and reliability. During decoding, LLR values ​​are used for error correction.

[0121] Taking single-level cell (SLC) flash memory as an example, LLR is briefly introduced. SLC is a NAND flash memory architecture, and each storage cell stores one bit of data. Therefore, the distribution state of the data in its storage cell is E state and P state.

[0122] For SLC, the data will be read three times, each time using a different voltage, and the read data will be divided into four areas, such as Figure 3c As shown, the four regions are E_L, E_H, P_L, and P_H (where E represents the E state, P represents the P state, L represents low confidence, and H represents high confidence). According to the LLR definition of SLC:

[0123] The LLRs in different regions correspond to different LLRs, reflecting different confidence levels and reliability.

[0124] As shown in Table 3 below, Table 3 is a schematic table of the probabilities of the bit data in the E_H region, the E_L region, the P_L region, and the P_H region being 0 or 1. For the bit data in the E_H region, the probability of 0 (P0) is 0.01, and the probability of 1 (P1) is 0.99; for the bit data in the E_L region, the probability of 0 is 0.12, and the probability of 1 is 0.88; for the bit data in the P_L region, the probability of 0 is 0.8, and the probability of 1 is 0.2; for the bit data in the P_H region, the probability of 0 is 0.99, and the probability of 1 is 0.01.

[0125] E_H E_L P_L P_H <![CDATA[P0]]> 0.01 0.12 0.8 0.99 <![CDATA[P1]]> 0.99 0.88 0.2 0.01 LLR -6.63 -2.87 2 6.63

[0126] Table 3

[0127] For TLC, the number of reading times when reading data is greater and the number of divided areas is greater. The general LLR value of TLC can be obtained by looking up the table, which will not be described in detail here.

[0128] S9: Based on the common LLR value, decode and correct the Jj block data corresponding to the Jj page logical page in the second logical page group using a decoding algorithm corresponding to the aforementioned third preset encoding algorithm to obtain Jj third code words.

[0129] Step S9 corresponds to the aforementioned step S5.

[0130] During the encoding process, the original data corresponding to the second logical page group is encoded twice, so the decoding also needs to be performed twice, and the first decoding is to obtain the third code word.

[0131] S10: Predicting the bit positions of the data in the Jj third code words that are changed due to the above modification operation.

[0132] The predicted bit positions are unreliable bit positions, and the other bit positions are reliable bit positions.

[0133] S11: setting the LLR value of the unreliable bit position to 0, setting the LLR value corresponding to the reliable bit position with a data value of 1 to -10, and setting the LLR value corresponding to the reliable bit position with a data value of 0 to 10.

[0134] In the third codeword, there are no other errors except the modification error, so the bit position where the modification error is located can be predicted and used as an unreliable bit position, and the other bit positions are reliable bit positions (because no error will occur). Therefore, in this embodiment, the LLR value of the reliable bit position can be set to 10 or -10, and the LLR value of the unreliable bit position can be set to 0.

[0135] S12: Based on the LLR value of each bit position, the Jj third code words are decoded and error corrected by using a decoding algorithm corresponding to the second preset encoding algorithm to obtain Jj blocks of original data.

[0136] The Jj blocks of original data and the j blocks of original data obtained in step S8 are the final results of decoding and can be output to the PC.

[0137] It can be seen that in the embodiment of the present invention, a part of the original data is first-level encoded to obtain j first code words. A two-level encoding method is used for other original data: after the first-level encoding process, Jj second code words are obtained, and the data corresponding to the Jj page logical page in the first bit unit group of the Jj second code words and the j first code words is modified to balance the bit error rate of each logical page. After performing the modification operation, the first bit unit group is modified to the second bit unit group, and the distribution state combination of the G bit units in the second bit unit group is the distribution state combination in the second distribution state combination set, and the distribution state combination of the G bit units in the first bit unit group is the distribution state combination in the first distribution state combination set. Compared with the distribution state combination in the first distribution state combination set, the distribution state combination in the second distribution state combination set can balance the bit error rate of the Upper Page, the Middle Page, and the Lower Page to a certain extent, thereby delaying the occurrence time of the read-out error correction and re-write operation.

[0138] It should be noted that the present invention introduces a third code word by modifying the error on the basis of the second code word, and encodes it again to obtain the fourth code word. As time goes by, other errors may occur in the bits of the fourth code word. When reading data, other errors will be corrected after the first decoding of the Jj block data corresponding to the Jj page logical page, and Jj third code words will be obtained.

[0139] Decoding is an error correction process based on LLR values. In the third codeword, there are no other errors except the modification error, so the bit position where the modification error is located can be predicted and regarded as an unreliable position, and the other bit positions can be regarded as reliable bit positions. Because there are no errors in other bit positions, their LLR values ​​can be set to 10 or -10, and the LLR values ​​of unreliable bit positions can be set to 0.

[0140] Taking G=3 as an example, the following focuses on how to determine the first distribution state combination set and the second distribution state combination set.

[0141] This application determines the first distribution state combination set and the second distribution state combination set based on the data modification evaluation model, and the establishment steps are as follows:

[0142] Step 1: define three memory cells corresponding to three adjacent WLs on a channel as a memory cell group.

[0143] Step 2: Calculate the bit error rate of the storage unit group corresponding to each distribution state combination in the codeword group:

[0144] The codeword group here includes the first S bits of data of the j first codewords and the Jj second codewords.

[0145] Taking a certain distribution combination ABD as an example, the three storage cells in each corresponding storage cell group are represented by WL(n+1), WL(n), and WL(n-1), respectively, and WL(n) is adjacent to WL(n+1) and WL(n-1), respectively.

[0146] ABD can also be referred to as the first to third distribution states, respectively.

[0147] In an example, the bit error rate Error Rate (ABD, t) of ABD at a predetermined time t may be calculated using the following calculation formula:

[0148] Error Rate(ABD,t)=Error Num(ABD,t) / Total Num(ABD).

[0149] The predetermined time t is the estimated data retention time. Those skilled in the art can flexibly design the time t according to actual conditions, which will not be elaborated here.

[0150] Error Num(ABD,t) represents the number of storage unit groups whose distribution state combination is ABD but errors occur at time t, and Total Num(ABD) represents the total number of storage unit groups whose distribution state combination is ABD.

[0151] Assume that ABD is to be modified to ACD. ABD can be regarded as the initial distribution state combination, and ACD can be regarded as the target distribution state combination. Taking TLC as an example, each distribution state of A, B, C, and D is any one of the states from E to P7, but ABD is different from ACD, that is, B is different from C, and C can also be called the fourth distribution state.

[0152] Similarly, the bit error rate of ACD at the predetermined time t is Error Rate (ACD, t) = Error Num (ACD, t) / Total Num (ACD).

[0153] The bit error rate calculation method of other distribution states at a predetermined time is similar to this and will not be described in detail here.

[0154] Step 3: Calculate the bit error rate change of WL(n) before and after modification:

[0155] The bit error rate change of WL(n) = Error Rate(ABD,t)-Error Rate(ACD,t).

[0156] That is, the bit error rate change of WL(n) is the difference between the initial distribution state combination and the target distribution state combination (which may be referred to as the first bit error rate difference).

[0157] Step 4: Calculate the bit error rate change of WL(n-1) before and after the modification:

[0158] When calculating the bit error rate change of WL(n-1) before and after the modification, WL(n-1) is used as an intermediate storage unit.

[0159] Before the modification, the distribution state of the storage unit group with WL(n-1) as the intermediate storage unit can be expressed as: XAB, and the distribution state X represents any distribution state.

[0160] XAB can be regarded as a distribution state combination set (which can be called the third distribution state combination set). Taking the TLC mode as an example, 0 corresponds to the E state, 1 corresponds to the P1 state, and so on. Then XAB may include: 0AB, 1AB, 2AB, 3AB, 4AB, 5AB, 6AB, and 7AB.

[0161] After modification, the distribution state of the storage unit group with WL(n-1) as the middle storage unit can be expressed as: XAC.

[0162] Similarly, XAC can be regarded as a distribution state combination set (which can be called the fourth distribution state combination set). Taking the TLC mode as an example, XAC may include: 0AC, 1AC, 2AC, 3AC, 4AC, 5AC, 6AC, and 7AC.

[0163] Assume that the bit error rate of WL(n-1) before modification is expressed as Error Rate aver(AB, t) or ERaver1, then

[0164] Error Rateaver(AB,t)=average(∑ X∈[0,7] Error Rate(XAB,t));

[0165] That is, the bit error rates of 0AB, 1AB, 2AB, 3AB, 4AB, 5AB, 6AB, and 7AB at the predetermined time t are added together and the average value is taken as Error Rate aver (AB, t).

[0166] Assume that the bit error rate of WL(n-1) after modification is expressed as Error Rate aver(AD, t) or ERaver2, then

[0167] Error Rateaver(AD,t)=average(∑ X∈[0,7] Error Rate(XAD,t)).

[0168] That is, the bit error rates of 0AC, 1AC, 2AC, 3AC, 4AC, 5AC, 6AC, and 7AC at the predetermined time t are added together and the average value is taken as Error Rate aver (AD, t).

[0169] Bit error rate variation of WL(n-1)=Error Rate aver(XAB)-Error Rate aver(XAC).

[0170] The bit error rate variation of WL(n-1) may be referred to as a second bit error rate difference.

[0171] Step 5: Calculate the bit error rate change of WL(n+1) before and after the modification:

[0172] When calculating the bit error rate change of WL(n+1) before and after the modification, WL(n+1) is also used as an intermediate storage unit.

[0173] Before modification, the distribution state of the storage cell group with WL(n+1) as the middle storage cell can be expressed as BDY, and the distribution state Y represents the distribution states from E to P7.

[0174] BDY can be regarded as a distribution state combination set (which can be called the fifth distribution state combination set). Taking the TLC mode as an example, 0 corresponds to the E state, 1 corresponds to the P1 state, and so on. Then BDY may include: BD0, BD1, ... BD7.

[0175] After modification, the distribution state of the storage unit group with WL(n-1) as the intermediate storage unit can be expressed as: BCY.

[0176] Similarly, BCY can be regarded as a distribution state combination set (which can be called the sixth distribution state combination set). Taking the TLC mode as an example, CDY can include: CD0, CD1, ... CD7.

[0177] The bit error rate at time tWL(n+1) before modification is represented by Error Rate aver(BDY) or ERaver3, and the bit error rate at time tWL(n+1) after modification is represented by Error Rate aver(CDY) or ERaver4, then:

[0178] The bit error rate variation of WL(n+1)=Error Rate aver(BDY)-Error Rate aver(CDY).

[0179] The bit error rate variation of WL(n+1) may be referred to as a third bit error rate difference.

[0180] Step 6: Calculate the change gain (change ABD to ACD):

[0181] Change gain = bit error rate change of WL(n) + bit error rate change of WL(n-1) + bit error rate change of WL(n+1).

[0182] The data modification evaluation model calculated for a certain codeword group is shown in Table 4 below. Each line in Table 4 is a data modification evaluation result, including an initial distribution state combination, a target distribution state combination, a bit error rate gain, etc.:

[0183]

[0184] Table 4

[0185] Taking the first row in Table 4 as an example, the initial distribution state combination is: 070 (that is, E state, P7 state, E state), the bit error rate is 0.45, and the target distribution state combination is 000 (that is, E state, E state, E state), that is, the distribution state of WL(k) is changed from P7 state to E state. It can be seen from Table 1 that the data on the Middle page is changed from "0" to "1".

[0186] In the first row of Table 4, the bit error rate of the target distribution state combination is equal to 0; the bit error rate gain of WL(n) is negative 0.447, indicating that the bit error rate of WL(n) is reduced by 0.447; the bit error rate gain of WL(n-1) is positive 0.002, indicating that the bit error rate of WL(n-1) is increased by 0.002; the bit error rate gain of WL(n+1) is positive 0.001, indicating that the bit error rate of WL(n+1) is increased by 0.001; the total gain is negative 0.444.

[0187] Based on the above Table 4, the data modification evaluation results that meet the preset conditions can be used as the target data modification evaluation results, the initial distribution state combination in the target data modification evaluation results can be placed into the first distribution state combination set, and the target distribution state combination in the target data modification evaluation results can be placed into the second distribution state combination set.

[0188] In one example, the preset condition may include: the gain is high, and the modified logical page is a lower page (that is, the aforementioned second logical page group includes the lower page).

[0189] For example, the first distribution state combination set may include any one or more of the following:

[0190] The first combination: E state, P7 state, E state, corresponding to 070 in Table 4;

[0191] The second combination: E state, P7 state, P1 state, corresponding to 071 in Table 4;

[0192] The third combination: P1 state, P7 state, E state, corresponding to 170 in Table 4;

[0193] The fourth combination: P2 state, P7 state, E state, corresponding to 270 in Table 4;

[0194] The fifth combination: P1 state, P7 state, P1 state, corresponding to 171 in Table 4;

[0195] The sixth combination: P2 state, P7 state, P1 state, corresponding to 271 in Table 4;

[0196] The seventh combination: P4 state, P7 state, E state, corresponding to 470 in Table 4;

[0197] The eighth combination: P1 state, P7 state, P2 state, corresponding to 172 in Table 4.

[0198] The second distribution state combination set may include at least one of the following combinations:

[0199] The ninth combination: E state, P2 state, E state, corresponding to 020 in Table 4;

[0200] The tenth combination: E state, P2 state, P1 state, corresponding to 021 in Table 4;

[0201] The eleventh combination: P1 state, P2 state, E state, corresponding to 120 in Table 4;

[0202] The twelfth combination: P2 state, E state, E state, corresponding to 200 in Table 4;

[0203] The thirteenth combination: P1 state, P2 state, P1 state, corresponding to 121 in Table 4;

[0204] The fourteenth combination: P2 state, P2 state, P1 state, corresponding to 221 in Table 4;

[0205] The fifteenth combination: P4 state, P2 state, E state, corresponding to 420 in Table 4;

[0206] The sixteenth combination: P1 state, P2 state, P2 state, corresponding to 122 in Table 4.

[0207] Based on Table 4 above, see Figure 4a , an exemplary method of bit error rate balancing may include the following steps:

[0208] S40: Obtain J blocks of original data;

[0209] S40 is the same as the aforementioned step S0 and will not be described in detail here.

[0210] S41: Encode the original data corresponding to the Upper page and the Middle page using the LDPC (9872, 8192) encoding algorithm to obtain the first codewords corresponding to the Upper page and the Middle page respectively.

[0211] S41 is similar to the aforementioned step S1 and will not be described in detail here.

[0212] S42: Encode the original data corresponding to the Lower page using an LDPC (8962, 8192) encoding algorithm to obtain a second codeword corresponding to the Lower page.

[0213] Please refer to the above records for the LDPC (8962, 8192) coding algorithm, which will not be elaborated here.

[0214] S43: According to the distribution states of the bit units, determine a bit unit group whose distribution states are combined into a first combination to an eighth combination as a first bit unit group.

[0215] Specifically, a bit unit group whose distribution states are combined into 070, 071, 170, 270, 171, 271, 470 and 172 may be determined as the first bit unit group.

[0216] The concept of bit unit group can be found in the above description and will not be elaborated here.

[0217] S44: modifying the bit data of the Lower Page of the bit cells whose distribution state of the first bit cell group is the first preset distribution state from 1 to 0.

[0218] In this embodiment, the first preset distribution state is the P7 state, and after modification, the P7 state becomes the P2 state, that is, the aforementioned second preset distribution state is specifically the P2 state.

[0219] After the modification, the first bit unit becomes the above-mentioned second bit unit, and the Jj second code words become Jj third code words.

[0220] The operations can be summarized as follows:

[0221] 070--->020[1;1;1;1;0;1;1;1;1]--->[1;1;1;0;0;1;1;1;1]

[0222] 071--->021[1;1;1;1;0;1;0;1;1]--->[1;1;1;0;0;1;0;1;1;1]

[0223] 170--->120[0;1;1;1;0;1;1;1;1]--->[0;1;1;0;0;1;1;1;1;1]

[0224] 270--->220[0; 0; 1; 1; 0; 1; 1; 1]--->[0; 0; 1; 0; 0; 1; 1; 1; 1]

[0225] 171--->121[0;1;1;1;0;1;0;1;1]--->[0;1;1;0;0;1;0;1;0;1;1]

[0226] 271--->221[0; 0; 1; 1; 0; 1; 0; 1; 1]--->[0; 0; 1; 0; 0; 1; 0; 1; 1]

[0227] 470--->420[0;1;0;1;0;1;1;1;1]--->[0;1;0;0;0;1;1;1;1;1]

[0228] 172--->122[0;1;1;1;0;1;0;0;1]--->[0;1;1;0;0;1;0;0;1;0;1]

[0229] S45: Encode the Jj third code words using an LDPC (9872, 8962) encoding algorithm to obtain Jj fourth code words.

[0230] The third code word can be represented by DalgPalgP2.

[0231] Step S45 is the same as the aforementioned step S5 and will not be described in detail here.

[0232] S46: Writing the j first code words and Jj fourth code words into the non-volatile memory.

[0233] Step S46 is the same as the aforementioned step S6 and will not be described in detail here.

[0234] In this embodiment, by modifying the cell group, a modification is introduced on the Lower page to reduce the bit error rate of the Middle page and the Upper page.

[0235] Correspondingly, the reading method may exemplarily include the following steps:

[0236] S47: Acquire J blocks of data corresponding to each logical page in the non-volatile memory.

[0237] If LDPC (9872, 8962) is used for secondary encoding, the length of the acquired data can be 9872*J.

[0238] It should be noted that, as time goes by, other errors may occur in the bits of the fourth codeword, so the acquired data is not the same as the fourth codeword.alg P′ alg P'2 represents the fourth code word in which an error occurs. The same is true for the first code word.

[0239] S48: Based on the common LLR value, the data corresponding to the Upper page and the Middle page are decoded and error corrected using a decoding algorithm corresponding to the LDPC (9872, 8162) coding algorithm to obtain the original data corresponding to the Upper page and the Middle page.

[0240] S48 is similar to the aforementioned S8 and will not be described in detail here.

[0241] S49: Based on the common LLR value, the data corresponding to the Lower page is decoded and error corrected using a decoding algorithm corresponding to the LDPC (9872, 8962) coding algorithm to obtain a third codeword.

[0242] The third codeword length is 8962.

[0243] For the relevant introduction, please refer to the previous records and I will not repeat them here.

[0244] S410: Determine a second bit unit group according to the distribution state of the bit units.

[0245] In an example, the original data corresponding to the Upper page and the Middle page obtained in step S49 (ie, the original data corresponding to each logical page in the first logical page group) may be re-encoded using the LDPC (9872, 8192) encoding algorithm to obtain the first codeword.

[0246] Then, the first S bits (the first 8962 bits in this embodiment) of each first codeword are observed together with the third codeword, for a total of 8962*J bits. In these 8962*J bits, the data corresponding to the same storage unit is a bit unit, and each bit unit includes J bits of data.

[0247] The second bit unit group includes a bit unit group whose distribution state combinations are: 020, 021, 120, 200, 121, 221, 420 and 122.

[0248] S411: Determine the bit position corresponding to the lower page in the second bit unit of the second bit unit group as an unreliable bit position, and determine the other bit positions in the third codeword as reliable positions.

[0249] The second bit unit is a bit unit whose distribution state is a second preset distribution state. In this embodiment, the second preset distribution state is P2, so in the second bit unit group, the bit unit whose distribution state is P2 is the second bit unit.

[0250] As described above, during encoding, the first distribution state combination set will be modified to the second distribution state combination set, for example, the P7 state will be modified to the P2 state.

[0251] Of course, in addition to the modified P2 state, there are also bit units that were originally in the P2 state. Therefore, the number of the second bit unit group is greater than that of the aforementioned first bit unit group.

[0252] S412: Set the LLR value of the unreliable bit position to 0, set the LLR value corresponding to the reliable bit position with data value 1 to -10, and set the LLR value corresponding to the reliable bit position with data value 0 to 10.

[0253] S413: Based on the LLR value of each bit position, a decoding algorithm corresponding to the LDPC (8962, 8192) coding algorithm is used to decode and correct errors on the third codeword to obtain original data corresponding to the lower page.

[0254] Specifically, the decoding algorithm used in this step can be called:

[0255] MCFU (Most Correct Few Uncertain)-LDPC (8962, 8192, 140).

[0256] The aforementioned steps S410 to S412 are also executed by MCFU-LDPC (8962, 8192, 140), where 140 represents the number of allowed error correction errors.

[0257] Compared with the error correction capability of ordinary LDPC, the MCFU-LDPC provided in this embodiment has the following characteristics:

[0258] In MCFU-LDPC, most bits can be guaranteed to be correct, and only about 200 bits in 1k bytes are uncertain (that is, there are about 200 bits of unreliable bit data).

[0259] In ordinary LDPC, about 1,000 bits are uncertain, and the others are not completely guaranteed to be correct, and the confidence level is not very high.

[0260] According to experiments, the error correction capability of MCFU-LDPC is more than three times that of ordinary LDPC. The error correction capability of MCFU-LDPC is: 105 / 1k bytes (95% code rate).

[0261] Compared with BCH code, its error correction capability is more outstanding.

[0262] Table 5 below shows the experimental data.

[0263]

[0264] Table 5

[0265] The number of errors allowed to be corrected by BCH (9872, 8192, 120) is 120.

[0266] Please refer to the experimental data shown in Table 5 (PIE in Table 5 indicates errors caused by modified data, and NE indicates common errors). If the original data is encoded using BCH (9872, 8192, 120) and then directly stored, taking 125 degrees Celsius as an example, after writing for 5.5 hours, when the number of errors in the Upper page reaches 120, the number of errors in the Middle page and the Lower page are 100 and 56 respectively.

[0267] If BCH (9872, 8192, 120) is used to encode the original data, and then the encoded codeword is operated as follows, taking 125 degrees Celsius as an example, after writing for 6.8 hours, when the errors of the Upper page reach 120, the errors of the Middlepage and Lower page are 118 respectively.

[0268] 070--->020[1;1;1;1;0;1;1;1;1]--->[1;1;1;0;0;1;1;1;1]

[0269] 071--->021[1;1;1;1;0;1;0;1;1]--->[1;1;1;0;0;1;0;1;1;1]

[0270] 170--->120[0;1;1;1;0;1;1;1;1]--->[0;1;1;0;0;1;1;1;1;1]

[0271] 270--->200[0;0;1;1;0;1;1;1;1]--->[0;0;1;1;1;1;1;1;1;1;1]

[0272] After adopting the solution provided in this embodiment, at 125 degrees Celsius, after 8.42 hours of writing, the number of errors in the Middle page reaches 120, the number of errors in the Upper page reaches 115, and the number of errors in the Lower page is 65NE+140PIE. Since there are two decodings for the Lower page, the first decoding can correct 65 common errors, and the second decoding can correct 140 errors caused by modified data.

[0273] This shows that the technical solution provided by this embodiment, in the TLC mode, the bit error rates of the three logical pages almost simultaneously exceed the error correction capability, so that the error correction capability is fully used, the effective time is extended, and the impact of the lateral charge diffusion effect and the longitudinal trapping on the NAND Flash data retention capability is reduced while adjusting the TLC bit error rate imbalance phenomenon. In addition, based on MCFU-LDPC, the ability to correct errors caused by modifications is effectively improved, and more cell groups can be modified, thereby more effectively improving the data retention capability of the NAND Flash.

[0274] The above describes the technical solution when G=3, but in practice G can be 1, 2, 4, 5, etc. For the case of G=1, the lateral charge diffusion effect is not considered, and only the longitudinal trapping effect is reduced.

[0275] For the case of G=1, the distribution state combination will no longer be considered, and only the high state will be considered to be modified to the low state. Taking the TLC mode as an example, the P7 state can be exemplarily modified to the P2 state.

[0276] The following is an introduction to the bit error rate balance device (ECC module), see Figure 5 , which exemplarily include:

[0277] A first acquisition unit 1, used to acquire original data;

[0278] The first encoding unit 2 is used for:

[0279] Using a first preset encoding algorithm to encode j blocks of original data, to obtain j first codewords; the j blocks of original data correspond to j logical pages in a first logical page group; wherein j is a positive integer less than J; and the length of the first codeword is L;

[0280] The second encoding unit 3 is used for:

[0281] The Jj blocks of original data are encoded using a second preset encoding algorithm to obtain Jj second codewords; the Jj blocks of original data correspond to the Jj logical pages in the second logical page group; the length of the second codeword is S; S is less than L; the first S bits of data of the j first codewords and the S bits of data of the Jj second codewords, data corresponding to the same storage unit is a bit unit; each bit unit includes J bits of data;

[0282] According to the distribution state of the bit unit, a first bit unit group is determined; the first bit unit group includes: G bit units corresponding to G consecutive storage units on the same channel, and the distribution state combination of the G bit units is a distribution state combination in the first distribution state combination set; G is a natural number;

[0283] A modification operation is performed on the data of the Jj page logical page in the first bit unit group to balance the bit error rate of each logical page, and Jj third code words are obtained; wherein, after performing the modification operation, the first bit unit group is modified into a second bit unit group; and the distribution state combination of the G bit units in the second bit unit group is a distribution state combination in a second distribution state combination set;

[0284] The Jj third code words are encoded using a third preset encoding algorithm to obtain Jj fourth code words; the length of the fourth code words is L;

[0285] The j first code words and Jj fourth code words are written into a nonvolatile memory.

[0286] For specific details, please refer to the previous record in this article and will not be repeated here.

[0287] In other embodiments of the present invention, see Figure 6 , the above-mentioned device may also include:

[0288] The evaluation unit 4 is used to establish a data modification evaluation model before executing the modification.

[0289] The first distribution state combination set and the second distribution state combination set are determined according to the data modification evaluation model.

[0290] In other embodiments of the present invention, the evaluation unit 4 is further used for:

[0291] Putting the initial distribution state combination in the target data modification evaluation result into the first distribution state combination set;

[0292] Putting the target distribution state combination in the target data modification evaluation result into the second distribution state combination set;

[0293] The target data modification evaluation result includes a data modification evaluation result that meets a preset condition.

[0294] For specific details, please refer to the previous record in this article and will not be repeated here.

[0295] The introduction and establishment method of the data modification assessment model can be found in the previous section of this article and will not be elaborated here.

[0296] Among the G bit units corresponding to the first bit unit group, the bit units whose distribution state is the first preset distribution state are the first bit unit group.

[0297] In other embodiments of the present invention, in terms of performing the modification operation, the second encoding module 3 in all the above embodiments may be specifically used for:

[0298] The bit data corresponding to the second logic page group in the first bit cell group is modified to obtain a second bit cell group, and the distribution state of the second bit cell group is a second preset distribution state.

[0299] For specific details, please refer to the previous record in this article and will not be repeated here.

[0300] In other embodiments of the present invention, the first distribution state combination set includes at least one of the following combinations:

[0301] The first combination: E state, P7 state, E state;

[0302] The second combination: E state, P7 state, P1 state;

[0303] The third combination: P1 state, P7 state, E state;

[0304] The fourth combination: P2 state, P7 state, E state;

[0305] The fifth combination: P1 state, P7 state, P1 state;

[0306] The sixth combination: P2 state, P7 state, P1 state;

[0307] The seventh combination: P4 state, P7 state, E state;

[0308] The eighth combination: P1 state, P7 state, P2 state.

[0309] The second distribution state combination set includes at least one of the following combinations:

[0310] The ninth combination: E state, P2 state, E state;

[0311] The tenth combination: E state, P2 state, P1 state;

[0312] The eleventh combination: P1 state, P2 state, E state;

[0313] The twelfth combination: P2 state, E state, E state;

[0314] The thirteenth combination: P1 state, P2 state, P1 state;

[0315] The fourteenth combination: P2 state, P2 state, P1 state;

[0316] The fifteenth combination: P4 state, P2 state, E state;

[0317] The sixteenth combination: P1 state, P2 state, P2 state.

[0318] For specific details, please refer to the previous record in this article and will not be repeated here.

[0319] When J is equal to 3, in other embodiments, the target logical page may be: Lower Page; the first preset distribution state may be P7 state, and the second preset distribution state may be P2 state;

[0320] In other embodiments of the present invention, in terms of modifying the bit data corresponding to the second logical page group in the first bit unit group, the encoding module 2 in all the above embodiments may be specifically used to:

[0321] The bit data of the Lower Page in the first bit unit group is changed from 1 to 0. For details, please refer to the above description of this article, which will not be repeated here.

[0322] The following describes the reading device (ECC module or controller in SSD), see Figure 6 , which exemplarily include:

[0323] The second acquisition unit 5 is used to: acquire data in the non-volatile memory;

[0324] The first decoding unit 6 is used for:

[0325] Based on a universal log-likelihood probability LLR value, decoding and error correction processing are performed on j blocks of data corresponding to j logical pages in the first logical page group using a decoding algorithm corresponding to the first preset encoding algorithm to obtain the j blocks of original data;

[0326] The second decoding unit 7 is used for:

[0327] Based on the universal log-likelihood probability LLR value, the Jj block data corresponding to the Jj page logical page in the second logical page group is decoded and error corrected by using a decoding algorithm corresponding to the third preset encoding algorithm to obtain the Jj third codewords;

[0328] Predicting the bit positions of the data changed by performing the modification operation in the Jj third codewords; the predicted bit positions are unreliable bit positions, and the other bit positions are reliable bit positions;

[0329] Set the LLR value of the unreliable bit position to 0;

[0330] The LLR value corresponding to the reliable bit position with data value 1 is -10, and the LLR value corresponding to the reliable bit position with data value 0 is 10;

[0331] Based on the LLR value of each bit, a decoding algorithm corresponding to the second preset encoding algorithm is used to decode and error correct the Jj third code words to obtain Jj blocks of original data.

[0332] For specific details, please refer to the previous record in this article and will not be repeated here.

[0333] In other embodiments of the present invention, G consecutive memory cells located on the same channel and having a distribution state combination matching the second distribution state combination set may be set as the second target memory cell group;

[0334] Among the G bit cells corresponding to the second target storage cell group, the bit cell having a distribution state of the second preset distribution state is the second bit cell; then the bit position in the second bit cell corresponding to the logical page in the second logical page group is an unreliable bit position.

[0335] For specific details, please refer to the previous record in this article and will not be repeated here.

[0336] In other embodiments of the present invention, J is equal to 3; the second preset distribution state is the P2 state; and the target logical page is: Lower Page. For specific details, please refer to the above description of this article, which will not be repeated here.

[0337] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the differences can be referred to the method part.

[0338] The professionals may further appreciate that the units and model steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0339] The steps of the method or model described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a WD-ROM, or any other form of storage medium known in the art.

[0340] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bit error rate balancing method, characterized in that: include: Get J blocks of raw data; J is the total number of logical pages; Using a first preset encoding algorithm to encode j blocks of original data, to obtain j first codewords; the j blocks of original data correspond to j logical pages in a first logical page group; wherein j is a positive integer less than J; and the length of the first codeword is L; The Jj blocks of original data are encoded using a second preset encoding algorithm to obtain Jj second code words; the Jj blocks of original data correspond to the Jj logical pages in the second logical page group; the length of the second code word is S; S is less than L; the first S bits of data of the j first code words and the Jj second code words correspond to data of the same storage unit as a bit unit; each bit unit includes J bits of data; According to the distribution state of the bit unit, a first bit unit group is determined; the first bit unit group includes: G bit units corresponding to G consecutive storage units on the same channel, and the distribution state combination of the G bit units is a distribution state combination in the first distribution state combination set; G is a natural number; A modification operation is performed on the data of the Jj page logical page in the first bit unit group to balance the bit error rate of each logical page, and Jj third code words are obtained; wherein, after performing the modification operation, the first bit unit group is modified into a second bit unit group; and the distribution state combination of the G bit units in the second bit unit group is a distribution state combination in a second distribution state combination set; The Jj third code words are encoded using a third preset encoding algorithm to obtain Jj fourth code words; the length of the fourth code words is L; The j first code words and Jj fourth code words are written into a nonvolatile memory.

2. The method according to claim 1, characterized in that Before performing the modification operation of balancing the bit error rates of each logical page, the method further includes: A data modification assessment model is established; the first distribution state combination set and the second distribution state combination set are determined according to the data modification assessment model.

3. The method according to claim 2, characterized in that The data modification assessment model includes: at least one data modification assessment result; Each data modification evaluation result includes: an initial distribution state combination, a target distribution state combination, and a bit error rate gain after modifying a bit unit group corresponding to the initial distribution state combination to a bit unit group corresponding to the target distribution state combination; the initial distribution state combination and the target distribution state combination are different arbitrary distribution state combinations; After establishing the data modification assessment model and before executing the modification operation, it also includes: Putting the initial distribution state combination in the target data modification evaluation result into the first distribution state combination set; Putting the target distribution state combination in the target data modification evaluation result into the second distribution state combination set; The target data modification evaluation result includes a data modification evaluation result that meets a preset condition.

4. The method according to claim 3, characterized in that G＝3； The establishing of the data modification evaluation model comprises: Calculating the bit error rate corresponding to each distribution state combination in the codeword group at a predetermined time; the codeword group includes the first S bits of data of the j first codewords and the Jj second codewords; Taking any distribution state combination as an initial distribution state combination, and taking any distribution state combination different from the initial distribution state combination as a target distribution state combination; the initial distribution state combination includes the first to third distribution states; the target distribution state combination includes the first distribution state, the fourth distribution state and the third distribution state; According to the bit error rate, an average value ERaver1 of the bit error rates of each distribution state combination in the third distribution state combination set is calculated; any distribution state combination in the third distribution state combination set includes distribution state X, the first and second distribution states; distribution state X is any distribution state; According to the bit error rate, an average value ERaver2 of the bit error rates of each distribution state combination in the fourth distribution state combination set is calculated; any distribution state combination in the fourth distribution state combination set includes distribution state X, the first and the fourth distribution states; According to the bit error rate, an average value ERaver3 of the bit error rates of each distribution state combination in the fifth distribution state combination set is calculated; any distribution state combination in the fifth distribution state combination set includes the second distribution state, the fourth distribution state and the distribution state Y; the distribution state Y is any distribution state; According to the bit error rate, an average value ERaver4 of the bit error rates of each distribution state combination in the sixth distribution state combination set is calculated; any distribution state combination in the fourth distribution state combination set includes the fourth distribution state, the third distribution state and the distribution state Y; Calculating a first bit error rate difference between an initial distribution state combination and a target distribution state combination; Calculate a second bit error rate difference between ERaver1 and ERaver2; Calculate the third bit error rate difference between ERaver3 and ERaver4; The sum of the first to third bit error rate differences is calculated as a bit error rate gain.

5. The method according to claim 4, characterized in that Among the G bit units of the first bit unit group, the bit unit whose distribution state is the first preset distribution state is the first bit unit; The performing modification operation comprises: The data corresponding to the Jj page logical page in the first bit unit is modified to obtain a second bit unit; wherein the distribution state corresponding to the second bit unit is a second preset distribution state.

6. A reading method, characterized in that: Used to read data written by the method according to any one of claims 1 to 5; The reading method comprises: Acquire J blocks of data corresponding to each logical page in the nonvolatile memory, where J is the total number of logical pages; Based on a universal log-likelihood probability LLR value, decoding and error correction processing are performed on j blocks of data corresponding to j logical pages in the first logical page group using a decoding algorithm corresponding to the first preset encoding algorithm to obtain the j blocks of original data; Based on the common LLR value, decode and correct the Jj block data corresponding to the Jj page logical page in the second logical page group using a decoding algorithm corresponding to the third preset encoding algorithm to obtain the Jj third code words; Predicting the bit positions of the data changed by performing the modification operation in the Jj third codewords; the predicted bit positions are unreliable bit positions, and the other bit positions are reliable bit positions; Set the LLR value of the unreliable bit position to 0; The LLR value corresponding to the reliable bit position with data value 1 is -10, and the LLR value corresponding to the reliable bit position with data value 0 is 10; Based on the LLR value of each bit position, a decoding algorithm corresponding to the second preset encoding algorithm is used to decode and error correct the Jj third code words to obtain Jj blocks of original data.

7. The method according to claim 6, characterized in that The predicting of the bit positions of the data changed due to the modification operation in the Jj third code words comprises: Determining a second bit unit group according to the distribution state of the bit units; Among the G bit units in the second bit unit group, the bit unit whose distribution state is the second preset distribution state is the second bit unit; The bit position in the second bit unit corresponding to the Jj page logical page is an unreliable bit position.

8. The method according to claim 7, characterized in that J is equal to 3, j=2; the second preset distribution state is the P2 state; the Jj page logical page is: Lower Page.

9. A bit error rate balancing device, characterized in that: include: A first acquisition unit is used to acquire J blocks of original data, where J is the total number of logical pages; The first encoding unit is used for: Using a first preset encoding algorithm to encode j blocks of original data, to obtain j first codewords; the j blocks of original data correspond to j logical pages in a first logical page group; wherein j is a positive integer less than J; and the length of the first codeword is L; The second encoding unit is used for: The Jj blocks of original data are encoded using a second preset encoding algorithm to obtain Jj second codewords; the Jj blocks of original data correspond to the Jj logical pages in the second logical page group; the length of the second codeword is S; S is less than L; the first S bits of data of the j first codewords and the S bits of data of the Jj second codewords, data corresponding to the same storage unit is a bit unit; each bit unit includes J bits of data; According to the distribution state of the bit unit, a first bit unit group is determined; the first bit unit group includes: G bit units corresponding to G consecutive storage units on the same channel, and the distribution state combination of the G bit units is a distribution state combination in the first distribution state combination set; G is a natural number; A modification operation is performed on the data of the Jj page logical page in the first bit unit group to balance the bit error rate of each logical page, and Jj third code words are obtained; wherein, after performing the modification operation, the first bit unit group is modified into a second bit unit group; and the distribution state combination of the G bit units in the second bit unit group is a distribution state combination in a second distribution state combination set; The Jj third code words are encoded using a third preset encoding algorithm to obtain Jj fourth code words; the length of the fourth code words is L; The j first code words and Jj fourth code words are written into a nonvolatile memory.

10. A reading device, characterized in that: Reading data written by the method according to any one of claims 1 to 5; The reading device comprises: The second acquisition unit is used for: Acquire J blocks of data in the non-volatile memory, where J is the total number of logical pages; The first decoding unit is used for: Based on a universal log-likelihood probability LLR value, decoding and error correction processing are performed on j blocks of data corresponding to j logical pages in the first logical page group using a decoding algorithm corresponding to the first preset encoding algorithm to obtain the j blocks of original data; The second decoding unit is used for: Based on the universal log-likelihood probability LLR value, the Jj block data corresponding to the Jj page logical page in the second logical page group is decoded and error corrected by using a decoding algorithm corresponding to the third preset encoding algorithm to obtain the Jj third codewords; Predicting the bit positions of the data changed by performing the modification operation in the Jj third codewords; the predicted bit positions are unreliable bit positions, and the other bit positions are reliable bit positions; Set the LLR value of the unreliable bit position to 0; The LLR value corresponding to the reliable bit position with data value 1 is -10, and the LLR value corresponding to the reliable bit position with data value 0 is 10; Based on the LLR value of each bit, a decoding algorithm corresponding to the second preset encoding algorithm is used to decode and error correct the Jj third code words to obtain Jj blocks of original data.

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