Communication method and communication device based on LDPC (Low Density Parity Check) code

Abstract

According to the communication method and the communication device based on the LDPC code, an area B of an LDPC basis matrix used for encoding or decoding comprises a first square matrix, the first square matrix comprises at least two columns with the column weight larger than or equal to 3 and / or at least one column with the column weight being an even number larger than or equal to 4, and the row weight of each row of the first square matrix is larger than or equal to 2. Thus, the column weight of the columns included in the first square matrix, namely the B area, is not limited to 2 or 3 and can be a numerical value except 2 and 3. In addition, the first square matrix comprises at least two columns with the column weight larger than or equal to 3 and / or at least one column with the column weight being an even number larger than or equal to 4, and the connecting edge density of the first square matrix is higher. Therefore, the degree distribution of the coding structure of the LDPC basis matrix is more flexible, the edge connection density is higher, the realization of rapid convergence is facilitated, and the coding or decoding performance is improved.

Description

Technical Field

[0001] The present application relates to the field of coding, and more specifically, to a communication method and a communication device based on LDPC codes. Background Art

[0002] In the field of channel coding, low-density parity check (LDPC) code is one of the most mature and widely used channel coding schemes. In the current LDPC code, the coding structure of the LDPC base matrix has a large restriction on the degree distribution, and the edge density of the coding structure is low, which is not conducive to fast convergence and affects the coding or decoding performance. Summary of the invention

[0003] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which are helpful to improve encoding or decoding performance.

[0004] In a first aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or by a module or unit in the transmitting device (eg, a chip). The transmitting device can be a terminal device or a network device.

[0005] The method includes: acquiring an information bit sequence; performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence, wherein a first matrix region of the LDPC base matrix includes a first square matrix, the first matrix region is composed of the 1st row to the wth row and the rth column to the r+w-1th column of the LDPC base matrix, the first square matrix includes at least two columns with column weights greater than or equal to 3 and / or at least one column with a column weight that is an even number greater than or equal to 4, the row weight of each row of the first square matrix is ​​greater than or equal to 2, and w and r are positive integers; and outputting the LDPC codeword sequence.

[0006] In the above method, the column weight of the columns included in the first square matrix is ​​not limited to 2 or 3, and can be a value other than 2 and 3, such as the column weight can be greater than 2, and the column weight can be greater than 3, and the column weight can be an even number greater than or equal to 4, so the degree distribution of the coding structure of the first square matrix is ​​more flexible, and the first square matrix includes at least two columns with a column weight greater than or equal to 3 and / or at least one column with a column weight greater than or equal to 4, so the weight or edge density of the first square matrix is ​​higher. Therefore, the degree distribution of the coding structure of the LDPC base matrix is ​​more flexible, and the weight or edge density of the coding structure is also higher, which helps to achieve rapid convergence and improve coding or decoding performance.

[0007] In a second aspect, a communication method based on LDPC codes is provided, which can be executed by a receiving device or by a module or unit in the receiving device (eg, a chip). The receiving device can be a terminal device or a network device.

[0008] The method includes: obtaining an LDPC codeword sequence; decoding the LDPC codeword sequence according to an LDPC base matrix to obtain an information bit sequence, wherein a first matrix region of the LDPC base matrix includes a first square matrix, the first matrix region is composed of the 1st row to the wth row and the rth column to the r+w-1th column of the LDPC base matrix, the first square matrix includes at least two columns with column weights greater than or equal to 3 and / or at least one column with a column weight that is an even number greater than or equal to 4, the row weight of each row of the first square matrix is ​​greater than or equal to 2, and w and r are positive integers.

[0009] In the above method, the column weight of the columns included in the first square matrix is ​​not limited to 2 or 3, and can be a value other than 2 and 3, such as the column weight can be greater than 2, and the column weight can be greater than 3, and the column weight can be an even number greater than or equal to 4, so the degree distribution of the coding structure of the first square matrix is ​​more flexible, and the first square matrix includes at least two columns with a column weight greater than or equal to 3 and / or at least one column with a column weight greater than or equal to 4, so the weight or edge density of the first square matrix is ​​higher. Therefore, the degree distribution of the coding structure of the LDPC base matrix is ​​more flexible, and the weight or edge density of the coding structure is also higher, which helps to achieve rapid convergence and improve coding or decoding performance.

[0010] In combination with any of the above aspects, in some implementations, the first square matrix is ​​an m×m matrix, where m is a positive integer. The first square matrix includes m-1 columns with even column weights and 1 column with odd column weights, each row of the first square matrix has a row weight of 2 or 3, and the number of rows with a row weight of 3 in the first square matrix is ​​the number of the at least one column with an even column weight greater than or equal to 4 plus 1. The m-1 columns with even column weights include the at least one column with an even column weight greater than or equal to 4.

[0011] In the above implementation, the first square matrix includes at least one column whose column weight is an even number greater than or equal to 4, and the number of rows whose row weight is 3 in the first square matrix is ​​the number of at least one column whose column weight is an even number greater than or equal to 4 plus 1, so the weight or edge density of the first square matrix is ​​higher. The advantages of this coding structure are that it can support a larger maximum column degree, has a better decoding threshold, and is easy to implement coding.

[0012] In combination with any one of the above aspects or any implementations, in other implementations, the first square matrix includes 1 column with a column weight of 4, 1 column with a column weight of 3, and m-2 columns with a column weight of 2.

[0013] In combination with any one of the above aspects or any implementations, in some other implementations, m=4, and the first square matrix is ​​the following matrix:

[0014]

[0015] Among them, "-1" represents a zero element, "x", "y", "z", "a", "b" or "c" represents a non-zero element and the offset values ​​are x, y, z, a, b or c respectively, x≠y, a≠b, x, y, z, a and c are positive integers, and b is a non-negative integer.

[0016] In combination with any one of the above aspects or any implementation manners, in some other implementation manners, m=5, and the first square matrix is ​​the following matrix:

[0017]

[0018] Among them, "-1" represents a zero element, "x", "y", "a", "b", "c", "d" or "p" represents a non-zero element and the offset values ​​are x, y, a, b, c, d or p respectively, x≠y, b≠d, x, y, a, p, c and d are positive integers, and b is a non-negative integer.

[0019] In combination with any one of the above aspects or any implementations, in other implementations, the first square matrix includes 2 columns with a column weight of 4, 1 column with a column weight of 3, and m-3 columns with a column weight of 2.

[0020] In combination with any one of the above aspects or any implementation manners, in some other implementation manners, m=5, and the first square matrix may be the following matrix:

[0021]

[0022] Among them, "-1" represents a zero element, "x", "y", "a", "b", "c", "d", "e" or "p" represents a non-zero element and the offset values ​​are x, y, a, b, c, d, e or p respectively, x≠y, b≠d, a≠e, x, y, a, p, c, d and e are positive integers, and b is a non-negative integer.

[0023] In combination with any one of the above aspects or any implementations, in other implementations, the column weight of each column of the first matrix is ​​2 or 3, and the number of columns with a column weight of 2 in the first matrix is ​​greater than 0.

[0024] In the above implementation, the first square matrix includes at least two columns with column weight greater than or equal to 3, so the weight or edge density of the first square matrix is ​​higher, has a better decoding threshold, and is easy to encode and implement.

[0025] In combination with any one of the above aspects or any one of the implementations, in other implementations, the number of columns with a column weight of 2 in the first matrix is ​​an even number.

[0026] In combination with any one of the above aspects or any implementations, in other implementations, the first square matrix is ​​an m×m matrix, where m is a positive integer. The first square matrix includes 2 columns with a column weight of 2 and m-2 columns with a column weight of 3.

[0027] In combination with any one of the above aspects or any implementations, in other implementations, the first square matrix is ​​an m×m matrix, where m is an even number greater than 0. The first square matrix includes m-2 columns with a column weight of 2 and 2 columns with a column weight of 3.

[0028] In combination with any one of the above aspects or any implementation manners, in some other implementation manners, m=4, and the first square matrix is ​​any one of the following matrices:

[0029]

[0030]

[0031] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "2x" means non-zero elements and the offset value is 2x, "-2x" means non-zero elements and the offset value is Z c -2x, Z c is the boost value, x is a positive integer.

[0032] In combination with any one of the above aspects or any implementations, in other implementations, the first square matrix is ​​an m×m matrix, where m is an odd number greater than 0. The first square matrix includes m-3 columns with a column weight of 2 and 3 columns with a column weight of 3.

[0033] In combination with any one of the above aspects or any implementation manners, in some other implementation manners, m=5, and the first square matrix is ​​any one of the following matrices:

[0034]

[0035] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c-x, "z" means non-zero elements and offset value is z, "-z" means non-zero elements and offset value is Z c -z,Z c is the boost value, x and z are positive integers.

[0036] In combination with any aspect or any implementation method above, in other implementation methods, the column weight of each column and the row weight of each row of the first matrix are both G, the first matrix includes a first row and a second row, the number of elements in the intersection of the set consisting of the column numbers of the columns where the non-zero elements of the first row are located and the set consisting of the column numbers of the columns where the non-zero elements of the second row are located is 2, the first row and the second row are any two rows of the first matrix, and G is greater than or equal to 3.

[0037] The degree distribution of the above implementation method helps the code distance of the LDPC code to grow linearly with the code length, and helps to construct a structure that is easy to implement coding.

[0038] In combination with any one of the above aspects or any one of the implementations, in some other implementations, G=3.

[0039] In combination with any one of the above aspects or any implementation methods, in other implementation methods, the first square matrix includes a first column and a second column, the intersection of a set consisting of row numbers of rows where non-zero elements of the first column are located and a set consisting of row numbers of rows where non-zero elements of the first column are located includes at most one row number, and the first column and the second column are any two columns of the first square matrix; the row numbers of any two rows of the first square matrix belong to the set consisting of row numbers of rows where non-zero elements of a column of the first square matrix are located.

[0040] In combination with any one of the above aspects or any implementation methods, in other implementation methods, the first square matrix is ​​an m×m matrix, and m is a positive integer. The non-zero elements of the first square matrix include first-category non-zero elements and second-category non-zero elements. Wherein, the positions of the first-category non-zero elements include: the 1st to 3rd columns of the 1st row of the first square matrix, the 4th to 5th columns of the 2nd row, ..., the 2tth to 2t+1th columns of the tth row, and the 1st to 3rd rows of the 1st column of the first square matrix, the 4th to 5th rows of the 2nd column, ..., the 2tth to 2t+1th rows of the tth column, where t is greater than or equal to 2. The second-category non-zero elements are located in a first sub-region of the first square matrix, and the first sub-region is composed of the first matrix region. Go to row m, row The structure consists of columns from the first column to the mth column.

[0041] In combination with any one of the above aspects or any implementation manners, in other implementation manners, the positions of the second type of non-zero elements correspond to the first sequence and the second sequence, and the elements in the first sequence are The elements in the second sequence are the same as The elements in the first sequence are the same as the elements in the second sequence, the arrangement order of the elements in the first sequence is different from the arrangement order of the elements in the second sequence, and the i-th element p in the first sequence or the second sequence i represents the i-th row and the p-th row of the first sub-region i Columns are non-zero elements, i is less than or equal to A positive integer.

[0042] In combination with any one of the above aspects or any implementations, in other implementations, s is a constant.

[0043] In combination with any one of the above aspects or any implementations, in some other implementations, the first sequence and / or the second sequence are obtained based on segmented cycles.

[0044] In combination with any one of the above aspects or any one of the implementations, in some other implementations, the offset value of the first type of non-zero elements is 0.

[0045] In combination with any one of the above aspects or any implementations, in some other implementations, the offset value of the second type of non-zero element is based on x 1 、x 2 , …, x t OK, x 1 、x 2 , …, x t are both greater than or equal to 0, and t is a positive integer.

[0046] In combination with any one of the above aspects or any implementations, in some other implementations, t is equal to 1, and the offset value of the second type of non-zero element is k 1 x 1 Or, t is equal to 2, and the offset value of the second type of non-zero elements is k 1 x 1 , -k 1 x 1 , k 2 x 2 , -k 2 x 2 or k 1 x 1 +k 2 x 2 .or,

[0047] t is greater than or equal to 3, the offset value of the second type of non-zero element is x 1 、x 2 , …, x t A linear combination of at most two terms in 1 and k 2Is a positive integer.

[0048] In combination with any one of the foregoing aspects or any implementation manners, in other implementation manners, the offset values ​​of the non-zero elements corresponding to the first sequence or the second sequence are all 0.

[0049] In combination with any one of the above aspects or any implementation manners, in other implementation manners, when m is an even number, the non-zero elements of the first matrix further include a third type of non-zero elements, and the third type of non-zero elements are located in the first matrix. Row, No. List.

[0050] In combination with any one of the above aspects or any implementations, in other implementations, the offset value of the third type of non-zero element is not 0. Alternatively, the offset value of the third type of non-zero element is based on x 1 、x 2 , …, x t OK, x 1 、x 2 , …, x t are both greater than or equal to 0, and t is a positive integer.

[0051] In combination with any one of the above aspects or any implementation manners, in other implementation manners, the first square matrix is ​​a 4×4 matrix, and the first square matrix is ​​any one of the following matrices:

[0052]

[0053] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "-2x" means non-zero elements and offset value is Z c -2x, "-3x" means non-zero elements and offset value is Z c -3x, "-4x" means non-zero elements and offset value is Z c -4x, Z c is the boost value, x is a positive integer.

[0054] In combination with any one of the above aspects or any implementation manners, in other implementation manners, the first square matrix is ​​a 5×5 matrix, and the first square matrix is ​​any one of the following matrices:

[0055]

[0056] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c-x, "-2x" means non-zero elements and offset value is Z c -2x, "y" means non-zero elements and offset value is y, Z c is the lifting value, x and y are positive integers.

[0057] In combination with any one of the above aspects or any implementation methods, in other implementation methods, the first matrix area also includes at least one second square matrix, the first square matrix and the at least one second square matrix do not overlap, and the second sub-area composed of the first square matrix and the at least one second square matrix includes all diagonal elements of the first matrix area; the elements in the first matrix area at the upper right of the second sub-area are all zero elements, and the elements in the first matrix area at the lower left of the second sub-area are all zero elements; or, the elements in the first matrix area at the upper right of the second sub-area are all zero elements, and the area of ​​the first matrix area at the lower left of the second sub-area includes non-zero elements; or, the area of ​​the first matrix area at the upper right of the second sub-area includes non-zero elements, and the elements in the first matrix area at the lower left of the second sub-area are all zero elements.

[0058] When the size of the first matrix area is very large, the encoding process may be more complicated and the number of circles may increase. In the above implementation, the first matrix area may have multiple square matrices (composed of a first square matrix and at least one second square matrix), which may support block encoding, thereby simplifying the encoding complexity and reducing the number of short circles.

[0059] In addition, when the elements in the first matrix area at the upper right of the second sub-area are all zero elements and the elements in the first matrix area at the lower left of the second sub-area are all zero elements, the first square matrix and at least one second square matrix can be encoded completely in parallel, which helps to speed up the encoding rate. When the elements in the first matrix area at the upper right of the second sub-area are all zero elements and the area at the lower left of the second sub-area of ​​the first matrix area includes non-zero elements, or the area at the upper right of the second sub-area of ​​the first matrix area includes non-zero elements and the elements in the first matrix area at the lower left of the second sub-area are all zero elements, a more flexible degree distribution can be supported, which helps to improve the decoding threshold of the LDPC code.

[0060] In combination with any one of the above aspects or any implementation methods, in other implementation methods, the at least one second square matrix is ​​an upper triangular structure, a lower triangular structure, a diagonal structure or a dual diagonal structure; the first square matrix is ​​located in the upper left corner of the first matrix region, the area of ​​the first matrix region to the upper right of the second sub-region includes non-zero elements, and the elements of the first matrix region to the lower left of the second sub-region are all zero elements; or, the first square matrix is ​​located in the lower right corner of the first matrix region, the elements of the first matrix region to the upper right of the second sub-region are all zero elements, and the area of ​​the first matrix region to the lower left of the second sub-region includes non-zero elements.

[0061] The advantage of the solution in the above embodiment is that it can achieve a coding structure column degree of at least 3 on the basis of simplified coding, which helps to ensure the property that the code distance of the LDPC code increases linearly with the code length.

[0062] In a third aspect, a communication device is provided, which is used to execute the method provided by any one of the above aspects or its implementation. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, for executing the method provided by any one of the above aspects or its implementation.

[0063] In one implementation, the apparatus is a transmitting end device or a receiving end device. When the apparatus is a transmitting end device or a receiving end device, the transceiver unit may be a transceiver, or an input / output interface, or a communication interface; the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0064] In another implementation, the device is a chip, a chip system or a circuit used in a transmitting device or a receiving device. When the device is a chip, a chip system or a circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit on the chip, the chip system or the circuit; the processing unit may be at least one processor, a processing circuit or a logic circuit.

[0065] In a fourth aspect, a communication device is provided, comprising: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to execute the method provided by any one of the above aspects or its implementation.

[0066] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0067] In another implementation, the apparatus is a chip, a chip system or a circuit used in a transmitting device or a receiving device.

[0068] In a fifth aspect, a communication device is provided, the device comprising: at least one processor and a communication interface, the at least one processor is used to obtain a computer program or instruction stored in a memory through the communication interface to execute the method provided by any one of the above aspects or its implementation. The communication interface can be implemented by hardware or software.

[0069] In one implementation, the device also includes the memory.

[0070] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0071] For the operations such as sending and acquiring / receiving involved in the processor, if there is no special explanation, or if it does not conflict with its actual function or internal logic in the relevant description, then it can be understood as the output and reception, input and other operations of the processor, and can also be understood as the sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0072] In a seventh aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any of the above aspects or its implementation.

[0073] In an eighth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0074] In a ninth aspect, a chip is provided, the chip comprising a processor and a communication interface, the processor reads instructions stored in a memory through the communication interface, and executes the method provided by any one of the above aspects or its implementation. The communication interface can be implemented by hardware or software.

[0075] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instructions are stored, and the processor is used to execute the computer program or instructions stored in the memory. When the computer program or instructions are executed, the processor is used to execute the method provided by any one of the above aspects or its implementation methods.

[0076] Among them, when the method provided by the present application is executed by a chip, the present application does not limit the number of chips that specifically implement the method of the present application. For example, it can be executed by one chip or by two or more chips. Moreover, when the number of chips that implement the method of the present application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0077] In a tenth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0078] In an eleventh aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 It is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0080] Figure 2 Schematic diagram of an LDPC check matrix H.

[0081] Figure 3 is the Tanner graph of a LDPC check matrix H.

[0082] Figure 4 It is a schematic diagram of the structure of the check matrix.

[0083] Figure 5 It is a schematic diagram of the information transmission process.

[0084] Figure 6 Schematic diagram of the coding structure of irregular repeat-accumulate (IRA) codes at different code rates.

[0085] Figure 7 It is a schematic flowchart of a communication method 700 based on LDPC code provided in the present application.

[0086] Figure 8 is an example of a first-class edge.

[0087] Fig. 9 is an example of an edge of the second type.

[0088] Fig.10 is another example of an edge of the second type.

[0089] Fig.11 is another example of an edge of the second type.

[0090] Fig.12 is an example of a third type of edge.

[0091] Fig.13 is an example of the blocks included in the B area.

[0092] Fig.14 It is a specific example of the blocks included in the B area.

[0093] Fig.15is another example of the blocks included in the B area.

[0094] Fig.16 is another example of the blocks included in the B area.

[0095] Fig.17 It is a schematic flowchart of the communication method 1700 based on LDPC code provided in the present application.

[0096] Fig.18 It is the simulation result of the signal noise ratio (SNR) of the base graph (BG) 2-type-Lapter coding structure and the 3-regular coding structure of the present application under different code lengths and different block error rates (BLER).

[0097] Fig.19 It is the simulation result of SNR of BG1 dual diagonal coding structure and 3 regular coding structure of this application under different boost values.

[0098] Fig. 20 It is a structural schematic diagram of the device provided in the embodiment of the present application.

[0099] Fig.21 It is another structural schematic diagram of the device provided in an embodiment of the present application.

[0100] Fig. 22 It is a schematic diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0101] To facilitate understanding of the embodiments of the present application, the following points are explained before introducing the embodiments of the present application.

[0102] "For indicating" or "indicating" may include direct indication and indirect indication, or "for indicating" or "indicating" may be indicated explicitly and / or implicitly. The first, second, and other digital numbers are only used for the convenience of description, and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device, and the present application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the field of communication, such as the long term evolution (LTE) protocol, the new radio (NR) protocol, and related protocols used in future communication systems, and the present application does not limit this. "Example", "for example", "exemplarily", "as (another) example" and other words are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "more than one" means two or more. "At most one" means one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively. The descriptions of network element A sending a message, information or data to network element B, and network element B receiving a message, information or data from network element A, are intended to explain to which network element the message, information or data is to be sent, but do not limit whether they are sent directly or indirectly via other network elements. Descriptions such as "when...", "under the circumstances of...", "if" and "if" all mean that the device will make corresponding processing under certain objective circumstances, but do not limit the time, nor do they require the device to have a judgment action when implementing, nor do they mean that there are other limitations.

[0103] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0104] A communication system to which the embodiments of the present application can be applied is described below.

[0105] Embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5th generation, 5G) system or NR system, LTE system, long term evolution-advanced (long term evolution-advanced, LTE-A) system, LTE frequency division duplex (frequency division duplex, FDD) system, LTE time division duplex (time division duplex, TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (device to device, D2D) communication, vehicle-to-everything (vehicle-to-everything, V2X) communication, machine to machine (machine to machine, M2M) communication, machine type communication (machine type communication, MTC), Internet of things (Internet of things, IoT) communication system, narrow band Internet of things system (narrow band-internet of things, NB-IoT) or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd generation partnership project (3GPP), without limitation.

[0106] The communication system applicable to the embodiments of the present application may include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device may be a terminal device, and the other may be a network device. Optionally, the transmitting end device and the receiving end device may both be terminal devices. Optionally, the transmitting end device and the receiving end device may both be network devices.

[0107] For example, Figure 1 A schematic diagram of a network architecture to which embodiments of the present application may be applied is shown.

[0108] like Figure 1 As shown, the embodiments of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 Only uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communication.

[0109] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiment of the present application may refer to a device that provides voice and / or data connectivity to a user, and may be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer (pad), a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0110] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (wireless fidelity, WiFi) system, the evolved node B (evolved node B, eNB) in the long term evolution (long term evolution, LTE) system, the radio network controller (radio network controller, RNC), node B (node ​​B, NB), base station controller (base station controller, BSC), home base station (for example, home evolved NodeB or home Node B, HNB), base band unit (base band unit, BBU), transmission reception point (transmission reception point, TRP), transmitting point (transmitting point, TP), base transceiver station (base transceiver station, BTS), satellite, drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, a relay station, a vehicle-mounted device, and a wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip used to be set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, a device that performs the base station function in a future communication system, and the like. The base station can support networks with the same or different access technologies without limitation.

[0111] Unless otherwise specified, the device used to implement the function of the terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC), a modem. The device can be installed in the terminal device or network device. In the embodiment of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0112] It should also be noted that some embodiments of this document use the 5G system as an example to introduce specific solution details. It is understandable that when the solution is used in other communication systems, such as the LTE system, or future communication systems, the messages, channels or information in the solution can be replaced by messages, channels or information in other communication systems that can achieve corresponding functions, and this application does not limit this.

[0113] In addition, the embodiments of the present application can be applied to various application scenarios, such as high throughput scenarios, high reliability scenarios, low latency scenarios, high reliability and low latency scenarios or low power consumption scenarios. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (Enhanced Mobile Broadband, eMBB) scenario, etc., the high reliability and low latency scenario can be, for example, a URLLC (UltraReliable Low Latency Communication) scenario, etc., and the low power consumption scenario can be, for example, an M2M scenario, an MTC scenario or an IoT scenario.

[0114] In order to facilitate the understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but it does not mean that the embodiments of the present application can only be applied to currently existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. And the specific names of the concepts or terms (such as concepts or terms involving functional descriptions) can be adjusted with the development of future systems.

[0115] 1. LDPC Code

[0116] LDPC code is a linear block code, and its check matrix is ​​a sparse matrix. The number of zero elements in the LDPC check matrix is ​​much greater than the number of non-zero elements, or in other words, the row weight and column weight of the check matrix are very small numbers compared to the LDPC code length. Among them, the LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by its check matrix.

[0117] In 1981, Tanner expressed the LDPC codeword in the form of a graph. This graph is now called a Tanner graph. The Tanner graph corresponds to the check matrix one by one. The Tanner graph consists of two types of vertices. One type of vertex represents the codeword bits, called variable nodes, and the other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. Figure 2 and Figure 3 Provide explanation.

[0118] Figure 2 Schematic diagram of an LDPC check matrix H.

[0119] Figure 2 In {V i} represents a variable node (VN) set, {C i} represents a check node (CN) set. Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. Figure 2 In the example, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0120] Figure 3 is the Tanner graph of a LDPC check matrix H.

[0121] like Figure 3 As shown, the Tanner graph represents the check matrix of LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H respectively, and the m check nodes correspond to the m rows of the check matrix H respectively. The cycle in the Tanner graph is composed of vertices connected to each other. The cycle uses one of the vertices in this group of vertices as both the starting point and the end point, and only passes through each node once. The length of the cycle is defined as the number of connections it contains, and the girth of the graph can also be called the size of the graph, which is defined as the minimum cycle length in the graph, such as Figure 3 In the figure, the girth is 4, such as Figure 3As shown by the black lines in the figure. The variable nodes in the Tanner graph correspond to each column of the check matrix H, that is, to each codeword bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, that is, to the check bits of the LDPC. The connection between the two types of nodes corresponds to the value of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, it means that the value of the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge. There is a connection between the check node and the variable node, which can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between the check node and the variable node can include two situations: the existence of an edge or the absence of an edge.

[0122] In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes, and edges connected end to end.

[0123] As mentioned above, LDPC is a linear block code. The linear block code divides the information sequence to be encoded into groups of q bits, and then the encoder performs linear operations on the q information bits to obtain m check bits. Then, the q information bits are combined with the m check bits to obtain a codeword of length n = q + m. The mapping relationship from q-bit information bits to codewords of length n bits is usually represented by a corresponding check matrix H. According to the check matrix H, a codeword sequence can be generated accordingly to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving device decodes the received signal accordingly to determine the original information bits.

[0124] 2. QC-LDPC Code

[0125] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of its check matrix, it can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC codes. When the code length is long, the check matrix H of the LDPC code will be very large, so H is usually represented in blocks: the complete check matrix H is regarded as a block consisting of multiple Z c ×Z c Specifically, the complete check matrix H can be generated from a base matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H.b The elements in can also be called quasi-cyclic (QC) blocks.

[0126] Based on the basis matrix H b And the improvement value Z c (lifting size), the basis matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0127] For example, the basis matrix H of the QC-LDPC code b As shown below:

[0128]

[0129] It can be seen that the basis matrix H b The size of the matrix H is 4 rows and 24 columns. b Each element in represents a Z c The square matrix of order, element represents the cyclic permutation matrix, i represents the cyclic shift value, and i is an integer. In addition, the basis matrix H b The "-1" in represents an all-zero matrix, and "0" represents the identity matrix.

[0130] For example, As shown below:

[0131]

[0132] Optionally, the basis matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0133] The above basis matrix can also be called basis graph (BG).

[0134] The BG graph model of QC-LDPC code is BG = (X, Y, F), where X corresponds to the variable, Y corresponds to the check equation, and F is the edge relationship. The value after lifting is Z c After the QC expansion of , we get the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is the edge relationship between the variable node and the check node. The corresponding check matrix column number N = |V| = Z c |X|, the number of check matrix rows M = |C| = Z c |Y|, the number of non-zero elements in the check matrix is ​​|E|=Z c |F|.

[0135] The current data channel supports information bits ranging from 1 to 8448. The standard describes two check matrices: BG 1 and BG 2 For a BG, different Z c To adapt the rate matching of different code lengths. c The storage of lists and offset value lists can be based on Z c Rate matching is performed using a list of values ​​and a list of offset values.

[0136] 3. Non-zero elements and zero elements

[0137] In the check matrix, a zero element indicates that there is no connection or edge between the variable node and the check node, and a non-zero element indicates that there is a connection or edge between the variable node and the check node.

[0138] In the LDPC basis matrix, the zero element represents Z c The non-zero elements represent Z c The identity matrix of order or based on Z c The circulant permutation matrix of the identity matrix of order , the value of the non-zero element represents the circulant shift value or offset value (shifting value, SV) relative to the identity matrix.

[0139] This application does not limit the specific forms of zero elements and non-zero elements. Figure 2 In the check matrix H shown in the figure, "0" is used to represent a zero element, and "1" is used to represent a non-zero element. For another example, as described above, the base matrix H b In the example, "-1" is used to represent zero elements, and "non-negative values" are used to represent non-zero elements.

[0140] 4. Column weight and row weight

[0141] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. Column weight can also be called column degree or column degree.

[0142] For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. Row weight can also be called row degree or row degree.

[0143] For example, Figure 2 As shown, the first column of the check matrix H has a column weight of 2 and the first row weight of 4. For another example, as described above, the base matrix H b The first column has a column weight of 4 and the first row has a row weight of 20.

[0144] 5. Structure of the check matrix

[0145] Figure 4 It is a schematic diagram of the structure of the check matrix.

[0146] like Figure 4 As shown in (a), the check matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region may include Figure 4 (b) shows part A and part B, where part A corresponds to information bits (or information bits, system bits, etc.), and part B is a square matrix and corresponds to core check bits (or core check bits). The all-zero area can correspond to Figure 4 Part C of (b) is an all-zero matrix. The incremental redundancy region can correspond to Figure 4 Part D of (b). The Lapter-like region may correspond to Figure 4 Part E of (b) can be a unit matrix, corresponding to the parity bits of the low code rate extension.

[0147] Figure 4 The check matrix of the LDPC code shown in FIG. 1 adopts a "raptor-like" structure, which can be gradually extended to a low code rate through a high code rate core matrix. In actual use, Figure 4 As shown in (a), the first X rows and Y columns of the check matrix can be truncated. As the code rate decreases from high to low, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0148] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0149] 6. Information column and check column

[0150] The columns of the LDPC base matrix consist of information columns and check columns.

[0151] Information column: corresponds to the information bit (also called information bit, system bit, etc.), which is the column corresponding to part A.

[0152] Check column: corresponds to the check bit (or check digit, etc.), and can include a core check column and an extended check column, where the core check column is the column corresponding to part B, and the extended check column is the column corresponding to part C or part E. The extended check column can also be called a raptor-like column. The extended check column corresponds to the extended node.

[0153] 7. Core rows, core columns, and core matrices

[0154] Core rows: The core rows of the LDPC base matrix are the rows corresponding to the core check bits. In other words, the core rows are the rows corresponding to the high code rate region, or the rows corresponding to part A, part B, or part C.

[0155] Core columns: may include all information columns and all core check columns. In other words, core columns are columns corresponding to the high bit rate area, or columns corresponding to part A + part B.

[0156] Kernel Matrix: It is a matrix region consisting of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is ​​the high-rate region of the LDPC base matrix, or the portion consisting of Part A and Part B.

[0157] 8. Information transmission process

[0158] Figure 5 It is a schematic diagram of the information transmission process. Figure 5 As shown in the figure, information is sent from the source, and after source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, it reaches the destination, completing the transmission of information from the source to the destination. Figure 5 The processing shown in the upper layer (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. Figure 5 Source coding, channel coding, channel decoding and source recovery are shown.

[0159] In the current LDPC codes, the coding structure of the LDPC base matrix has a large restriction on the degree distribution, and the weight of the coding structure is light, which is not conducive to fast convergence and affects the coding or decoding performance. For example, the coding structure of the IRA code is a dual diagonal structure, and its main features are that it contains a dual diagonal structure and a column with a column weight of 3, and the degree distribution is a column with a column weight of 3 and several columns with a column weight of 2, and has a coupled structure. Figure 6It is a schematic diagram of the coding structure of IRA code at different code rates, where blank squares represent zero elements, "0" represents non-zero elements with an offset value of 0 (i.e., the unit matrix), and "1" represents non-zero elements with an offset value of 1. The degree distribution of the coding structure of IRA code is very restricted; the column weight of the dual diagonal structure is relatively light, and the nodes with a column weight of 2 are coupled with each other, making it difficult to ensure the code distance, and it is not suitable for high-reliability and low-latency scenarios; the coding structure of IRA code is relatively light (or the edge density is low), which is not conducive to fast convergence and is not suitable for high-throughput scenarios. For another example, the quasi-LaptrinhX coding structure is a unit matrix, and the column degree of this coding structure is all 1. The degree distribution of the coding structure is more restricted and has low flexibility, which is not conducive to the error floor required for high-reliability and low-latency scenarios and the fast convergence required for high-throughput scenarios. For example, the lower triangular coding structure or the upper triangular coding structure has non-zero elements only on the diagonal and below (or above) the diagonal, and there are also a certain number of columns with a column degree of 1, which is also not conducive to the error leveling required by high-reliability and low-latency scenarios and the rapid convergence required by high-throughput scenarios.

[0160] In response to the above problems, the present application provides a communication method and a communication device based on LDPC codes, in order to improve the degree distribution flexibility and edge density of the coding structure of the LDPC base matrix, thereby achieving rapid convergence and improving encoding or decoding performance.

[0161] The method embodiments of the present application are described below in conjunction with the accompanying drawings.

[0162] Figure 7 It is a schematic flowchart of a communication method 700 based on LDPC code provided in the present application.

[0163] The method 700 may be executed by a transmitting device. Unless otherwise specified, the "transmitting device" may refer to the transmitting device itself or to a device that can support the transmitting device to implement its functions. For the sake of convenience, the transmitting device is used to describe the method 700. The transmitting device may be a terminal device or a network device.

[0164] Method 700 may include at least part of the following.

[0165] Step 701: The transmitting end device obtains an information bit sequence.

[0166] That is to say, if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0167] The transmitting end device acquires the information bit sequence, which may refer to: the transmitting end device performs source coding on the source symbols to generate the information bit sequence. The transmitting end device acquires the information bit sequence, which may also refer to: the transmitting end device receives the information bit sequence from other communication devices.

[0168] Step 702: The transmitting end device performs LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain an LDPC codeword sequence.

[0169] The LDPC base matrix may be a base matrix stored in the device or a base matrix predefined by the protocol, or may be a base matrix further obtained based on the stored base matrix or the base matrix predefined by the protocol, without limitation.

[0170] In an embodiment of the present application, the LDPC base matrix includes a first matrix region, which is composed of the 1st row to the wth row and the rth column to the r+w-1th column of the LDPC base matrix, where w and r are positive integers. For example, the LDPC base matrix can be divided into Figure 4 In the case of the five regions A, B, C, D, and E shown, the first matrix region may be region B. The following describes various embodiments of the present application by taking the first matrix region as region B as an example.

[0171] The first matrix region may include a first square matrix. The first square matrix includes at least two columns with a column weight greater than or equal to 3 and / or at least one column with a column weight greater than or equal to an even number of 4, and each row of the first square matrix has a row weight greater than or equal to 2. The encoding structure of the first square matrix will be described below in conjunction with Figure 8 Fig.12 Describe in detail.

[0172] Step 703: The transmitting end device outputs an LDPC codeword sequence.

[0173] The subsequent transmitting device may map the LDPC codeword sequence into an air interface signal and send the air interface signal to the receiving device.

[0174] The column weight of the columns included in the first square matrix of the LDPC base matrix of the embodiment of the present application is not limited to 2 or 3, and can be a value other than 2 and 3, such as the column weight can be greater than 2, and the column weight can be greater than 3, and the column weight can be an even number greater than or equal to 4. Therefore, the degree distribution of the coding structure of the first square matrix is ​​more flexible, and the first square matrix includes at least two columns with column weights greater than or equal to 3 and / or at least one column with a column weight greater than or equal to 4. Even number, so the weight or edge density of the first square matrix is ​​higher. Therefore, the degree distribution of the coding structure of the LDPC base matrix of the embodiment of the present application is more flexible, and the weight or edge density of the coding structure is also higher, which helps to achieve rapid convergence and improve coding or decoding performance.

[0175] The embodiments of the present application focus on improving the B region of the LDPC base matrix, that is, improving the coding structure of the LDPC base matrix.

[0176] The encoding structure of the first matrix is ​​described in detail below.

[0177] The embodiments of the present application provide three possible degree distributions of the first matrix, which are introduced below respectively.

[0178] 1. Degree distribution 1

[0179] When the first square matrix adopts degree distribution 1, the column weight of each column and the row weight of each row of the first square matrix are both G, and G is greater than or equal to 3. And the first square matrix includes the first row and the second row, the number of elements of the intersection of the set composed of the column numbers of the columns where the non-zero elements of the first row are located and the set composed of the column numbers of the columns where the non-zero elements of the second row are located is 2, the first row and the second row are any two rows of the first square matrix, for example, the set composed of the column numbers of the columns where the non-zero elements of the first row are located is {1,2,3}, the set composed of the column numbers of the columns where the non-zero elements of the second row are located is {2,3,4}, and the intersection of the two sets is {2,3}.

[0180] In other words, the column degree distribution of the first square matrix is ​​G-regular and the row degree distribution is G-regular, and G is greater than or equal to 3. Degree distribution one can also be called G-regular degree distribution. For example, when G=3, degree distribution one is 3-regular degree distribution.

[0181] The degree distribution helps the code distance of LDPC code to grow linearly with the code length, and helps to construct a coding structure that is easy to implement.

[0182] In a possible implementation, the first square matrix includes a first column and a second column, the intersection of a set consisting of row numbers of rows where non-zero elements of the first column are located and a set consisting of row numbers of rows where non-zero elements of the first column are located includes at most one row number, the first column and the second column are any two columns of the first square matrix; the row numbers of any two rows of the first square matrix belong to the set consisting of row numbers of rows where non-zero elements of a column of the first square matrix are located. In this implementation, the encoding structure of the first square matrix may correspond to a Stinier system.

[0183] Taking G=3 as an example, some examples of the first square matrix are given below.

[0184] Example 1

[0185] The first square matrix is ​​a 4×4 matrix, and the distribution of zero elements and non-zero elements of the first square matrix can be:

[0186]

[0187] Among them, "0" represents a zero element and "1" represents a non-zero element.

[0188] The embodiments of the present application do not limit the specific values ​​of the non-zero elements of the first matrix (ie, the offset values).

[0189] Exemplarily, the first square matrix is ​​a 4×4 matrix, and the values ​​of the non-zero elements of the first square matrix can be shown in any of the following matrices:

[0190]

[0191] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "-2x" means non-zero elements and offset value is Z c -2x, "-3x" means non-zero elements and offset value is Z c -3x, "-4x" means non-zero elements and offset value is Z c -4x, Z c is the lifting value, and x is a positive integer. It can be seen from the above matrices that the offset values ​​of the non-zero elements in the first row and the first column are all 0. Each matrix has only one unknown number x that can float, and the values ​​of all other positions are determined by this unknown number. The value of x can be any positive integer, and the general value is 1~Z c -1.

[0192] Example 2

[0193] The first square matrix is ​​a 5×5 matrix, and the distribution of zero elements and non-zero elements of the first square matrix can be:

[0194]

[0195] Among them, "0" represents a zero element and "1" represents a non-zero element.

[0196] The embodiments of the present application do not limit the specific values ​​of the non-zero elements of the first matrix (ie, the offset values).

[0197] Exemplarily, the first square matrix is ​​a 5×5 matrix, and the values ​​of the non-zero elements of the first square matrix can be shown in any of the following matrices:

[0198]

[0199] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "-2x" means non-zero elements and offset value is Zc -2x, "y" means non-zero elements and offset value is y, Z c is the lifting value, x and y are positive integers. Among them, x and y can be the same or different. It can be seen from the above matrices that the offset values ​​of the non-zero elements in the first row and the first column are all 0. Each matrix has two floating unknowns, x and y, and the values ​​of all other positions are determined by these unknowns. The values ​​of x and y can be any positive integers, generally ranging from 1 to Z. c -1.

[0200] Taking G=3 and a first square matrix of m×m as an example, the distribution characteristics of the edges of the first square matrix are given below, where m is a positive integer.

[0201] "Edges" can also be called "non-zero elements". In the following text, "edges" will be used to describe them.

[0202] The edges of the first matrix include first-category edges, second-category edges, and optional third-category edges.

[0203] 1) The first type of edge connection

[0204] The locations of the first type of edges include: the 1st to 3rd columns of the 1st row of the first matrix, the 4th to 5th columns of the 2nd row, …, the 2tth to 2t+1th columns of the tth row, and, the 1st to 3rd rows of the 1st column of the first matrix, the 4th to 5th rows of the 2nd column, …, the 2tth to 2t+1th rows of the tth column, among which the 2tth to 2t+1th columns of the tth row and the 2tth to 2t+1th rows of the tth column are true when t is greater than or equal to 2.

[0205] In other words, the first type of edge is the first edge in each row of the first matrix or the first edge in each column of the first matrix.

[0206] Figure 8 is an example of a first-class edge. The light grey blocks are where the first-class edges are located.

[0207] like Figure 8 As shown in (a), for the first 4×4 square matrix, the positions of the first type of edges include: the 1st column to the 3rd column of the 1st row, the 4th column of the 2nd row, and the 1st row to the 3rd row of the 1st column of the first square matrix, and the 4th row of the 2nd column.

[0208] like Figure 8 As shown in (b), for the first square matrix of 5×5, the positions of the first type of edges include: the 1st column to the 3rd column of the 1st row, the 4th column to the 5th column of the 2nd row, and the 1st row to the 3rd row of the 1st column of the first square matrix, and the 4th row to the 5th row of the 2nd column.

[0209] like Figure 8As shown in (c), for the first 6×6 square matrix, the positions of the first type of edges include: the 1st column to the 3rd column of the 1st row, the 4th column to the 5th column of the 2nd row, and the 6th column of the 3rd row, as well as the 1st row to the 3rd row of the 1st column of the first square matrix, the 4th row to the 5th row of the 2nd column, and the 6th row of the 3rd column.

[0210] 2) The second type of edge connection

[0211] The second type of edge is located in the first sub-region of the first matrix. The first sub-region is composed of the first matrix region. Go to row m, row The structure consists of columns from the first column to the mth column.

[0212] The second type of edge position can be replaced by Q Indicates that Q permutations are mutually different, and Q is a positive integer. And p i ≠p j For any i≠j, i and j are less than or equal to A positive integer. The i-th row of the first sub-region and the p-th row i Column correlation, or in other words, the i-th row and the p-th row of the first sub-region i A complete permutation indicates that the number of edges corresponding to the permutation is the permutation Length

[0213] If the position of the second type of edge is represented by Q permutations, if the position of the second type of edge is represented by Q complete permutations, then the total number of edges included in the first sub-region is permutations Length Q times, that is

[0214] For example, when the first matrix adopts 3-regular degree distribution, the second type of edge can be composed of two edges with length Specifically, the position of the second type of edge can correspond to two sequences, namely the first sequence and the second sequence. The first sequence and the second sequence are Two permutation forms of . Among them, the elements in the first sequence are The elements in the second sequence are the same as The elements in the first sequence are the same, and the order of the elements in the first sequence is different from the order of the elements in the second sequence. i Indicates the i-th row and p-th row of the first sub-region i Columns are non-zero elements, i is less than or equal to A positive integer.

[0215] For example, m=5, The permutation forms of {1,2,3} include {1,2,3}, {1,3,2}, {2,1,3}, {2,3,1}, {3,1,2} and {3,2,1}. The first sequence and the second sequence may be any two of the permutation forms of {1,2,3}, such as the first sequence is {1,2,3} and the second sequence is {2,3,1}.

[0216] The embodiments of the present application do not limit the specific method of replacement.

[0217] In a possible implementation, at least one of the Q permutations is a cycle. Taking the sequence {1,2,3,4,5,6,7,8,9,10} as an example, the sequence obtained by the cycle may be, for example, {1,2,3,4,5,6,7,8,9,10}, {2,3,4,5,6,7,8,9,10,1} or {3,4,5,6,7,8,9,10,1,2}, etc.

[0218] As an example, replace Satisfy the conditions Where s is a constant and mod means remainder. Optionally, s is greater than or equal to 0 and less than or equal to

[0219] As another example, the above cycle is a segmented cycle. Take the sequence {1,2,3,4,5,6,7,8,9,10} as an example, assuming that it is divided into two segments {1,2,3,4,5} and {6,7,8,9,10}, each segment is a cycle, and the sequence obtained by the cycle can be, for example, {2,3,4,5,1,6,7,8,9,10}, {3,4,5,1,2,7,8,9,10,6} or {3,4,5,1,2,8,9,10,6,7}, etc.

[0220] Fig. 9 is an example of an edge of the second type.

[0221] The dotted box is the first sub-area, and the dark gray and black squares are the locations of the second type of edges.

[0222] like Fig. 9As shown in (a), for the first 4×4 matrix, the first sub-region is the region from the 3rd row to the 4th row and the 3rd column to the 4th column of the first matrix, the position of the dark gray square corresponds to permutation 1, which is the sequence {1,2}, and the position of the black square corresponds to permutation 2, which is the sequence {2,1}. Permutation 1 and permutation 2 are two permutation forms of the sequence {1,2}, {1,2} indicates that the 1st row and the 1st column of the first sub-region have a connecting edge and the 2nd row and the 2nd column have a connecting edge, {2,1} indicates that the 1st row and the 2nd column of the first sub-region have a connecting edge and the 2nd row and the 1st column have a connecting edge, so that the positions of the second type of connecting edges include: the 1st row and the 1st column of the first sub-region, the 2nd row and the 2nd column of the first sub-region, the 2nd row and the 1st column of the first sub-region, and the 1st row and the 2nd column of the first sub-region.

[0223] like Fig. 9 As shown in (b), for the first square matrix of 5×5, the first sub-region is the region from the 3rd row to the 5th row and the 3rd column to the 5th column of the first square matrix. The position of the dark gray square corresponds to permutation 1, which is the sequence {1,2,3}. The position of the black square corresponds to permutation 2, which is the sequence {2,3,1}. Permutation 1 and permutation 2 are two permutation forms of the sequence {1,2,3}. {1,2,3} means that the 1st row and the 1st column of the first sub-region have a connected edge, the 2nd row and the 2nd column have a connected edge, and the 3rd row and the 3rd column have a connected edge. {2,3,1} means that the 1st row and the 2nd column of the first sub-region have a connected edge, the 2nd row and the 3rd column have a connected edge, and the 3rd row and the 1st column have a connected edge. In this way, the locations of the second type of edges include: the 1st row and 1st column of the first sub-area, the 2nd row and 2nd column of the first sub-area, the 3rd row and 3rd column of the first sub-area, the 1st row and 2nd column of the first sub-area, the 2nd row and 3rd column of the first sub-area, and the 3rd row and 1st column of the first sub-area.

[0224] like Fig. 9As shown in (c), for the first 6×6 square matrix, the first sub-region is the region from the 4th row to the 6th row and the 4th column to the 6th column of the first square matrix. The position of the dark gray square corresponds to permutation 1, which is the sequence {1,2,3}. The position of the black square corresponds to permutation 2, which is the sequence {2,3,1}. Permutation 1 and permutation 2 are two permutation forms of the sequence {1,2,3}. {1,2,3} means that the 1st row and the 1st column of the first sub-region have a connected edge, the 2nd row and the 2nd column have a connected edge, and the 3rd row and the 3rd column have a connected edge. {2,3,1} means that the 1st row and the 2nd column of the first sub-region have a connected edge, the 2nd row and the 3rd column have a connected edge, and the 3rd row and the 1st column have a connected edge. In this way, the locations of the second type of edges include: the 1st row and 1st column of the first sub-area, the 2nd row and 2nd column of the first sub-area, the 3rd row and 3rd column of the first sub-area, the 1st row and 2nd column of the first sub-area, the 2nd row and 3rd column of the first sub-area, and the 3rd row and 1st column of the first sub-area.

[0225] Fig. 9 The permutations 1 and 2 corresponding to the first sub-regions of the three first matrices shown are both cyclic.

[0226] Fig.10 is another example of an edge of the second type.

[0227] The dotted box is the first sub-area, and the dark gray and black squares are the locations of the second type of edges. Fig.10 As shown, for the 7×7 first square matrix, the first sub-region is the region from the 4th row to the 7th row and the 4th column to the 7th column of the first square matrix. The position of the dark gray square corresponds to permutation 1, which is the sequence {1,2,3,4}. The position of the black square corresponds to permutation 2, which is the sequence {3,4,2,1}. Permutation 1 and permutation 2 are two permutation forms of the sequence {1,2,3,4}. {1,2,3,4} indicates that the 1st row and the 1st column of the first sub-region have a connected edge, the 2nd row and the 2nd column have a connected edge, the 3rd row and the 3rd column have a connected edge, and the 4th row and the 4th column have a connected edge. {3,4,2,1} indicates that the 1st row and the 3rd column of the first sub-region have a connected edge, the 2nd row and the 4th column have a connected edge, the 3rd row and the 2nd column have a connected edge, and the 4th row and the 1st column have a connected edge. In this way, the positions of the second type of edges include: the 1st row and 1st column of the first sub-area, the 2nd row and 2nd column of the first sub-area, the 3rd row and 3rd column of the first sub-area, the 4th row and 4th column of the first sub-area, the 1st row and 3rd column of the first sub-area, the 2nd row and 4th column of the first sub-area, the 3rd row and 2nd column of the first sub-area, and the 4th row and 1st column of the first sub-area.

[0228] Fig.10 The permutation 2 corresponding to the first sub-region of the first matrix shown is a segmented cycle. Fig.10The first square matrix shown may correspond to a Stoney system. The description of the Stoney system can be found above.

[0229] If there are some columns with a column weight of 2 in the first square matrix, then this part is composed of a subset of the edges corresponding to the two permutations. For example, among the two permutations corresponding to the first sub-region, one can be a complete permutation and the other can be an incomplete permutation. For another example, both permutations corresponding to the first sub-region are incomplete permutations. In this case, the first square matrix is ​​actually not a 3-regular degree distribution, but a degree distribution three, which will be described below.

[0230] Fig.11 is another example of an edge of the second type.

[0231] The dotted box is the first sub-area, and the dark gray and black squares are the locations of the second type of edges.

[0232] Fig.11 As shown in (a), for the first 6×6 matrix, the first sub-region is the region from the 4th row to the 6th row and the 4th column to the 6th column of the first matrix. The position of the dark gray square corresponds to permutation 1, and the position of the black square corresponds to permutation 2. Permutation 1 is an incomplete permutation of the sequence {1,2,3}, and permutation 2 is a complete permutation of the sequence {1,2,3}.

[0233] Fig.11 As shown in (b), for the first 6×6 matrix, the first sub-region is the region from the 4th row to the 6th row and the 4th column to the 6th column of the first matrix. The position of the dark gray square corresponds to permutation 1, and the position of the black square corresponds to permutation 2. Both permutation 1 and permutation 2 are incomplete permutations of the sequence {1,2,3}.

[0234] 3) The third type of edge connection

[0235] If m is an even number, the first matrix also includes the third type of edges, which are located in the first matrix. Row, No. If m is an odd number, the first square matrix does not include the third type of edges.

[0236] Fig.12 is an example of a third type of edge.

[0237] exist Fig.12 In the figure, the obliquely crossed squares are where the third type of edges are located.

[0238] like Fig.12 As shown in (a), for the first 4×4 square matrix, m=4 is an even number, then the first square matrix has a third type of edge, and the position of the third type of edge is the 2nd row and 2nd column of the first square matrix.

[0239] like Fig.12 As shown in (b), for the first square matrix of 5×5, m=5 is an odd number, and the first square matrix does not include the third type of edges.

[0240] like Fig.12 As shown in (c), for the first 6×6 square matrix, m=6 is an even number, then the first square matrix has a third type of edge, and the position of the third type of edge is the 3rd row and the 3rd column of the first square matrix.

[0241] The above describes the distribution characteristics of the edges of the first square matrix of the 3-regular degree distribution. The following describes the characteristics of the offset values ​​of the positions of the edges of the first square matrix (ie, the non-zero elements of the first square matrix).

[0242] 1) The offset value of the first type of edge position

[0243] In a possible implementation, the offset values ​​of the positions where the first type of edges are located can all be 0. An offset value of 0 indicates that the position is a unit matrix after being lifted according to the lifting value.

[0244] 2) The offset value of the second type of edge position

[0245] In a possible implementation, the offset value of the second type of edge position can be determined by t values, where all t values ​​are greater than or equal to 0, and t is a positive integer. Assume that t values ​​are x 1 、x 2 , …, x t , the offset value of a position with a second-class edge can be k i x i +k j x j +..., where k i It should be noted that the offset values ​​corresponding to the second-type edges at different positions may be the same or different.

[0246] Exemplarily, t=1.

[0247] For example, all locations with second-class edges have an offset value of x 1 .

[0248] For example, the offset value of the position with the second type of edge belongs to {x 1 ,-x 1}.

[0249] For another example, the offset value of the position with the second type of edge can be k 1 x 1 , k 1 is a non-negative integer. The offset values ​​corresponding to the second-type edges at different positions can be the same or different, that is, the k corresponding to the second-type edges at different positions 1Can be the same or different, such as k 1 = 1, -1 or -3, the offset value of the position with the second type of edge belongs to {x 1 ,-x 1 ,-3x 1}, as shown in the first matrix in the values ​​of the non-zero elements of the first square matrix in Example 1 above.

[0250] In the above examples, the elimination methods go from simple to complex, and the cycle properties gradually become better. In actual implementation, we can balance the complexity and cycle properties and choose the appropriate solution.

[0251] Exemplarily, t=2.

[0252] For example, the offset value of the position of the second type of edge belongs to {x 1 ,x 2}.

[0253] For example, the offset value of the position of the second type of edge belongs to {x 1 ,-x 1 ,x 2 ,-x 2}.

[0254] For another example, the offset value of the position with the second type of edge can be k 1 x 1 +k 2 x 2 , k 1 and k 2 is a non-negative integer. The offset values ​​corresponding to the second-type edges at different positions can be the same or different, that is, the k corresponding to the second-type edges at different positions 1 and k 2 The value combination of can be the same or different, such as k 1 and k 2 The value combinations include: k 1 =3 and k 2 =2, k 1 = -1 and k 2 =0, k 1 =1 and k 2 =1, and k 1 = 0 and k 2 = -1, the offset value of the position of the second type of edge belongs to {3x 1 +2x 2 ,-x 1 ,x 1 +x 2 ,x 1}.

[0255] In the above examples, the elimination methods go from simple to complex, and the cycle properties gradually become better. In actual implementation, we can balance the complexity and cycle properties and choose the appropriate solution.

[0256] Exemplarily, t is greater than or equal to 3.

[0257] For example, the offset value of the position with the second type of edge can be x 1 、x 2 , …, x t The linear combination of at most two items in is k i x i +k j x j The offset values ​​corresponding to the second-type edges at different positions may be the same or different.

[0258] In another possible implementation, the second type of edge corresponds to two permutations, and the offset values ​​of all edge positions corresponding to one of the two permutations are 0. An offset value of 0 indicates that the position is a unit matrix after being lifted according to the lifting value.

[0259] 3) The offset value of the location of the third type of edge

[0260] In a possible implementation, the offset value of the location where the third type of edge is located is not 0.

[0261] In another possible implementation, the offset value of the location of the third type of edge can be determined by t values, where all t values ​​are greater than or equal to 0, and t is a positive integer. For a specific description, reference can be made to the method for determining the offset value of the location of the second type of edge.

[0262] 2. Degree distribution 2

[0263] Assume that the first square matrix is ​​an m×m matrix, where m is a positive integer. When the first square matrix adopts degree distribution 2, the first square matrix includes m-1 columns with even weight and 1 column with odd weight, and the weight of each row of the first square matrix is ​​2 or 3. Among them, the m-1 columns with even weight include at least one column with an even weight greater than or equal to 4, and the number of rows with a weight of 3 in the first square matrix is ​​the number of columns with an even weight greater than or equal to 4 plus 1.

[0264] The advantage of degree distribution 2 is that it can support larger column degrees, thus having a better decoding threshold and being easy to encode and implement.

[0265] In a possible implementation, the first square matrix includes 1 column with a column weight of 4, 1 column with a column weight of 3, and m-2 columns with a column weight of 2.

[0266] Example 3: The first square matrix is ​​a 4×4 matrix, that is, m=4. The degrees of the four columns of the first square matrix are 4, 2, 3, and 2, respectively. The degrees of the four rows of the first square matrix are 3, 2, 3, and 3, respectively. The distribution of zero elements and non-zero elements of the first square matrix can be:

[0267]

[0268] Among them, "0" represents a zero element, and "1" represents a non-zero element. The embodiment of the present application does not limit the specific values ​​(i.e., offset values) of the non-zero elements of the first matrix. Exemplarily, the values ​​of the non-zero elements of the first matrix can be shown in the following matrix:

[0269]

[0270] Among them, "-1" represents a zero element, "x", "y", "z", "a", "b" or "c" represents a non-zero element and the offset values ​​are x, y, z, a, b or c respectively, x≠y, a≠b, x, y, z, a and c are positive integers, and b is a non-negative integer.

[0271] Example 4: The first square matrix is ​​a 5×5 matrix, that is, m=5. The degrees of the five columns of the first square matrix are 4, 3, 2, 2, and 2, respectively. The degrees of the five rows of the first square matrix are 3, 3, 3, 2, and 2, respectively. The distribution of zero elements and non-zero elements of the first square matrix can be:

[0272]

[0273] Among them, "0" represents a zero element, and "1" represents a non-zero element. The embodiment of the present application does not limit the specific values ​​(i.e., offset values) of the non-zero elements of the first matrix. Exemplarily, the values ​​of the non-zero elements of the first matrix can be shown in the following matrix:

[0274]

[0275] Among them, "-1" represents a zero element, "x", "y", "a", "b", "c", "d" or "p" represents a non-zero element and the offset values ​​are x, y, a, b, c, d or p respectively, x≠y, b≠d, x, y, a, p, c and d are positive integers, and b is a non-negative integer.

[0276] In a possible implementation, the first square matrix includes 2 columns with a column weight of 4, 1 column with a column weight of 3, and m-3 columns with a column weight of 2.

[0277] Example 5: The first square matrix is ​​a 5×5 matrix, that is, m=5. The degrees of the five columns of the first square matrix are 4, 3, 2, 2, and 4, respectively. The degrees of the five rows of the first square matrix are 3, 3, 4, 3, and 2, respectively. The distribution of zero elements and non-zero elements of the first square matrix can be:

[0278]

[0279] Among them, "0" represents a zero element, and "1" represents a non-zero element. The embodiment of the present application does not limit the specific values ​​(i.e., offset values) of the non-zero elements of the first matrix. Exemplarily, the values ​​of the non-zero elements of the first matrix can be shown in the following matrix:

[0280]

[0281] Among them, "-1" represents a zero element, "x", "y", "a", "b", "c", "d", "e" or "p" represents a non-zero element and the offset values ​​are x, y, a, b, c, d, e or p respectively, x≠y, b≠d, a≠e, x, y, a, p, c, d and e are positive integers, and b is a non-negative integer.

[0282] It should be noted that the way of taking values ​​of the non-zero elements of the first matrix shown in the above matrix is ​​only an example. The general description can be as follows:

[0283] 1) Each column of the first matrix has at least one value among x, y, z, a, c, d, e or p, and the number of times a certain value appears in the column is an even number, such as x, y, z, a, c, d, e and p appear 2 times each in the above matrix.

[0284] 2) Different letters in the same column represent different offset values, and different letters in different columns represent the same or different offset values.

[0285] 3) Assume that the row sets where x, y, z, a, c, d, e, and p appear are R x ,R y ,R z ,R a ,R c ,R d ,R e ,R p , then the intersection of any two of these row sets contains at most one element. Specifically, the intersection of row sets corresponding to different letters in different columns contains one element, such as R in Example 4. x ={1,2}, R a ={2,5}, R x and R a The intersection of the rows corresponding to different letters in the same column is an empty set, such as R in Example 4. x ={1,2}, R y ={3,4}, R x and R y The intersection of is the empty set.

[0286] 4) The column where b is located has an odd column weight, and the column intersects with at least one row with a weight of 2. For example, in Example 4, b is in the 2nd column, and the 2nd column intersects with the 4th and 5th rows with a weight of 2. And if the column intersects with only one row with a weight of 2, then the other column intersecting with the row with a weight of 2 and the column intersect with a row with a weight of 3. For example, in Example 3, b is in the 3rd column, and the 3rd column intersects with the 2nd row with a weight of 2, and the other column intersecting with the 2nd row is the 1st column, and the 3rd column and the 1st column intersect with the 3rd row with a weight of 3. For example, in Example X, b is in the 2nd column, and the 2nd column intersects with the 5th row with a weight of 2, and the other column intersecting with the 5th row is the 5th column, and the 2nd column and the 5th column intersect with the 4th row with a weight of 3.

[0287] 3. Degree distribution three

[0288] Assume that the first square matrix is ​​an m×m matrix, where m is a positive integer. When the first square matrix adopts degree distribution three, the column weight of each column of the first square matrix is ​​2 or 3, and the number of columns with a column weight of 3 in the first square matrix is ​​greater than or equal to 2, and the number of columns with a column weight of 2 is greater than 0.

[0289] In a possible implementation, the number of columns with a column weight of 2 in the first matrix is ​​an even number.

[0290] In another possible implementation, the first square matrix includes 2 columns with a column weight of 2 and m-2 columns with a column weight of 3.

[0291] In another possible implementation, m is an even number greater than 0, and the first square matrix includes m-2 columns with a column weight of 2 and 2 columns with a column weight of 3.

[0292] In another possible implementation, m is an odd number greater than 0, and the first square matrix includes m-3 columns with a column weight of 2 and 3 columns with a column weight of 3.

[0293] Example 6: The first square matrix is ​​a 4×4 matrix, that is, m=4. The degrees of the four columns of the first square matrix are 3, 3, 2, and 2 respectively. The degrees of the four rows of the first square matrix are 3, 3, 2, and 2 respectively. The distribution of zero elements and non-zero elements of the first square matrix can be:

[0294]

[0295] Among them, "0" represents a zero element and "1" represents a non-zero element. The distribution of the zero element and the non-zero element has two rows that are completely orthogonal, that is, the columns associated with these two rows do not overlap, such as the 3rd and 4th rows of the matrix are completely orthogonal. The embodiment of the present application does not limit the specific values ​​(i.e., offset values) of the non-zero elements of the first square matrix. Exemplarily, the values ​​of the non-zero elements of the first square matrix can be shown in any of the following matrices:

[0296]

[0297]

[0298] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "2x" means non-zero elements and the offset value is 2x, "-2x" means non-zero elements and the offset value is Z c -2x, Z c is the lifting value, and x is a positive integer. It can be seen from the above matrices that the offset values ​​of the non-zero elements in the first row and the first column are all 0. Each matrix has only one unknown number x that can float, and the values ​​of all other positions are determined by this unknown number. The value of x can be any positive integer, and the general value is 1~Z c -1.

[0299] Example 7: The first square matrix is ​​a 5×5 matrix, that is, m=5. The degrees of the five columns of the first square matrix are 3, 3, 3, 2, and 2, respectively. The degrees of the five rows of the first square matrix are 3, 3, 3, 2, and 2, respectively. The distribution of zero elements and non-zero elements of the first square matrix can be:

[0300]

[0301] Among them, "0" represents a zero element, and "1" represents a non-zero element. The embodiment of the present application does not limit the specific value (ie, offset value) of the non-zero element of the first square matrix. Exemplarily, the value of the non-zero element of the first square matrix can be shown in any of the following matrices:

[0302]

[0303] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "z" means non-zero elements and offset value is z, "-z" means non-zero elements and offset value is Z c -z,Z c is the boost value, x and z are positive integers.

[0304] Example 8: The first square matrix is ​​a 5×5 matrix, that is, m=5. The degrees of the five columns of the first square matrix are 3, 3, 3, 3 and 2 respectively. The degrees of the five rows of the first square matrix are 3, 3, 3, 3 and 2 respectively. The distribution of zero elements and non-zero elements of the first square matrix can be:

[0305]

[0306] Among them, "0" represents a zero element, and "1" represents a non-zero element. The embodiment of the present application does not limit the specific values ​​(i.e., offset values) of the non-zero elements of the first matrix. Exemplarily, the values ​​of the non-zero elements of the first matrix can be shown in the following matrix:

[0307]

[0308] Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, "z" represents a non-zero element with an offset value of z, and "-z" represents a non-zero element with an offset value of Z c -z,Z c is the boost value, x and z are positive integers.

[0309] It should be noted that the embodiments of the present application do not limit the storage method of the offset value of the non-zero element. Exemplarily, the storage rule can be used, and the stored value can be the value before modulo (i.e., remainder), and the modulo of the boost value when used, or the value after the modulo of the maximum boost value is stored, without limitation.

[0310] It should also be noted that, due to the basic characteristics of LDPC codes, the equivalent matrices of the matrices listed in the above examples (such as Examples 1 to 7) after row swapping and / or column swapping also fall within the scope of the embodiments of the present application. The equivalent matrices of the non-zero elements of the matrices listed above, wherein the values ​​of the entire row and / or the entire column are added with an integer (such as the first row as a whole is added with 1 or the first row as a whole is added with 2, etc.), also fall within the scope of the embodiments of the present application.

[0311] In some other embodiments of the present application, the first matrix region, that is, region B, may further include at least one second matrix. The first matrix and the at least one second matrix do not overlap, and the second sub-region composed of the first matrix and the at least one second matrix includes all diagonal elements of the first matrix region. The embodiment of the present application does not limit the size of the second matrix, and the second matrix may include one element or more elements.

[0312] Specifically, region B may include multiple blocks, and the i-th block in the multiple blocks is composed of the r-th i +1 row to r i+1 row, r i +1+k 0 Column to r i+1 +k 0 Column composition, where k 0 is the number of information columns, r 1=0, i is an integer greater than 1. The number of values ​​of i corresponds to the number of multiple blocks. It can be seen that the multiple blocks do not overlap and are all square matrices, and the multiple blocks contain all diagonal elements of area B. The multiple blocks correspond to the first square matrix and at least one second square matrix mentioned above.

[0313] Fig.13 is an example of the blocks included in the B area. Fig.13 In the example, the B region includes two blocks, block 1 and block 2, that is, the B region includes a first matrix and a second matrix.

[0314] Fig.14 It is a specific example of the blocks included in the B area.

[0315] exist Fig.14 In the example, "-1" represents a zero element, "0" represents a non-zero element with an offset of 0, "x" represents a non-zero element with an offset of x, "y" represents a non-zero element with an offset of y, "z" represents a non-zero element with an offset of z, and "-z" represents a non-zero element with an offset of Z. c -z,Z c is the boost value, x, y, and z are positive integers.

[0316] like Fig.14 (a) and Fig.14 As shown in (b), the 1st to 5th rows and the 1st to 5th columns of area B are the first block, the 6th row and the 6th column are the second block, the degree distribution of the first block is the degree distribution three described above, and the second block has only one element, which is a non-zero element. Figure 4 The shown region B also satisfies degree distribution three as a whole.

[0317] The implementation of this application does not limit the distribution of zero elements and non-zero elements in the area outside the first block and the second block, and the offset value of the non-zero elements. Fig.14 (a) or Fig.14 (b) or other forms are possible.

[0318] Taking the i-th block and the i+1-th block as examples, the distribution of zero elements and non-zero elements in the areas outside the multiple blocks is described below. The following description is valid for any i.

[0319] In a possible implementation, all elements in the region except the ith block and the i+1th block are zero elements. The advantage of this structure is that the ith block and the i+1th block can be encoded completely in parallel, which speeds up the encoding rate.

[0320] Another possible implementation method can be a lower triangular structure, that is, the rth i +1 row to r i+1row, r i+1 +1+k 0 Column to r i+2 +k 0 All the elements in the column are zero elements, and the rth i+1 +1 row to r i+2 row, r i +1+k 0 Column to r i+1 +k 0 The columns may include non-zero elements. The benefit of this structure is that it can support more flexible degree distribution, which helps to improve the decoding threshold of LDPC codes.

[0321] Another possible implementation method can be an upper triangular structure, that is, the rth i +1 row to r i+1 row, r i+1 +1+k 0 Column to r i+2 +k 0 The columns contain non-zero elements, and the rth i+1 +1 row to r i+2 row, r i +1+k 0 Column to r i+1 +k 0 All the elements in the column are zero elements. The advantage of this structure is that it can support more flexible degree distribution, which helps to improve the decoding threshold of LDPC codes.

[0322] Fig.15 is another example of region B. Fig.15 In the example, area B includes two blocks, block 1 and block 2.

[0323] like Fig.15 As shown in (a), the area outside block 1 and block 2 is all zero elements. Fig.15 As shown in (b), the area outside block 1 and block 2 and in the upper right corner of area B includes non-zero elements, and the area outside block 1 and block 2 and in the lower left corner of area B is all zero elements. Fig.15 As shown in (c), the area outside block 1 and block 2 and at the upper right corner of region B is all zero elements, and the area outside block 1 and block 2 and at the lower left corner of region B includes non-zero elements.

[0324] The above description is based on two adjacent blocks as an example, which is actually applicable to more adjacent blocks, such as three adjacent blocks: the i-th block, the i+1-th block and the i+2-th block.

[0325] Fig.16 is another example of region B. Fig.16In the example, area B includes three blocks: block 1, block 2 and block 3.

[0326] like Fig.16 As shown in (a), the areas outside of block 1, block 2, and block 3 are all zero elements. Fig.16 As shown in (b), the area outside of block 1, block 2, and block 3 and in the upper right corner of region B includes non-zero elements, and the area outside of block 1, block 2, and block 3 and in the lower left corner of region B is all zero elements. Fig.16 As shown in (c), the area outside block 1, block 2 and block 3 and at the upper right corner of area B is all zero elements, and the area outside block 1, block 2 and block 3 and at the lower left corner of area B includes non-zero elements.

[0327] Based on the above content, the distribution of zero elements and non-zero elements in the area outside the first sub-area including the first matrix and at least one second matrix can be: the elements in the upper right of the first sub-area are all zero elements, and the elements in the lower left of the first sub-area are all zero elements; or, the elements in the upper right of the first sub-area are all zero elements, and the area in the lower left of the first sub-area includes non-zero elements; or, the area in the upper right of the first sub-area includes non-zero elements, and the elements in the lower left of the first sub-area are all zero elements.

[0328] The present application also does not limit the degree distribution structure or coding structure adopted by at least one second matrix. At least one second matrix can adopt the degree distribution provided by the embodiments of the present application in its entirety, or can partially or completely adopt other degree distributions (such as a dual diagonal structure, a diagonal structure, an upper triangular structure, or a lower triangular structure, etc.).

[0329] A possible implementation method is that when only the first matrix in area B adopts the degree distribution of the embodiment of the present application, that is, when at least one second matrix does not adopt the degree distribution of the embodiment of the present application, the first matrix is ​​in the upper left corner of area B (that is, the first matrix is ​​the block with the smallest number), the area in the upper right corner of the first sub-area includes non-zero elements, and the elements in the lower left corner of the first sub-area are all zero elements.

[0330] Another possible implementation method is that when only the first matrix in area B adopts the degree distribution of the embodiment of the present application, that is, when at least one second matrix does not adopt the degree distribution of the embodiment of the present application, the first matrix is ​​in the lower right corner of area B (that is, the first matrix is ​​the block with the largest number), the elements in the upper right corner of the first sub-area are all zero elements, and the area in the lower left corner of the first sub-area includes non-zero elements.

[0331] In the above two implementations, the first matrix can adopt degree distribution 1. The advantage of this solution is that it can achieve a coding structure column degree of at least 3 on the basis of simplified coding, which helps to ensure that the code distance of the LDPC code increases linearly with the code length.

[0332] It should be noted that the above-mentioned lower left corner, upper right corner and other directional descriptions are for the LDPC base matrix or the first matrix area, and are relative directions.

[0333] The embodiments of the present application focus on improving the B region of the LDPC base matrix, that is, improving the coding structure of the LDPC base matrix, and do not limit the structure and characteristics of the region other than the B region of the LDPC base matrix.

[0334] In a possible implementation, when region B has 3 regular edges, the column weights of all columns in region A are 3 or more, more specifically, the column weights of all columns in region A are 3; or, in the case of perforated columns, at least one column in the perforated columns has a column weight greater than 3, and the column weights of the remaining columns are 3. In terms of row weights, the row weights of rows in region A are the same or differ by at most 1.

[0335] In another possible implementation, when area B has degree distribution 2 or degree distribution 3, the row weights of the rows in area A are non-uniform, with a difference of 1 or 2 between rows.

[0336] Fig.17 It is a schematic flowchart of the communication method 1700 based on LDPC code provided in the present application.

[0337] Method 1700 may be executed by a receiving device. Unless otherwise specified, "receiving device" may refer to the receiving device itself or to a device that can support the receiving device to implement its functions. For ease of description, the receiving device is used in the following description. The receiving device may be a terminal device or a network device.

[0338] Method 1700 may include at least part of the following.

[0339] Step 1701: A receiving device obtains an LDPC codeword sequence.

[0340] The receiving device obtains the LDPC codeword sequence, which may refer to: the receiving device obtains the LDPC codeword sequence from the memory, and the LDPC codeword sequence may be the LDPC codeword sequence obtained by the receiving device based on the air interface signal from the transmitting device. The receiving device obtains the LDPC codeword sequence, which may refer to: the receiving device receives the air interface signal from the transmitting device and obtains the LDPC codeword sequence according to the air interface signal.

[0341] Step 1702: The receiving end device decodes the LDPC codeword sequence according to the LDPC base matrix to obtain an information bit sequence.

[0342] It should be noted that since channel noise signals may be introduced during the transmission of air interface signals, the air interface signals output or sent by the transmitting device may be different from the air interface signals received by the receiving device, and the LDPC codeword sequence obtained thereby may also be different from the LDPC codeword sequence output by the transmitting device.

[0343] Similarly, the LDPC base matrix can be a base matrix stored in the receiving device or a base matrix predefined by the protocol, or can also be a base matrix further obtained based on the stored base matrix or the base matrix predefined by the protocol, without limitation. The LDPC base matrix in method 1700 can refer to the relevant description of the transmitting device, which will not be described in detail here.

[0344] The performance of the LDPC code of the embodiment of the present application is described below in conjunction with simulation results.

[0345] Fig.18 It is the simulation result of SNR of BG2-type-Laptrinhedral coding structure and 3-regular coding structure of the present application under different code lengths and different BLERs.

[0346] High reliability and low latency scenarios (such as URLLC scenarios) have very high reliability requirements. The degree distribution of the BG2-type Laputa coding structure is not conducive to the linear growth of the code distance with the code length. When the BLER is reduced, there will be a relatively serious error floor; the 3-regular coding structure (that is, the 3-regular degree distribution) of this application can improve the degree of the check node and provide a more flexible coding structure, which helps to reduce the error floor. Fig.18 As shown, no error floor occurs until the BLER is below 1e-7. Compared with the BG2-like-Laptrinhedral coding structure, the 3-regular coding structure has a performance gain of about 0.5 dB at 1e-7.

[0347] Fig.19 It is the simulation result of SNR of BG1 dual diagonal coding structure and 3 regular coding structure of this application under different boost values.

[0348] Fig.19 Shown are the simulation results of SNR under different improvement values ​​when the bit rate is 0.926 and the number of iterations is 3. High-throughput scenarios have very high requirements on convergence speed. The 3-regular coding structure (that is, 3-regular degree distribution) of this application can improve the overall edge density and thus improve the convergence speed relative to the dual diagonal coding structure of BG1. In scenarios where the peak bit rate exceeds the core array bit rate, the core check columns need to be punctured, and core check columns with larger column degrees can bring performance gains.

[0349] In this way, based on the coding structure provided by the embodiment of the present application, encoding can be achieved through Gaussian elimination of QC level, and the degree distribution is more flexible, which can adapt to the needs of different communication scenarios. For example, in a high-reliability, low-latency scenario (such as a URLLC scenario), the coding structure provided by the embodiment of the present application can achieve decoupling between 2-degree nodes, a larger minimum trap set, and simple coding can still be achieved when the scale of the coding structure is larger. For another example, in a high-throughput scenario, the coding structure provided by the embodiment of the present application can provide a larger column weight, which helps to converge quickly.

[0350] Combination of the above Figures 7 to 19 , describes in detail the method embodiment provided by the present application, and will be combined with Figure 20 to Figure 22 , describing an apparatus embodiment of the present application.

[0351] It can be understood that in order to realize the functions in the above embodiments, Figure 20 to Figure 22 The device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, this application can be implemented in the form of hardware or a combination of hardware and computer software.

[0352] Fig. 20 and Fig.21 The following is a schematic diagram of the structure of possible devices provided by the embodiments of the present application. These devices can be used to implement the functions of the sending end device or the receiving end device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0353] like Fig. 20 As shown, the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0354] When the apparatus 10 is used to implement the functions of the transmitting end device in the above-mentioned method embodiments, the transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting end device, such as steps 701 and 703, and the processing unit 12 is used to execute the processing step 702 of the transmitting end device. When the apparatus 10 is used to implement the functions of the receiving end device in the above-mentioned method embodiments, the transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving end device, such as step 1701, and the processing unit 12 is used to execute the processing steps of the receiving end device, such as step 1702.

[0355] For a more detailed description of the transceiver unit 11 and the processing unit 12, reference may be made to the relevant description in the above method embodiment, which will not be described again here.

[0356] like Fig.21As shown, the device 20 includes a processing circuit 21. The processing circuit 21 is coupled to a memory 23, and the memory 23 is used to store instructions. When the device 20 is used to implement the method described above, the processing circuit 21 is used to execute the instructions in the memory 23 to implement the functions of the processing unit 12 described above.

[0357] Optionally, the device 20 further includes a memory 23 .

[0358] Optionally, the device 20 further includes a transceiver circuit 22. The transceiver circuit may be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It is understood that the transceiver circuit 22 may be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuit 21 is used to execute instructions to implement the functions of the processing unit 12, and the transceiver circuit 22 is used to implement the functions of the transceiver unit 11.

[0359] Optionally, the apparatus 20 may be a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be a transceiver.

[0360] Optionally, the apparatus 20 may be a chip applied to a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be an input / output interface.

[0361] Exemplarily, when the device 20 is a chip applied to a transmitting device or a receiving device, the chip implements the functions of the transmitting device or the receiving device in the above method embodiment. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, and the information is sent to the transmitting device or the receiving device by other devices; or, the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, and the information is sent to other devices by the transmitting device or the receiving device.

[0362] Fig. 22 Schematic diagram of a chip system 30 provided in an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0363] Among them, the logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to the storage unit and call the instructions in the storage unit so that the chip system 30 can implement the methods and functions of each embodiment of the present application. The input / output interface 32 can be an input / output circuit in the chip system 30, outputting information processed by the chip system 30, or inputting data or signaling information to be processed into the chip system 30 for processing.

[0364] As a solution, the chip system 30 is used to implement the operations performed by the transmitting end device or the receiving end device in each of the above method embodiments.

[0365] For example, the logic circuit 31 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiments; the input / output interface 32 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiments.

[0366] The present application also provides a communication device, including a processing circuit, the processing circuit is coupled to a memory, the memory is used to store computer programs or instructions and / or data, and the processing circuit is used to execute the computer programs or instructions stored in the memory, or read the data stored in the memory to execute the methods in the above method embodiments. Optionally, the processing circuit is one or more. Optionally, the communication device includes a memory. Optionally, the memory is one or more. Optionally, the memory is integrated with the processing circuit, or is separately arranged.

[0367] The present application also provides a chip, including a processing circuit, the processing circuit and a memory are coupled, the memory is used to store computer programs or instructions, and the processing circuit is used to execute the computer programs or instructions stored in the memory to implement the methods executed by the transmitting end device or the receiving end device in the above-mentioned method embodiments. The memory can be located in the chip, or can be independent of the chip and located outside the chip, which is not limited here.

[0368] The present application also provides a computer-readable storage medium on which are stored computer instructions for implementing the methods executed by a transmitting end device or a receiving end device in the above-mentioned method embodiments.

[0369] The present application also provides a computer program product, comprising instructions, which, when executed by a computer, implement the methods performed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0370] The present application also provides a communication system, which includes at least one of the sending end device or the receiving end device in the above embodiments.

[0371] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0372] It is understood that the processing circuit in the embodiments of the present application can be a processor or a circuit in a processor for performing processing operations, and the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0373] The method steps in the embodiments of the present application can be implemented by hardware, or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, register, hard disk, mobile hard disk, compact disc read-only memory (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting end device or a receiving end device. Of course, the processor and the storage medium can also be present in a transmitting end device or a receiving end device as discrete components.

[0374] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc; it may also be a semiconductor medium, for example, a solid-state hard disk.

[0375] In the various embodiments of the present application, unless otherwise specified or provided for in any logical conflict, the terms and / or descriptions between the different embodiments are consistent and may be referenced to each other, and the technical features in the different embodiments may be combined to form new embodiments according to their inherent logical relationships.

[0376] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. It should be understood that the above is for illustration, and the examples above are only to help those skilled in the art understand the embodiments of the present application, rather than to limit the application embodiments to the specific numerical values ​​or specific scenarios illustrated. It is obvious that various equivalent modifications or changes can be made by those skilled in the art according to the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Obtaining an information bit sequence; Performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence, wherein a first matrix region of the LDPC base matrix includes a first square matrix, the first matrix region is composed of the 1st row to the wth row and the rth column to the r+w-1th column of the LDPC base matrix, the first square matrix includes at least two columns with column weights greater than or equal to 3 and / or at least one column with a column weight that is an even number greater than or equal to 4, each row of the first square matrix has a row weight greater than or equal to 2, and w and r are positive integers; Output the LDPC codeword sequence.

2. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Get LDPC codeword sequence; The LDPC codeword sequence is decoded according to an LDPC base matrix to obtain an information bit sequence, wherein a first matrix region of the LDPC base matrix includes a first square matrix, the first matrix region is composed of the 1st row to the wth row and the rth column to the r+w-1th column of the LDPC base matrix, the first square matrix includes at least two columns with column weights greater than or equal to 3 and / or at least one column with a column weight that is an even number greater than or equal to 4, the row weight of each row of the first square matrix is ​​greater than or equal to 2, and w and r are positive integers.

3. The method according to claim 1 or 2, characterized in that: The first square matrix is ​​an m×m matrix, where m is a positive integer; The first square matrix includes m-1 columns with even column weights and 1 column with odd column weights, the row weight of each row of the first square matrix is ​​2 or 3, and the number of rows with row weights of 3 in the first square matrix is ​​the number of the at least one column with an even column weight greater than or equal to 4 plus 1, wherein the m-1 columns with even column weights include the at least one column with an even column weight greater than or equal to 4.

4. The method according to claim 3, characterized in that The first square matrix includes 1 column with a column weight of 4, 1 column with a column weight of 3, and m-2 columns with a column weight of 2.

5. The method according to claim 3 or 4, characterized in that: m=4, the first square matrix is ​​the following matrix: Where "-1" represents a zero element, "x", "y", "z", "a", "b", or "c" represents a non-zero element and the offset values ​​are x, y, z, a, b, or c respectively, x≠y, a≠b, x, y, z, a, and c are positive integers, and b is a non-negative integer.

6. The method according to claim 3 or 4, characterized in that: m=5, the first square matrix is ​​the following matrix: Where "-1" represents a zero element, "x", "y", "a", "b", "c", "d", or "p" represents a non-zero element and the offset values ​​are x, y, a, b, c, d, or p, respectively, x ≠ y, b ≠ d, x, y, a, p, c, and d are positive integers, and b is a non-negative integer.

7. The method according to claim 3, characterized in that The first square matrix includes 2 columns with a column weight of 4, 1 column with a column weight of 3, and m-3 columns with a column weight of 2.

8. The method according to claim 3 or 7, characterized in that: m=5, the first square matrix can be the following matrix: Where "-1" represents a zero element, "x", "y", "a", "b", "c", "d", "e" or "p" represents a non-zero element and the offset values ​​are x, y, a, b, c, d, e or p respectively, x≠y, b≠d, a≠e, x, y, a, p, c, d and e are positive integers, and b is a non-negative integer.

9. The method according to claim 1 or 2, characterized in that: The column weight of each column of the first matrix is ​​2 or 3, and the number of columns with a column weight of 2 in the first matrix is ​​greater than 0.

10. The method according to claim 9, characterized in that The number of columns with a column weight of 2 in the first square matrix is ​​an even number.

11. The method according to claim 9 or 10, characterized in that: The first square matrix is ​​an m×m matrix, where m is a positive integer; The first square matrix includes 2 columns with a column weight of 2 and m-2 columns with a column weight of 3.

12. The method according to any one of claims 9 to 11, characterized in that The first square matrix is ​​an m×m matrix, where m is an even number greater than 0; The first square matrix includes m-2 columns with a column weight of 2 and 2 columns with a column weight of 3.

13. The method according to any one of claims 9 to 12, characterized in that m=4, the first square matrix is ​​any one of the following matrices: Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "2x" means non-zero elements and the offset value is 2x, "-2x" means non-zero elements and the offset value is Z c -2x, Z c is the boost value, x is a positive integer.

14. The method according to any one of claims 9 to 11, characterized in that The first square matrix is ​​an m×m matrix, where m is an odd number greater than 0; The first square matrix includes m-3 columns with a column weight of 2 and 3 columns with a column weight of 3.

15. The method according to claim 1, 2, 9, 10, 11 or 14, characterized in that m=5, the first square matrix is ​​any one of the following matrices: Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "z" means non-zero elements and the offset value is z, "-z" means non-zero elements and the offset value is Z c -z,Z c is the boost value, x and z are positive integers.

16. The method according to claim 1 or 2, characterized in that: The column weight of each column and the row weight of each row of the first square matrix are both G, the first square matrix includes a first row and a second row, the number of elements in the intersection of the set consisting of the column numbers of the columns where the non-zero elements of the first row are located and the set consisting of the column numbers of the columns where the non-zero elements of the second row are located is 2, the first row and the second row are any two rows of the first square matrix, and G is greater than or equal to 3.

17. The method according to claim 16, characterized in that G＝3。 18. The method according to claim 17, characterized in that The first square matrix includes a first column and a second column, the intersection of a set consisting of row numbers of rows where non-zero elements of the first column are located and a set consisting of row numbers of rows where non-zero elements of the first column are located includes at most one row number, and the first column and the second column are any two columns of the first square matrix; The row numbers of any two rows of the first square matrix belong to the set consisting of the row numbers of the rows where the non-zero elements of a column of the first square matrix are located.

19. The method according to claim 17 or 18, characterized in that The first square matrix is ​​an m×m matrix, where m is a positive integer; The non-zero elements of the first square matrix include first-category non-zero elements and second-category non-zero elements, wherein: The positions of the first type of non-zero elements include: the 1st column to the 3rd column of the 1st row, the 4th column to the 5th column of the 2nd row, ..., the 2tth column to the 2t+1th column of the tth row, and the 1st row to the 3rd row of the 1st column, the 4th row to the 5th row of the 2nd column, ..., the 2tth row to the 2t+1th row of the tth column of the first square matrix, where t is greater than or equal to 2; The second type of non-zero elements are located in a first sub-region of the first matrix, and the first sub-region is composed of the first matrix region Go to row m, row The structure consists of columns from the first column to the mth column.

20. The method according to claim 19, characterized in that The offset value of the first type of non-zero elements is 0.

21. The method according to claim 19 or 20, characterized in that The offset value of the second type of non-zero element is based on x1, x2, ..., x t The values ​​are determined, x1, x2, …, x t are both greater than or equal to 0, and t is a positive integer.

22. The method according to claim 21, characterized in that t is equal to 1, the offset value of the second type of non-zero elements is k1x1; or, t is equal to 2, and the offset value of the second type of non-zero elements is k1x1, -k1x1, k2x2, -k2x2 or k1x1+k2x2; or, t is greater than or equal to 3, the offset values ​​of the second type of non-zero elements are x1, x2, ..., x t A linear combination of at most two terms in ; Wherein, k1 and k2 are positive integers.

23. The method according to any one of claims 19 to 22, characterized in that When m is an even number, the non-zero elements of the first matrix also include a third type of non-zero elements, and the third type of non-zero elements are located in the first matrix. Row, No. List.

24. The method according to claim 23, characterized in that The offset value of the third type of non-zero element is not 0; or, The offset value of the third type of non-zero element is based on x1, x2, ..., x t Determine, x1, x2, …, x t are both greater than or equal to 0, and t is a positive integer.

25. The method according to any one of claims 16 to 24, characterized in that The first square matrix is ​​a 4×4 matrix, and the first square matrix is ​​any one of the following matrices: Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "-2x" means non-zero elements and offset value is Z c -2x, "-3x" means non-zero elements and the offset value is Z c -3x, "-4x" means non-zero elements and the offset value is Z c -4x, Z c is the boost value, x is a positive integer.

26. The method according to any one of claims 16 to 24, characterized in that The first square matrix is ​​a 5×5 matrix, and the first square matrix is ​​any one of the following matrices: Among them, "-1" represents a zero element, "0" represents a non-zero element with an offset value of 0, "x" represents a non-zero element with an offset value of x, and "-x" represents a non-zero element with an offset value of Z c -x, "-2x" means non-zero elements and offset value is Z c -2x, "y" means non-zero elements and offset value is y, Z c is the lifting value, x and y are positive integers.

27. The method according to any one of claims 1 to 26, characterized in that The first matrix region further includes at least one second square matrix, the first square matrix and the at least one second square matrix do not overlap, and a first sub-region formed by the first square matrix and the at least one second square matrix includes all diagonal elements of the first matrix region; All elements in the first matrix region at the upper right of the first sub-region are zero elements, and all elements in the first matrix region at the lower left of the first sub-region are zero elements; Alternatively, the elements in the first matrix region at the upper right of the first sub-region are all zero elements, and the region of the first matrix region at the lower left of the first sub-region includes non-zero elements; or, the region of the first matrix region at the upper right of the first sub-region includes non-zero elements, and the elements in the first matrix region at the lower left of the first sub-region are all zero elements.

28. The method according to claim 27, characterized in that The at least one second square matrix is ​​an upper triangular structure, a lower triangular structure, a diagonal structure or a double diagonal structure; The first square matrix is ​​located at the upper left corner of the first matrix region, the region of the first matrix region above the right of the first sub-region includes non-zero elements, and the elements of the first matrix region below the left of the first sub-region are all zero elements; Alternatively, the first square matrix is ​​located at the lower right corner of the first matrix region, the elements in the first matrix region above the right of the first sub-region are all zero elements, and the region of the first matrix region below the left of the first sub-region includes non-zero elements.

29. A communication device, characterized in that: The method comprises a module or a unit for executing the method as claimed in any one of claims 1 to 28.

30. A communication device, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method as described in any one of claims 1 to 28 through a logic circuit or executing code instructions.

31. The communication device according to claim 30, characterized in that: The communication device is a chip or a chip system.

32. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or an instruction, and when the computer program or the instruction is executed by the communication device, the method according to any one of claims 1 to 28 is implemented.

33. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 28.

34. A communication system, characterized in that: include: A sending end device for executing the method as claimed in any one of claims 1, 3 to 28; A receiving device for executing the method as claimed in any one of claims 2 to 28.

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