Promote and 2 C backward compatibility with I3C hubs

Abstract

This application relates to a method for promoting 2 C backward compatibility. The hub device enables the deployment of I 2 The hub has an I3C-compliant interface, by which the hub communicates with an I3C master device on an I3C bus; 2 C interface, the hub uses the I 2 C interface with I 2 I C bus 2 C-device communications; and logic and memory, which supports conversion between the two domains.

Description

Technical Field

[0001] The present application relates generally to an integrated circuit, and in particular to an I3C hub. Background Art

[0002] Integrated Circuit (I 2 C) standard describes a multi-master, multi-slave serial computer bus widely used to attach lower speed peripheral integrated circuits (ICs) and sensors to processors and microcontrollers in short-range intra-board communications. The proliferation of sensors in mobile wireless and related products has created a significant design challenge. Since there is no consistent way to interface with physical sensors in such products, device and platform designers are faced with a fragmentation of digital serial interfaces, including I / O interfaces, CAN interfaces, and CAN busses. 2 C, Serial Peripheral Interface (SPI) and Universal Asynchronous Receiver-Transmitter (UART) and others. Figure 1 These challenges are understandable.

[0003] Figure 1 The display includes connections to various I 2 In an example of a system of host system-on-chip (SOC) integrated circuits that have C and SPI devices. In addition to the main serial bus interface for each of the devices, the system also requires other interfaces for sideband signals (e.g., dedicated interrupts, chip select signals, enable signals, sleep signals, etc.) dedicated to each of the devices. This means that as the number of peripheral devices increases, the required number of general-purpose input / output (GPIO) pins and printed circuit board (PCB) layer counts for the host increase, driving up system cost and complexity. As a result, the number of sensors in current products is becoming increasingly difficult to support.

[0004] To address these issues, the Mobile Industry Processor Interface (MIPI) Alliance has developed an improved Inter-Integrated Circuit (I3C) standard that describes a fast two-wire digital serial interface for peripheral devices such as sensors. 2 C standard features while retaining the same 2 C device backward compatibility. Figure 2 As shown in Figure 1 For the same number of I3C peripheral devices in a system, I3C requires only two connections to the I3C host SOC. Therefore, the I3C standard has the potential to greatly increase the flexibility of designers to effectively support the expanding array of sensors in mobile systems.

[0005] Despite this possibility, there is 2Several issues arise in I3C systems with I3C devices. For example, I3C devices use in-band interrupts and therefore do not require an additional sideband communication channel with the host. By contrast, even when deployed on an I3C bus, I 2 C devices still require a dedicated sideband channel to interrupt the I3C master. 2 If each of the I3C devices has its own interrupt pin on the host, the significant advantages of the I3C standard cannot be realized. 2 C devices share the same interrupt line, the I3C master needs to poll the I3C devices sequentially. 2 C device to determine which device transmitted the interrupt, which undesirably consumes I3C host processing time.

[0006] In addition, I 2 C devices typically exhibit much higher capacitance at their connection to the I3C bus than I3C devices. This not only limits the frequency of the bus to the slowest I 2 C devices, which can also significantly reduce the number of devices that can be deployed on the bus.

[0007] Finally, the I3C standard explicitly limits the I2C bus connections allowed in various situations. 2 For example, the I3C bus does not allow I 2 C auxiliary master device, only allows I 2 In another example, inclusion in some I 2 In another example, I3C is not allowed on the I3C bus. 2 C standard "clock stretching" feature. Therefore, in addition to the implementation of I 2 Apart from the performance issues caused by the use of I3C devices, the I3C standard is different from many traditional I3C devices that may continue to exist in the market for several years. 2 C-devices are not 100% backwards compatible. Summary of the invention

[0008] According to a particular class of implementations, the interconnect hub includes a 2 C standard and I 2 Multiple I C bus 2 C slave device communicates in accordance with I 2 The interconnect hub also includes a controller configured to receive an interface from the I 2 C receives I 2 The interconnect hub also includes one or more interrupt interfaces configured for storing the I 2 C slave device identifier, the I 2C interrupt information from each of the devices and from the I 2 C is received from the device or directed to the I 2 The interconnect hub also includes an I3C-compliant interface configured for communicating with an I3C master device on an I3C bus according to the I3C standard. The I3C-compliant interface is also configured to transmit data from the I3C slave device to the I3C bus using the identifier, the data, and the interrupt information. 2 C from the device's I 2 C interrupt is converted to an I3C interrupt for transmission on the I3C bus and is consistent with the I 2 C interface to cooperate with the I 2 I C bus 2 C communications to and from I3C communications on the I3C bus.

[0009] According to a specific embodiment of this class, the 2 The interface of C is I 2 C main device core.

[0010] According to another specific embodiment of this class, the 2 The interface of C is configured to communicate with a first I 2 C slave device and communicates with a second I 2 C slave device communication.

[0011] According to another specific embodiment of this class, the 2 The interface of C is configured to communicate with a first I configured to implement a clock stretching feature 2 C slave device communication.

[0012] According to another specific implementation of this class, the I3C compliant interface is an I3C slave core.

[0013] According to another specific implementation of this class, the I3C-compliant interface is configured for communicating with the I3C master device via the I3C-bus at a maximum operating frequency of the I3C master device.

[0014] According to another specific embodiment of this class, the 2 The interface of C is configured to 2 The first voltage level of the I3C slave device is converted to a second voltage level associated with the I3C bus.

[0015] According to another specific implementation of this class, the I3C compliant interface and the I 2The interface of the I3C is configured to provide a hardware reset signal to the I3C master in response to a reset request received from the I3C master. 2 The I C bus 2 C is one of the slave devices.

[0016] According to another specific implementation of this class, the I3C compliant interface or the I 2 C interface is configured to respond to the absence of 2 The I 2 An acknowledgement or response from one of the C devices 2 The signal line of C remains low and an error signal is generated.

[0017] According to another specific implementation of this class, the memory is further configured to store a 2 C is the value of the operating frequency of each of the slave devices.

[0018] According to another specific implementation of this class, the one or more interrupt interfaces include a 2 C receives I 2 Single interrupt interface for C interrupts.

[0019] According to another specific implementation of this class, the one or more interrupt interfaces include a plurality of interrupt interfaces, each interrupt interface being configured to receive from the I 2 C receives the I from a corresponding one of the devices 2 C interrupts one of the.

[0020] A further understanding of the nature and advantages of the various embodiments may be realized by reference to the remaining portions of the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 isI 2 Simplified block diagram of an example of a C system.

[0022] Figure 2 is a simplified block diagram of an example of an I3C system.

[0023] Figure 3 is a simplified block diagram of an example of a system with an I3C hub implemented by the present disclosure.

[0024] Figure 4 is a simplified block diagram of an example of an I3C hub implemented by the present disclosure. DETAILED DESCRIPTION

[0025] The present disclosure describes a method for enabling deployment of I 2C device hub device, the system also includes an I3C device. The hub isolates the I 2 The I3C device is connected to the I3C bus on which the I3C device is deployed and enables communication over the I3C bus. 2 The hub has an I3C-compliant interface, by which the hub communicates with an I3C master device on an I3C bus; an I3C-compliant interface. 2 C interface, the hub uses the I 2 C interface with I 2 I C bus 2 C device communication; and logic and memory, which supports the conversion between the two domains. In this way, the I3C master device can communicate with the I 2 In the case where a hub is achieved through the present invention, the advantages of the I3C standard can be fully realized in the I3C domain, while the I3C 2 C domain supports I 2 100% backward compatibility with C devices.

[0026] Reference will now be made in detail to specific embodiments. Examples of these embodiments are illustrated in the accompanying drawings. It should be noted that these examples are described for illustrative purposes and are not intended to limit the scope of the present disclosure. Specifically, alternatives, modifications and equivalents of the described embodiments are included within the scope of the present disclosure as defined by the appended claims. In addition, specific details may be provided to facilitate a thorough understanding of the described embodiments. Some embodiments within the scope of the present disclosure may be practiced without some or all of these details. In addition, well-known features may not be described in detail for clarity.

[0027] Now refer to Figure 3 and 4 Specific implementations are described. Figure 3 is an I3C and I 2 3C hub device 302. Figure 4 3 is a simplified block diagram of an I3C hub device 302 according to a particular class of implementations. The depicted implementation includes an I3C-compliant interface 402 (which may be implemented as an I3C slave core) that interfaces with an I3C bus in an I3C domain (not shown for clarity reasons) via signal lines I3C SCL and I3C SDA. The hub device 302 also includes a I3C slave device core that interfaces with an I3C bus in an I3C domain (not shown for clarity reasons). 2 C SCL and I 2 C SDA and I 2 C domain (also not shown) 2 C bus interface compliant with I 2C interface 404 (which may be implemented as I 2 C main device core).

[0028] The I3C hub 302 interfaces with an I3C master device 304 via an I3C bus 306 in accordance with the I3C standard. Other I3C compliant devices (e.g., an I3C slave device 308 and an I3C auxiliary master device 310) may be present on the I3C bus 306. The I3C hub 302 also interfaces with an I3C master device 304 in accordance with the I3C standard via an I3C bus 306. 2 C standard via I 2 C bus 320 and I 2 I3C slave devices 312 to 318 are interfaced. The I3C hub 302 also includes I3C interfaces that can represent, for example, an interrupt line, an enable line, etc. 2 I3C hub 302 provides additional interfaces (e.g., signal lines 322 to 328) to I3C slave devices. 2 C slave device behaves in some ways like an I 2 C master device. As shown, I 2 C slave devices are not directly connected to the I3C bus 306. By isolating the I 2 C device with I3C bus, may support I 2 C standard, such as, for example, clock stretching and others.

[0029] When the I3C master device 304 initiates communication with a specific I 2 When a slave device communicates with an I3C slave, it sends an I3C compliant message to the hub 302. The hub 302 converts the message to I 2 C domain, and when completed with the specified I 2 When the hub 302 manages the interaction with the I3C slave device, it reports back to the I3C master device 304. 2 C slave device, so the I3C master device 304 does not need to wait for the I 2 C slave device and may alternatively handle other communications with any of the I3C devices on the I3C bus 306 according to the I3C standard. This includes an I3C hub 302, which may, for example, represent an I3C bus between 2 The other of the I3C slave devices communicates with the I3C master device 304. Once the communication with the specific I3C slave device is completed, 2 C slave device transaction, the hub 302 sends an interrupt to the I3C master device 304.

[0030] The I3C master 304 is programmed to know the I3C master 304 attached to the hub 302. 2 That is, the I3C master device 304 has an I 2 C slave device address and combines it with I 2C slave communication sends these addresses to the I3C hub 302. And because the I 2 C slave is no longer on the I3C bus, so its capacitance does not affect the I3C domain.

[0031] That is, the I3C master does not have to wait for the I 2 C slave device response, which is not necessarily due to the presence of I 2 C slave device does not slow down the operation speed of the I3C bus, but can use the maximum speed allowed in the I3C domain. 2 C interrupt, so the I3C master can communicate with all devices in the system using only two lines as expected by the I3C standard.

[0032] Reference again Figure 4 The I3C hub 302 includes an I3C slave device core 402 and a device for storing I 2 C slave device address (406), read / write data (408) and I 2 C interrupt status (410) registers and / or buffers. The slave device address register 406 and read / write buffer 408 are connected to the I 2 C interface 404, and interrupt status register 410 connected to the I3C slave device core 402. As shown in the figure and according to some embodiments, the I3C hub 302 may include a dedicated I3C slave device core 402. 2 C from each of the devices. Alternatively, it is contemplated that only one or less inputs are needed to 2 C receives an interrupt from the device (i.e., I 2 C more than one of the slave devices can share the interrupt line) implementation.

[0033] According to some embodiments, 2 The interface 404 of I 2 C standard implementation of the physical layer interface, that is, only I 2 A reduced subset of the features of the C master device conforms to I 2 C interface. For some implementations, only the most basic I 2 C read and write functions. However, it should be noted that it is contemplated that 2 C host core to implement interface 404 to communicate with I 2 Implementation scheme for C device communication.

[0034] The I3C hub 302 is based on I 2 C standard and I 2 C slave device and has a dedicated 2The I3C hub 302 stores one or more I / Os and registers of interrupts from the I3C slave devices so that it can track which device sent a given interrupt. 2 C hardware interrupt (i.e., from I 2 The I3C slave core 402 reads the interrupt status register 410 and generates an I3C-compliant in-band interrupt and transmits the I3C-compliant in-band interrupt to the I3C master on the I3C bus.

[0035] Hub 302 also communicates on I 2 C domain and I3C domain. For example, when the I3C master device is 2 C reads from one of the devices or 2 When one of the I3C slaves writes, it sends a read or write command on the I3C bus to the I3C slave core 402 hub, which indicates which I3C slave is to be written. 2 The I3C slave core 402 passes commands to the I3C slave device to read or write (e.g., by address) and how many bytes of data will be read and written. 2 C interface 404,I 2 C interface 404 then executes the 2 C bus with specified I 2 The result of the transaction is passed onward to the I3C slave core 402, which then communicates the result (eg, a number of bytes of read data or a successful write acknowledgement) to the I3C master.

[0036] In one example, when I 2 I C bus 2 When an I3C slave sends an interrupt, the I3C hub issues an in-band interrupt (IBI) to the I3C master. The I3C master reads the interrupt status register of the I3C hub to identify the I3C slave to which the interrupt corresponds. 2 C from the device. For I 2 C slave device write operation, the I3C master device recognizes the number of bytes to be written and the I 2 The I3C hub sends an IBI to the I3C master when the write operation is complete.

[0037] For a read operation, the I3C master will identify the number of bytes to be read and the I 2The I3C hub sends an IBI to the I3C master when the read operation is complete.

[0038] Depending on the implementation, one or more of the following advantages may be achieved when an I3C hub is implemented through the present disclosure. For example, due to the I 2 The large load capacitance of the C slave devices is isolated from the I3C bus so that the I3C bus can achieve its highest operating speed and / or maximize the number of I3C devices connected to the I3C bus.

[0039] In another example, the I3C master does not need to read individual I 2 C interrupt, so relative to which I 2 I3C slaves are connected directly to the I3C bus to simplify the configuration of the I3C master. This also reduces the need for I 2 C The delay associated with the processing of interrupts.

[0040] In another example, an I3C hub implemented by the present disclosure may support execution of a 2 C standard specifies clock stretching for I 2 C device.

[0041] In another example, an I3C hub implemented by the present disclosure can reduce or eliminate the need for dedicated hardware pins on an I3C master or host (e.g., for I 2 C hardware interrupt pin).

[0042] In another example, the I3C hub achieved by the present disclosure eliminates or reduces the use of I3C bus bandwidth to achieve slow I 2 C communication.

[0043] In another example, an I3C hub implemented by the present disclosure is used to isolate an I3C bus with an inaccurate 50 nanosecond spike filter. 2 C devices and the I3C bus, thereby allowing such devices to be included in the overall system without adversely affecting the operating speed of the I3C bus.

[0044] According to some embodiments, the I3C hub implemented by the present disclosure may also include a frequency register to support I 2 C from different operating frequencies of the device. According to one such embodiment, I 2 The operating frequency of the I3C slave device is set by the value of the internal register of the I3C hub. In this way, each slave device can operate at its optimal frequency.

[0045] According to some embodiments, an I3C hub implemented by the present disclosure may be included in an I 2 C interface to support I2 For example, there are ICs on the market that operate with different supply voltages ranging from 1.8V to 5V. 2 C devices, while the I3C host operates using a supply voltage ranging from 1.2 to 3.3V. According to such implementations, different I 2 C devices can be connected to different I3C devices with different voltages via an I3C hub achieved through the present disclosure. 2 C bus.

[0046] According to some embodiments, an I3C hub implemented by the present disclosure may include logic for generating an error signal for reporting to an I3C master device in the following situations, for example: 2 The SDA / SCL signal line on the C bus is held low, or the I 2 C Acknowledgement from the device, i.e., NACK.

[0047] According to some embodiments, an I3C hub implemented by the present disclosure may be an I3C master that responds to a reset request from an I3C master. 2 C provides active high and low outputs from the device's hardware reset.

[0048] Those skilled in the art will appreciate that changes in form and detail of the embodiments described herein may be made without departing from the scope of the present disclosure. In addition, although various advantages, aspects, and objects have been described with reference to various embodiments, the scope of the present disclosure should not be limited by reference to such advantages, aspects, and objects. Rather, the scope of the present disclosure should be determined with reference to the appended claims.

Claims

1. An interconnect hub, comprising: Comply with the integrated circuit I 2 C interface, which is configured for use according to I 2 C standard and I 2 Multiple I C bus 2 C slave device communication; One or more interrupt interfaces configured to receive interrupts from the I 2 C receives I 2 C interrupt signal; A memory configured to store the I 2 C slave device identifier, including the I 2 C interrupt information from the interrupt status of each of the devices and from the I 2 C is received from the device or directed to the I 2 C data from the device; and An improved inter-IC I3C compliant interface configured for communicating with an I3C master on an I3C bus according to an I3C standard, the improved inter-IC I3C compliant interface further configured to transmit data from the I3C master to the I3C master using the identifier, the data, and the interrupt information. 2 C from the device's I 2 The I3C interrupt signal is converted into an I3C interrupt signal for transmission on the I3C bus and is communicated with the integrated circuit I3C. 2 C interface to cooperate with the I 2 I C bus 2 C communications and I3C communications on the I3C bus, wherein the interconnect hub is configured to use a corresponding I3C bus 2 C The interrupt status of the slave device is handled with the I 2 C slave device, so that the I3C master device can initiate a transaction with the first I 2 C slave device and upon receiving a transaction from the first I 2 C slave device responds before the I3C slave device or the second I 2 C slave device communication.

2. The interconnect hub of claim 1 , wherein the integrated circuit 2 The interface of C is I 2 C main device core.

3. The interconnect hub of claim 1 , wherein the integrated circuit 2 The interface of C is configured to communicate with a first I 2 C slave device and communicates with a second I 2 C slave device communication.

4. The interconnect hub of claim 1 , wherein the integrated circuit 2 The interface of C is configured to communicate with a first I configured to implement a clock stretching feature 2 C slave device communication.

5. The interconnect hub of claim 1, wherein the improved inter-integrated circuit (I3C) compliant interface is an I3C slave core.

6. The interconnect hub of claim 1, wherein the improved inter-integrated circuit (I3C) compliant interface is configured for communicating with the I3C master via the I3C bus at a maximum operating frequency of the I3C master.

7. The interconnect hub of claim 1, wherein the integrated circuit 2 The interface of C is configured to 2 The first voltage level of the I3C slave device is converted to a second voltage level associated with the I3C bus.

8. The interconnect hub of claim 1, wherein the interface compliant with improved inter-IC I3C and the interface compliant with inter-IC I3C 2 The interface of the I3C is configured to provide a hardware reset signal to the I3C master in response to a reset request received from the I3C master. 2 The I 2 C is one of the slave devices.

9. The interconnect hub of claim 1, wherein the interface compliant with the improved inter-IC I3C or the interface compliant with the inter-IC I3C 2 C interface is configured to respond to the absence of 2 The I 2 C from one of the devices to confirm or respond to I 2 The signal line of C remains low and an error signal is generated.

10. The interconnect hub of claim 1, wherein the memory is further configured to store a 2 C is the value of the operating frequency of each of the slave devices.

11. The interconnect hub of claim 1 , wherein the one or more interrupt interfaces include a 2 C receives I 2 Single interrupt interface for C interrupt signal.

12. The interconnect hub of claim 1, wherein the one or more interrupt interfaces include a plurality of interrupt interfaces, each interrupt interface being configured to receive interrupts from the I 2 C receives the I from a corresponding one of the devices 2 C One of the interrupt signals.

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