Asynchronous ram read-write method and device, terminal equipment and readable storage medium

Abstract

Embodiments of the present application disclose an asynchronous RAM reading and writing method and device, a terminal device and a readable storage medium. The asynchronous RAM can ensure that, under different reading and writing frequencies, when 0≤the current moment's write address-the current moment's read address<the first threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, the reading operation of the asynchronous RAM is suspended (that is, the position of the read pointer Rdr is ensured to be unchanged), the writing operation of the asynchronous RAM is maintained (that is, the write pointer Wdr is normally moved), data is ensured to be normally written into the address empty of data, the distance between the write pointer Wdr and the read pointer Rdr is ensured to be enlarged, reading and writing conflicts are avoided, and then the asynchronous RAM can stably read and write data, thereby ensuring the stability of the storage process.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory, in particular to an asynchronous RAM read-write method, device, terminal equipment and readable storage medium. BACKGROUND

[0002] According to the difference of sampling clock, random access memory (RAM) can be divided into synchronous RAM and asynchronous RAM, the synchronous RAM refers to the same clock for reading and writing, and the asynchronous RAM refers to different clocks for reading and writing. For the asynchronous RAM, since the write clock and the read clock are different in frequency, it may cause the conflict of RAM data reading and writing, and further affect the effective writing and reading of RAM data. SUMMARY

[0003] In view of the above problems, the present application provides an asynchronous RAM read-write method, device, terminal equipment and readable storage medium.

[0004] The present application provides an asynchronous RAM read-write method, which comprises:

[0005] obtaining a read address at a current time in a read time domain and a write address at the current time in a write time domain;

[0006] synchronizing the read address at the current time and the write address at the current time to the same time domain;

[0007] In the same time domain, if 0≤the write address at the current time-the read address at the current time<the first threshold value, and the write full flag of the asynchronous RAM indicates that it is not full, the reading operation of the asynchronous RAM is suspended, and the writing operation of the asynchronous RAM is kept normal.

[0008] The asynchronous RAM read-write method provided by the present application further comprises:

[0009] In the same time domain, if 0≤the write address at the current time-the read address at the current time, and the write full flag of the asynchronous RAM indicates that it is full, the writing operation of the asynchronous RAM is suspended, and the reading operation of the asynchronous RAM is kept normal.

[0010] The asynchronous RAM read-write method provided by the present application further comprises:

[0011] In the same time domain, if the second threshold value<the write address at the current time-the read address at the current time≤0, and the write full flag of the asynchronous RAM indicates that it is full, the writing operation of the asynchronous RAM is suspended, and the reading operation of the asynchronous RAM is kept normal.

[0012] The asynchronous RAM read-write method provided by the present application further comprises:

[0013] In the same time domain, if the write address of the current moment minus the read address of the current moment is less than or equal to 0, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, the read operation of the asynchronous RAM is suspended, and the write operation of the asynchronous RAM is normal.

[0014] The asynchronous RAM read-write method provided in the application further comprises:

[0015] In the same time domain, if the write address of the current moment minus the read address of the current moment is greater than or equal to the first threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, the write operation and the read operation of the asynchronous RAM are normal.

[0016] In the same time domain, if the write address of the current moment minus the read address of the current moment is less than or equal to the second threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is full, the write operation and the read operation of the asynchronous RAM are normal.

[0017] The asynchronous RAM read-write method provided in the application, the read address of the current moment in the read time domain and the write address of the current moment in the write time domain are binary, and the read address of the current moment and the write address of the current moment are synchronized to the same time domain, comprising:

[0018] Converting the binary write address of the current moment in the write time domain into a Gray code write address;

[0019] Synchronizing the Gray code write address to the read time domain;

[0020] Converting the Gray code write address synchronized to the read time domain into a binary write address, so that the write address of the current moment in the write time domain is synchronized to the read time domain.

[0021] The asynchronous RAM read-write method provided in the application, the read address of the current moment in the read time domain and the write address of the current moment in the write time domain are binary, and the read address of the current moment and the write address of the current moment are synchronized to the same time domain, comprising:

[0022] Converting the binary read address of the current moment in the read time domain into a Gray code read address;

[0023] Synchronizing the Gray code read address to the write time domain;

[0024] Converting the Gray code read address synchronized to the write time domain into a binary read address, so that the read address of the current moment in the read time domain is synchronized to the write time domain.

[0025] The application provides an asynchronous RAM read-write device, which comprises:

[0026] an acquisition module configured to acquire a read address at a current time in a read time domain and a write address at the current time in a write time domain;

[0027] a synchronization module configured to synchronize the read address at the current time and the write address at the current time to the same time domain;

[0028] a read-write module configured to, in the same time domain, if 0≤the write address at the current time-the read address at the current time≤a first threshold value and a write-full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, suspend a read operation of the asynchronous RAM and keep a write operation of the asynchronous RAM normal.

[0029] The application provides a terminal device, comprising a memory and a processor, wherein the memory comprises an asynchronous RAM, the asynchronous RAM stores a computer program, and the computer program executes the asynchronous RAM read-write method when running on the processor.

[0030] The application provides a readable storage medium, which stores a computer program, and the computer program executes the asynchronous RAM read-write method when running on a processor.

[0031] The application provides an asynchronous RAM read-write method, which does not need to increase a FIFO cache register, only needs to control read-write operations of the asynchronous RAM according to a difference between a write address at a current time and a read address at the current time, and can ensure that, under different read-write frequencies, in a case where 0≤the write address at the current time-the read address at the current time<the first threshold value and the write-full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, the read operation of the asynchronous RAM is suspended (i.e., the position of a read pointer Rdr is kept unchanged), the write operation of the asynchronous RAM is kept normal (i.e., a write pointer Wdr moves normally), data is normally written into an address empty of data, the distance between the write pointer Wdr and the read pointer Rdr is enlarged, read-write conflicts are avoided, and then the asynchronous RAM can stably read and write data, thereby ensuring the stability of a storage process. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope of protection of the present application. In each drawing, similar components are denoted by similar reference numerals.

[0033] Figure 1 a flowchart of a first asynchronous RAM read-write method according to an embodiment of the present application is shown;

[0034] Figure 2 a schematic diagram of an asynchronous RAM storage matrix according to an embodiment of the present application is shown;

[0035] Figure 3 A timing synchronization diagram is shown according to an embodiment of the present application;

[0036] Figure 4 A first read pointer and write pointer position diagram is shown according to an embodiment of the present application;

[0037] Figure 5 A flow diagram of a second asynchronous RAM read-write method is shown according to an embodiment of the present application;

[0038] Figure 6 A second read pointer and write pointer position diagram is shown according to an embodiment of the present application;

[0039] Figure 7 A flow diagram of a third asynchronous RAM read-write method is shown according to an embodiment of the present application;

[0040] Figure 8 A third read pointer and write pointer position diagram is shown according to an embodiment of the present application;

[0041] Figure 9 A flow diagram of a fourth asynchronous RAM read-write method is shown according to an embodiment of the present application;

[0042] Figure 10 A fourth read pointer and write pointer position diagram is shown according to an embodiment of the present application;

[0043] Figure 11 A flow diagram of a fifth asynchronous RAM read-write method is shown according to an embodiment of the present application;

[0044] Figure 12 A fifth read pointer and write pointer position diagram is shown according to an embodiment of the present application;

[0045] Figure 13 A flow diagram of a sixth asynchronous RAM read-write method is shown according to an embodiment of the present application;

[0046] Figure 14 A sixth read pointer and write pointer position diagram is shown according to an embodiment of the present application;

[0047] Figure 15 A flow diagram of an asynchronous RAM read-write device is shown according to an embodiment of the present application.

[0048] Main element symbol explanation:

[0049] 10 - asynchronous RAM read-write device; 11 - acquisition module; 12 - synchronization module; 13 - read-write module. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application.

[0051] The components of the embodiments of the present application generally described and illustrated in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0052] Hereinafter, the terms "include", "have", and their conjugates, used in the various embodiments of the present application, are merely intended to denote a certain characteristic, number, step, operation, element, component, or a combination thereof, and not to exclude the presence or possibility of one or more other characteristics, numbers, steps, operations, elements, components, or combinations thereof.

[0053] In addition, the terms "first", "second", "third", and the like are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as terms defined in a generally used dictionary) will be interpreted as having the same meaning as the context in the relevant technical field and will not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the present application.

[0055] Adding an intermediate FIFO buffer register on the asynchronous RAM, writing the address and data content of the data to be updated into the FIFO, reading out the data address and data content from the FIFO, although there is a certain improvement effect compared with the traditional two-level synchronizer processing method, but only the asynchronous RAM read enable and write enable are synchronized, when there is a clock offset or frequency difference in reading and writing, the asynchronous RAM cannot be read and written stably, and it may still cause asynchronous RAM read and write errors or unable to read data, thereby affecting the stability of the entire chip.

[0056] To address the aforementioned issues, this application proposes an asynchronous RAM read / write method applicable to asynchronous RAM comprising a RAM write module, a RAM read module, a Gray code conversion module, a synchronization module, and a comparison module. This method eliminates the need for an additional FIFO cache register on the asynchronous RAM; instead, the comparison module compares the current write address with the current read address and controls the read / write operations based on the difference between the two addresses. This ensures stable data read / write operations at different read / write frequencies, thereby guaranteeing the stability of the storage process.

[0057] Example 1

[0058] One embodiment of this application, such as Figure 1 As shown, the first asynchronous RAM read / write method includes the following steps:

[0059] S100: Get the current read address in the read time domain and the current write address in the write time domain.

[0060] RAM read / write addresses can be determined based on Figure 2 The asynchronous RAM storage matrix shown can be represented by X0 to Xn, which can be used to represent row selection lines and Y0 to Yn, which can be used to represent column selection lines. X0 to Xn and Y0 to Yn can be used to represent read addresses and write addresses.

[0061] For example, if the address is 00010001, it represents the address "1" at the intersection of row X0 and row Y0; if the address is 00010011, it represents the address "3" at the intersection of row X0 and row Y2.

[0062] S200: Synchronize the current read address and the current write address to the same time domain.

[0063] like Figure 3 As shown, clk1 and clk2 represent two read / write clock signals for the asynchronous RAM. clk1 can represent the read clock signal, and clk2 can represent the write clock signal. Figure 3 As can be seen from the data, clk2 synchronizes with clk1 after 3 clock cycles. Therefore, before comparing the current read address and the current write address, it is necessary to synchronize the current read address and the current write address to the same time domain.

[0064] Synchronizing the current read address and the current write address to the same time domain includes synchronizing the current read address to the write time domain of the asynchronous RAM and synchronizing the current write address to the read time domain of the asynchronous RAM.

[0065] It can be understood that the read address of the current time in the read time domain and the write address of the current time in the write time domain are binary, and the read address of the current time and the write address of the current time can be synchronized to the same time domain by the following method:

[0066] The binary write address of the current time in the write time domain is converted into a Gray code write address; the Gray code write address is synchronized to the read time domain; and the Gray code write address synchronized to the read time domain is converted into a binary write address, so that the write address of the current time in the write time domain is synchronized to the read time domain.

[0067] Alternatively, the read address of the current time and the write address of the current time can also be synchronized to the same time domain by the following method:

[0068] The binary read address of the current time in the read time domain is converted into a Gray code read address; the Gray code read address is synchronized to the write time domain; and the Gray code read address synchronized to the write time domain is converted into a binary read address, so that the read address of the current time in the read time domain is synchronized to the write time domain.

[0069] It can be understood that although the Gray code is represented by 0 and 1, only one bit changes in adjacent numbers represented by the Gray code. This feature makes it possible to effectively control the movement of the read or write pointer when the read address or the write address is represented by the Gray code count, and it is possible to suppress the competition hazard and further avoid the metastable state.

[0070] For example, 3 and 4 in decimal are taken as an example, 3 corresponds to binary 0011, and 4 corresponds to binary 0100. It can be seen that three bits (the 0 of the second bit changes to 1, the 1 of the third bit changes to 0, and the 1 of the fourth bit changes to 0) in the binary of adjacent numbers change. The Gray code corresponding to 3 is 0010, and the Gray code corresponding to 4 is 0110. Obviously, only one bit (the 0 of the second bit changes to 1) in the Gray code of adjacent numbers changes.

[0071] S310: In the same time domain, if 0≤the write address of the current time-the read address of the current time<the first threshold value, and the write full flag of the asynchronous RAM indicates that it is not full, the read operation of the asynchronous RAM is suspended, and the write operation of the asynchronous RAM is kept normal.

[0072] If 0≤the write address of the current time-the read address of the current time<the first threshold value, and the write full flag of the asynchronous RAM indicates that it is not full, the read operation of the asynchronous RAM is suspended, and the write operation of the asynchronous RAM is kept normal. Figure 4As shown, the read pointer Rdr has read out the data data1, data2 and data3 written at the addresses 1-3, and the addresses 1-3 are emptied. The write pointer Wdr has not written to the maximum address N of the asynchronous RAM, i.e. the write pointer Wdr has not written a round and has not been re-written from the minimum address "1". And, the write address corresponding to the current time of the write pointer Wdr minus the read address corresponding to the current time of the read pointer Rdr is greater than or equal to 0, and less than the first threshold (the first threshold can be set to be any natural number greater than 1, and the optional first threshold is 2), at this time, the distance between the write pointer Wdr and the read pointer Rdr is too small, which can cause read-write conflict, and thus the read operation of the asynchronous RAM needs to be paused (i.e. the position of the read pointer Rdr is kept unchanged), the write operation of the asynchronous RAM is kept normal (i.e. the write pointer Wdr moves normally), the data is normally written into the address emptied of data, and the distance between the write pointer Wdr and the read pointer Rdr is enlarged to avoid read-write conflict.

[0073] It can be understood that if the read address corresponding to the current time of the read pointer Rdr minus the write address corresponding to the current time of the write pointer Wdr, the read address corresponding to the current time of the read pointer Rdr minus the write address corresponding to the current time of the write pointer Wdr should be less than or equal to 0, and greater than the first threshold (the first threshold can be set to be any natural number less than -1, and the optional first threshold is -2).

[0074] A variable parameter can be set as a full-write mark of the asynchronous RAM in advance, when the write pointer Wdr points to the address N, the full-write mark of the asynchronous RAM indicates that it is full, the variable parameter can be set to 1, for example, the variable parameter is represented by F, F can be set to 1 when the write pointer Wdr points to the address N; when the read pointer Rdr points to the address N, the full-write mark of the asynchronous RAM indicates that it is not full, the variable parameter can be set to 0, F is set to 0. Further, whether the asynchronous RAM is full or not can be determined by judging whether F is equal to 1 or 0.

[0075] Embodiment 2

[0076] An embodiment of the present application is as follows: Figure 5 As shown, a second asynchronous RAM read-write method is proposed, which further includes the following steps after step S200:

[0077] S320: on the same time domain, if 0≤the write address of the current time-the read address of the current time, and the full-write mark of the asynchronous RAM indicates that it is full, pause the write operation of the asynchronous RAM, and keep the read operation of the asynchronous RAM normal.

[0078] If 0≤the write address of the current time-the read address of the current time, and the full-write mark of the asynchronous RAM indicates that it is full, as shown in Figure 6As shown, the write pointer Wdr writes to the maximum address N of the asynchronous RAM, and after completing one round of writing, it starts writing again from the minimum address "1", exceeding the read pointer Rdr. This causes the unread data data4 and data5 to be overwritten by data dataN+4 and dataN+5. At this point, the write operation is too fast, so it's necessary to pause the asynchronous RAM write operation while maintaining normal read operations to ensure data is read correctly. This allows the read pointer to exceed the write pointer, increasing the distance between the write pointer Wdr and the read pointer Rdr, thus ensuring the effective reading of already written data and preventing data from being overwritten due to read-write conflicts.

[0079] Example 3

[0080] One embodiment of this application, such as Figure 7 As shown, a third asynchronous RAM read / write method is proposed, which includes the following steps after step S200:

[0081] S330: In the same time domain, if the second threshold < the write address at the current time - the read address at the current time ≤ 0, and the write-full flag of the asynchronous RAM indicates that it is full, then the write operation of the asynchronous RAM is paused, and the read operation of the asynchronous RAM is kept normal.

[0082] If the second threshold < the current write address - the current read address ≤ 0, and the asynchronous RAM is full (indicating it is full), then... Figure 8 As shown, the write pointer Wdr writes to the maximum address N of the asynchronous RAM. That is, after one round of writing by the write pointer Wdr, it rewrites from the minimum address "1". Furthermore, the difference between the current write address corresponding to the write pointer Wdr and the current read address corresponding to the read pointer Rdr is less than or equal to 0 and greater than the second threshold (the second threshold can be set to any natural number less than -1, with -2 being an optional value). In this case, the distance between the write pointer Wdr and the read pointer Rdr is too small, which may lead to read-write conflicts. Therefore, it is necessary to pause the write operation of the asynchronous RAM (i.e., keep the write pointer Wdr unchanged) while maintaining the normal read operation of the asynchronous RAM (i.e., keep the read pointer Rdr moving normally) to ensure that the data already written is read correctly, thereby increasing the distance between the write pointer Wdr and the read pointer Rdr and avoiding read-write conflicts.

[0083] It is understandable that if the current read address corresponding to the read pointer Rdr is subtracted from the current write address corresponding to the write pointer Wdr, then it should be determined that the difference between the current read address corresponding to the read pointer Rdr and the current write address corresponding to the write pointer Wdr is greater than or equal to 0 and less than the second threshold (the second threshold can be set to any natural number greater than 1, and the optional second threshold is 2).

[0084] Example 4

[0085] One embodiment of the present application, as shown in Figure 9 The fourth asynchronous RAM read-write method is further comprised of the following steps after step S200:

[0086] S340: In the same time domain, if the write address of the current time - the read address of the current time ≤ 0, and the write full flag of the asynchronous RAM indicates not full, suspend the read operation of the asynchronous RAM, and keep the write operation of the asynchronous RAM normal.

[0087] If the write address of the current time - the read address of the current time ≤ 0, and the write full flag of the asynchronous RAM indicates not full, as shown in Figure 10 the write pointer Wdr has not written to the maximum address N of the asynchronous RAM, i.e. the write pointer Wdr has not written a round, and has not been re-written from the minimum address "1". And, the write address corresponding to the current time of the write pointer Wdr minus the read address corresponding to the current time of the read pointer Rdr is less than or equal to 0, at this time, the read pointer Rdr exceeds the write pointer Wdr, but after the read pointer Rdr exceeds the write pointer Wdr, since the write pointer Wdr has not written data to the subsequent address, the data read by the read pointer Rdr is not controlled, so it is necessary to suspend the read operation of the asynchronous RAM (i.e. to keep the position of the read pointer Rdr unchanged), keep the write operation of the asynchronous RAM normal (i.e. the write pointer Wdr moves normally), and ensure that the data is normally written and then read out, to avoid reading out empty data.

[0088] Embodiment 5

[0089] One embodiment of the present application, as shown in Figure 11 The fifth asynchronous RAM read-write method is further comprised of the following steps after step S200:

[0090] S350: In the same time domain, if the write address of the current time - the read address of the current time ≥ the first threshold, and the write full flag of the asynchronous RAM indicates not full, keep the write operation and the read operation of the asynchronous RAM normal.

[0091] If the write address of the current time - the read address of the current time ≥ the first threshold, and the write full flag of the asynchronous RAM indicates not full, as shown in Figure 12As shown, the write pointer Wdr has not written to the maximum address N of the asynchronous RAM, meaning that the write pointer Wdr has not completed a full write cycle and has not rewritten from the minimum address "1". Furthermore, the difference between the current write address corresponding to the write pointer Wdr and the current read address corresponding to the read pointer Rdr is greater than or equal to a first threshold (the first threshold can be any natural number greater than 1, and a possible first threshold is 2). In this case, the distance between the read pointer Rdr and the write pointer Wdr is sufficiently large, ensuring effective data writing and reading, thus maintaining normal write and read operations in the asynchronous RAM.

[0092] Understandably, if we subtract the current write address corresponding to the write pointer Wdr from the current read address corresponding to the read pointer Rdr, then we should determine that the difference between the current read address corresponding to the read pointer Rdr and the current write address corresponding to the write pointer Wdr is less than or equal to 0 and greater than the first threshold (the first threshold can be set to any natural number less than -1, and the optional first threshold is -2).

[0093] Example 6

[0094] One embodiment of this application, such as Figure 13 As shown, a sixth asynchronous RAM read / write method is proposed, which includes the following steps after step S200:

[0095] S360: In the same time domain, if the current write address - the current read address ≤ the second threshold, and the write-full flag of the asynchronous RAM indicates that it is full, the write and read operations of the asynchronous RAM remain normal.

[0096] If the current write address minus the current read address is less than or equal to the second threshold, and the asynchronous RAM is full (indicating it is full), then... Figure 14 As shown, the write pointer Wdr writes to the maximum address N of the asynchronous RAM. That is, after one round of writing by the write pointer Wdr, it rewrites from the minimum address "1". Furthermore, the difference between the current write address corresponding to the write pointer Wdr and the current read address corresponding to the read pointer Rdr is less than or equal to a second threshold (the second threshold can be any natural number less than -1, and an optional second threshold is -2). At this point, the distance between the read pointer Rdr and the write pointer Wdr is sufficiently large, ensuring effective data writing and reading, thus maintaining normal write and read operations in the asynchronous RAM.

[0097] Understandably, if we subtract the current write address corresponding to the write pointer Wdr from the current read address corresponding to the read pointer Rdr, then we should determine that the difference between the current read address corresponding to the read pointer Rdr and the current write address corresponding to the write pointer Wdr is greater than or equal to 0 and less than the second threshold (the second threshold can be set to any natural number greater than 1, and the optional second threshold is 2).

[0098] Embodiment 7

[0099] One embodiment of the present application, as shown in Figure 15 The asynchronous RAM read-write device 10 comprises an acquisition module 11, a synchronization module 12 and a read-write module 13.

[0100] The acquisition module 11 is configured to acquire a read address at a current time in a read time domain and a write address at the current time in a write time domain. The synchronization module 12 is configured to synchronize the read address at the current time and the write address at the current time to the same time domain. The read-write module 13 is configured to, in the same time domain, if 0≤ the write address at the current time - the read address at the current time≤ a first threshold value, and a write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, suspend a read operation of the asynchronous RAM and keep a write operation of the asynchronous RAM normal.

[0101] Further, the read-write module 13 is further configured to, in the same time domain, if 0≤ the write address at the current time - the read address at the current time, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is full, suspend the write operation of the asynchronous RAM and keep the read operation of the asynchronous RAM normal.

[0102] Further, the read-write module 13 is further configured to, in the same time domain, if a second threshold value < the write address at the current time - the read address at the current time≤ 0, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is full, suspend the write operation of the asynchronous RAM and keep the read operation of the asynchronous RAM normal.

[0103] Further, the read-write module 13 is further configured to, in the same time domain, if the write address at the current time - the read address at the current time≤ 0, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, suspend the read operation of the asynchronous RAM and keep the write operation of the asynchronous RAM normal.

[0104] Further, the read-write module 13 is further configured to, in the same time domain, if the write address at the current time - the read address at the current time≥ the first threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, keep the write operation and the read operation of the asynchronous RAM normal.

[0105] Further, the read-write module 13 is further configured to, in the same time domain, if the write address at the current time - the read address at the current time≤ the second threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is full, keep the write operation and the read operation of the asynchronous RAM normal.

[0106] Further, the read address of the current time in the read time domain and the write address of the current time in the write time domain are binary, and the synchronizing the read address of the current time and the write address of the current time to the same time domain comprises: converting the write address of the current time in the write time domain in binary into a Gray code write address; synchronizing the Gray code write address to the read time domain; and converting the Gray code write address synchronized to the read time domain into a binary write address, so as to synchronize the write address of the current time in the write time domain to the read time domain.

[0107] Further, the read address of the current time in the read time domain and the write address of the current time in the write time domain are binary, and the synchronizing the read address of the current time and the write address of the current time to the same time domain comprises: converting the write address of the current time in the write time domain in binary into a Gray code write address; synchronizing the Gray code write address to the read time domain; and converting the Gray code write address synchronized to the read time domain into a binary write address, so as to synchronize the write address of the current time in the write time domain to the read time domain.

[0108] The asynchronous RAM reading and writing device 10 disclosed in the embodiment is used for executing the asynchronous RAM reading and writing method disclosed in the above embodiment through the cooperation of the acquisition module 11, the synchronization module 12 and the reading and writing module 13, and the implementation schemes and beneficial effects involved in the above embodiment are also applicable to the embodiment, which will not be repeated here.

[0109] It can be understood that the present application relates to a terminal device comprising a memory and a processor, wherein the memory comprises an asynchronous RAM, and the asynchronous RAM stores a computer program, and the computer program executes the asynchronous RAM reading and writing method when running on the processor.

[0110] It can be understood that the present application relates to a readable storage medium, which stores a computer program, and the computer program executes the asynchronous RAM reading and writing method when running on the processor.

[0111] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other manners. The apparatus embodiments described above are merely illustrative, for example, the flowcharts and structural diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in alternative implementation manners, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flowchart, and the combination of blocks in the structural diagram and / or flowchart, can be implemented by a dedicated hardware-based system for executing the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0112] In addition, each functional module or unit in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0113] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0114] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. An asynchronous RAM read-write method, characterized by, The method comprises: acquiring a read address at a current time in a read time domain and a write address at the current time in a write time domain; synchronizing the read address at the current time and the write address at the current time to the same time domain; in the same time domain, if 0≤the write address at the current time-the read address at the current time<the first threshold value, and the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is not full, then pausing the read operation of the asynchronous RAM while keeping the write operation of the asynchronous RAM normal; wherein when the write pointer points to the maximum address of the asynchronous RAM, the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is full; when the read pointer points to the maximum address of the asynchronous RAM, the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is not full; in the same time domain, if the second threshold value<the write address at the current time-the read address at the current time≤0, and the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is full, then pausing the write operation of the asynchronous RAM while keeping the read operation of the asynchronous RAM normal; in the same time domain, if the write address at the current time-the read address at the current time≥the first threshold value, and the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is not full, then keeping the write operation and the read operation of the asynchronous RAM normal; in the same time domain, if the write address at the current time-the read address at the current time≤the second threshold value, and the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is full, then keeping the write operation and the read operation of the asynchronous RAM normal.

2. The asynchronous RAM read-write method according to claim 1, wherein, Further comprising: in the same time domain, if 0≤the write address at the current time-the read address at the current time, and the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is full, then pausing the write operation of the asynchronous RAM while keeping the read operation of the asynchronous RAM normal.

3. The asynchronous RAM read-write method of claim 1, wherein, Further comprising: in the same time domain, if the write address at the current time-the read address at the current time≤0, and the full-write flag of the asynchronous RAM indicates that the asynchronous RAM is not full, then pausing the read operation of the asynchronous RAM while keeping the write operation of the asynchronous RAM normal.

4. The asynchronous RAM read-write method according to any one of claims 1 to 3, characterized in that, The read address at the current time in the read time domain and the write address at the current time in the write time domain are binary, and the synchronization of the read address at the current time and the write address at the current time to the same time domain comprises: converting the write address at the current time in the write time domain in binary into a Gray code write address; synchronizing the Gray code write address to the read time domain; converting the Gray code write address synchronized to the read time domain into a binary write address, so as to synchronize the write address at the current time in the write time domain to the read time domain.

5. The asynchronous RAM read-write method according to any one of claims 1 to 3, characterized in that, The read address at the current time in the read time domain and the write address at the current time in the write time domain are binary, and the synchronization of the read address at the current time and the write address at the current time to the same time domain comprises: converting the read address at the current time in the read time domain in binary into a Gray code read address; synchronizing the Gray code read address to the write time domain; converting the Gray code read address synchronized to the write time domain into a binary read address, so as to synchronize the read address at the current time in the read time domain to the write time domain.

6. An asynchronous RAM read / write device, characterized by, The device comprises: an acquisition module, configured to acquire a read address at a current time in a read time domain and a write address at the current time in a write time domain; The synchronization module is configured to synchronize the read address at the current time and the write address at the current time to the same time domain. The read-write module is configured to, in the same time domain, if 0≤the write address at the current time-the read address at the current time<the first threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, suspend the read operation of the asynchronous RAM while keeping the write operation of the asynchronous RAM normal. The read-write module is further configured to: In the same time domain, if the second threshold value<the write address at the current time-the read address at the current time≤0, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is full, suspend the write operation of the asynchronous RAM while keeping the read operation of the asynchronous RAM normal. In the same time domain, if the write address at the current time-the read address at the current time≥the first threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is not full, keep the write operation and the read operation of the asynchronous RAM normal. In the same time domain, if the write address at the current time-the read address at the current time≤the second threshold value, and the write full flag of the asynchronous RAM indicates that the asynchronous RAM is full, keep the write operation and the read operation of the asynchronous RAM normal.

7. A terminal device, characterized by comprising: The memory includes an asynchronous RAM, and the asynchronous RAM stores a computer program, which is executed on the processor to perform the asynchronous RAM read-write method according to any one of claims 1 to 5.

8. A readable storage medium, characterized by, The memory stores a computer program, which is executed on the processor to perform the asynchronous RAM read-write method according to any one of claims 1 to 5.

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