Semiconductor device

Abstract

A semiconductor device includes: a transistor located on a substrate; a first interlayer insulating layer located on the transistor; a first lower interconnect line and a second lower interconnect line in an upper portion of the first interlayer insulating layer; and a first via hole and a second via hole respectively located on the first lower interconnect line and the second lower interconnect line. A line width of the first lower interconnect line is greater than a line width of the second lower interconnect line. Each of the first lower interconnect line and the second lower interconnect line includes a first metal pattern. The first lower interconnect line further includes a second metal pattern located on the first metal pattern and including a metal material different from that of the first metal pattern. The second metal pattern does not exist in the second lower interconnect line. The second via hole includes a first portion and a second portion respectively contacting a top surface of the first interlayer insulating layer and a top surface of the second lower interconnect line, and a lowest level height of a bottom surface of the second portion is lower than a lowest level height of a bottom surface of the first via hole.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0167872, filed with the Korean Intellectual Property Office on December 16, 2019, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a field - effect transistor and a method of manufacturing the same. Background art

[0004] Semiconductor devices include integrated circuits having metal - oxide - semiconductor field - effect transistors (MOS - FETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and / or reduced design rules, MOS - FETs are continuously scaled down. The scaling down of MOS - FETs can lead to deterioration of the operating characteristics of semiconductor devices. Various studies are underway to overcome the technical limitations associated with the scaling down of semiconductor devices and to implement higher - performance semiconductor devices. Summary of the invention

[0005] Some example embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics.

[0006] According to some example embodiments of the inventive concept, a semiconductor device may include: a transistor located on a substrate; a first interlayer insulating layer located on the transistor; a first lower interconnect and a second lower interconnect in an upper portion of the first interlayer insulating layer; and a first via and a second via respectively located on the first lower interconnect and the second lower interconnect. The line width of the first lower interconnect may be greater than the line width of the second lower interconnect. Each of the first lower interconnect and the second lower interconnect may include a first metal pattern. The first lower interconnect may further include a second metal pattern located on the first metal pattern and including a metal material different from that of the first metal pattern, and the second metal pattern may not be present in the second lower interconnect. The second via may include a first portion and a second portion, the first portion being in contact with the top surface of the first interlayer insulating layer, the second portion being in contact with the top surface of the second lower interconnect, and the lowest horizontal height of the bottom surface of the second portion may be lower than the lowest horizontal height of the bottom surface of the first via.

[0007] According to some example embodiments of the inventive concept, a semiconductor device may include: a transistor located on a substrate; a first interlayer insulating layer located on the transistor; and a first lower interconnect line and a second lower interconnect line in an upper portion of the first interlayer insulating layer. A line width of the first lower interconnect line may be greater than a line width of the second lower interconnect line. Each of the first lower interconnect line and the second lower interconnect line may include a first metal pattern, and the first lower interconnect line may further include a second metal pattern disposed on the first metal pattern and including a metal material different from a metal material of the first metal pattern. The second metal pattern may have a maximum volume in the first lower interconnect line, and the first metal pattern may have a maximum volume in the second lower interconnect line. A highest horizontal height of a top surface of the second lower interconnect line may be lower than a highest horizontal height of a top surface of the first lower interconnect line, and a top surface of the second metal pattern of the first lower interconnect line may be higher than a top surface of the first metal pattern of the first lower interconnect line.

[0008] According to some example embodiments of the inventive concept, a semiconductor device may include: a substrate including an active region; a device isolation layer located on the active region to define active patterns and covering a lower portion of side surfaces of each of the active patterns, an upper portion of each of the active patterns protruding above the device isolation layer; a pair of source / drain patterns located in the upper portion of each of the active patterns; a channel pattern located between the pair of source / drain patterns; a gate electrode crossing the channel pattern and extending in a first direction; gate spacers on both sides of the gate electrode and extending in the first direction together with the gate electrode; a gate dielectric pattern located between the gate electrode and the channel pattern and between the gate electrode and the gate spacers; a gate capping pattern located on a top surface of the gate electrode and extending in the first direction together with the gate electrode; a first interlayer insulating layer located on the gate capping pattern; an active contact passing through the first interlayer insulating layer and electrically connected to at least one of the source / drain patterns; a first metal layer disposed in a second interlayer insulating layer on the first interlayer insulating layer; and a second metal layer located in a third interlayer insulating layer on the second interlayer insulating layer. The first metal layer may include a first lower interconnect and a second lower interconnect, the first lower interconnect and the second lower interconnect extending in a second direction crossing the first direction and at least one of them being electrically connected to the active contact. The second metal layer may include a first upper interconnect and a second upper interconnect, the first upper interconnect and the second upper interconnect being electrically connected to the first lower interconnect and the second lower interconnect through a first via and a second via, respectively. A line width of the first lower interconnect may be greater than a line width of the second lower interconnect. Each of the first lower interconnect and the second lower interconnect may include a first metal pattern, and the first lower interconnect may further include a second metal pattern disposed on the first metal pattern and including a metal material different from that of the first metal pattern. The second metal pattern may not be present in the second lower interconnect. The second via may include a first portion and a second portion, the first portion contacting a top surface of the second interlayer insulating layer, the second portion contacting a top surface of the second lower interconnect. A lowest horizontal height of a bottom surface of the second portion may be lower than a lowest horizontal height of a bottom surface of the first via. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following brief description in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments as described herein.

[0010] Figure 1 is a plan view showing a semiconductor device according to some example embodiments of the inventive concept.

[0011] Figures 2A to 2D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 1 respectively.

[0012] Figure 3 is an enlarged cross-sectional view showing portions M and N of Figure 2D .

[0013] Figure 4 is a graph showing the resistivity of a metal for a lower interconnect according to some example embodiments of the inventive concept.

[0014] Figure 5 , Figure 7 , Figure 9 and Figure 11 is a plan view showing a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0015] Figure 6 , Figure 8A , Figure 10A and Figure 12A are cross-sectional views taken along lines A-A' of Figure 5 , Figure 7 , Figure 9 and Figure 11 respectively.

[0016] Figure 8B , Figure 10B and Figure 12B are cross-sectional views taken along lines B-B' of Figure 7 , Figure 9 and Figure 11 respectively.

[0017] Figure 10C and Figure 12C are cross-sectional views taken along lines C-C' of Figure 9 and Figure 11 respectively.

[0018] Figure 10D and Figure 12D are cross-sectional views taken along lines D-D' of Figure 9 and Figure 11 respectively.

[0019] Figures 13 to 19 is a view showing a method of forming a lower interconnect according to some example embodiments of the inventive concept and particularly shows an enlarged cross-sectional view of portions M and N of Figure 2D .

[0020] Figure 20 is a view showing a lower interconnect according to some example embodiments of the inventive concept and particularly shows an enlarged cross-sectional view of portions M and N of Figure 2D .

[0021] Figure 21 is a cross-sectional view of a lower interconnect according to some example embodiments of the inventive concept.

[0022] Figure 22 is a cross-sectional view of a first lower interconnect line showing some example embodiments according to the inventive concept.

[0023] Figures 23A to 23D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' respectively to show a semiconductor device according to some example embodiments of the inventive concept. Figure 1

[0024] It should be noted that these drawings are intended to show the general characteristics of the methods, structures, and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as defining or limiting the scope of the values or properties included in the example embodiments. For example, for clarity, the relative thicknesses and positions of molecules, layers, regions, and / or structural elements may be reduced or enlarged. The use of like or identical reference numerals in the various drawings is intended to indicate the presence of like or identical elements or features. DETAILED DESCRIPTION

[0025] Figure 1 is a plan view of a semiconductor device showing some example embodiments according to the inventive concept. Figures 2A to 2D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' respectively. Figure 1 Figure 3 is an enlarged cross-sectional view showing portions M and N of Figure 2D

[0026] Referring to Figure 1 and Figures 2A to 2D , a logic unit LC may be disposed on a substrate 100. In the present specification, the logic unit LC may refer to a logic device (e.g., an inverter, a flip-flop, etc.) configured to perform a specific function. For example, the logic unit LC may include transistors constituting the logic device and interconnect lines connecting the transistors to each other.

[0027] The substrate 100 may include a first active region PR and a second active region NR. In some example embodiments, the first active region PR may be a PMOSFET region and the second active region NR may be an NMOSFET region. The substrate 100 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or a silicon-germanium substrate) or a compound semiconductor substrate. For example, the substrate 100 may be a silicon wafer.

[0028] ​​​The first active region PR and the second active region NR may be defined by a second trench TR2 in the upper portion of the substrate 100. The second trench TR2 may be disposed between the first active region PR and the second active region NR. The first active region PR and the second active region NR may be spaced apart from each other in a first direction D1, and the second trench TR2 is interposed between the first active region PR and the second active region NR. Each of the first active region PR and the second active region NR may extend in a second direction D2 different from the first direction D1.

[0029] The first active pattern AP1 and the second active pattern AP2 may be disposed on the first active region PR and the second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2 and may be parallel to each other. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 that protrude in a vertical direction (e.g., a third direction D3). A first trench TR1 may be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trench TR1 may be shallower than the second trench TR2.

[0030] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may be formed of or include silicon oxide. The upper portions of the first active pattern AP1 and the second active pattern AP2 may be protruding patterns (e.g., see Figure 2D ) that extend vertically above the device isolation layer ST. Each of the upper portions of the first active pattern AP1 and the second active pattern AP2 may be fin-shaped. The device isolation layer ST may not cover the upper portions of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover lower portions of the side surfaces of the first active pattern AP1 and the second active pattern AP2.

[0031] The first source / drain pattern SD1 may be disposed in the upper portion of the first active pattern AP1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type). A first channel pattern CH1 may be interposed between a pair of first source / drain patterns SD1. The second source / drain pattern SD2 may be disposed in the upper portion of the second active pattern AP2. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). A second channel pattern CH2 may be interposed between a pair of second source / drain patterns SD2.

[0032] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth process. As an example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be coplanar with the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. As another example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0033] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element in the substrate 100. Accordingly, the first source / drain pattern SD1 may apply compressive stress on the first channel pattern CH1. As an example, the second source / drain pattern SD2 may include a semiconductor element (e.g., Si) that serves as the substrate 100.

[0034] The gate electrode GE may be disposed to cross the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. The gate electrodes GE may be arranged to be spaced apart from each other in the second direction D2 by a first pitch P1. When viewed in a plan view, the gate electrode GE may overlap with the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE may surround the top surface and the opposing side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2.

[0035] Return reference Figure 2D The gate electrode GE may be disposed on the first top surface TS1 of the first channel pattern CH1 and on at least one first side surface SW1 of the first channel pattern CH1. The gate electrode GE may be disposed on the second top surface TS2 of the second channel pattern CH2 and on at least one second side surface SW2 of the second channel pattern CH2. For example, a transistor according to some example embodiments may be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrode GE is disposed to three-dimensionally surround the channel patterns CH1 and CH2.

[0036] Return reference Figure 1 and Figures 2A to 2D, a pair of gate spacers GS may be disposed on opposite side surfaces of each of the gate electrodes GE. The gate spacers GS may extend along the gate electrodes GE in a first direction D1. A top surface of the gate spacers GS may be higher than a top surface of the gate electrodes GE. The top surface of the gate spacers GS may be coplanar with a top surface of a first interlayer insulating layer 110 to be described below. The gate spacers GS may be formed of at least one of SiCN, SiCON, and SiN, or include at least one of them. In some example embodiments, the gate spacers GS may be a multi-layer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0037] A gate capping pattern GP may be disposed on each of the gate electrodes GE. The gate capping pattern GP may extend along the gate electrodes GE in the first direction D1. The gate capping pattern GP may be formed of, or include, at least one material having an etching selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to be described below. For example, the gate capping pattern GP may be formed of, or include, at least one of SiON, SiCN, SiCON, and SiN.

[0038] A gate dielectric pattern GI may be interposed between the gate electrode GE and the first active pattern AP1 and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI may extend along a bottom surface of the gate electrode GE thereon. As an example, the gate dielectric pattern GI may cover a first top surface TS1 and a first side surface SW1 of the first channel pattern CH1. The gate dielectric pattern GI may cover a second top surface TS2 and two second side surfaces SW2 of the second channel pattern CH2. The gate dielectric pattern GI may cover a top surface of the device isolation layer ST under the gate electrode GE (e.g., see Figure 12D ).

[0039] In some example embodiments, the gate dielectric pattern GI may be formed of, or include, a high-k dielectric material having a dielectric constant higher than that of a silicon oxide layer. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0040] The gate electrode GE may include a first metal and a second metal on the first metal. The first metal may be disposed on the gate dielectric pattern GI and may be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal may include a work function metal for adjusting the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal, a transistor having a desired threshold voltage can be achieved.

[0041] The first metal may include a metal nitride layer. For example, the first metal may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). In some exemplary embodiments, the first metal may further include carbon (C). The first metal may include a plurality of stacked work function metal layers.

[0042] The second metal may include a metal having a lower resistance than the resistance of the first metal. For example, the second metal may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0043] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate capping pattern GP and the top surface of the gate spacer GS. The second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate capping pattern GP. The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In some exemplary embodiments, the first interlayer insulating layer 110 to the fourth interlayer insulating layer 140 may be formed of silicon oxide or include silicon oxide.

[0044] A pair of isolation structures DB may be disposed on opposite sides of the logic unit LC in the second direction D2. The isolation structures DB may extend in the first direction D1 and be parallel to the gate electrode GE. In some exemplary embodiments, the pitch between adjacent isolation structures DB and the gate electrode GE may be equal to the first pitch P1.

[0045] The isolation structures DB may be configured to pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and may extend into the first active pattern AP1 and the second active pattern AP2. The isolation structures DB may pass through the upper portions of each of the first active pattern AP1 and the second active pattern AP2. The isolation structures DB may separate the first active region PR and the second active region NR of the logic unit LC from the active regions of adjacent logic units.

[0046] The active contact AC can be configured to pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. Each of the active contacts AC can be disposed between a pair of gate electrodes GE.

[0047] The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed by a self-alignment process using a gate capping pattern GP and a gate spacer GS. For example, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. Although not shown, in some example embodiments, the active contact AC can cover a portion of the top surface of the gate capping pattern GP.

[0048] A silicide pattern SC can be interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC can be formed of at least one metal silicide material (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide), or include the at least one metal silicide material.

[0049] The gate contact GC can be configured to pass through the second interlayer insulating layer 120 and the gate capping pattern GP and connect to the gate electrode GE. When viewed in a plan view, the gate contact GC can be disposed between the first active region PR and the second active region NR. The bottom surface of the gate contact GC can be in contact with the top surface of the gate electrode GE. The top surface of the gate contact GC can be coplanar with the top surface of the second interlayer insulating layer 120.

[0050] Each of the active contact AC and the gate contact GC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM can be formed of at least one metal among aluminum, copper, tungsten, molybdenum, and cobalt, or include the at least one metal. The barrier pattern BM can cover the side surface and the bottom surface of the conductive pattern FM. The barrier pattern BM can include at least one of a metal layer and a metal nitride layer. The metal layer can be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer can be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0051] The first metal layer M1 can be disposed in the third interlayer insulating layer 130. The first metal layer M1 can include a first lower interconnect line LIL1, a second lower interconnect line LIL2, and a lower via VI. The lower via VI can be disposed below the first lower interconnect line LIL1 and the second lower interconnect line LIL2.

[0052] The first lower interconnect line LIL1 can be arranged to extend in the second direction D2 and cross the logic cell LC. The first lower interconnect line LIL1 can be used as a power line. For example, a drain voltage VDD or a source voltage VSS can be applied to the first lower interconnect line LIL1.

[0053] Referring to Figure 1 , a first cell boundary CB1 extending in the second direction D2 can be defined in the region of the logic cell LC. A second cell boundary CB2 extending in the second direction D2 can be defined in the region of the logic cell LC opposite to the first cell boundary CB1. The first lower interconnect line LIL1 to which the drain voltage VDD (e.g., power supply voltage) is applied can be disposed on the first cell boundary CB1. The first lower interconnect line LIL1 to which the drain voltage VDD is applied can extend along the first cell boundary CB1 or in the second direction D2. The first lower interconnect line LIL1 to which the source voltage VSS (e.g., ground voltage) is applied can be disposed on the second cell boundary CB2. The first lower interconnect line LIL1 to which the source voltage VSS is applied can extend along the second cell boundary CB2 or in the second direction D2.

[0054] The second lower interconnect line LIL2 can be disposed between the first lower interconnect line LIL1 to which the drain voltage VDD is applied and the first lower interconnect line LIL1 to which the source voltage VSS is applied. The second lower interconnect line LIL2 can extend in the second direction D2 and can be parallel to each other. When viewed in a plan view, the second lower interconnect line LIL2 can be a linear or bar-shaped pattern. The second lower interconnect line LIL2 can be arranged to be spaced apart from each other in the first direction D1 at a second pitch P2. The second pitch P2 can be smaller than the first pitch P1.

[0055] The line width of each of the first lower interconnect lines LIL1 can be a first width W1. The line width of each of the second lower interconnect lines LIL2 can be a second width W2. The second width W2 can be smaller than the first width W1. For example, the first width W1 can be greater than 12 nm. The second width W2 can be smaller than 12 nm.

[0056] The lower via VI can be inserted between the first lower interconnect line LIL1 and the second lower interconnect line LIL2 and the active contact AC. The lower via VI can be inserted between the second lower interconnect line LIL2 and the gate contact GC.

[0057] The etch stop layer ESL may be interposed between the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140. The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include upper interconnect lines UIL.

[0058] The upper interconnect lines UIL may extend in a first direction D1 and may be parallel to each other. When viewed in a plan view, the upper interconnect lines UIL may be linear or strip-shaped patterns. The upper interconnect lines UIL may be arranged in a second direction D2.

[0059] The upper interconnect lines UIL may include line portions HEP and via portions VEP. The line portions HEP may be disposed in the upper portion of the fourth interlayer insulating layer 140 and may extend in the first direction D1. The via portions VEP may be disposed in the lower portion of the fourth interlayer insulating layer 140 and may extend from the line portions HEP toward the first metal layer M1. For example, the via portions VEP may be via plugs inserted between the first metal layer M1 and the line portions HEP to connect them to each other.

[0060] The line portions HEP and the via portions VEP may be connected to each other to form a single conductive element (e.g., serving as the upper interconnect lines UIL). In some example embodiments, the line portions HEP and the via portions VEP constituting the upper interconnect lines UIL may be formed by a dual damascene process.

[0061] Reference will be made to Figure 3 the first lower interconnect line LIL1 and the second lower interconnect line LIL2 according to some example embodiments will be described in more detail.

[0062] First, the first lower interconnect line LIL1 will be described in more detail. The first lower interconnect line LIL1 may include a barrier metal pattern BAP, a first metal pattern MEP1 on the barrier metal pattern BAP, a second metal pattern MEP2 on the first metal pattern MEP1, and a metal capping pattern CAP on the second metal pattern MEP2.

[0063] The upper portion of the barrier metal pattern BAP may be recessed to define a recessed region RS. In some example embodiments, the top surface BAPt of the barrier metal pattern BAP may be lower than the top surface 130t of the third interlayer insulating layer 130. The barrier metal pattern BAP may have a 'U'-shaped cross-section.

[0064] The barrier metal pattern BAP can improve the adhesion property between the first lower interconnecting line LIL1 and the third interlayer insulating layer 130. The barrier metal pattern BAP can be used as a barrier to reduce or prevent the diffusion of metal elements in the second metal pattern MEP2 into the third interlayer insulating layer 130. The barrier metal pattern BAP can be formed of at least one of tantalum nitride (TaN), titanium nitride (TiN), tantalum oxide (TaO), titanium oxide (TiO), manganese nitride (MnN), and manganese oxide (MnO), or include at least one of tantalum nitride (TaN), titanium nitride (TiN), tantalum oxide (TaO), titanium oxide (TiO), manganese nitride (MnN), and manganese oxide (MnO).

[0065] The first metal pattern MEP1 can include a lower portion LP and a pair of upper portions UP extending from the lower portion LP in the third direction D3. For example, the first metal pattern MEP1 can have a 'U'-shaped cross-section. The top surface 130t of the third interlayer insulating layer 130 can be at a first horizontal height LV1. The top surface MEP1t of the upper portion UP of the first metal pattern MEP1 can be at a second horizontal height LV2. The second horizontal height LV2 can be lower than the first horizontal height LV1. The upper portion UP of the first metal pattern MEP1 can have a first thickness T1 in the first direction D1.

[0066] The first metal pattern MEP1 can be formed of a metal material having a relatively short electron mean free path (eMFP) (e.g., ruthenium (Ru), cobalt (Co), tungsten (W), or molybdenum (Mo)), or include the metal material, and the eMFP will be described below. The first metal pattern MEP1 can have a low resistivity property when it has a relatively small thickness (e.g., a first thickness T1 of 12 nm or less).

[0067] The second metal pattern MEP2 can be disposed in the space surrounded by the lower portion LP of the first metal pattern MEP1 and the pair of upper portions UP. In other words, the bottom surface of the second metal pattern MEP2 can be in contact with the lower portion LP of the first metal pattern MEP1. The two side surfaces of the second metal pattern MEP2 can be in contact with the pair of upper portions UP of the first metal pattern MEP1, respectively. Among the metal patterns constituting the first lower interconnecting line LIL1, the second metal pattern MEP2 can have the largest volume.

[0068] The second metal pattern MEP2 can have a curved top surface MEP2t. The highest horizontal height of the top surface MEP2t of the second metal pattern MEP2 can be at a third horizontal height LV3. The third horizontal height LV3 can be between the first horizontal height LV1 and the second horizontal height LV2.

[0069] The second metal pattern MEP2 may be formed of a metal material different from that of the first metal pattern MEP1, or include a metal material different from that of the first metal pattern MEP1. The second metal pattern MEP2 may be formed of a metal material having a relatively long eMFP (e.g., copper (Cu)), or include such a metal material. The second metal pattern MEP2 may have a low resistivity property when it has a relatively large line width.

[0070] The metal capping pattern CAP may cover the top surface MEP1t of the first metal pattern MEP1 and the top surface MEP2t of the second metal pattern MEP2. The metal capping pattern CAP may be set to have a thin and uniform thickness. The metal capping pattern CAP may be formed of or include at least one of ruthenium (Ru), cobalt (Co), and graphene.

[0071] The highest level height of the top surface LIL1t of the first lower interconnect line LIL1 may be at the fourth level height LV4. In some example embodiments, the fourth level height LV4 may be the same as or substantially the same as the first level height LV1. In some example embodiments, the fourth level height LV4 may be between the first level height LV1 and the third level height LV3.

[0072] Next, the second lower interconnect line LIL2 will be described in more detail. The second lower interconnect line LIL2 may include a barrier metal pattern BAP, a first metal pattern MEP1 on the barrier metal pattern BAP, and a metal capping pattern CAP on the first metal pattern MEP1. Different from the first lower interconnect line LIL1, the second metal pattern MEP2 may be omitted from the second lower interconnect line LIL2.

[0073] The barrier metal pattern BAP of the second lower interconnect line LIL2 may be formed of a material the same as that of the barrier metal pattern BAP of the first lower interconnect line LIL1, or include a material the same as that of the barrier metal pattern BAP of the first lower interconnect line LIL1. The first metal pattern MEP1 of the second lower interconnect line LIL2 may be formed of a material the same as that of the first metal pattern MEP1 of the first lower interconnect line LIL1, or include a material the same as that of the first metal pattern MEP1 of the first lower interconnect line LIL1. The metal capping pattern CAP of the second lower interconnect line LIL2 may be formed of a material the same as that of the metal capping pattern CAP of the first lower interconnect line LIL1, or include a material the same as that of the metal capping pattern CAP of the first lower interconnect line LIL1.

[0074] The first metal pattern MEP1 of the second lower interconnect LIL2 may have a second thickness T2 in a first direction D1. The second thickness T2 may be greater than twice the first thickness T1. In some example embodiments, the second thickness T2 may be less than 12 nm.

[0075] The top surface MEP1t of the first metal pattern MEP1 of the second lower interconnect LIL2 may have a curved shape. The highest horizontal height of the top surface MEP1t of the first metal pattern MEP1 may be at a second horizontal height LV2. The second horizontal height LV2 may be lower than the first horizontal height LV1. The metal capping pattern CAP of the second lower interconnect LIL2 may cover the top surface MEP1t of the first metal pattern MEP1.

[0076] The highest horizontal height of the top surface LIL2t of the second lower interconnect LIL2 may be at a fifth horizontal height LV5. The fifth horizontal height LV5 may be lower than the fourth horizontal height LV4 of the top surface LIL1t of the first lower interconnect LIL1. The fifth horizontal height LV5 may be between the first horizontal height LV1 and the second horizontal height LV2.

[0077] The etch stop layer ESL may cover the top surface LIL1t of the first lower interconnect LIL1, the top surface LIL2t of the second lower interconnect LIL2, and the top surface 130t of the third interlayer insulating layer 130. The etch stop layer ESL may fill the recessed area RS on the barrier metal pattern BAP.

[0078] The via portion VEP of the upper interconnect UIL may pass through the etch stop layer ESL and may contact the top surface LIL1t of the first lower interconnect LIL1. Since the first lower interconnect LIL1 has a relatively large line width, the via portion VEP may be aligned with the first lower interconnect LIL1 without misalignment. In some example embodiments, the via portion VEP of the upper interconnect UIL may be aligned with the center of the first lower interconnect LIL1. The via portion VEP may have a bottom surface that is curved along the top surface LIL1t of the first lower interconnect LIL1. The lowest horizontal height of the bottom surface of the via portion VEP on the first lower interconnect LIL1 may be at a sixth horizontal height LV6.

[0079] The via portion VEP of the upper interconnect UIL may pass through the etch stop layer ESL and may contact the top surface LIL2t of the second lower interconnect LIL2. In some example embodiments, the via portion VEP of the upper interconnect UIL may be offset in the first direction D1 relative to the center of the second lower interconnect LIL2. Thus, the via portion VEP may include a first portion PA1 that contacts the top surface 130t of the third interlayer insulating layer 130 and a second portion PA2 that contacts the top surface LIL2t of the second lower interconnect LIL2.

[0080] Compared with the first part PA1, the second part PA2 can protrude towards the second lower interconnecting line LIL2 or protrude in the downward direction. Therefore, the first part PA1 and the second part PA2 can form a staircase structure. The bottom surface of the first part PA1 can be higher than the bottom surface of the second part PA2.

[0081] The bottom surface of the second part PA2 of the via portion VEP can have a profile that bends along the top surface LIL2t of the second lower interconnecting line LIL2. The lowest horizontal height of the bottom surface of the second part PA2 of the via portion VEP can be at the seventh horizontal height LV7. The seventh horizontal height LV7 can be lower than the sixth horizontal height LV6.

[0082] In some exemplary embodiments in which the via pattern is formed in an offset manner on the second lower interconnecting line LIL2 with a relatively small line width and pitch, a short circuit can be formed between adjacent second lower interconnecting lines LIL2. This can cause a failure of the semiconductor device. Refer back to Figure 2D , the second lower interconnecting line LIL2 can be formed such that its top surface is lower than the top surface of the third interlayer insulating layer 130. Therefore, even if the via portion VEP on the second lower interconnecting line LIL2 is offset in the first direction D1, the via portion VEP may not contact other second lower interconnecting lines LIL2 adjacent to the second lower interconnecting line LIL2. That is, even if the via portion VEP is formed in an offset manner, a short circuit formed between adjacent second lower interconnecting lines LIL2 can be reduced or prevented.

[0083] Figure 4 is a graph showing the resistivity of a metal for a lower interconnecting line according to some exemplary embodiments of the inventive concept. Specifically, Figure 4 shows the change in the resistivity of a metal according to the line width of the lower interconnecting line.

[0084] As Figure 4 shown, the resistivity of the interconnecting line can vary according to the type of metal material constituting the interconnecting line and the line width of the interconnecting line. When the interconnecting line has a line width of several tens of nanometers or less, the resistivity of the interconnecting line can increase as the line width decreases. This increase in resistivity caused by reducing the line width of the interconnecting line can be non-linear.

[0085] In some example embodiments in which the line width of the interconnecting lines is reduced to below a specific value, a resistivity inversion phenomenon may occur between metal materials that are different from each other in eMFP. Specifically, compared with copper (Cu) having an eMFP value of 12 nm or greater, in ruthenium (Ru) and cobalt (Co) having an eMFP value of 12 nm or less, the increase in resistivity caused by reducing the line width may be smaller. For example, when the line has a line width of about 12 nm or less, the resistivity of the line containing ruthenium or cobalt may be lower than the resistivity of the line containing copper. The eMFP values of copper, cobalt, and ruthenium may be 39 nm, 11.8 nm, and 6.6 nm, respectively, at room temperature and atmospheric pressure.

[0086] Conversely, at a relatively large line width, the resistivity of copper may be lower than the resistivity of ruthenium and cobalt. For example, when the line has a line width of about 20 nm, the resistivity of the line containing copper may be lower than the resistivity of the line containing ruthenium or cobalt.

[0087] In some example embodiments, with reference to Figure 3 and Figure 4 , the second metal pattern MEP2 formed of a metal having a relatively large eMFP value (e.g., copper (Cu)) may have the largest volume in the first lower interconnecting line LIL1 having a relatively large line width.

[0088] The first metal pattern MEP1 formed of a metal having a relatively small eMFP value (e.g., ruthenium or cobalt) may have the largest volume in the second lower interconnecting line LIL2 having a relatively small line width.

[0089] According to some example embodiments of the inventive concept, considering the non-linearity of the line width and resistivity of the interconnecting lines, a metal material for the interconnecting lines may be selected to optimize or reduce the resistivity characteristics of the interconnecting lines. Accordingly, it may be possible to improve the operating speed and / or electrical characteristics of the semiconductor device.

[0090] Figure 5 、 Figure 7 、 Figure 9 and Figure 11 are plan views showing a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept. Figure 6 、 Figure 8A 、 Figure 10A and Figure 12A are cross-sectional views taken along line A-A' of Figure 5 、 Figure 7 、 Figure 9 and Figure 11 respectively. Figure 8B 、 Figure 10B and Figure 12B are cross-sectional views taken along Figure 7 、 Figure 9 and Figure 11Cross-sectional view taken along line B-B'. Figure 10C and Figure 12C are cross-sectional views taken along lines C-C' of Figure 9 and Figure 11 respectively. Figure 10D and Figure 12D are cross-sectional views taken along lines D-D' of Figure 9 and Figure 11 respectively.

[0091] Referring to Figure 5 and Figure 6 , a substrate 100 including a first active region PR and a second active region NR can be provided. The first active region PR and the second active region NR can define logic cells LC on the substrate 100.

[0092] The first active pattern AP1 and the second active pattern AP2 can be formed by patterning the substrate 100. The first active pattern AP1 can be formed on the first active region PR, and the second active pattern AP2 can be formed on the second active region NR. A first trench TR1 can be formed between the first active patterns AP1 and between the second active patterns AP2. A second trench TR2 can be formed by patterning a portion of the substrate 100 located between the first active region PR and the second active region NR. The second trench TR2 can be formed to have a depth greater than that of the first trench TR1.

[0093] A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be formed of an insulating material (e.g., silicon oxide) or include the insulating material. The device isolation layer ST can be recessed to expose upper portions of the first active pattern AP1 and the second active pattern AP2. For example, the upper portions of the first active pattern AP1 and the second active pattern AP2 can protrude vertically above the device isolation layer ST.

[0094] Referring to Figure 7 , Figure 8A and Figure 8B , a sacrificial pattern PP can be formed to cross the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP can be formed to have a linear or strip shape extending in a first direction D1. As shown in Figure 1 , the sacrificial pattern PP can be formed to be spaced apart from each other at a first pitch P1 in a second direction D2.

[0095] Specifically, the formation of the sacrificial pattern PP can include: forming a sacrificial layer on the substrate 100; forming a hard mask pattern MA on the sacrificial layer; and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer can be formed of polysilicon or include polysilicon.

[0096] A pair of gate spacers GS may be formed on two side surfaces of each of the sacrificial patterns PP. The formation of the gate spacers GS may include: conformally forming a gate spacer layer on the substrate 100; and anisotropically etching the gate spacer layer. In some example embodiments, the gate spacer layer may be formed of, or include at least one of SiCN, SiCON, and SiN. In some example embodiments, the gate spacer layer may be a multi-layer structure including at least two layers of a SiCN layer, a SiCON layer, and a SiN layer.

[0097] Referring Figure 9 and Figures 10A to 10D , a first source / drain pattern SD1 may be formed in the upper portion of the first active pattern AP1. A pair of first source / drain patterns SD1 may be formed on both sides of each of the sacrificial patterns PP.

[0098] Specifically, the upper portion of the first active pattern AP1 may be etched by using the hard mask pattern MA and the gate spacers GS as etching masks to form a first recess RSR1. The device isolation layer ST between the first active patterns AP1 may be recessed during the etching of the upper portion of the first active pattern AP1 (e.g., see Figure 10C ).

[0099] The first source / drain pattern SD1 may be formed by performing a selective epitaxial growth process by using the inner surface of the first recess RSR1 of the first active pattern AP1 as a seed layer. As a result of forming the first source / drain pattern SD1, a first channel pattern CH1 may be defined between each pair of the first source / drain patterns SD1. In some example embodiments, the selective epitaxial growth process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element in the substrate 100. Each of the first source / drain patterns SD1 may be a multi-layer structure including a plurality of semiconductor layers.

[0100] In some example embodiments, the first source / drain pattern SD1 may be in-situ doped during the selective epitaxial growth process. In some example embodiments, after the first source / drain pattern SD1 is formed, impurities may be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0101] A second source / drain pattern SD2 may be formed on the second active pattern AP2. A pair of second source / drain patterns SD2 may be formed on both sides of each of the sacrificial patterns PP.

[0102] Specifically, the upper portion of the second active pattern AP2 may be etched by using the hard mask pattern MA and the gate spacer GS as an etch mask to form the second recess RSR2. The second source / drain pattern SD2 may be formed by performing a selective epitaxial growth process by using the inner surface of the second recess RSR2 of the second active pattern AP2 as a seed layer. As a result of forming the second source / drain pattern SD2, the second channel pattern CH2 may be defined between each pair of the second source / drain patterns SD2. In some example embodiments, the second source / drain pattern SD2 may include a semiconductor element (e.g., Si) used as the substrate 100. The second source / drain pattern SD2 may be doped to have a second conductivity type (e.g., n-type).

[0103] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be sequentially formed by different processes. In other words, the first source / drain pattern SD1 and the second source / drain pattern SD2 may not be formed simultaneously.

[0104] Referring to Figure 11 and Figures 12A to 12D FIGS. 11 and 12, the first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MA, and the gate spacer GS. In some example embodiments, the first interlayer insulating layer 110 may be formed of or include silicon oxide.

[0105] The first interlayer insulating layer 110 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 may be performed by using an etch-back process or a chemical mechanical polishing (CMP) process. In some example embodiments, the planarization process may be performed to completely remove the hard mask pattern MA. Thus, the top surface of the first interlayer insulating layer 110 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0106] The sacrificial patterns PP may be replaced with gate electrodes GE, respectively. For example, the exposed sacrificial patterns PP may be selectively removed. As a result of removing the sacrificial patterns PP, empty spaces may be formed. A gate dielectric pattern GI, a gate electrode GE, and a gate capping pattern GP may be formed in each of the empty spaces. The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be formed of a work function metal capable of adjusting the threshold voltage of the transistor, and the second metal pattern may be formed of a metal material having a low resistance.

[0107] A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may be formed of or include silicon oxide. The active contact AC may be formed to pass through the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and electrically connect to the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate contact GC may be formed to pass through the second interlayer insulating layer 120 and the gate capping pattern GP and electrically connect to the gate electrode GE.

[0108] A pair of isolation structures DB may be formed along opposite sides of the logic cell LC in the second direction D2. The isolation structures DB may be formed to overlap the gate electrodes GE formed on the opposite sides of the logic cell LC. For example, forming the isolation structures DB may include: forming holes that extend through the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the gate electrode GE into the first active pattern AP1 and the second active pattern AP2; and subsequently filling the holes with an insulating layer.

[0109] Returning to Figure 1 and Figures 2A to 2D , a third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. A first metal layer M1 may be formed in the third interlayer insulating layer 130. Forming the first metal layer M1 may include: forming a first lower interconnect LIL1, a second lower interconnect LIL2, and a lower via VI.

[0110] An etch stop layer ESL may be formed on the first metal layer M1. A fourth interlayer insulating layer 140 may be formed on the etch stop layer ESL. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140. Forming the second metal layer M2 may include: forming an upper interconnect UIL. The upper interconnect UIL may be formed by a dual damascene process.

[0111] Figures 13 to 19 is a method of forming a lower interconnect according to some example embodiments of the inventive concept and specifically shows an Figure 2D enlarged cross-sectional view of portions M and N. Hereinafter, a method of forming the first lower interconnect LIL1 and the second lower interconnect LIL2 according to some example embodiments of the inventive concept will be described in more detail with reference to Figures 13 to 19 .

[0112] Referring to Figure 13, the first wiring hole ILH1 and the second wiring hole ILH2 can be formed by patterning the upper portion of the third interlayer insulating layer 130. Each of the first wiring hole ILH1 and the second wiring hole ILH2 can be a linear trench extending in the second direction D2. The first wiring hole ILH1 and the second wiring hole ILH2 can define regions in which the first lower interconnect line LIL1 and the second lower interconnect line LIL2 will be formed.

[0113] The first wiring hole ILH1 can have a first width W1 in the first direction D1. The second wiring hole ILH2 can have a second width W2 in the upper first direction D1. The first width W1 can be greater than the second width W2.

[0114] Referring to Figure 14 , a barrier layer BAL and a first metal layer MEL1 can be sequentially formed in the first wiring hole ILH1 and the second wiring hole ILH2. The barrier layer BAL can be formed to have a thin and uniform thickness. An atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process can be used to form the barrier layer BAL.

[0115] The barrier layer BAL can be used as an adhesion layer that allows the first metal layer MEL1 to be stably attached thereto in a subsequent step. The barrier layer BAL can be formed of, or include, at least one of tantalum nitride (TaN), titanium nitride (TiN), tantalum oxide (TaO), titanium oxide (TiO), manganese nitride (MnN), and manganese oxide (MnO).

[0116] The first metal layer MEL1 can be conformally formed on the barrier layer BAL. An ALD or CVD process can be used to form the first metal layer MEL1. The first metal layer MEL1 can be formed to partially fill the first wiring hole ILH1 and completely fill the second wiring hole ILH2.

[0117] For example, the first metal layer MEL1 can be formed to have a third thickness T3 in the first direction D1 on the inner surface of the first wiring hole ILH1. The first metal layer MEL1 on the inner surface of the second wiring hole ILH2 can have a second thickness T2 in the first direction D1. The third thickness T3 can be greater than half of the second thickness T2.

[0118] The first metal layer MEL1 can be formed of, or include, a metal material having a relatively small eMFP value (e.g., ruthenium (Ru), cobalt (Co), tungsten (W), or molybdenum (Mo)). The first metal layer MEL1 filling the second wiring hole ILH2 can have a low resistivity property when it has a relatively small thickness (e.g., the second thickness T2, or 12 nm or less).

[0119] After forming the first metal layer MEL1, a heat treatment process can be performed on the first metal layer MEL1. The resistivity of the first metal layer MEL1 can be further reduced by the heat treatment process.

[0120] Referring to Figure 15 , an etching process WE can be performed on the first metal layer MEL1 to isotropically reduce the thickness of the first metal layer MEL1. In some exemplary embodiments, the etching process WE can include an isotropic etching process (e.g., a wet etching process). In some exemplary embodiments, a dry etching process can be used to perform the etching process WE.

[0121] As a result of the etching process WE, the total thickness of the first metal layer MEL1 in the first wiring hole ILH1 can be reduced. For example, the thickness of the first metal layer MEL1 on the inner surface of the first wiring hole ILH1 can be reduced from the third thickness T3 to the first thickness T1. In other words, the volume of the first metal layer MEL1 in the first wiring hole ILH1 can be reduced.

[0122] During the etching process WE, in the region located on the third interlayer insulating layer 130, the thickness of the first metal layer MEL1 on the second wiring hole ILH2 can be reduced, but the first metal layer MEL1 in the second wiring hole ILH2 can be unaffected by the etching process WE. The first metal layer MEL1 on the inner surface of the second wiring hole ILH2 can be maintained at the second thickness T2. In other words, the etching process WE can reduce the volume of the first metal layer MEL1 in the first wiring hole ILH1, but can not cause a change in the volume of the first metal layer MEL1 in the second wiring hole ILH2.

[0123] Referring to Figure 16 , a second metal layer MEL2 can be formed on the first metal layer MEL1. The second metal layer MEL2 can be formed to completely fill the first wiring hole ILH1. Since the second wiring hole ILH2 has been filled with the first metal layer MEL1, the second metal layer MEL2 can not be formed in the second wiring hole ILH2. A reflow process or an electroplating process can be used to form the second metal layer MEL2.

[0124] The second metal layer MEL2 may be formed of a metal material different from that of the first metal layer MEL1, or may include a metal material different from that of the first metal layer MEL1. The second metal layer MEL2 may be formed of a metal material having a relatively large eMFP (e.g., copper (Cu)), or may include such a metal material. As a result of the etching process WE described above, the volume of the second metal layer MEL2 filling the first via hole ILH1 may be maximized. The second metal layer MEL2 filling the first via hole ILH1 having a relatively large width may have a low resistivity property.

[0125] Referring Figure 17 , a planarization process (e.g., a CMP process) may be performed until the top surface of the third interlayer insulating layer 130 is exposed to the outside. Accordingly, the barrier metal pattern BAP, the first metal pattern MEP1, and the second metal pattern MEP2 may be formed of the barrier layer BAL, the first metal layer MEL1, and the second metal layer MEL2, respectively.

[0126] During the planarization process, the first metal pattern MEP1 may be recessed more than the second metal pattern MEP2. After the planarization process, the highest level height of the top surface of the first metal pattern MEP1 may be located at the second level height LV2. The highest level height of the top surface of the second metal pattern MEP2 may be located at the third level height LV3. The third level height LV3 may be higher than the second level height LV2. The third level height LV3 may be lower than the first level height LV1 of the top surface of the third interlayer insulating layer 130.

[0127] Referring Figure 18 , an etching process may be performed to selectively recess the barrier metal pattern BAP. Due to the selective recess of the barrier metal pattern BAP, a recessed region RS may be formed between the third interlayer insulating layer 130 and the first metal pattern MEP1.

[0128] Referring Figure 19 , a metal capping pattern CAP may be selectively formed on the top surfaces of the first metal pattern MEP1 and the second metal pattern MEP2. The metal capping pattern CAP may be formed using a selective atomic layer deposition process or a selective chemical vapor deposition process. The metal capping pattern CAP may be formed of at least one of ruthenium (Ru), cobalt (Co), and graphene, or may include at least one of them.

[0129] Figure 20 is a magnified cross-sectional view of a lower interconnect line according to some example embodiments of the inventive concept and specifically shows Figure 2D portions M and N. For simplicity of description, the elements previously described with reference to Figure 3 may be identified by the same reference numerals without repeating their repeated description.

[0130] Referring to Figure 20 , the first metal pattern MEP1 of the first lower interconnect line LIL1 may have a third thickness T3. The third thickness T3 may be greater than half of the second thickness T2 of the first metal pattern MEP1 of the second lower interconnect line LIL2. According to some example embodiments, the first metal pattern MEP1 of the first lower interconnect line LIL1 may be formed by omitting the etching process WE described with reference to Figure 15 .

[0131] In some example embodiments, the first metal pattern MEP1 of the first lower interconnect line LIL1 may have a curved top surface. In the first lower interconnect line LIL1, the volume of the first metal pattern MEP1 may be greater than the volume of the second metal pattern MEP2.

[0132] Figure 21 is a cross-sectional view of a lower interconnect line according to some example embodiments of the inventive concept. Referring to Figure 21 , in addition to the first lower interconnect line LIL1 and the second lower interconnect line LIL2, the lower interconnect line may further include a third lower interconnect line LIL3. The line width of the third lower interconnect line LIL3 may be a third width W3. The third width W3 may be greater than the first width W1 of the first lower interconnect line LIL1. In other words, according to some example embodiments of the inventive concept, the lower interconnect lines of the semiconductor device may have various line widths.

[0133] The volume ratio of the second metal pattern MEP2 in the third lower interconnect line LIL3 may be greater than the volume ratio of the second metal pattern MEP2 in the first lower interconnect line LIL1. Here, the volume ratio may be the ratio of the volume of the second metal pattern to the total volume of the lower interconnect line.

[0134] According to some example embodiments of the inventive concept, if the line width of the lower interconnect line increases, the volume ratio of the metal material having a large eMFP value and disposed in the lower interconnect line may increase. Accordingly, even if the line width of the lower interconnect line increases, the lower interconnect line may have a low resistance.

[0135] Figure 22 is a cross-sectional view of a first lower interconnect line according to some example embodiments of the inventive concept. Referring to Figure 22 , the first lower interconnect line LIL1 may include a line portion HEP and a via portion VEP. The via portion VEP of the first lower interconnect line LIL1 according to some example embodiments may correspond to the lower via VI according to Figure 2C . For example, the first lower interconnect line LIL1 according to some example embodiments may include an interconnect line and a via plug formed by a dual damascene process and constituting a single conductive structure.

[0136] The via portion VEP may be disposed below the lower portion LP of the on-wire portion HEP. The via portion VEP may include a barrier metal pattern BAP and a first metal pattern MEP1. The thickness of the via portion VEP in the first direction D1 may be a fourth thickness T4. The fourth thickness T4 may be greater than the first thickness T1. For example, the fourth thickness T4 may be less than or equal to 12 nm. Since the via portion VEP is formed of a metal material having a relatively low eMFP, the resistance of the via portion VEP may be reduced.

[0137] Figures 23A to 23D are cross-sections taken along lines A-A', B-B', C-C', and D-D', respectively, to show a semiconductor device according to some example embodiments of the inventive concept. For simplicity of description, elements previously described with reference to Figure 1 and Figure 1 and Figures 2A to 2D may be identified by the same reference numerals without repeating their repeated description.

[0138] Referring to Figure 1 and Figures 23A to 23D , a substrate 100 including a first active region PR and a second active region NR may be provided. A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 in an upper portion of the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be defined on the first active region PR and the second active region NR, respectively.

[0139] The first active pattern AP1 may include a first channel pattern CH1 vertically stacked on the substrate 100. The stacked first channel patterns CH1 may be spaced apart from each other in a third direction D3. When viewed in a plan view, the stacked first channel patterns CH1 may overlap each other. The second active pattern AP2 may include a second channel pattern CH2 vertically stacked on the substrate 100. The stacked second channel patterns CH2 may be spaced apart from each other in the third direction D3. When viewed in a plan view, the stacked second channel patterns CH2 may overlap each other. The first channel pattern CH1 and the second channel pattern CH2 may be formed of at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), or include at least one of them.

[0140] The first active pattern AP1 may further include a first source / drain pattern SD1. The stacked first channel patterns CH1 may be interposed between each adjacent pair of first source / drain patterns SD1. The stacked first channel patterns CH1 may connect each adjacent pair of first source / drain patterns SD1 to each other.

[0141] The second active pattern AP2 may further include a second source / drain pattern SD2. The stacked second channel pattern CH2 may be interposed between each pair of adjacent second source / drain patterns SD2. The stacked second channel pattern CH2 may connect each pair of adjacent second source / drain patterns SD2 to each other.

[0142] The gate electrode GE may be configured to extend in a first direction D1 and cross the first channel pattern CH1 and the second channel pattern CH2. When viewed in a plan view, the gate electrode GE may be superimposed on the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS may be disposed on two side surfaces of the gate electrode GE. A gate capping pattern GP may be disposed on the gate electrode GE.

[0143] The gate electrode GE may be configured to surround each of the first channel pattern CH1 and the second channel pattern CH2 (e.g., see Figure 23D ). The gate electrode GE may be disposed on a first top surface TS1, at least one first side surface SW1, and a first bottom surface BS1 of the first channel pattern CH1. The gate electrode GE may be disposed on a second top surface TS2, at least one second side surface SW2, and a second bottom surface BS2 of the second channel pattern CH2. In other words, the gate electrode GE may surround the top surface, the bottom surface, and two side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2. The transistor according to some example embodiments may be a three-dimensional field effect transistor (e.g., a multi-bridge-channel field effect transistor (MBCFET)), in which the gate electrode GE is configured to surround the channel patterns CH1 and CH2 three-dimensionally.

[0144] A gate dielectric pattern GI may be disposed between each of the first channel pattern CH1 and the second channel pattern CH2 and the gate electrode GE. The gate dielectric pattern GI may surround each of the first channel pattern CH1 and the second channel pattern CH2.

[0145] On the second active region NR, an insulating pattern IP may be interposed between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE may be spaced apart from the second source / drain pattern SD2 through the gate dielectric pattern GI and the insulating pattern IP. In contrast, on the first active region PR, the insulating pattern IP may be omitted.

[0146] The first interlayer insulating layer 110 and the second interlayer insulating layer 120 may be provided to cover the substrate 100. The active contact AC may be provided to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and may be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The gate contact GC may be provided to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP, and may be connected to the gate electrode GE.

[0147] The third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130. The first metal layer M1 may be provided in the third interlayer insulating layer 130. The second metal layer M2 may be provided in the fourth interlayer insulating layer 140. The first metal layer M1 and the second metal layer M2 may be the same as or substantially the same as the first metal layer M1 and the second metal layer M2 in the previous exemplary embodiments described with reference Figure 1 and Figures 2A to 2D to.

[0148] In a semiconductor device according to some exemplary embodiments of the inventive concept, considering the non-linearity of the line width and resistivity of the interconnect lines, a metal material for the interconnect lines may be selected to optimize or reduce the resistivity characteristics of the interconnect lines. The interconnect lines having a small line width and pitch may be formed such that their top surfaces are lower than the top surface of the interlayer insulating layer. Accordingly, a short-circuit problem that may occur when vias are formed in an offset manner may be reduced or prevented. Accordingly, the electrical characteristics of the semiconductor device may be improved.

[0149] Although exemplary embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a transistor located on a substrate; a first interlayer insulating layer located on the transistor; a first lower interconnect line and a second lower interconnect line located in an upper portion of the first interlayer insulating layer; and a first via hole and a second via hole respectively located on the first lower interconnect line and the second lower interconnect line, wherein a line width of the first lower interconnect line is greater than a line width of the second lower interconnect line, each of the first lower interconnect line and the second lower interconnect line includes a first metal pattern, the first lower interconnect line further includes a second metal pattern, the second metal pattern is located on the first metal pattern and includes a metal material different from the metal material of the first metal pattern, the second metal pattern does not exist in the second lower interconnect line, the second via hole includes a first portion and a second portion, the first portion is in contact with a top surface of the first interlayer insulating layer, the second portion is in contact with a top surface of the second lower interconnect line, and a lowest horizontal height of a bottom surface of the second portion is lower than a lowest horizontal height of a bottom surface of the first via hole, a highest horizontal height of a top surface of the second lower interconnect line is lower than a highest horizontal height of a top surface of the first lower interconnect line.

2. The semiconductor device according to claim 1, wherein, The first metal pattern includes a metal material having an electron mean free path less than 12 nm, and the second metal pattern includes a metal material having an electron mean free path greater than 12 nm.

3. The semiconductor device according to claim 2, wherein, The first metal pattern includes ruthenium (Ru), cobalt (Co), tungsten (W), or molybdenum (Mo), and the second metal pattern includes copper (Cu).

4. The semiconductor device according to claim 1, wherein, The second metal pattern has a maximum volume in the first lower interconnect line, and the first metal pattern has a maximum volume in the second lower interconnect line.

5. The semiconductor device according to claim 1, wherein, An upper portion of the first metal pattern of the first lower interconnect line has a first thickness in a horizontal direction, the first metal pattern of the second lower interconnect line has a second thickness in the horizontal direction, and the second thickness is greater than twice the first thickness.

6. The semiconductor device according to claim 1, wherein, The first metal pattern of the first lower interconnect line includes a lower portion and a pair of upper portions vertically extending from the lower portion, and the second metal pattern of the first lower interconnect line is in a space surrounded by the lower portion and the pair of upper portions.

7. The semiconductor device according to claim 1, wherein, Each of the first lower interconnect line and the second lower interconnect line further includes a barrier metal pattern located between the first interlayer insulating layer and the first metal pattern, and an upper portion of the barrier metal pattern is recessed to define a recessed area between the first interlayer insulating layer and the first metal pattern.

8. The semiconductor device according to claim 1, wherein, The first lower interconnect line further includes a metal capping pattern, the metal capping pattern covers a top surface of the first metal pattern and a top surface of the second metal pattern, and the metal capping pattern includes ruthenium (Ru), cobalt (Co), or graphene.

9. The semiconductor device according to claim 1, further comprising: a second interlayer insulating layer located on the first interlayer insulating layer; and an upper interconnect line located in the second interlayer insulating layer, Each of the upper interconnect lines includes a line portion extending in a horizontal direction and a via portion located below the line portion. The upper interconnect lines include a first upper interconnect line and a second upper interconnect line. The via portion of the first upper interconnect line constitutes the first via, and The via portion of the second upper interconnect line constitutes the second via.

10. The semiconductor device according to claim 1, wherein, The transistor includes gate electrodes arranged at a first pitch. The second lower interconnect line is arranged at a second pitch, and The second pitch is smaller than the first pitch.

11. The semiconductor device according to claim 1, wherein, The first lower interconnect line includes a via portion as the lower portion of the first lower interconnect line, and The second metal pattern does not exist in the via portion.

12. A semiconductor device, comprising: A transistor located on a substrate; A first interlayer insulating layer located on the transistor; And A first lower interconnect line and a second lower interconnect line located in an upper portion of the first interlayer insulating layer, Wherein, the line width of the first lower interconnect line is greater than the line width of the second lower interconnect line. Each of the first lower interconnect line and the second lower interconnect line includes a first metal pattern, and the first metal patterns of each of the first lower interconnect line and the second lower interconnect line have the same height. The first lower interconnect line further includes a second metal pattern, the second metal pattern is located on the first metal pattern and includes a metal material different from the metal material of the first metal pattern, and the first metal pattern of the first lower interconnect line has a U shape. The second metal pattern has the largest volume in the first lower interconnect line. The first metal pattern has the largest volume in the second lower interconnect line. The highest horizontal height of the top surface of the second lower interconnect line is lower than the highest horizontal height of the top surface of the first lower interconnect line, and The top surface of the second metal pattern of the first lower interconnect line is higher than the top surface of the first metal pattern of the first lower interconnect line.

13. The semiconductor device according to claim 12, wherein, The second metal pattern does not exist in the second lower interconnect line.

14. The semiconductor device according to claim 12, further comprising a third lower interconnect line located in an upper portion of the first interlayer insulating layer. Among them, The line width of the third lower interconnect line is greater than the line width of the first lower interconnect line. The third lower interconnect line includes the first metal pattern and the second metal pattern, and The volume ratio of the second metal pattern in the third lower interconnect line is greater than the volume ratio of the second metal pattern in the first lower interconnect line.

15. The semiconductor device according to claim 12, wherein, The first metal pattern includes a metal material with an electron mean free path less than 12 nm, and The second metal pattern includes a metal material with an electron mean free path greater than 12 nm.

16. The semiconductor device according to claim 12, wherein, The upper portion of the first metal pattern of the first lower interconnect line has a first thickness in the horizontal direction. The first metal pattern of the second lower interconnect line has a second thickness in the horizontal direction, and The second thickness is greater than twice the first thickness.

17. The semiconductor device according to claim 12, further comprising: A second interlayer insulating layer located on the first interlayer insulating layer; And A first upper interconnect line and a second upper interconnect line in the second interlayer insulating layer. Each of the first upper interconnecting line and the second upper interconnecting line includes a line portion extending in a horizontal direction and a via portion located below the line portion. The via portion of the first upper interconnecting line contacts the top surface of the first lower interconnecting line. The via portion of the second upper interconnecting line contacts the top surface of the second lower interconnecting line, and The lowest horizontal height of the bottom surface of the via portion of the second upper interconnecting line is lower than the lowest horizontal height of the bottom surface of the via portion of the first upper interconnecting line.

18. A semiconductor device, comprising: A substrate including an active region; A device isolation layer located on the active region to define an active pattern, the device isolation layer covering a lower portion of a side surface of each of the active patterns, and an upper portion of each of the active patterns protruding above the device isolation layer; A pair of source / drain patterns located in an upper portion of each of the active patterns; A channel pattern located between the pair of source / drain patterns; A gate electrode intersecting the channel pattern and extending in a first direction; Gate spacers located on both sides of the gate electrode and extending in the first direction together with the gate electrode; A gate dielectric pattern located between the gate electrode and the channel pattern and between the gate electrode and the gate spacers; A gate capping pattern located on the top surface of the gate electrode and extending in the first direction together with the gate electrode; A first interlayer insulating layer located on the gate capping pattern; An active contact passing through the first interlayer insulating layer and electrically connected to at least one of the source / drain patterns; A first metal layer located in a second interlayer insulating layer on the first interlayer insulating layer; And A second metal layer located in a third interlayer insulating layer on the second interlayer insulating layer, Wherein the first metal layer includes a first lower interconnecting line and a second lower interconnecting line, the first lower interconnecting line and the second lower interconnecting line extend in a second direction intersecting the first direction, and at least one of the first lower interconnecting line and the second lower interconnecting line is electrically connected to the active contact, The second metal layer includes a first upper interconnecting line and a second upper interconnecting line, the first upper interconnecting line and the second upper interconnecting line are electrically connected to the first lower interconnecting line and the second lower interconnecting line through a first via and a second via respectively, The line width of the first lower interconnecting line is greater than the line width of the second lower interconnecting line, Each of the first lower interconnecting line and the second lower interconnecting line includes a first metal pattern, The first lower interconnecting line further includes a second metal pattern, the second metal pattern is disposed on the first metal pattern and includes a metal material different from the metal material of the first metal pattern, The second metal pattern does not exist in the second lower interconnecting line, The second via includes a first portion and a second portion, the first portion contacts the top surface of the second interlayer insulating layer, the second portion contacts the top surface of the second lower interconnecting line, and The lowest horizontal height of the bottom surface of the second portion is lower than the lowest horizontal height of the bottom surface of the first via. The highest horizontal height of the top surface of the second lower interconnecting line is lower than the highest horizontal height of the top surface of the first lower interconnecting line.

19. The semiconductor device according to claim 18, wherein, The first metal pattern includes a metal material having an electron mean free path of less than 12 nm, and The second metal pattern includes a metal material having an electron mean free path of greater than 12 nm.

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