Method for controlling gate formation of semiconductor device and system for manufacturing semiconductor device

Abstract

A method for controlling gate formation of a semiconductor device includes: obtaining a correlation between a gate critical dimension (CD) and an etching scheme for forming a gate trench; measuring the gate CD on a target wafer; determining an etching scheme based on the corrected and measured gate CD; and performing an etching process on the target wafer to form a gate trench using the determined etching scheme. Embodiments of the present application also relate to a system for manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to a method of controlling gate formation of a semiconductor device and a system for manufacturing the semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] As design rules shrink and process windows (i.e., margins for error in processing) become smaller, inspection and measurement of critical dimensions (CD) of device components and their cross-sectional shapes ("profiles") become increasingly important. Deviations of critical dimensions and profiles of components from the designed dimensions may adversely affect the performance of the finished semiconductor device. In addition, measurements of critical dimensions and profiles of components may indicate processing problems. Therefore, critical dimension and profile values, especially gate CD and gate profile and their variations from the designed dimensions, are important indicators of the accuracy and stability of the manufacturing process. For example, the drive current of a transistor is sensitive to gate CD and gate profile. Therefore, controlling the stability of gate formation contributes to the improvement of overall chip performance.

[0004] Although equipment is available to measure gate CD and profile, such equipment does not typically provide immediate feedback to the photolithography step to reduce variations, and the results of routine inspections are typically not used to adjust subsequent etch processes. In addition, due to process variations, gate CD and profile may be affected by factors unknown to the designer, making it difficult to have a universal setting for process control. Therefore, a simple and cost-effective system and method is needed for gate formation control without significantly reducing yield. Summary of the invention

[0005] Some embodiments of the present application provide a method for controlling gate formation of a semiconductor device, comprising: obtaining a correlation between a gate critical dimension (CD) and an etching scheme for forming a gate trench; measuring the gate critical dimension on a target wafer; determining the etching scheme based on the corrected and measured gate critical dimension; and performing an etching process on the target wafer to form a gate trench using the determined etching scheme.

[0006] Other embodiments of the present application provide a method for controlling gate formation of a semiconductor device, comprising: measuring the gate length of a dummy gate stack on a target wafer; selecting an etching scheme based on the measured gate length; etching the dummy gate stack using the etching scheme to form a gate trench; and forming a metal gate stack in the gate trench.

[0007] Still other embodiments of the present application provide a system for manufacturing a semiconductor device, comprising: a gate forming tool configured to form a gate structure; a device dimension measurement tool configured to measure a gate critical dimension (CD) of the gate structure; and a determination unit configured to read the gate critical dimension from the device dimension measurement tool and provide one of a series of etching schemes based on the gate critical dimension to the gate forming tool for use in a gate etching process implemented by the gate forming tool. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components can be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B and Fig. 6A A perspective view illustrating an intermediate stage in forming a semiconductor structure in accordance with some embodiments.

[0010] Figure 6B , Figure 8 , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B A cross-sectional view of a semiconductor structure is shown in accordance with some embodiments.

[0011] Figure 7 Gate profiles measured at different regions of a semiconductor structure are shown in accordance with some embodiments.

[0012] Fig.12 Gate profiles of semiconductor structures as a function of various etching schemes are shown in accordance with some embodiments.

[0013] Fig.13 A flow chart of a method for forming a semiconductor structure according to aspects of the present invention is shown.

[0014] Fig.14 A gate formation control system and its workflow according to aspects of the present invention are shown.

[0015] Fig.15 A schematic diagram showing intra-wafer non-uniformity across a wafer in accordance with aspects of the present invention.

[0016] Fig.16A and Fig. 16B A method of improving within-wafer uniformity according to aspects of the present invention is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, when "about," "approximately," etc. are used to describe a value or a range of values, the term is intended to cover values ​​within + / - 10% of the value, unless otherwise stated. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0019] The present invention generally relates to semiconductor devices and manufacturing methods. More specifically, the present invention relates to a gate profile description method and a gate manufacturing technology that provides better control of gate critical dimensions (CD) and correspondingly better yields. In forming a field effect transistor (FET), the gate CD affects many operating parameters of the integrated circuit, such as the speed performance and power consumption of the circuit. Generally, a larger gate CD provides stronger control in the drive current of the FET, and thus can better control the transistor performance. On the other hand, a larger gate CD reduces the distance between the gate stack and the source / drain (S / D) metal contact, which may cause device-level metal shorts and affect the yield. The target gate CD is determined based on a balance between device performance and yield. During semiconductor device manufacturing, it is also important to achieve the target gate CD and maintain the target gate CD uniformity between different IC chips and wafers. Manufacturing variations may cause gate CD wafer-to-wafer (WTW) non-uniformity and wafer-in-wafer (WIW) non-uniformity. This may lead to circuit defects and reduced chip yield. Therefore, a gate CD measurement method is needed to provide accurate gate CD and gate profile descriptions, as well as a gate manufacturing technology that provides gate profile WIW and WTW uniformity.

[0020] According to various exemplary embodiments, transistors formed using a replacement gate (or "gate last") process and methods of forming the same are provided. According to some embodiments, intermediate stages of forming a transistor are shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, similar reference numerals are used to indicate similar elements. In the exemplary embodiments shown, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concepts of the present invention. Full-all-around gate (GAA) transistors or planar transistors may also employ embodiments of the present invention.

[0021] Figures 1 to 6B and Figures 8 to 11B Perspective and cross-sectional views are shown of intermediate stages in the formation of a FinFET according to some embodiments of the present invention. Figures 1 to 6B and Figures 8 to 11B The steps shown are also schematically reflected in Fig.13 In the process flow 200 shown.

[0022] Figure 11 shows a perspective view of the initial structure. The initial structure includes a wafer 10, which also includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. An isolation region 22 (such as a shallow trench isolation (STI) region) may be formed to extend from the top surface of the substrate 20 into the substrate 20. The portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. According to some exemplary embodiments, the top surface of the semiconductor strip 24 and the top surface of the STI region 22 may be substantially flush with each other. According to some embodiments of the present invention, the semiconductor strip 24 is a portion of the original substrate 20, and thus the material of the semiconductor strip 24 is the same as the material of the substrate 20. According to an optional embodiment of the present invention, the semiconductor strip 24 is a replacement strip formed by etching a portion of the substrate 20 between the STI regions 22 to form a groove, and performing epitaxy to grow another semiconductor material in the groove. Therefore, the semiconductor strip 24 is formed of a semiconductor material different from the substrate 20. According to some exemplary embodiments, semiconductor strips 24 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0023] STI regions 22 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The pad oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 22 may also include a dielectric material over the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0024] refer to Figure 2 , the STI region 22 is recessed so that the top of the semiconductor strip 24 protrudes higher than the top surface 22A of the remaining portion of the STI region 22 to form a protruding fin 24'. The corresponding steps are shown as Fig.13 Step 202 in the process flow 200 shown. Etching can be performed using a dry etching process, wherein HF3 and NH3 are used as etching gases. According to an alternative embodiment of the present invention, recessing of the STI region 22 is performed using a wet etching process. The etching chemistry may include, for example, HF solution.

[0025] In the exemplary embodiments shown above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0026] The material of the protruding fin 24' may also be replaced with a material different from that of the substrate 20. For example, the protruding fin 24' may be formed of Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.

[0027] refer to Figure 3 , a dummy gate stack 30 is formed on the top surface and sidewalls of the protruding fin 24'. The corresponding steps are shown as Fig.13 Step 204 in the process flow 200 shown. The dummy gate stack 30 may include a dummy gate dielectric layer 32 and a dummy gate electrode layer 34 above the dummy gate dielectric layer 32. The dummy gate dielectric layer 32 is formed above the protruding fin 24'. The dummy gate dielectric layer 32 may be formed by thermal oxidation, CVD, sputtering, or any other method known in the art and used to form a dummy gate dielectric layer. In some embodiments, the dummy gate dielectric layer may be made of one or more suitable dielectric materials, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), low-k dielectrics (such as carbon-doped oxides), extremely low-k dielectrics (such as porous carbon-doped silicon dioxide), polymers (such as polyimide), etc., or combinations thereof. In other embodiments, the dummy gate dielectric layer includes a dielectric material having a high dielectric constant (k value), for example, greater than 3.9. The material may include metal oxides such as HfO2, HfZrO x 、HfSiO x 、HfTiO x 、HfAlO x, TiN, etc. or a combination thereof. In the illustrated embodiment, the pseudo gate dielectric layer 32 is an oxide layer, such as silicon oxide. The pseudo gate electrode layer 34 can be formed, for example, using polysilicon, and other materials can also be used. The pseudo gate electrode layer 34 can be deposited by PVD, CVD, sputtering deposition or other techniques known in the art and used to deposit conductive materials. Each of the pseudo gate stacks 30 can also include one (or more) hard mask layers 36 above the pseudo gate electrode layer 34. The hard mask layer 36 can be formed of silicon nitride, silicon oxide, silicon carbonitride or a multilayer thereof. The pseudo gate stack 30 can span a single or multiple protruding fins 24' and / or STI regions 22. The pseudo gate stack 30 also has a length direction perpendicular to the length direction of the protruding fin 24'. The overall height of the pseudo gate stack 30 is the distance from the top surface of the pseudo gate stack 30 to the top surface 22A of the remaining portion of the STI region 22, represented as H1. The overall height of the protruding fin 24 ′ is the distance from the top surface of the protruding fin 24 ′ to the top surface 22A of the remaining portion of the STI region 22 , denoted as H2 .

[0028] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present invention, the gate spacer 38 is formed of a dielectric material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, etc., and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

[0029] According to some embodiments of the present invention, an etching step (referred to as source / drain recessing) is performed to etch the portions of the protruding fins 24' not covered by the dummy gate stack 30 and the gate spacers 38, thereby obtaining Figure 4 The structure shown. The recess may be anisotropic, and thus the portion of the fin 24' directly below the dummy gate stack 30 and the gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 may be lower than the top surface 22A of the STI region 22. Recesses 40 are correspondingly formed between the STI regions 22. The recesses 40 are located on opposite sides of the dummy gate stack 30.

[0030] Next, an epitaxial region (source / drain region) 42 is formed by selectively growing a semiconductor material in the groove 40 to obtain Figure 5A The corresponding steps are shown as Fig.13Step 206 in the process flow 200 shown. According to some exemplary embodiments, the epitaxial region 42 includes silicon germanium, silicon or silicon carbon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an optional embodiment of the present invention, the epitaxial region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the epitaxial region 42 completely fills the recess 40, the epitaxial region 42 begins to expand horizontally, and facets can be formed.

[0031] After the epitaxy step, the epitaxy region 42 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated by reference numeral 42. According to an optional embodiment of the present invention, when the epitaxy region 42 is in-situ doped with p-type or n-type impurities during epitaxy to form source / drain regions, the implantation step is skipped. The epitaxy source / drain region 42 includes a lower portion formed in the STI region 22 and an upper portion formed above the top surface of the STI region 22.

[0032] Figure 5B 4 shows the formation of cladding source / drain regions 42 according to alternative embodiments of the present invention. According to these embodiments, Figure 3 The protruding fin 24' shown is not recessed, and an epitaxial region 41 is grown on the protruding fin 24'. The material of the epitaxial region 41 may be similar to Figure 5A The material of the epitaxial semiconductor material 42 shown depends on whether the resulting FinFET is a p-type or n-type FinFET. Thus, the source / drain 42 includes the protruding fin 24' and the epitaxial region 41. Implantation may (or may not) be performed to implant n-type impurities or p-type impurities.

[0033] Fig. 6A FIG. 4 is a perspective view of the structure after forming a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48. The corresponding steps are shown as follows: Fig.13Step 208 in the process flow 200 shown. CESL 46 can be formed of silicon nitride, silicon carbonitride, etc. For example, CESL 46 can be formed using a conformal deposition method such as ALD or CVD. ILD 48 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 48 can also be formed of an oxygen-containing dielectric material, which can be based on silicon oxide, such as tetraethyl orthosilicate (TEOS) oxide, plasma enhanced CVD (PECVD) oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization step such as chemical mechanical polishing (CMP) or mechanical grinding is performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacer 38 flush with each other.

[0034] Figure 6B It is shown in Fig. 6A A cross-sectional view of the structure shown. Fig. 6A The cross-section is obtained from the horizontal plane containing the AA line. Figure 6B , one of the dummy gate stacks 30 is shown. The gate length (measured along a direction perpendicular to the length direction of the gate stack; i.e., along Figure 6B The X direction in the dummy gate stack 30 is denoted as the gate critical dimension (CD). Due to process reasons such as etching effects in the formation of the dummy gate stack 30, the portion where the dummy gate stack 30 intersects with the protruding fin 24' may be wider than other portions away from the protruding fin 24'. The widening in the portion where the dummy gate stack 30 intersects with the protruding fin 24' is called a "footing effect", and the widened portion is called a footing region (or portion), as marked by portion 30'. Therefore, the gate CD measured at different portions of the dummy gate stack 30 may have different values. Figure 6B The gate CD measured at three different regions of the dummy gate stack 30 are shown, denoted as CD1-CD4. CD1 is measured at the region between two adjacent protruding fins 24', which is referred to as the "intra-fin" region. Figure 6B From the top view shown, the "in-fin" region generally has a necking profile between the two footing portions 30'. The gate CD measured at the "in-fin" region (i.e., CD1) can show the smallest gate CD value. On the other hand, CD2 is measured at the region on the other side of the protruding fin 24' away from the "in-fin" region, which is called the "out-of-fin" region. CD3 and CD4 are measured respectively close to the two edges (sidewalls) of the protruding fin 24', which are called the "on-fin" region. The term "close to" refers to a distance less than about 2nm or directly on the edge of the protruding fin.

[0035] In addition, in the Z direction, the dummy gate stack 30 may include an upper portion having straight and vertical sidewalls and a lower portion having inclined sidewalls. The inclined sidewalls may also be straight, or may be substantially straight with a slight curvature. The gate spacer 38 may follow the profile of the sidewalls of the dummy gate stack 30 and therefore have an inclined bottom. By measuring the gate CD at different heights of the dummy gate stack 30, the gate profile of the dummy gate stack 30 may be obtained. In various embodiments, the gate CD may be measured by prior art metrology, such as cross-sectional scanning electron microscopy (SEM), transmission electron microscopy (TEM), critical dimension scanning electron microscopy (CD-SEM). Others such as optical critical dimension (OCD), atomic force metrology (AFM), and critical dimension-atomic force metrology (CD-AFM) may also be used to measure the gate CD.

[0036] Figure 7 A graph showing exemplary gate profiles measured at different regions of a gate stack. Figure 7 The graph in is common to both dummy gate stacks and replacement gate stacks (e.g., high-k metal gate stacks). The X-axis of the graph represents the gate CD value. The Y-axis of the graph represents the height of the gate stack relative to the top surface of the STI region. The overall height of the gate stack (H1) and the overall height of the protruding fin (H2) are also marked on the Y-axis for reference. Specifically, in the figure, line 80 represents the gate CD measured in the "in-fin" area of ​​the gate stack (e.g., CD1 in Figure 6), line 82 represents the gate CD measured in the "out-fin" area of ​​the gate stack (e.g., CD2 in Figure 6), and line 84 represents the weighted value of the two gate CDs measured in the "on-fin" area of ​​the gate stack (e.g., CD3 and CD4 in Figure 6). CD3 and CD4 are measured respectively close to the two edges (sidewalls) of the same protruding fin. In the illustrated embodiment, the weighted value is to select the larger value between the two gate CDs (e.g., the maximum value of CD3, CD4). In some embodiments, the weighted value is an average of the two gate CDs (eg, (CD3+CD4) / 2). In some other embodiments, the weighted value is any one of the two gate CDs (eg, any one of CD3 or CD4).

[0037] Still reference Figure 7, for the portion of the gate stack above the fin top of the protruding fin (>H2), the gate profiles represented by lines 80, 82, and 84 are close to each other. This is mainly because the pedestal region is usually present at the intersection of the gate stack and the protruding fin and does not extend into the region above the fin top of the protruding fin. Therefore, the gate CD measured in the "in-fin", "on-fin", and "out-of-fin" regions has substantially the same value above the fin top of the protruding fin. As a comparison, when the gate height is below the fin top of the protruding fin (<H2), the gate profile represented by line 84 always shows a larger gate CD value than the other gate profiles at a given gate height. In some embodiments, the difference is greater than about 8 nm and can be in the range between about 8 nm and about 12 nm. This is mainly due to the widening of the pedestal region of the gate stack. Generally, after-develop inspection (ADI) checks the gate CD at the "in-fin" region, which usually shows the smallest gate CD value at the necking region between two adjacent pedestal portions. However, as IC technology advances towards smaller technology nodes (e.g., 20 nm, 16 nm, 10 nm, 7 nm and below), as the gate size decreases, the transistor performance affected by the additional gate CD at the pedestal portion is no longer negligible. As Figure 7 shown, the gate CD measured in the "in-fin" or "out-of-fin" region does not capture the current drive introduced by the pedestal portion and becomes less precise in terms of transistor description. Instead, the gate CD measured in the "on-fin" region can more accurately represent the gate length for describing transistor performance.

[0038] After forming the corresponding structures as Fig. 6A and Figure 6B shown, next, the dummy gate stack 30 is replaced with a replacement gate stack including a metal gate layer and a replacement gate dielectric layer. According to some embodiments of the present invention, the replacement includes etching the dummy gate stack 30 in one or more etching steps, which includes the hard mask layer 36, the dummy gate electrode layer 34, and the dummy gate dielectric layer 32, so as to form an opening (also referred to as a gate trench) between opposite portions of the gate spacer 38. The corresponding step is shown as Fig.13 step 210 in the process flow 200 shown.

[0039] In some embodiments, removing the dummy gate stack 30 includes two or more etching steps, each targeting a specific material composition in the dummy gate stack 30. For example, the first etching step can have a high etching selectivity adjusted to the dummy gate electrode layer 34, while substantially no (or minimal) etching loss occurs to the gate spacer 38 and the dummy gate dielectric layer 32. According to some embodiments of the present invention, the first etching step can be an anisotropic etching process using a process gas selected from, but not limited to, Cl2, BCl3, Ar, CH4, CF4, and combinations thereof. The etching can be performed at a pressure in a range between about 3mTorr and about 10mTorr. RF power is applied in the main etching, and the RF power can be in a range between about 500 watts and about 900 watts. A bias voltage of less than about 150 watts can also be applied. During the removal of the gate electrode layer 34, a native oxide layer 35 can be formed on the exposed surface of the gate spacer 38. The native oxide layer 35 can have a thickness in a range from about 1 nm to about 3 nm. The resulting structure after the first etching step is Figure 8 Shown in.

[0040] The second etching step can be adjusted to have a high etching selectivity to the dummy gate dielectric layer 32 (e.g., oxide layer) and the native oxide layer 35, while substantially no (or minimal) etching loss occurs to the gate spacer 38 and the protruding fin 24'. According to some embodiments of the present invention, the second etching step can be a dry etching process, a wet etching process, or other suitable etching process. In some embodiments, the second etching step uses a chemical solution, which can be diluted HF. The etching can be performed at a temperature in a range between about 20°C and about 30°C, and the etching time can be in a range between about 30 seconds and about 60 seconds. The weight ratio of water to HF in the diluted HF is greater than about 1500:1, and can be in a range between about 1500:1 and about 2500:1. The etching intensity can be adjusted by adjusting the etching process scheme, such as parameters in the second etching step, including etchant concentration, etchant flow rate, etching temperature, etching duration, or different etchants. Because the dummy gate dielectric layer 32 in the corners of the footing region 30' is relatively difficult to reach by the etchant, by selecting a less severe etching scheme, remnants of the dummy gate dielectric layer 32 may remain in the corners of the footing region 30'. The remnants of the dummy gate dielectric layer 32 produce different gate trench openings at the "on-fin" region. Fig. 9A , Fig. 10A , Fig.11A Three exemplary resulting structures are shown after relatively strong, mild, and relatively weak etching schemes, respectively. Fig. 9B , Fig. 10B , Fig. 11B Shown in Fig. 9A , Fig. 10A , Fig.11AThree exemplary resulting structures after depositing a high-k metal gate stack 60 (also referred to as a replacement gate stack 60) in the corresponding gate trench 52 in FIG. The corresponding steps are shown as Fig.13 Step 212 of the process flow 200 is shown. Subsequently, the process flow 200 may proceed to step 214 to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines, and multi-layer interconnect components (e.g., metal layers and interlayer dielectrics) are configured to connect various components to form functional circuits.

[0041] Still reference Fig. 9B , Fig. 10B , Fig. 11B , the high-k metal gate stack 60 includes a high-k dielectric layer 54 and a conductive layer 56. The high-k metal gate stack 60 may further include an interface layer (not shown) between the high-k dielectric layer 54 and the protruding fin 24'. The interface layer may be formed using chemical oxidation, thermal oxidation, ALD, CVD and / or other suitable methods. The high-k dielectric layer 54 may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials), such as hafnium silicon oxide (HfSiO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3) or a combination thereof. The high-k dielectric layer 54 may be deposited using CVD, ALD and / or other suitable methods. The conductive layer 56 includes one or more metal layers, such as a work function metal layer, a conductive barrier layer and a metal filling layer. The work function metal layer can be a p-type or n-type work function layer, depending on the type of device (PFET or NFET). The p-type work function layer includes a metal with a sufficiently large effective work function, selected from but not limited to the group of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt) or a combination thereof. The n-type work function layer includes a metal with a sufficiently low effective work function, selected from but not limited to the group of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN) or a combination thereof. The metal fill layer may include aluminum (Al), tungsten (W), cobalt (Co) and / or other suitable materials. The conductive layer 56 may be deposited using methods such as CVD, PVD, plating and / or other suitable processes.

[0042] like FIG. 9A to FIG. 11B As shown in the comparison of the three exemplary structures in , by measuring the gate CD at the “on-fin” region, it is possible to fine-tune the gate CD by controlling the etching of the dummy gate dielectric layer 32 in the footing region 30 ′. Fig. 9A and Fig. 9BIn the embodiment, by completely removing the dummy gate dielectric layer 32, the replacement gate CD in different regions (e.g., the "inside fin" region or the "outside fin" region) is substantially equal to the dummy gate CD in the corresponding region. In some embodiments, due to the etching loss of the gate spacer 38 during the over-etching, the replacement gate CD can even be larger than the dummy gate CD (e.g., about 1 nm to about 2 nm). Fig. 10A and Fig. 10B In FIG. 5 , with a mild etch regime, some remnants of the dummy gate dielectric layer 32 are difficult to remove from the corner spaces and remain in the footing region 30 ′, resulting in a reduction in the replacement gate CD at the “on-fin” region. However, gate CD measurements at other regions (such as the “in-fin” and “out-of-fin” regions) will not capture the reduction in replacement gate CD because the removal of the native oxide layer 35 from the open spaces is not sensitive to etch strength. Fig.11A and Fig. 11B In FIG. 5 , with a relatively weak etching scheme, a large portion of the dummy gate dielectric layer 32 remains in the footing region 30 ′, resulting in a further reduction in the replacement gate CD at the “on-fin” region. Similarly, because the native oxide layer 35 is substantially removed outside of the footing region 30 ′, the gate CD measurements at the “in-fin” and “out-of-fin” regions will not capture this reduction in replacement gate CD.

[0043] The relationship between the replacement gate CD and different etching schemes is given by Fig.12 The gate outline shown is shown. Specifically, Fig.12 An exemplary graph of gate profiles measured at the “on-fin” region with three different etching schemes for removing the dummy gate stack is shown. The gate CD is based on the weighted values ​​of the two gate CDs at the “on-fin” region (e.g., Fig. 9B , Fig. 10B , Fig. 11B In the embodiment shown, the weighted value is the larger value between the two gate CDs (e.g., the maximum value of CD3 and CD4). In some embodiments, the weighted value is the average value of the two gate CDs (e.g., (CD3+CD4) / 2). In some other embodiments, the weighted value is any one of the two gate CDs (e.g., any one of CD3 or CD4). Fig.12In [the figure], when the gate height is above the fin top of the protruding fin 24' (>H2), the gate profiles represented by lines 86, 87, and 88 are close to each other. This is mainly because the pedestal region usually exists at the intersection of the dummy gate stack and the protruding fin and does not extend into the portion above the fin top of the protruding fin 24'. Therefore, the dummy gate dielectric layer 32 and the native oxide layer 35 are substantially removed by three etching schemes. As a comparison, when the gate height is below the fin top of the protruding fin 24' (<H2), the gate profile represented by line 86 formed by a relatively strong etching scheme shows a larger gate CD than the gate profiles formed by other etching schemes, because the dummy gate dielectric layer 32 is substantially removed from the pedestal region 30'. The gate profile represented by line 86 is also closest to Figure 7 the dummy gate profile represented by line 84 in [the figure]. Compared with line 86, the gate profile represented by line 87 formed by a mild etching scheme shows a reduced gate CD, because some residues of the dummy gate dielectric layer 32 remain in the pedestal region 30'. Compared with lines 86 and 87, the gate profile represented by line 88 formed by a relatively weak etching scheme shows the smallest gate CD, because most of the dummy gate dielectric layer 32 remains in the pedestal region 30'.

[0044] With joint reference to Figure 7 and Fig.12 , it has been found that there is a correlation between the "on-fin" gate CD measurement and a series of replacement gate CDs, depending on the etching scheme used for gate trench formation. It should be noted that in the example shown in Fig.12 , the schemes mainly vary in the dummy gate dielectric layer removal stage. However, the schemes including the removal of the dummy gate electrode layer and the dummy gate dielectric layer can also be used for the correlation. In addition, the correlation is shown in the form of a graph in Figure 7 and Fig.12 . The correlation can also be represented in other forms, such as a look-up table and an equation. The correlation can be pre-measured and derived using a set of sample devices. The correlation can include multiple gate profiles and multiple series of replacement gate profiles, where each series of replacement gate profiles corresponds to a specific dummy gate profile. In production, based on the "on-fin" gate CD measurement at a specific gate height on the target wafer, the gate profile having the "on-fin" gate CD at the specific gate height can be identified (e.g., line 84 in Figure 7 ), and a series of corresponding replacement gate profiles can be retrieved (e.g., lines 86, 87, 88 in Fig.12 ). Subsequently, the etching scheme can be selected to achieve the desired gate CD or correct the originally deviated gate CD.

[0045] Fig.14A gate formation control system 300 and its workflow are shown, which may include subsystems such as a device dimension measurement tool (e.g., post-development inspection (ADI)) 308, a determination unit 310, and a gate formation tool 301, which may further include a dummy gate formation tool 302, a dummy gate etching tool 304, and a replacement gate formation tool 306. The dummy gate formation tool 302 and the replacement gate formation tool 306 may share some equipment, such as an ALD deposition device in some embodiments. As discussed above, the gate CD can be fine-tuned by adjusting the etching scheme in the gate trench formation, during which the dummy gate electrode layer and the dummy gate dielectric layer are removed. Various parameters can be used to determine the best etching scheme. An exemplary workflow for determining the best etching scheme is as follows: first, a correlation between the "on-fin" gate CD and a series of corresponding replacement gate CDs is obtained from a sample device (or sample wafer); then, the "on-fin" gate CD is measured on a target device (or target wafer), and an etching scheme is selected based on the correlation obtained earlier.

[0046] To obtain correlation, after the dummy gate stack is patterned and formed by the dummy gate forming tool 302, it corresponds to Fig.13 At step 204 in the process flow 200 shown, the device dimension measurement tool 308 performs a post-development inspection to measure the "on-fin" gate CD of different gate heights to obtain the gate profile of the dummy gate stack. The "on-fin" gate CD can be measured by equipment such as a cross-sectional scanning electron microscope (SEM), a transmission electron microscope (TEM), or a critical dimension scanning electron microscope (CD-SEM). Other equipment such as optical critical dimension (OCD), atomic force metrology (AFM), and critical dimension-atomic force metrology (CD-AFM) can also be used to measure the "on-fin" gate CD. There is no need to perform a post-development inspection after step 204 in the process flow 200. In some embodiments, a post-development inspection can be performed after step 206 in the process flow 200 of forming the epitaxial source / drain region. In some embodiments, a post-development inspection can be performed after step 208 in the process flow 200 of depositing CESL and ILD. The gate CD measurement value is stored and processed by the determination unit 310. A similar structure to that of FIG. 8 may be generated by the determination unit 310 with one or more “on-fin” lines 84 (without necessarily having lines 80 / 82 that are not at the “on-fin” region). Figure 7 Subsequently, the dummy gate etch tool 304 etches the dummy gate stack by applying a series of etching schemes, which corresponds to Fig.13Step 210 of the process flow 200 shown. After removing the dummy gate stack, each etching scheme results in a corresponding gate trench opening. In some embodiments, there is at least one parameter difference between the series of etching schemes, such as etchant concentration, etchant flow rate, etching temperature, etching duration, and etchant type. In a specific example, the difference between the series of etching schemes is etching duration.

[0047] After forming the gate trenches, the replacement gate forming tool 306 forms a replacement gate stack in the gate trenches, which corresponds to the Fig.13 The device dimension measurement tool 308 performs another post-development inspection to measure the "on-fin" gate CD at different gate heights to obtain the gate profile of the replacement gate stack associated with the corresponding etching scheme. The gate CD measurements are stored and processed by the determination unit 310. A similar Fig.12 One or more graphs, each graph corresponding to one of the "on-fin" lines 84 stored earlier by the determination unit 310. In some embodiments, the determination unit 310 also derives an optimal solution for each gate CD value.

[0048] In order to determine the etching scheme to be applied to the target wafer, after the dummy gate stack is patterned and formed on the target wafer by the dummy gate formation tool 302, the device size measurement tool 308 performs a post-development inspection to measure one or more "on-fin" gate CDs at one or more gate heights. The determination unit 310 receives the "on-fin" gate CD from the device size measurement tool 308 and finds which "on-fin" line 84 has the gate CD value at a given gate height. Once the sample "on-fin" line 84 is determined, the corresponding correlation of the "on-fin" gate profile associated with different etching schemes is retrieved. Based on the target gate CD, the determination unit 310 determines whether a deviation from the standard gate CD has occurred, and selects an etching scheme to correct the deviation and provides it to the dummy gate etching tool 304. The standard gate CD can be a predetermined value that balances the need for greater gate drive (i.e., a larger gate CD) and the need to avoid gate source / drain metal shorts (i.e., a smaller gate CD). Subsequently, the dummy gate etching tool 304 etches the dummy gate stack with a given etching scheme to form a gate trench, and the replacement gate forming tool 306 deposits a replacement gate stack in the gate trench.

[0049] Although in the above discussion, the correlation between the "on-fin" gate CD and the etching scheme is measured and interpreted in advance, the correlation can be dynamically interpreted by the gate formation control system 300. For example, when manufacturing a first wafer with a "on-fin" gate CD of a dummy gate stack, a default etching scheme is used. After forming the replacement gate stack, the device dimension measurement tool 308 obtains the "on-fin" gate CD of the replacement gate stack. If the gate CD deviates from the predetermined value, the etching scheme will be adjusted when the second wafer is loaded for manufacturing. For example, if the measured gate CD of the replacement gate stack of the previous wafer is too large, the etching scheme will be adjusted weaker; if the measured gate CD of the replacement gate stack of the previous wafer is too small, the etching scheme will be adjusted stronger. After quickly measuring a sufficient number of wafers, the correlation between the "on-fin" gate CD and the etching scheme can be determined, and the correlation can be used for subsequent device formation. Another advantage of embodiments of the present invention is that gate profile errors caused by other factors can also be corrected by fine tuning of the etching scheme, even if the designer does not know the mechanism of these factors, provided that the effects of these factors are not random and persist from wafer to wafer.

[0050] In some embodiments, the device size measurement tool 308 may also measure the gate CD in the "in-fin" region, and the determination unit 310 also adopts the "in-fin" gate CD in its decision. This is because the gate CD usually has a minimum value in the "in-fin" region. Small gate CD increases the difficulty of filling the work function metal in the gate trench during the replacement gate process. The determination unit 310 can consider the "on-fin" gate CD together with the "in-fin" gate CD. If the "in-fin" gate CD is close to or even less than a predetermined threshold, the determination unit 310 can still pick a strong etching scheme for over-etching to ensure that the minimum gate CD remains at least at the "in-fin" region.

[0051] Wafer-to-wafer process variations can be mitigated by the previously discussed embodiments. Other variations that lead to within-wafer non-uniformity can also be mitigated. Fig.15 A schematic diagram of a wafer 400 is shown with "on-fin" gate CD having within-wafer (WIW) non-uniformity. Typically, from the center to the outer edge of the wafer 400, chips with equal distance to the center have similar gate CDs. Therefore, rings such as r1, r2, and r3 can be used to symbolize different gate CDs. For example, the chip in r1 has a larger gate CD than the chip in r2, and the chip in r2 has a larger gate CD than the chip in r3. Within-wafer non-uniformity of gate CD will result in within-wafer non-uniformity of gate profile.

[0052] Fig.16A and Fig. 16BA method for improving intra-wafer uniformity by using adjustable etchant injection is shown. The flow rate of the etchant is a parameter that affects the etch rate of the etching scheme. Because the etching gas is usually injected symmetrically into the reaction chamber, such as Fig.15 As shown, the etching rate on the wafer can also be shown as a ring structure, with each ring having a similar etching rate. The etching gas can be injected into the chamber in a center mode or an edge mode. In the center mode, as shown in FIG. Fig.16A As shown, the gas is injected into the reaction chamber primarily from a central point (preferably toward the center of the wafer). Therefore, chips close to and / or facing the center will have a higher etch rate, while other chips will have a lower etch rate. In edge mode, as Fig. 16B As shown, the gas is injected into the reaction chamber from more distributed locations away from the center. When switching from the center mode to the edge mode, the etching rate at the center of the chip decreases, and the etching rate at the edge of the chip increases.

[0053] Therefore, if the post-development inspection shows that there is intra-wafer non-uniformity in the "on-fin" gate CD, adjustable gas injection can be used. In one embodiment, depending on the difference in the "on-fin" gate CD at the center and the edge, an appropriate gas injection mode is adopted, which is any one of the center mode or the edge mode. In a further embodiment, a combination of a center mode and an edge mode can be used, in which the etching gas is injected into the chamber from the center and the distributed position at the same time. For example, if the "on-fin" gate CD at the center is larger than that at the edge, the profile at the center will have a larger footing effect than at the edge. Therefore, less center gas injection (and / or more edge gas injection) can be used to reduce the etching rate at the center. This will alleviate more gate footing effects at the center of the wafer rather than at the edge, and thus form a wafer with a more uniform gate profile. Conversely, if the "on-fin" gate CD at the center is smaller than the gate CD at the edge, more center gas injection (and / or less edge gas injection) can be used to increase the etching rate at the center.

[0054] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits to semiconductor devices and their formation. For example, embodiments of the present invention provide simple and cost-effective systems and methods for gate formation control without significantly reducing yield. In the present invention, the gate critical dimension measured near or on the edge of the fin on which the gate stack is bonded provides a more accurate representation of the gate length for describing transistor performance. In addition, the workflow of gate formation can be easily integrated into existing semiconductor manufacturing processes.

[0055] In one exemplary aspect, the present invention is directed to a method for controlling gate formation of a semiconductor device. The method includes: obtaining a correlation between a gate critical dimension (CD) and an etching scheme for forming a gate trench; measuring a gate CD on a target wafer; determining an etching scheme based on the corrected and measured gate CD; and performing an etching process on the target wafer to form a gate trench using the determined etching scheme. In some embodiments, measuring the gate CD on the target wafer includes: measuring at least one gate length at a position close to an edge of a fin. In some embodiments, measuring the gate CD on the target wafer includes: measuring a first gate length at a first position close to a first edge of the fin; measuring a second gate length at a second position close to a second edge of the fin; and calculating a weighted value of the first gate length and the second gate length as the measured gate CD. In some embodiments, the weighted value is a larger value of the first gate length and the second gate length. In some embodiments, the weighted value is an average of the first gate length and the second gate length. In some embodiments, the gate CD is measured at a position below the fin. In some embodiments, obtaining the correlation includes: forming a dummy gate stack on a wafer; measuring a gate CD of the dummy gate stack; etching the dummy gate stack with an etching scheme to form a gate trench; forming a replacement gate stack in the gate trench; and measuring a gate CD of the replacement gate stack. In some embodiments, the etching schemes differ in etching duration. In some embodiments, the gate CD is a first gate CD measured at a first position close to an edge of a first fin, and the method further includes: measuring a second gate CD at a second position between the first fin and the second fin, wherein determining the etching scheme includes comparing the second gate CD to a predetermined minimum gate CD value.

[0056] In another exemplary aspect, the present invention is directed to a method for controlling gate formation of a semiconductor device. The method comprises: measuring the gate length of a dummy gate stack on a target wafer; selecting an etching scheme based on the measured gate length; etching the dummy gate stack with the etching scheme to form a gate trench; and forming a metal gate stack in the gate trench. In some embodiments, the gate length is measured in a position of the dummy gate stack close to the sidewall of the fin joined by the dummy gate stack. In some embodiments, measuring the gate length comprises: measuring a first gate length and a second gate length in two positions of the dummy gate stack, wherein the two positions sandwich the fin joined by the dummy gate stack; and selecting a weighted value of the first gate length and the second gate length as the measured gate length. In some embodiments, the weighted value is the larger value of the first gate length and the second gate length. In some embodiments, the weighted value is the average of the first gate length and the second gate length. In some embodiments, the gate length is measured at a height of the dummy gate stack that is less than the fin joined by the dummy gate stack. In some embodiments, the etching scheme is selected from a series of etching schemes with different etching durations.

[0057] In yet another exemplary aspect, the present invention is directed to a system for manufacturing a semiconductor device. The system includes: a gate formation tool configured to form a gate structure; a device dimension measurement tool configured to measure a gate critical dimension (CD) of the gate structure; and a determination unit configured to read the gate CD from the device dimension measurement tool and provide one of a series of etching schemes based on the gate CD to the gate formation tool for a gate etching process performed by the gate formation tool. In some embodiments, the device dimension measurement tool measures the gate CD at a location on an edge of a fin joined by the gate structure. In some embodiments, the location is below the fin. In some embodiments, a correlation between a cell storage gate CD and a series of etching schemes is determined.

[0058] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand aspects of the present invention. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for controlling gate formation of a semiconductor device, comprising: Obtaining a correlation between a gate critical dimension (CD) and an etching scheme used to form a gate trench; forming a dummy gate stack on a target wafer; measuring a gate critical dimension of the dummy gate stack on the target wafer; determining an etching scheme based on the corrected and measured gate CD; as well as performing an etching process on the target wafer to form a gate trench using a determined etching scheme by partially removing the dummy gate stack, wherein a portion of the dummy gate stack remains on the target wafer after the etching process, and a size of the portion of the dummy gate stack is controlled by the determined etching scheme; and A replacement gate stack is formed in the gate trench, wherein the replacement gate stack is in physical contact with the portion of the dummy gate stack.

2. The method according to claim 1, wherein: Measuring the gate CD on the target wafer includes measuring at least one gate length of the dummy gate stack at a location proximate to an edge of a fin.

3. The method according to claim 1, wherein: Measuring the gate critical dimension on the target wafer includes: measuring a first gate length of the dummy gate stack at a first location proximate to a first edge of the fin; measuring a second gate length of the dummy gate stack at a second location proximate to a second edge of the fin; and A weighted value of the first gate length and the second gate length is calculated as the measured gate critical dimension.

4. The method according to claim 3, wherein: The weighted value is a larger value of the first gate length and the second gate length.

5. The method according to claim 3, wherein: The weighted value is an average value of the first gate length and the second gate length.

6. The method according to claim 1, wherein: The gate critical dimension is measured at a location below the fin.

7. The method according to claim 1, wherein: Obtaining the correlation includes: forming a dummy gate stack on the wafer; measuring a gate critical dimension of the dummy gate stack; etching the dummy gate stack using the etching scheme to form the gate trench; forming a replacement gate stack in the gate trench; and A gate critical dimension of the replacement gate stack is measured.

8. The method according to claim 1, wherein: The etching schemes differ in etching duration.

9. The method according to claim 1, wherein: The gate critical dimension of the dummy gate stack is a first gate critical dimension measured at a first location proximate to an edge of a first fin, further comprising: measuring a second gate critical dimension at a second location between the first fin and the second fin, Wherein, determining the etching scheme includes comparing the second gate critical dimension with a predetermined minimum gate critical dimension value.

10. A method for controlling gate formation of a semiconductor device, comprising: measuring a gate length of a dummy gate stack on a target wafer; selecting an etching scheme based on the measured gate length; etching the dummy gate stack by partially removing the dummy gate stack using the etching scheme to form a gate trench, wherein after etching the dummy gate stack, a portion of the dummy gate stack remains on the target wafer, and a size of the portion of the dummy gate stack is controlled by the etching scheme; as well as A metal gate stack is formed in the gate trench, wherein the metal gate stack is in physical contact with the portion of the dummy gate stack.

11. The method according to claim 10, wherein: The gate length is measured in a location of the dummy gate stack proximate to a sidewall of a fin joined by the dummy gate stack.

12. The method according to claim 10, wherein: Measuring the gate length includes: measuring a first gate length and a second gate length in two locations of the dummy gate stack, wherein the two locations sandwich a fin joined by the dummy gate stack; and A weighted value of the first gate length and the second gate length is selected as the measured gate length.

13. The method according to claim 12, wherein: The weighted value is a larger value of the first gate length and the second gate length.

14. The method according to claim 13, wherein: The weighted value is an average value of the first gate length and the second gate length.

15. The method according to claim 10, wherein: The gate length is measured at a height of the dummy gate stack that is less than a height of a fin joined by the dummy gate stack.

16. The method according to claim 10, wherein: The etching scheme is selected from a series of etching schemes having different etching durations.

17. A system for manufacturing a semiconductor device, comprising: a gate formation tool configured to form a sacrificial gate structure and a replacement gate structure; a device dimension measurement tool configured to measure a gate critical dimension (CD) of the sacrificial gate structure; as well as a determining unit configured to read the gate critical dimension from the device dimension measurement tool and provide one of a series of etching schemes based on the gate critical dimension to the gate forming tool for a gate etching process performed by the gate forming tool, wherein the gate etching process is configured to partially remove the sacrificial gate structure to form a gate trench, and the gate trench is used to fill the replacement gate structure in the gate trench, wherein, after the gate etching process, a portion of the sacrificial gate structure is still exposed in the gate trench, and the filled replacement gate structure is in physical contact with the portion of the sacrificial gate structure.

18. The system of claim 17, wherein: The device dimension measurement tool measures the gate critical dimension at a location on an edge of a fin joined by the sacrificial gate structure.

19. The system of claim 18, wherein: The position is below the fin.

20. The system of claim 17, wherein: The determining unit stores a correlation between the gate CD and the series of etching schemes.

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