A semiconductor package including stacked semiconductor chips

Abstract

A semiconductor package including stacked semiconductor chips. A semiconductor package includes: a substrate having a first substrate pad formed at one side edge thereof along a first direction and a second substrate pad formed at the other side edge thereof along the first direction; a sub-semiconductor package formed on the substrate, the sub-semiconductor package including a sub-semiconductor chip, a sub-molding layer, and a redistribution conductive layer, the sub-molding layer surrounding the side surfaces of the sub-semiconductor chip, the redistribution conductive layer extending onto the sub-molding layer in a state of being connected to a sub-chip pad of the sub-semiconductor chip and connected to a first redistribution pad and a second redistribution pad respectively formed at one side edge and the other side edge of the sub-molding layer along the first direction; a first chip stack formed on the sub-semiconductor package, the first chip stack including a first main semiconductor chip; and a second chip stack formed on the first chip stack, the second chip stack including a second main semiconductor chip.

Description

Technical Field

[0001] This patent document relates to a semiconductor package, and more particularly, to a semiconductor package in which a plurality of chips are stacked on a substrate. Background Art

[0002] Electronic products are increasingly required to process a large amount of data even when their volume is reduced. Therefore, there is an increasing need to improve the integration degree of semiconductor devices used in such electronic products.

[0003] However, due to the limitations of semiconductor integration technology, it is difficult to meet the required functions with only a single semiconductor chip, and thus, a semiconductor package in which a plurality of semiconductor chips are embedded in one semiconductor package is manufactured.

[0004] Even if a semiconductor package includes a plurality of semiconductor chips, it is necessary to manufacture the semiconductor package to have a specified size according to the requirements of the application using the semiconductor package. Summary of the Invention

[0005] In one embodiment, a semiconductor package may include: a substrate having a first substrate pad formed at one side edge thereof along a first direction and a second substrate pad formed at the other side edge thereof along the first direction; a sub-semiconductor package formed on the substrate, the sub-semiconductor package including a sub-semiconductor chip, a sub-molding layer, and a redistribution conductive layer, the sub-molding layer surrounding the side surface of the sub-semiconductor chip, the redistribution conductive layer extending onto the sub-molding layer in a state of being connected to a sub-chip pad of the sub-semiconductor chip and connected to a first redistribution pad and a second redistribution pad respectively formed at one side edge and the other side edge of the sub-molding layer along the first direction; a first chip stack formed on the sub-semiconductor package, the first chip stack including one or more first main semiconductor chips; and a second chip stack formed on the first chip stack, the second chip stack including one or more second main semiconductor chips, wherein the sub-semiconductor chip is connected to the substrate through a first sub-package interconnector connecting the first redistribution pad and the first substrate pad and a second sub-package interconnector connecting the second redistribution pad and the second substrate pad, wherein the first chip stack is connected to the substrate through a first interconnector connecting a first chip pad of one or more first main semiconductor chips and the first substrate pad, and wherein the second chip stack is connected to the substrate through a second interconnector connecting a second chip pad of one or more second main semiconductor chips and the second substrate pad.

[0006] In one embodiment, a semiconductor package may include: a substrate having a first substrate pad formed at one side edge thereof along a first direction and a second substrate pad formed at the other side edge thereof along the first direction; a sub-semiconductor package formed on the substrate, the sub-semiconductor package including a sub-semiconductor chip, a sub-molding layer, and a redistribution conductive layer, the sub-molding layer surrounding the side surfaces of the sub-semiconductor chip, the redistribution conductive layer extending onto the sub-molding layer in a state of being connected to a sub-chip pad of the sub-semiconductor chip and connected to a first redistribution pad and a second redistribution pad respectively formed at one side edge and the other side edge of the sub-molding layer along the first direction; and a chip stack formed on the sub-semiconductor package, the chip stack including one or more main semiconductor chips, wherein the sub-chip pad includes a first sub-chip pad and a third sub-chip pad respectively disposed at two side edges of the sub-semiconductor chip along the first direction, and a second sub-chip pad and a fourth sub-chip pad respectively disposed at two side edges of the sub-semiconductor chip along a second direction perpendicular to the first direction, wherein the redistribution conductive layer connected to the first sub-chip pad and the second sub-chip pad extends to the first redistribution pad, and wherein the redistribution conductive layer connected to the third sub-chip pad and the fourth sub-chip pad extends to the second redistribution pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view showing a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 2 is a view showing Figure 1 a plan view of a part of the semiconductor package shown, in which the first chip stack, the second chip stack, and the interconnectors connected to the first chip stack and the second chip stack are omitted.

[0009] Figure 3 is a view showing Figure 1 a cross-sectional view of the semiconductor package shown.

[0010] Figure 4 is a plan view showing a semiconductor package according to another embodiment of the present disclosure.

[0011] Figure 5 is a view showing Figure 4 a plan view of a part of the semiconductor package shown, in which the first chip stack, the second chip stack, and the interconnectors connected to the first chip stack and the second chip stack are omitted.

[0012] Figures 6 to 9 is a view showing Figure 4 a cross-sectional view of the semiconductor package shown.

[0013] Figure 10Shows a block diagram of an electronic system showing a memory card employing a semiconductor package according to one embodiment.

[0014] Figure 11 Shows a block diagram of another electronic system including a semiconductor package according to one embodiment. Detailed Description

[0015] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0016] The drawings are not necessarily drawn to scale. In some cases, the scale of at least some of the structures in the drawings may be exaggerated in order to clearly show certain features of the described embodiments. When a specific example of a multi-layer structure having two or more layers is presented in the drawings or description, the relative positional relationship or the order of arranging these layers shown reflects a specific implementation of the described or shown example, and there may be different relative positional relationships or orders of arranging these layers. In addition, the example of the multi-layer structure described or shown may not reflect all the layers present in the specific multi-layer structure (for example, one or more additional layers may be present between two shown layers). As a specific example, when the first layer in the described or shown multi-layer structure is referred to as being "on" or "above" the second layer, or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but one or more other intermediate layers may be present between the first layer and the second layer or the substrate.

[0017] Various embodiments relate to a semiconductor package that can implement a semiconductor package in which a main semiconductor chip is disposed on a sub-semiconductor chip and can ensure operating characteristics.

[0018] Figure 1 Is a plan view showing a semiconductor package according to an embodiment of the present disclosure. Figure 2 Is showing Figure 1 A plan view of a part of the semiconductor package shown, in which the first chip stack, the second chip stack, and the interconnects connecting the first chip stack and the second chip stack are omitted. Figure 3 Is showing Figure 1 A cross-sectional view of the semiconductor package shown. Figure 1 And Figure 2 Are respectively a top view of the semiconductor package according to the present embodiment and a part thereof. Figure 3 Shows along through Figure 1 The cross-section taken along the lines of reference numerals 102-1C, 118B-1, 118B-2, and 102-2C.

[0019] Refer to Figures 1 to 3, the semiconductor package may include a substrate 100, a sub-semiconductor package 110 disposed on the substrate 100, and a first chip stack 120 and a second chip stack 130 disposed on the sub-semiconductor package 110.

[0020] The substrate 100 may be a substrate for a semiconductor package such as a printed circuit board (PCB), which has a circuit and / or wiring structure for transmitting electrical signals.

[0021] The substrate 100 may have a top surface and a bottom surface. The sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 may be disposed on the top surface. The bottom surface faces away from the top surface, and external connection terminals 140 for connecting the semiconductor package to the outside may be disposed on the bottom surface. For reference, the top surface and the bottom surface described below are expressions for indicating the relative positions of the respective surfaces of the components, and do not indicate absolute positions. For example, in the case where the semiconductor package is turned upside down different from the illustration, the surface on which the sub-semiconductor package 110 and the first chip stack 120 and the second chip stack 130 are disposed may be the bottom surface of the substrate 100, and the surface on which the external connection terminals 140 are disposed may be the top surface of the substrate 100.

[0022] The substrate 100 may include a top surface substrate pad 102 and a bottom surface substrate pad 104. The top surface substrate pad 102 may be disposed on the top surface of the substrate 100 to electrically connect the sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 to the substrate 100. The bottom surface substrate pad 104 may be disposed on the bottom surface of the substrate 100 to electrically connect the external connection terminals 140 to the substrate 100. For reference, the substrate pad may refer to a conductive element or terminal exposed on the surface of the substrate 100 to electrically connect the substrate 100 to other components. For example, the top surface substrate pad 102 may be a bonding finger for wire bonding, and the bottom surface substrate pad 104 may be a ball land for bonding with solder balls. The top surface substrate pad 102 and the bottom surface substrate pad 104 may be connected to the circuit and / or wiring structure inside the substrate 100.

[0023] The top surface substrate pad 102 may be disposed on both side edges of the substrate 100 that do not overlap with the sub-semiconductor package 110, for example, both side edges of the substrate 100 along a first direction. The top surface substrate pad 102 disposed on one side edge of the substrate 100 along the first direction may be referred to as a first top surface substrate pad 102-1, and the top surface substrate pad 102 disposed on the other side edge of the substrate 100 along the first direction may be referred to as a second top surface substrate pad 102-2. For reference, one side along the first direction described below may correspond to Figure 1 and Figure 2 the upper side in Figure 3on the left side in, and the other side along the first direction to be described below may correspond to Figure 1 and Figure 2 the lower side in, and may correspond to Figure 3 the right side in. In the present embodiment, a plurality of first top surface substrate pads 102-1 and a plurality of second top surface substrate pads 102-2 may be arranged in a row along a second direction intersecting the first direction, respectively. However, it should be noted that the present disclosure is not limited thereto, and the number and arrangement, etc. of the first top surface substrate pads 102-1 and the second top surface substrate pads 102-2 located on both side edges of the substrate 100 may be variously changed.

[0024] Some of the plurality of first top surface substrate pads 102-1 (see reference numeral 102-1A) may be connected to the sub-semiconductor chip 114 to be described later, and will be hereinafter referred to as the first sub-pad 102-1A. Some other of the plurality of first top surface substrate pads 102-1 (see reference numeral 102-1B) may be connected to the first main semiconductor chip 124 to be described later, and will be hereinafter referred to as the first main pad 102-1B. Other of the plurality of first top surface substrate pads 102-1 (see reference numeral 102-1C) may be commonly connected to the sub-semiconductor chip 114 and the first main semiconductor chip 124, and will be hereinafter referred to as the first common pad 102-1C.

[0025] Some of the plurality of second top surface substrate pads 102-2 (see reference numeral 102-2A) may be connected to the sub-semiconductor chip 114, and will be hereinafter referred to as the second sub-pad 102-2A. Some other of the plurality of second top surface substrate pads 102-2 (see reference numeral 102-2B) may be connected to the second main semiconductor chip 134 to be described later, and will be hereinafter referred to as the second main pad 102-2B. Other of the plurality of second top surface substrate pads 102-2 (see reference numeral 102-2C) may be commonly connected to the sub-semiconductor chip 114 and the second main semiconductor chip 134, and will be hereinafter referred to as the second common pad 102-2C.

[0026] The sub-semiconductor package 110 may have a planar area smaller than the top surface of the substrate 100. The sub-semiconductor package 110 may be arranged to at least expose both side edges of the substrate 100 along the first direction and / or the top surface substrate pads 102. For example, the sub-semiconductor package 110 may be arranged on the central portion of the substrate 100.

[0027] The sub-semiconductor package 110 may include a sub-semiconductor chip 114, a sub-molding layer 116 surrounding the side surfaces of the sub-semiconductor chip 114, and a redistribution structure 118 formed on the top surfaces of the sub-semiconductor chip 114 and the sub-molding layer 116. A sub-package adhesive layer 112 for attaching the sub-semiconductor package 110 to the substrate 100 may be formed on the bottom surface of the sub-semiconductor package 110.

[0028] The sub-semiconductor chip 114 may be various semiconductor chips that perform functions required for the operation of the first main semiconductor chip 124 and / or the second main semiconductor chip 134. For example, in the case where each of the first main semiconductor chip 124 and the second main semiconductor chip 134 includes a non-volatile memory (e.g., NAND flash memory), the sub-semiconductor chip 114 may include a controller for controlling the first main semiconductor chip 124 and the second main semiconductor chip 134. However, it should be noted that the present disclosure is not limited thereto, and the sub-semiconductor chip 114 may include a volatile memory (e.g., dynamic random access memory (DRAM) and static random access memory (SRAM)), a non-volatile memory (e.g., NAND flash, resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM)), or other various active or passive components.

[0029] The sub-semiconductor chip 114 may have a bottom surface facing the top surface of the substrate 100, a top surface facing away from the bottom surface, and side surfaces connecting the top surface and the bottom surface. In the present embodiment, the sub-semiconductor chip 114 may have four side surfaces, and these four side surfaces will be referred to as the first side surface to the fourth side surfaces S1, S2, S3, S4. The first side surface S1 and the third side surface S3 may be located on one side and the other side along the first direction, respectively, and the second side surface S2 and the fourth side surface S4 may be located on one side and the other side along a second direction substantially perpendicular to the first direction, respectively. As a reference, one side along the second direction to be described later may correspond to Figure 1 and Figure 2 the right side in Figure 1 and Figure 2 the left side in

[0030] Such a sub-semiconductor chip 114 may be located in the central portion of the sub-semiconductor package 110. This is to make the lengths of the first redistribution conductive layer 118B-1 and the second redistribution conductive layer 118B-2 to be described later as similar to each other as possible.

[0031] The sub-chip pad 115 may be disposed on the top surface of the sub-semiconductor chip 114. The sub-semiconductor chip 114 may have a relatively small planar area, while the number of sub-chip pads 115 may be relatively large. For example, it may be assumed that the sub-semiconductor chip 114 is a memory controller and the first main semiconductor chip 124 and the second main semiconductor chip 134 are memories. In this case, although the size of the sub-semiconductor chip 114 decreases as technology develops, in order to connect each of the first chip stack 120 and the second chip stack 130 and the sub-semiconductor chip 114 through independent channels, the number of sub-chip pads 115 corresponding to the number of input / output signals may be required. Accordingly, the sub-chip pads 115 may be arranged along the entire edge of the sub-semiconductor chip 114. That is, the sub-chip pads 115 may be arranged adjacent to the first to fourth side surfaces S1, S2, S3, and S4 of the sub-semiconductor chip 114 along the first to fourth side surfaces S1, S2, S3, and S4.

[0032] The sub-molding layer 116 may have a top surface having a height substantially the same as the height of the top surface of the sub-semiconductor chip 114 while surrounding the side surfaces of the sub-semiconductor chip 114, thereby exposing the top surface of the sub-semiconductor chip 114 and the sub-chip pads 115. In the present embodiment, the sub-molding layer 116 may have a bottom surface having a height substantially the same as the height of the bottom surface of the sub-semiconductor chip 114. However, it should be noted that the present disclosure is not limited thereto, and the sub-molding layer 116 may cover the bottom surface of the sub-semiconductor chip 114. The sub-molding layer 116 may include various molding materials, such as an epoxy molding compound (EMC).

[0033] The sub-package adhesive layer 112 for attaching the sub-semiconductor package 110 to the substrate 100 may include an insulating adhesive material, such as a die attach film (DAF). The sub-package adhesive layer 112 may be omitted.

[0034] The redistribution structure 118 may extend onto the top surface of the sub-molding layer 116 while being electrically connected to the sub-chip pads 115. In other words, the sub-semiconductor package 110 according to the present embodiment may be a fan-out package.

[0035] Specifically, the redistribution structure 118 may include a first redistribution insulating layer 118A, a redistribution conductive layer 118B, and a second redistribution insulating layer 118C. The first redistribution insulating layer 118A may be formed on the top surfaces of the sub-semiconductor chip 114 and the sub-molding layer 116. The first redistribution insulating layer 118A may have an opening exposing the sub-chip pad 115. The redistribution conductive layer 118B may be formed on the first redistribution insulating layer 118A. The redistribution conductive layer 118B may be electrically connected to the sub-chip pad 115 through the opening of the first redistribution insulating layer 118A. The second redistribution insulating layer 118C may cover the first redistribution insulating layer 118A and the redistribution conductive layer 118B. The second redistribution insulating layer 118C may have an opening exposing an end portion of the redistribution conductive layer 118B. The first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include an insulating material such as an oxide, a nitride, or an oxynitride. Alternatively, the first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include a resin material such as an epoxy resin, a polyimide, a polybenzoxazole (PBO), a benzocyclobutene (BCB), a silicone resin, or an acrylate. The redistribution conductive layer 118B may include a metal material such as gold, copper, or a copper alloy.

[0036] Specifically, a portion of the redistribution conductive layer 118B exposed by the opening of the second redistribution insulating layer 118C will hereinafter be referred to as the redistribution pad 118BP. In Figure 1 and Figure 2 In a top view, for ease of explanation, the first redistribution insulating layer 118A and the second redistribution insulating layer 118C of the redistribution structure 118 are not shown. Similar to the arrangement of the top surface substrate pads 102, the redistribution pads 118BP may be provided on both side edges of the sub-molding layer 116 along a first direction. The redistribution pad 118BP provided on one side edge of the sub-molding layer 116 along the first direction may be referred to as the first redistribution pad 118BP-1, and the redistribution pad 118BP provided on the other side edge of the sub-molding layer 116 along the first direction may be referred to as the second redistribution pad 118BP-2. The first redistribution pad 118BP-1 may be relatively adjacent to the first top surface substrate pad 102-1, and the second redistribution pad 118BP-2 may be relatively adjacent to the second top surface substrate pad 102-2. In the present embodiment, the first redistribution pads 118BP-1 may be arranged in a row along a second direction. In addition, the second redistribution pads 118BP-2 may be arranged in a row along the second direction. However, it should be noted that the present disclosure is not limited thereto, and various changes may be made to the number and arrangement, etc. of the first redistribution pads 118BP-1 and the second redistribution pads 118BP-2 located on both side edges of the sub-molding layer 116.

[0037] According to the above arrangement of the redistribution pads 118BP, the redistribution conductive layer 118B can extend from the sub-chip pads 115 arranged along the first side surface S1 and the second side surface S2 of the sub-semiconductor chip 114 to the first redistribution pad 118BP-1, and can extend from the sub-chip pads 115 arranged along the third side surface S3 and the fourth side surface S4 of the sub-semiconductor chip 114 to the second redistribution pad 118BP-2. The redistribution conductive layer 118B extending to the first redistribution pad 118BP-1 can be referred to as the first redistribution conductive layer 118B-1, and the redistribution conductive layer 118B extending to the second redistribution pad 118BP-2 can be referred to as the second redistribution conductive layer 118B-2. The first redistribution conductive layer 118B-1 extending from the second side surface S2 of the sub-semiconductor chip 114 can have a shape bent toward the first redistribution pad 118BP-1 to be connected to the first redistribution pad 118BP-1. Since the first redistribution conductive layer 118B-1 extending from the first side surface S1 of the sub-semiconductor chip 114 faces the first redistribution pad 118BP-1, they do not need to be bent to be connected to the first redistribution pad 118BP-1. However, in order to have a similar length to the first redistribution conductive layer 118B-1 extending from the second side surface S2 of the sub-semiconductor chip 114, the first redistribution conductive layer 118B-1 extending from the first side surface S1 of the sub-semiconductor chip 114 can also have a bent shape. In addition, the second redistribution conductive layer 118B-2 extending from the fourth side surface S4 of the sub-semiconductor chip 114 can have a shape bent toward the second redistribution pad 118BP-2. In order to have a similar length to the second redistribution conductive layer 118B-2 extending from the fourth side surface S4 of the sub-semiconductor chip 114, the second redistribution conductive layer 118B-2 extending from the third side surface S3 of the sub-semiconductor chip 114 can also have a bent shape. As a result, the redistribution conductive layer 118B can have a shape similar to a tornado, for example, a spiral shape centered on the sub-semiconductor chip 114. Through this connection scheme, the lengths of the redistribution conductive layers 118B can be similar to each other.

[0038] The sub-package interconnector 117 can include: a first sub-package interconnector 117-1 that connects the first redistribution pad 118BP-1 and the first top surface substrate pad 102-1; and a second sub-package interconnector 117-2 that connects the second redistribution pad 118BP-2 and the second top surface substrate pad 102-2. Thus, the sub-semiconductor chip 114 and the substrate 100 can be electrically connected. The sub-package interconnector 117 can be a bonding lead, one end of which is connected to the top surface substrate pad 102, and the other end of which is connected to the redistribution pad 118BP. However, it should be noted that the embodiments are not limited thereto, and various types of electrical interconnectors can be used as the sub-package interconnector 117.

[0039] The first chip stack 120 may include a plurality of first main semiconductor chips 124, which are formed on the sub-semiconductor package 110 and stacked in a vertical direction with respect to the top surface of the substrate 100. Although the present embodiment shows a case where the first chip stack 120 includes four first main semiconductor chips 124, it should be noted that the present disclosure is not limited thereto, and the number of first main semiconductor chips 124 included in the first chip stack 120 may vary variously among one or more first main semiconductor chips.

[0040] Each first main semiconductor chip 124 may include a NAND flash memory as described above. However, it should be noted that the present disclosure is not limited thereto, and a volatile memory (e.g., dynamic random access memory (DRAM) and static RAM (SRAM)) or a non-volatile memory (e.g., resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM)) may be included in each first main semiconductor chip 124.

[0041] The first main semiconductor chips 124 may be stacked with a predetermined offset in a direction on the other side along the first direction (e.g., a direction along the lower side in Figure 1 and the right side in Figure 3 ). Thus, the first chip stack 120 having a stepped shape when viewed as a whole may be formed. The offset stacking direction of the first main semiconductor chips 124 may be referred to as the first offset direction. According to this offset stacking, one side edge (e.g., Figure 1 the upper side edge in Figure 3 and Figure 1As shown in the top view, a part of the first chip stack 120 is shown, for example, a side edge portion of the lowermost first main semiconductor chip 124.

[0042] Each first main semiconductor chip 124 can be attached to the sub-semiconductor package 110 directly below it or the first main semiconductor chip 124 through the first adhesive layer 122. The first adhesive layer 122 can be formed on the bottom surface of each first main semiconductor chip 124 and have a shape overlapping with the bottom surface.

[0043] The first chip stack 120 or the first main semiconductor chip 124 can have a planar area smaller than that of the sub-semiconductor package 110 and can have a planar area larger than that of the sub-semiconductor chip 114. The first chip stack 120 can be arranged to at least expose the redistribution pads 118BP on both side edges of the sub-semiconductor package 110 along the first direction.

[0044] The first interconnect 127 can connect the first chip pads 125 adjacent to each other in the vertical direction and can electrically connect the first chip pads 125 of the lowermost first main semiconductor chip 124 to the first top surface substrate pad 102-1. Thus, the first main semiconductor chips 124 can be electrically connected to each other, and the first chip stack 120 can be electrically connected to the substrate 100. The first interconnect 127 can be a bonding wire. However, it should be noted that the embodiments are not limited thereto, and various types of electrical interconnects can be used as the first interconnect 127. The first interconnect 127 can be commonly connected to the first common pad 102-1C with the first sub-package interconnect 117-1, or can be independently connected to the first main pad 102-1B that is not connected to the first sub-package interconnect 117-1.

[0045] The second chip stack 130 can include a plurality of second main semiconductor chips 134 formed on the first chip stack 120 and stacked in the vertical direction. Although this embodiment shows the case where the second chip stack 130 includes four second main semiconductor chips 134, it should be noted that the present disclosure is not limited thereto, and the number of second main semiconductor chips 134 included in the second chip stack 130 can be variously changed to be at least one. In addition, although in this embodiment, the number of second main semiconductor chips 134 included in the second chip stack 130 is the same as the number of first main semiconductor chips 124 included in the first chip stack 120, it should be noted that these numbers can be different from each other.

[0046] Each second main semiconductor chip 134 may include a NAND flash memory as described above. However, it should be noted that the present disclosure is not limited thereto, and each second main semiconductor chip 134 may include a volatile memory (e.g., dynamic random access memory (DRAM) and static RAM (SRAM)), or a non-volatile memory (e.g., resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM)). In the present embodiment, the second main semiconductor chip 134 is the same semiconductor chip as the first main semiconductor chip 124, but it should be noted that the second main semiconductor chip 134 may be a semiconductor chip different from the first main semiconductor chip 124.

[0047] The second main semiconductor chips 134 may be stacked with a predetermined offset in a direction along one side in the first direction (e.g., in a direction along the upper side in Figure 1 and the left side in Figure 3 ). Thus, a second chip stack 130 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the second main semiconductor chips 134 may be referred to as the second offset direction. The second offset direction may be opposite to the first offset direction. According to this offset stacking, the other side edge of the top surface of each of the remaining second main semiconductor chips 134 except the topmost second main semiconductor chip 134 in the second main semiconductor chips 134 (e.g., Figure 1 the lower side edge in Figure 3 and the right side edge in

[0048] can be exposed and not covered by the second main semiconductor chip 134 directly located thereon. The topmost second main semiconductor chip 134 may be in a state where its entire top surface is exposed. The second chip pads 135 may be provided on the exposed portions of the remaining second main semiconductor chips 134 except the topmost second main semiconductor chip 134, and the second chip pads 135 of the topmost second main semiconductor chip 134 may also be provided at the same positions as the second chip pads 135 of the remaining second main semiconductor chips 134. The plurality of second chip pads 135 may be arranged in a row in the second direction at the other side edge of the top surface of each second main semiconductor chip 134. However, it should be noted that the present disclosure is not limited thereto, and the number and arrangement of the second chip pads 135 located at the other side edge of the top surface of each second main semiconductor chip 134 may be variously changed.

[0049] Each second main semiconductor chip 134 may be attached to a second main semiconductor chip 134 directly thereunder or the uppermost first main semiconductor chip 124 of the first chip stack 120 through a second adhesive layer 132. The second adhesive layer 132 may be formed on the bottom surface of each second main semiconductor chip 134 and have a shape overlapping with the bottom surface.

[0050] The second chip stack 130 or the second main semiconductor chip 134 may have a planar area smaller than that of the sub-semiconductor package 110 and may have a planar area larger than that of the sub-semiconductor chip 114. The second chip stack 130 may be arranged to expose at least both side edges (i.e., the redistribution pads 118BP) of the sub-semiconductor package 110 along the first direction.

[0051] The second interconnector 137 may connect the second chip pads 135 adjacent to each other in the vertical direction and may electrically connect the second chip pads 135 of the lowermost second main semiconductor chip 134 to the second top surface substrate pads 102-2. Thus, the second main semiconductor chips 134 may be electrically connected to each other, and the second chip stack 130 may be electrically connected to the substrate 100. The second interconnector 137 may be a bonding wire. However, it should be noted that the embodiments are not limited thereto, and various types of electrical interconnectors may be used as the second interconnector 137. The second interconnector 137 may be commonly connected to the second common pad 102-2C with the second sub-package interconnector 117-2, or may be independently connected to the second main pad 102-2B not connected to the second sub-package interconnector 117-2.

[0052] In Figure 1 and Figure 2 In the top view, for the convenience of distinction, the sub-package interconnector 117, the first interconnector 127, and the second interconnector 137 are shown by solid lines and dashed lines. However, it should be noted that such solid lines and dashed lines do not of course reflect the actual shapes of the interconnectors 117, 127, and 137.

[0053] The sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 may be covered by a molding layer 150 formed on the substrate 100. The molding layer 150 may include various molding materials, such as EMC.

[0054] The above external connection terminals 140 may include solder balls. However, it should be noted that the present disclosure is not limited thereto, and various conductive terminals such as bumps may be used as the external connection terminals 140.

[0055] In the above semiconductor package, the first chip stack 120 can be recognized as a single semiconductor chip while being connected to the first top surface substrate pad 102-1 of the substrate 100 through the first interconnector 127. The circuit path from the first chip stack 120 to the substrate 100 can be referred to as the first channel. The second chip stack 130 can be recognized as another single semiconductor chip different from the first chip stack 120 while being connected to the second top surface substrate pad 102-2 of the substrate 100 through the second interconnector 137. The circuit path from the second chip stack 130 to the substrate 100 can be referred to as the second channel. The first channel and the second channel can be electrically and physically isolated from each other. The sub-semiconductor chip 114 can be connected to the first top surface substrate pad 102-1 and the second top surface substrate pad 102-2 of the substrate 100 through the redistribution structure 118 and the sub-package interconnector 117.

[0056] The first sub-pad 102-1A independently connected to the sub-semiconductor chip 114 can be a power pad (e.g., a controller power pad) of the sub-semiconductor chip 114 or a signal transmission pad (e.g., an input / output signal transmission pad) of the sub-semiconductor chip 114. The first main pad 102-1B independently connected to the first chip stack 120 can be a power pad (e.g., a memory power pad) of the first chip stack 120 or a signal transmission pad (e.g., an input / output signal transmission pad) of the first chip stack 120. In the case where the first sub-pad 102-1A is a signal transmission pad of the sub-semiconductor chip 114 and the first main pad 102-1B is a signal transmission pad of the first chip stack 120, these signal transmission pads can be connected to each other through a circuit or a wiring structure (not shown) in the substrate 100 to achieve signal transmission between the sub-semiconductor chip 114 and the first chip stack 120. The first common pad 102-1C commonly connected to the sub-semiconductor chip 114 and the first chip stack 120 can be a ground power pad.

[0057] Similarly, the second sub-pad 102-2A independently connected to the sub-semiconductor chip 114 can be a power pad (e.g., a controller power pad) of the sub-semiconductor chip 114 or a signal transmission pad of the sub-semiconductor chip 114. The second main pad 102-2B to which the second chip stack 130 is independently connected can be a power pad (e.g., a memory power pad) of the second chip stack 130 or a signal transmission pad of the second chip stack 130. In the case where the second sub-pad 102-2A is a signal transmission pad of the sub-semiconductor chip 114 and the second main pad 102-2B is a signal transmission pad of the second chip stack 130, these signal transmission pads can be connected to each other through a circuit or a wiring structure (not shown) in the substrate 100 to achieve signal transmission between the sub-semiconductor chip 114 and the second chip stack 130. The second common pad 102-2C to which the sub-semiconductor chip 114 and the second chip stack 130 are commonly connected can be a ground power pad.

[0058] According to the semiconductor package described above, the following effects can be achieved.

[0059] First, since the sub-chip pads 115 are arranged along the entire edge of the sub-semiconductor chip 114, a relatively large number of sub-chip pads 115 can be arranged compared to the size of the sub-semiconductor chip 114. In addition, by using the fan-out technology to re-distribute the sub-chip pads 115, the connection between the sub-chip pads 115 and the chip pads 125 and 135 of the main semiconductor chips 124 and 134 can be easily achieved. For example, if bonding leads are directly connected to the sub-semiconductor chip 114, the arrangement of the sub-chip pads 115 may be restricted due to physical limitations (e.g., the size and movement radius of the wire bond capillary). On the other hand, as in the present embodiment, if the sub-chip pads 115 are re-distributed by using the re-distribution pads 118BP through the fan-out technology, the design can be free from such limitations.

[0060] Furthermore, since the sub-semiconductor package 110 larger than the first main semiconductor chip 124 is arranged below the first chip stack 120 by using the fan-out technology, the first chip stack 120 can be stably formed. In the structure where the first chip stack 120 is formed on the sub-semiconductor chip 114, if the sub-semiconductor chip 114 is smaller than the first main semiconductor chip 124, a problem of tilting of the first chip stack 120 may occur. By using the fan-out technology to significantly increase the area of the sub-semiconductor chip 114, such a problem can be avoided.

[0061] In addition, by adjusting the shape and / or arrangement of each redistribution conductive layer 118B that connects the die pad 115 and the redistribution pad 118BP such that each redistribution conductive layer 118B has a similar length, the operating characteristics of the semiconductor package can be ensured. For example, in a case where a first channel connecting the first chip stack 120 to the substrate 100 is connected to the sub-semiconductor chip 114 via the substrate 100, the first sub-package interconnector 117-1, and the first redistribution conductive layer 118B-1 / first redistribution pad 118BP-1 to exchange signals with the sub-semiconductor chip 114, and a second channel connecting the second chip stack 130 to the substrate 100 is connected to the sub-semiconductor chip 114 via the substrate 100, the second sub-package interconnector 117-2, and the second redistribution conductive layer 118B-2 / second redistribution pad 118BP-2 to exchange signals with the sub-semiconductor chip 114, by adjusting the lengths of the first redistribution conductive layer 118B-1 and the second redistribution conductive layer 118B-2 to a similar level, the transmission rate of signals (such as data) can be maximally prevented from becoming different between channels.

[0062] In the above-described embodiment, the first chip stack 120 and the sub-semiconductor chip 114 are connected to each other via the substrate 100, and the second chip stack 130 and the sub-semiconductor chip 114 are also connected to each other via the substrate 100. However, in another embodiment, the first chip stack 120 and the sub-semiconductor chip 114 may be connected to each other by using an interconnector without using the substrate 100, and the second chip stack 130 and the sub-semiconductor chip 114 may be connected to each other by using an interconnector without using the substrate 100. This will be described below with reference to Figures 4 to 9 for description.

[0063] Figure 4 is a plan view showing a semiconductor package according to another embodiment of the present disclosure, Figure 5 is showing Figure 4 a plan view of a part of the semiconductor package shown, in which the first chip stack, the second chip stack, and the interconnectors connecting to the first chip stack and the second chip stack are omitted, Figures 6 to 9 is showing Figure 4 a cross-sectional view of the semiconductor package shown. Figure 4 and Figure 5 are top views of the semiconductor package and a part thereof according to the present embodiment, respectively. Figure 6 shows a cross-section taken along a line passing through Figure 4 reference numerals 202-1A, 218B-1, 218B-2, and 202-2A, Figure 7 shows a cross-section taken along a line passing through Figure 4 reference numerals 202-1B, 218B-1, 218B-2, and 202-2B,Figure 8 shows a cross-section taken along a line of reference numerals 202-1C, 218B-1, 218B-2, and 202-2C passing through Figure 4 , and Figure 9 shows a cross-section taken along a line of reference numerals 227A, 218B-1, 218B-2, and 237A passing through Figure 4 . Hereinafter, the description will mainly focus on the differences from the above-described embodiments.

[0064] Referring to Figures 4 to 9 , a semiconductor package according to another embodiment of the present disclosure may include a substrate 200, a sub-semiconductor package 210 disposed on the substrate 200, and first and second chip stacks 220 and 230 disposed on the sub-semiconductor package 210.

[0065] The substrate 200 may include top surface substrate pads 202 disposed on its top surface and bottom surface substrate pads 204 disposed on its bottom surface. Among the top surface substrate pads 202, the pads disposed on one side in the first direction may be referred to as first top surface substrate pads 202-1, and the pads disposed on the other side in the first direction may be referred to as second top surface substrate pads 202-2.

[0066] Some of the plurality of first top surface substrate pads 202-1 (see reference numeral 202-1A) may be connected only to a sub-semiconductor chip 214 to be described later, and hereinafter, will be referred to as first sub-pads 202-1A. Some other of the plurality of first top surface substrate pads 202-1 (see reference numeral 202-1B) may be connected only to a first main semiconductor chip 224 to be described later, and hereinafter will be referred to as first main pads 202-1B. Other of the plurality of first top surface substrate pads 202-1 (see reference numeral 202-1C) may be commonly connected to the sub-semiconductor chip 214 and the first main semiconductor chip 224, and hereinafter, will be referred to as first common pads 202-1C. Differently, in the above-described embodiment, the interconnector connected to the sub-semiconductor chip and the interconnector connected to the first main semiconductor chip are commonly connected to the first common pad, while in the present embodiment, the interconnector (see reference numeral 227C) connected to the first main semiconductor chip 224 is not directly connected to the first common pad 202-1C. The interconnector 227C connected to the first main semiconductor chip 224 may be electrically connected to the first common pad 202-1C through the interconnector 217-1B connected to the sub-semiconductor chip 214. That is, only the interconnector 217-1B connected to the sub-semiconductor chip 214 can be directly connected to the first common pad 202-1C.

[0067] In addition, some of the multiple second top surface substrate pads 202-2 (see reference numeral 202-2A) may be connected only to the sub-semiconductor chip 214, and hereinafter will be referred to as second sub-pads 202-2A. Some other pads of the multiple second top surface substrate pads 202-2 (see reference numeral 202-2B) may be connected only to the second main semiconductor chip 234 to be described later, and will be referred to as second main pads 202-2B hereinafter. Other pads of the multiple second top surface substrate pads 202-2 (see reference numeral 202-2C) may be commonly connected to the sub-semiconductor chip 214 and the second main semiconductor chip 234, and hereinafter will be referred to as second common pads 202-2C. Similar to the first common pad 202-1C, only the interconnector (see reference numeral 217-2B) connected to the sub-semiconductor chip 214 may be directly connected to the second common pad 202-2C. The interconnector 237C connected to the second main semiconductor chip 234 may not be directly connected to the second common pad 202-2C.

[0068] The sub-semiconductor package 210 may include: a sub-semiconductor chip 214, which includes: sub-chip pads 215 formed on the top surface of the sub-semiconductor chip 214; a sub-molding layer 216 surrounding the side surfaces of the sub-semiconductor chip 214; and a redistribution structure 218 formed on the top surfaces of the sub-semiconductor chip 214 and the sub-molding layer 216. A sub-package adhesive layer 212 for attaching the sub-semiconductor package 210 to the substrate 200 may be formed on the bottom surfaces of the sub-semiconductor chip 214 and the sub-molding layer 216.

[0069] The redistribution structure 218 may include: a first redistribution insulating layer 218A formed on the top surfaces of the sub-semiconductor chip 214 and the sub-molding layer 216 and having an opening exposing the sub-chip pad 215; a redistribution conductive layer 218B formed on the first redistribution insulating layer 218A and electrically connected to the sub-chip pad 215 through the opening of the first redistribution insulating layer 218A; and a second redistribution insulating layer 218C covering the first redistribution insulating layer 218A and the redistribution conductive layer 218B and having an opening exposing an end portion of the redistribution conductive layer 218B. The portion of the redistribution conductive layer 218B exposed by the opening of the second redistribution insulating layer 218C will hereinafter be referred to as the redistribution pad 218BP. The redistribution pad 218BP may include a first redistribution pad 218BP-1 provided at one side edge of the sub-molding layer 216 along the first direction, and a second redistribution pad 218BP-2 provided at the other side edge of the sub-molding layer 216 along the first direction. The redistribution conductive layer 218B may include a first redistribution conductive layer 218B-1 connected to the first redistribution pad 218BP-1, and a second redistribution conductive layer 218B-2 connected to the second redistribution pad 218BP-2.

[0070] The sub-package interconnector 217 may include a first sub-package interconnector 217-1 connecting the first redistribution pad 218BP-1 and the first top surface substrate pad 202-1, and a second sub-package interconnector 217-2 connecting the second redistribution pad 218BP-2 and the second top surface substrate pad 202-2. Thus, the sub-semiconductor chip 214 and the substrate 200 can be electrically connected. In addition, the first sub-package interconnector 217-1 may include a first independent sub-package interconnector 217-1A that only connects the sub-semiconductor chip 214 to the first sub-pad 202-1A, and a first common sub-package interconnector 217-1B that is also electrically connected to the first chip stack 220. One end of the first independent sub-package interconnector 217-1A may be connected to the first sub-pad 202-1A, and one end of the first common sub-package interconnector 217-1B may be connected to the first common pad 202-1C. The second sub-package interconnector 217-2 may include a second independent sub-package interconnector 217-2A that only connects the sub-semiconductor chip 214 to the second sub-pad 202-2A, and a second common sub-package interconnector 217-2B that is also electrically connected to the second chip stack 230. One end of the second independent sub-package interconnector 217-2A may be connected to the second sub-pad 202-2A, and one end of the second common sub-package interconnector 217-2B may be connected to the second common pad 202-2C.

[0071] The first chip stack 220 may have a structure in which one or more first main semiconductor chips 224 are offset-stacked along a first offset direction. Each of the first main semiconductor chips 224 may include a first chip pad 225 formed at one side edge of its top surface. Each of the first main semiconductor chips 224 may be attached to a sub-semiconductor package 210 or a first main semiconductor chip 224 directly thereunder through a first adhesive layer 222 formed on its bottom surface.

[0072] The first interconnector 227 may connect the first chip pads 225 adjacent to each other in the vertical direction, and may electrically connect the first chip pad 225 of the lowermost first main semiconductor chip 224 to the first top surface substrate pad 202-1 or the first redistribution pad 218BP-1. Accordingly, the first main semiconductor chips 224 may be electrically connected to each other, and the first chip stack 220 may be electrically connected to the substrate 200 or the sub-semiconductor chip 214. The first interconnector 227 may include: a first common interconnector 227C connected to the first redistribution pad 218BP-1 connected to the first common sub-package interconnector 217-1B; a first independent interconnector 227B connected to the first main pad 202-1B in the first top surface substrate pad 202-1; and a first signal interconnector 227A connected to the first redistribution pad 218BP-1 that is not connected to the first sub-package interconnector 217-1 among the first redistribution pads 218BP-1. The first signal interconnector 227A may connect the first chip stack 220 and the sub-semiconductor chip 214 to each other to enable signal transmission therebetween.

[0073] The second chip stack 230 may have a structure in which one or more second main semiconductor chips 234 are offset-stacked along a second offset direction. Each of the second main semiconductor chips 234 may include a second chip pad 235 formed at one side edge of its top surface. Each of the second main semiconductor chips 234 may be attached to the first chip stack 220 or a second main semiconductor chip 234 directly thereunder through a second adhesive layer 232 formed on its bottom surface.

[0074] The second interconnector 237 can connect the second chip pads 235 adjacent to each other in the vertical direction, and can electrically connect the second chip pads 235 of the lowermost second main semiconductor chip 234 to the second top surface substrate pad 202-2 or the second redistribution pad 218BP-2. Thus, the second main semiconductor chips 234 can be electrically connected to each other, and the second chip stack 230 can be electrically connected to the substrate 200 or the sub-semiconductor chip 214. The second interconnector 237 can include: a second common interconnector 237C, which is connected to the second redistribution pad 218BP-2 connected to the second common sub-package interconnector 217-2B; a second independent interconnector 237B, which is connected to the second main pad 202-2B in the second top surface substrate pad 202-2; and a second signal interconnector 237A, which is connected to the second redistribution pad 218BP-2 in the second redistribution pad 218BP-2 that is not connected to the second sub-package interconnector 217-2. The second signal interconnector 237A can connect the second chip stack 230 and the sub-semiconductor chip 214 to each other to enable signal transmission therebetween.

[0075] The sub-semiconductor package 210, the first chip stack 220, and the second chip stack 230 can be covered by a molding layer 250 formed on the substrate 200.

[0076] The external connection terminal 240 can be connected to the bottom surface substrate pad 204 of the substrate 200.

[0077] The signal transmission path and the power supply path in the semiconductor package configured as described above will be described below.

[0078] First, referring again to Figures 4 to 6 , only the sub-semiconductor chip 214 can be connected to the first sub-pad 202-1A. Specifically, the first sub-pad 202-1A and the sub-semiconductor chip 214 can be electrically connected through a path passing through the sub-chip pad 215, the first redistribution conductive layer 218B-1, and the first independent sub-package interconnector 217-1A. The first sub-pad 202-1A can be the first power supply pad or the first signal transmission pad of the sub-semiconductor chip 214. Herein, the first signal transmission may not represent signal exchange with the first chip stack 220. This is because the signal exchange between the sub-semiconductor chip 214 and the first chip stack 220 is achieved through the first signal interconnector 227A.

[0079] Similarly, the second sub-pad 202-2A and the sub-semiconductor chip 214 can be electrically connected through a path passing through the sub-chip pad 215, the second redistribution conductive layer 218B-2, and the second independent sub-package interconnector 217-2A.

[0080] Next, referring again to Figure 4 , Figure 5and Figure 7 , only the first chip stack 220 can be connected to the first main pad 202-1B through the first independent interconnector 227B. The first main pad 202-1B can be the second power pad or the second signal transmission pad of the first chip stack 220. In this document, the second signal transmission may not represent signal exchange with the sub-semiconductor chip 214. This is because the signal exchange between the sub-semiconductor chip 214 and the first chip stack 220 is achieved through the first signal interconnector 227A.

[0081] When the sub-semiconductor chip 214 is a memory controller and the first main semiconductor chip 224 is a memory, the first main semiconductor chip 224 can exchange signals / data with the outside only through the sub-semiconductor chip 214. In this case, the first main pad 202-1B can be used only as the second power pad in the substrate 200.

[0082] Similarly, only the second chip stack 230 can be connected to the second main pad 202-2B through the second independent interconnector 237B. The second main pad 202-2B can be the third power pad or the third signal transmission pad for the second chip stack 230 in the substrate 200.

[0083] When the sub-semiconductor chip 214 is a memory controller and the second main semiconductor chip 234 is a memory, the second main semiconductor chip 234 can exchange signals / data with the outside only through the sub-semiconductor chip 214. In this case, the second main pad 202-2B can be used only as the second power pad in the substrate 200.

[0084] Next, referring again to Figure 4 , Figure 5 and Figure 8 , the sub-semiconductor chip 214 and the first chip stack 220 can be connected to the first common pad 202-1C. Specifically, the sub-semiconductor chip 214 can be electrically connected to the first common pad 202-1C through a path passing through the sub-chip pad 215, the first redistribution conductive layer 218B-1 / the first redistribution pad 218BP-1, and the first common sub-package interconnector 217-1B. In addition, the first chip stack 220 can be electrically connected to the first common pad 202-1C through a path passing through the first common interconnector 227C and the first common sub-package interconnector 217-1B. The first common pad 202-1C can be a ground power pad.

[0085] Similarly, the sub-semiconductor chip 214 and the second chip stack 230 can be connected to the second common pad 202-2C. The second common pad 202-2C can be a ground power pad. Specifically, the sub-semiconductor chip 214 can be electrically connected to the second common pad 202-2C through a path passing through the sub-chip pad 215, the second redistribution conductive layer 218B-2 / second redistribution pad 218BP-2, and the second common sub-package interconnector 217-2B. In addition, the second chip stack 230 can be electrically connected to the second common pad 202-2C through a path passing through the second common interconnector 237C and the second common sub-package interconnector 217-2B.

[0086] Next, referring to Figure 4 , Figure 5 and Figure 9 , the first chip stack 220 and the sub-semiconductor chip 214 can be electrically connected to each other through a path passing through the sub-chip pad 215, the first redistribution conductive layer 218B-1, and the first signal interconnector 227A. In the case where the sub-semiconductor chip 214 is a memory controller and the first main semiconductor chip 224 is a memory, each first main semiconductor chip 224 can exchange signals / data with the outside only through the sub-semiconductor chip 214. Therefore, the signals / data input to or output from the first main semiconductor chip 224 can be transmitted from the sub-semiconductor chip 214 through this path.

[0087] Similarly, the second chip stack 230 and the sub-semiconductor chip 214 can be electrically connected to each other through a path passing through the sub-chip pad 215, the second redistribution conductive layer 218B-2, and the second signal interconnector 237A.

[0088] According to the above semiconductor package, effects the same as or similar to those described in the foregoing embodiments can be achieved.

[0089] In addition, instead of being connected to the sub-semiconductor chip 214 through the substrate 200, the first chip stack 220 or the second chip stack 230 can be directly connected to the sub-semiconductor chip 214 through the interconnectors 227A and 237A. Therefore, since the signal / data exchange path between the first chip stack 220 or the second chip stack 230 and the sub-semiconductor chip 214 is short, the operation speed can be increased. In addition, since the circuit / wiring structure in the substrate 200 for connecting the first chip stack 220 or the second chip stack 230 and the sub-semiconductor chip 214 is not necessary, the design of the circuit / wiring structure in the substrate 200 can be further simplified.

[0090] Figure 10A block diagram showing an electronic system including a memory card 7800 incorporating at least one semiconductor package according to an embodiment is shown. The memory card 7800 includes a memory 7810 (e.g., a non-volatile memory device) and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read stored data. At least one of the memory 7810 and the memory controller 7820 can include at least one semiconductor package according to the embodiment.

[0091] The memory 7810 can include a non-volatile memory device applying the technology of the embodiments of the present disclosure. The memory controller 7820 can control the memory 7810 such that stored data is read or data is stored in response to a read / write request from a host 7830.

[0092] Figure 11 A block diagram showing an electronic system 8710 including at least one semiconductor package according to the embodiment is shown. The electronic system 8710 can include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 can be coupled to each other via a bus 8715 providing a path for data movement.

[0093] In one embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 can include one or more semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 can include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 can store data and / or commands to be executed by the controller 8711, etc.

[0094] The memory 8713 can include a volatile memory device such as DRAM and / or a non-volatile memory device such as flash memory. For example, flash memory can be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory can constitute a solid state drive (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

[0095] The electronic system 8710 can further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 can be of a wired type or a wireless type. For example, the interface 8714 can include an antenna or a wired transceiver or a wireless transceiver.

[0096] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system can be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0097] If the electronic system 8710 represents a device capable of performing wireless communication, the electronic system 8710 can be used in a communication system using code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), enhanced time division multiple access (E-TDMA), wideband code division multiple access (WCDMA), CDMA2000, long term evolution (LTE), or wireless broadband internet (Wibro) technology.

[0098] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined by the appended claims.

[0099] Cross - reference to related applications

[0100] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0168772, filed on December 17, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package, the semiconductor package comprises: a substrate having a first substrate pad formed at one side edge of the substrate along a first direction and a second substrate pad formed at the other side edge of the substrate along the first direction; a sub-semiconductor package formed on the substrate, and the sub-semiconductor package includes: a sub-semiconductor chip; a sub-molding layer surrounding the side surface of the sub-semiconductor chip; and a redistribution conductive layer extending onto the sub-molding layer in a state of being connected to a sub-chip pad of the sub-semiconductor chip and connected to a first redistribution pad and a second redistribution pad respectively formed at one side edge and the other side edge of the sub-molding layer along the first direction; a first chip stack formed on the sub-semiconductor package, and the first chip stack includes one or more first main semiconductor chips; and a second chip stack formed on the first chip stack, and the second chip stack includes one or more second main semiconductor chips, wherein the sub-semiconductor chip is connected to the substrate through a first sub-package interconnector connecting the first redistribution pad and the first substrate pad and a second sub-package interconnector connecting the second redistribution pad and the second substrate pad, wherein the first chip stack is connected to the substrate through a first interconnector connecting a first chip pad of the one or more first main semiconductor chips and the first substrate pad, wherein the second chip stack is connected to the substrate through a second interconnector connecting a second chip pad of the one or more second main semiconductor chips and the second substrate pad, wherein a substrate pad of the first substrate pads that is connected to the first sub-package interconnector and not connected to the first interconnector, or a substrate pad of the second substrate pads that is connected to the second sub-package interconnector and not connected to the second interconnector serves as a power supply pad or a signal transmission pad of the sub-semiconductor chip, wherein a substrate pad of the first substrate pads that is not connected to the first sub-package interconnector and is connected to the first interconnector serves as a power supply pad or a signal transmission pad of the first chip stack, and a substrate pad of the second substrate pads that is not connected to the second sub-package interconnector and is connected to the second interconnector serves as a power supply pad or a signal transmission pad of the second chip stack, and wherein a substrate pad of the first substrate pads that is commonly connected to the first sub-package interconnector and the first interconnector, or a substrate pad of the second substrate pads that is commonly connected to the second sub-package interconnector and the second interconnector serves as a ground power supply pad.

2. The semiconductor package according to claim 1, wherein, the one or more first main semiconductor chips are stacked in a state of being offset in a direction away from the first substrate pad in the first direction in sequence, and The one or more second main semiconductor chips are stacked in sequence with an offset in a direction away from the second substrate pad along the first direction.

3. The semiconductor package according to claim 2, wherein the first chip pad is disposed at a side edge of the one or more first main semiconductor chips that is exposed according to the stacking of the one or more first main semiconductor chips, and the second chip pad is disposed at the other side edge of the one or more second main semiconductor chips that is exposed according to the stacking of the one or more second main semiconductor chips.

4. The semiconductor package according to claim 1, wherein a first end of the first sub-package interconnector and a first end of the first interconnector are in direct contact with the ground power pad among the first substrate pads, and a first end of the second sub-package interconnector and a first end of the second interconnector are in direct contact with the ground power pad among the second substrate pads.

5. The semiconductor package according to claim 1, the semiconductor package further comprises: a third interconnector that connects the first chip pad and the first redistribution pad; and a fourth interconnector that connects the second chip pad and the second redistribution pad.

6. The semiconductor package according to claim 5, wherein a substrate pad among the first substrate pads that is electrically connected to the third interconnector via the first sub-package interconnector and the first redistribution pad serves as the ground power pad, and a substrate pad among the second substrate pads that is electrically connected to the fourth interconnector via the second sub-package interconnector and the second redistribution pad serves as the ground power pad.

7. The semiconductor package according to claim 5, wherein the third interconnector is configured for signal exchange between the sub-semiconductor chip and the first chip stack, and the fourth interconnector is configured for signal exchange between the sub-semiconductor chip and the second chip stack.

8. The semiconductor package according to claim 1, wherein the one or more first main semiconductor chips and the one or more second main semiconductor chips are memories, and the sub-semiconductor chip is a memory controller.

9. The semiconductor package according to claim 1, wherein the sub-chip pads include a first sub-chip pad and a third sub-chip pad respectively disposed at two side edges of the sub-semiconductor chip along the first direction, and a second sub-chip pad and a fourth sub-chip pad respectively disposed at two side edges of the sub-semiconductor chip along a second direction perpendicular to the first direction, the redistribution conductive layer connected to the first sub-chip pad and the second sub-chip pad extends to the first redistribution pad, and the redistribution conductive layer connected to the third sub-chip pad and the fourth sub-chip pad extends to the second redistribution pad.

10. The semiconductor package according to claim 9, wherein, the redistribution conductive layer connected to the first sub-chip pad has a bent shape, and The redistribution conductive layer connected to the third sub-chip pad has a curved shape.

11. The semiconductor package according to claim 10, wherein, when viewed from above, the redistribution conductive layer has a spiral shape centered on the sub-semiconductor chip.

12. The semiconductor package according to claim 1, wherein when viewed from above, the sub-semiconductor chip is located in the central portion of the sub-semiconductor package.

13. The semiconductor package according to claim 1, wherein, the first chip stack and the second chip stack are arranged to expose the first redistribution pad and the second redistribution pad.

14. The semiconductor package according to claim 1, wherein, the sub-semiconductor package is arranged to expose the first substrate pad and the second substrate pad.

15. A semiconductor package, the semiconductor package comprising: a substrate having a first substrate pad formed at one side edge of the substrate along a first direction and a second substrate pad formed at the other side edge of the substrate along the first direction; a sub-semiconductor package formed on the substrate, and the sub-semiconductor package includes: a sub-semiconductor chip; a sub-molding layer surrounding the side surface of the sub-semiconductor chip; and a redistribution conductive layer extending onto the sub-molding layer in a state of being connected to the sub-chip pads of the sub-semiconductor chip and connected to a first redistribution pad and a second redistribution pad respectively formed at one side edge and the other side edge of the sub-molding layer along the first direction; and a chip stack formed on the sub-semiconductor package, and the chip stack includes one or more main semiconductor chips, wherein the sub-chip pads include a first sub-chip pad and a third sub-chip pad respectively provided at both side edges of the sub-semiconductor chip along the first direction, and a second sub-chip pad and a fourth sub-chip pad respectively provided at both side edges of the sub-semiconductor chip along a second direction perpendicular to the first direction, wherein the redistribution conductive layer connected to the first sub-chip pad and the second sub-chip pad extends to the first redistribution pad, and wherein the redistribution conductive layer connected to the third sub-chip pad and the fourth sub-chip pad extends to the second redistribution pad.

16. The semiconductor package according to claim 15, wherein, when viewed from above, the redistribution conductive layer has a spiral shape centered on the sub-semiconductor chip.

17. The semiconductor package according to claim 15, wherein, when viewed from above, the sub-semiconductor chip is located in the central portion of the sub-semiconductor package.

18. The semiconductor package according to claim 15, wherein the first redistribution pad and the first substrate pad are connected to each other, and the second redistribution pad and the second substrate pad are connected to each other.

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