Semiconductor device

Abstract

A semiconductor device includes a first gate stack including a plurality of first gate electrodes, a second gate stack disposed on the first gate stack and including a plurality of second gate electrodes, and a plurality of channel structures disposed in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each channel hole includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, a ratio of a second width of an upper end of the first channel hole portion in a second direction to a first width thereof in a first direction is smaller than a ratio of a fourth width of an upper end of the second channel hole portion in the second direction to a third width thereof in the first direction.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] As the integration of memory devices increases, memory devices having a vertical transistor structure have been proposed as an alternative to memory devices having a general planar transistor structure. Memory devices having a vertical transistor structure include a channel structure extending in a vertical direction on a substrate. SUMMARY

[0003] Embodiments are directed to a semiconductor device including a first gate stack disposed on a substrate and including a plurality of first gate electrodes and a plurality of first insulating layers alternately disposed, a second gate stack disposed on the first gate stack and including a plurality of second gate electrodes and a plurality of second insulating layers alternately disposed, and a plurality of channel structures disposed in a plurality of channel holes penetrating the first gate stack and the second gate stack and spaced apart from each other in a first direction and a second direction parallel to a top surface of the substrate. Each of the plurality of channel holes can include a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width of a first channel hole upper end of the first channel hole portion in the second direction to a first width thereof in the first direction can be less than a ratio of a fourth width of a second channel hole upper end of the second channel hole portion in the second direction to a third width thereof in the first direction.

[0004] Embodiments are also directed to a semiconductor device including a plurality of first gate electrodes disposed on a substrate and spaced apart from each other in a direction perpendicular to a top surface of the substrate, a plurality of second gate electrodes disposed on the plurality of first gate electrodes and spaced apart from each other in the direction perpendicular to the top surface of the substrate, a plurality of channel structures in a plurality of channel holes penetrating the plurality of first gate electrodes and the plurality of second gate electrodes, and a common source line region extending in a first direction parallel to the top surface of the substrate on a side of the plurality of first gate electrodes and the plurality of second gate electrodes. Each of the plurality of channel holes can include a first channel hole portion penetrating the plurality of first gate electrodes and a second channel hole portion penetrating the plurality of second gate electrodes, and a ratio of a second width of a first channel hole upper end of the first channel hole portion in the second direction to a first width thereof in the first direction can be less than a ratio of a fourth width of a second channel hole upper end of the second channel hole portion in the second direction to a third width thereof in the first direction.

[0005] Embodiments are also directed to a semiconductor device including: a plurality of first gate electrodes arranged on a substrate and spaced apart from each other in a direction perpendicular to a top surface of the substrate; a plurality of second gate electrodes arranged on the plurality of first gate electrodes and spaced apart from each other in the direction perpendicular to the top surface of the substrate; a plurality of channel structures in a plurality of channel holes penetrating the plurality of first gate electrodes and the plurality of second gate electrodes; and a common source line extending along a first direction parallel to the top surface of the substrate on one side of the plurality of first gate electrodes and the plurality of second gate electrodes. Each of the plurality of channel structures can include a first horizontal cross section at a same height as a height of an uppermost first gate electrode and a second horizontal cross section at a same height as a height of an uppermost second gate electrode, the first horizontal cross section can have an elliptical shape having a long axis in the first direction, and the second horizontal cross section has an elliptical shape having a long axis in a second direction parallel to the top surface of the substrate and perpendicular to the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0007] Figure 1 An equivalent circuit diagram of a memory cell array of a semiconductor device according to an example embodiment is shown;

[0008] Figure 2 is a top view showing a representative configuration of a semiconductor device according to an example embodiment;

[0009] Figure 3 is a cross-sectional view taken along line A1-A1' in Figure 2 ;

[0010] Figure 4 is a cross-sectional view taken along line A2-A2' in Figure 2 ;

[0011] Figure 5 shows horizontal cross-sectional views of regions B1 in Figure 2 at first to third vertical levels of Figure 3 ;

[0012] Figure 6 is a top view schematically showing an arrangement at a connection portion between a first channel portion and a second channel portion.

[0013] Figure 7 is an enlarged cross-sectional view of region CX1 in Figure 3 ;

[0014] Figure 8is a top view of a semiconductor device according to an example embodiment;

[0015] Figure 9 is a top view of a semiconductor device according to an example embodiment;

[0016] Figure 10 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0017] Figure 11 is a top view schematically illustrating an arrangement at a connection portion between a second channel portion and a third channel portion;

[0018] Figure 12 is a top view schematically illustrating an arrangement at a connection portion between a first channel portion and a second channel portion;

[0019] Figure 13 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0020] Figure 14 is a plan view schematically illustrating an arrangement at a connection portion between a lower pad contact and an upper pad contact;

[0021] Figure 15 is a top view showing a representative configuration of a semiconductor device according to an example embodiment;

[0022] Figure 16 is a cross-sectional view taken along line A3-A3' in Figure 15 ;

[0023] Figure 17 is a top view schematically illustrating an arrangement at a connection portion between a lower through electrode and an upper through electrode; and

[0024] Figures 18A to 22B is a schematic diagram of a method of manufacturing a semiconductor device according to an example embodiment in a process sequence, wherein Figure 18A , Figure 19A , Figure 20 , Figure 21 and Figure 22A are cross-sectional views corresponding to a cross-section taken along line Al-Al' in Figure 2 , Figure 18B , Figure 19B and Figure 22B are cross-sectional views taken along line A2-A2' in Figure 2 , Figure 18C is a horizontal cross-sectional view at a first vertical height, Figure 19C is a horizontal cross-sectional view at a second vertical height and a third vertical height. DETAILED DESCRIPTION

[0025] Figure 1 An equivalent circuit diagram of a memory cell array (MCA) of a semiconductor device according to an example embodiment is shown.

[0026] Figure 1 An example of an equivalent circuit diagram for a vertical NAND (VNAND) flash memory device with a vertical channel structure is shown. (Refer to...) Figure 1 The memory cell array (MCA) can be included in the vertical direction ( Figure 1 The storage cells MS are multiple strings of memory cells MS on a substrate (not shown) in the Z direction. Each of the multiple strings of memory cells MS may include multiple memory cells MC1, MC2, ..., MCn-1 and MCn connected in series with each other, a string select transistor SST, and a ground select transistor GST. The multiple memory cells MC1, MC2, ..., MCn-1 and MCn can store data, and multiple word lines WL1, WL2, ..., WLn-1 and WLn can be connected to memory cells MC1, MC2, ..., MCn-1 and MCn respectively to control the corresponding memory cells MC1, MC2, ..., MCn-1 and MCn.

[0027] The gate terminal of the ground select transistor GST can be connected to the ground select line GSL, and the source terminal of the ground select transistor GST can be connected to the common source line CSL. The gate terminal of the series select transistor SST can be connected to the series select line SSL, the source terminal of the series select transistor SST can be connected to the drain terminal of the memory cell MCn, and the drain terminal of the series select transistor SST can be connected to the corresponding bit line among multiple bit lines BL1, BL2, ..., BLm (collectively labeled BL). Although Figure 1 An example is shown where each memory cell string MS includes one ground select transistor GST and two string select transistors SST. However, unlike this case, for example, one or more ground select transistors GST and one or more string select transistors SST may be formed in each memory cell string MS.

[0028] When a signal is applied to the gate terminal of the serial select transistor SST via the serial select line SSL, signals applied via the multiple bit lines BL can be applied to the multiple memory cells MC1, MC2, ..., MCn-1 and MCn to perform a data write operation. When a signal is applied to the gate terminal of the ground select transistor GST via the ground select line GSL, an erase operation can be performed on the multiple memory cells MC1, MC2, ..., MCn-1 and MCn.

[0029] Figures 2 to 7 This is a diagram used to illustrate a semiconductor device 100 according to an example embodiment.

[0030] Figure 2This is a plan view showing a representative configuration of a semiconductor device 100 according to an example embodiment. Figure 3 It is along Figure 2 The cross-sectional view taken by line A1-A1' in the diagram. Figure 4 It is along Figure 2 The cross-sectional view taken by line A2-A2' in the diagram. Figure 5 It shows relative to Figure 2 Region B1 in Figure 3 Horizontal cross-sectional views at the first to third vertical heights LV1, LV2 and LV3. Figure 6 It is a top view schematically showing the arrangement at the connection between the first channel section and the second channel section. Figure 7 yes Figure 3 An enlarged cross-sectional view of region CX1 in the image. Figure 2 For ease of illustration and understanding, only some components of the semiconductor device 100 are shown schematically.

[0031] Reference Figures 2 to 7 The substrate 110 may include a memory cell region (MCR), a connection region (CON), and a peripheral circuit region (PERI). A memory cell array (MCA) may be located on the memory cell region (MCR), and the memory cell array (MCA) may include a NAND memory device with a vertical channel structure as described above. Figure 1 The described method is driven. A peripheral circuit transistor 190T for driving the memory cell array MCA can be located on the peripheral circuit region PERI. The peripheral circuit transistor 190T may include a peripheral circuit active region 192, a peripheral circuit gate electrode 194 on the peripheral circuit active region 192, and a peripheral circuit contact 196 connecting the peripheral circuit active region 192 and the peripheral circuit gate electrode 194. The connection region CON may be a region in which a pad portion PAD is formed for connecting the memory cell array MCA in the memory cell region MCR to the peripheral circuit transistor 190T.

[0032] Substrate 110 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium. Substrate 110 may be provided as a bulk wafer or an epitaxial layer. In another example embodiment, substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0033] On substrate 110, a first gate stack 120S can extend in a first horizontal direction (X direction) and a second horizontal direction (Y direction) parallel to the top surface of substrate 110. The first gate stack 120S may include a plurality of first gate electrodes 122 and a plurality of first insulating layers 124. The plurality of first gate electrodes 122 and the plurality of first insulating layers 124 can be alternately stacked in a vertical direction (Z direction) perpendicular to the top surface of substrate 110. Figure 7 As shown, the first gate electrode 122 may include a buried conductive layer 122A and a conductive barrier layer 122B surrounding the top surface, bottom surface and side surface of the buried conductive layer 122A.

[0034] The second gate stack 130S can be on top of the first gate stack 120S. The second gate stack 130S may include a plurality of second gate electrodes 132 and a plurality of second insulating layers 134. The plurality of second gate electrodes 132 and the plurality of second insulating layers 134 may be stacked alternately in the vertical direction (Z direction). Figure 7 As shown, the second gate electrode 132 may include a buried conductive layer 132A and conductive barrier layers 132B surrounding the top, bottom, and side surfaces of the buried conductive layer 132A. An insulating layer 160 may be further disposed on the second gate stack 130S.

[0035] In one example embodiment, the plurality of first gate electrodes 122 and the plurality of second gate electrodes 132 may correspond to the ground select line GSL, word lines WL1, WL2, ..., WLn-1 and WLn, and string select line SSL (see reference) constituting the memory cell string MS. Figure 1 For example, the bottommost first gate electrode 122 can be used as the ground select line GSL, the topmost second gate electrode 132 can be used as the string select line SSL, and the remaining first gate electrodes 122 and the remaining second gate electrodes 132 can be used as word lines WL1, WL2, ..., WLn-1 and WLn. Therefore, a string of memory cells MS can be provided in which the ground select transistor GST, the string select transistor SST, and the memory cells MC1, MC2, ..., MCn-1 and MCn are connected in series.

[0036] In one example implementation, at least one of the uppermost second gate electrode 132, the uppermost first gate electrode 122, and the lowermost second gate electrode 132 among the remaining second gate electrodes 132 can be used as a dummy word line.

[0037] like Figure 2As shown, multiple word line dicing regions (WLCs) (also referred to as common source line regions) can extend parallel to the top surface of the substrate 110 in a first horizontal direction (X direction). A first gate stack 120S and a second gate stack 130S between two adjacent word line dicing regions WLCs can form a block, and the two adjacent word line dicing regions WLCs can limit the width of the first gate stack 120S and the second gate stack 130S in a second horizontal direction (Y direction).

[0038] On substrate 110, multiple common source lines 180 that vertically overlap with the plurality of word line cut regions (WLC) can extend in a first horizontal direction (X direction). Insulating spacers 182 can be on two sidewalls of the plurality of common source lines 180. For example, insulating spacers 182 can be between the plurality of first gate electrodes 122 and the common source lines 180, and between the plurality of second gate electrodes 132 and the common source lines 180.

[0039] In one example implementation, the multiple common source lines 180 may extend to a height below the top surface of the substrate 110. Figure 3 The diagram shows the top surfaces of the plurality of common source lines 180 at the same height as the top surface of the second gate stack 130S. However, unlike this case, the top surfaces of the plurality of common source lines 180 may be at a lower height than the top surface of the second gate stack 130S, and an additional insulating layer (not shown) may fill portions of the plurality of word line cut regions WLC on the plurality of common source lines 180.

[0040] Multiple common source regions 112 may be located in the substrate 110 below the common source line 180 in a first horizontal direction (X direction). The multiple common source regions 112 may be impurity regions including heavily doped n-type impurities thereon. The multiple common source regions 112 may serve as source regions for supplying current to the multiple memory cells MC1, MC2, ..., MCn-1 and MCn. The multiple common source regions 112 may be positioned to overlap with the multiple word line cut regions WLC.

[0041] like Figure 3 and Figure 4 As shown, multiple channel structures C150 can penetrate the first gate stack 120S and the second gate stack 130S from the top surface of the substrate 110 in the memory cell region MCR, and can extend in the vertical direction (Z direction). The multiple channel structures C150 can be spaced apart from each other at a specific interval in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a third horizontal direction (e.g., diagonal direction). For example, the multiple channel structures C150 can be in a Z-shaped shape or an interlaced shape.

[0042] Each of the plurality of channel structures C150 may reside in a channel via C150H and may include a first channel portion C150_1 and a second channel portion C150_2. The first channel portion C150_1 may reside in a first channel via portion C150H1 that passes through the first gate stack 120S. The second channel portion C150_2 may reside in a second channel via portion C150H2 that passes through the second gate stack 130S. The second channel portion C150_2 may be arranged such that its lower end is connected to the upper end of the first channel portion C150_1. Figure 7 As shown, at the connection between the upper end of the first channel portion C150_1 and the lower end of the second channel portion C150_2, the width of the upper end of the first channel portion C150_1 can be greater than the width of the lower end of the second channel portion C150_2. Therefore, a step portion protruding outward from the side wall of the second channel portion C150_2 of the channel structure C150 can be defined.

[0043] Each of the plurality of channel structures C150 may include a gate insulating layer 152, a channel layer 154, a buried insulating layer 156, and a conductive plug 158. The gate insulating layer 152 and the channel layer 154 may be sequentially disposed on the inner wall of the channel via C150H. For example, the gate insulating layer 152 may be conformally disposed on the sidewalls of the second channel via portion C150H2 and the first channel via portion C150H1, and the channel layer 154 may be conformally disposed along the shape of the sidewalls of the second channel via portion C150H2 and the first channel via portion C150H1. The buried insulating layer 156 may be disposed on the channel layer 154 and may fill the remaining space of the channel via C150H. The conductive plug 158 can contact the channel layer 154 and block the entrance to the channel hole C150H (e.g., the upper end of the second channel hole portion C150H2), and can be located on the upper side of the channel hole C150H. In another example embodiment, the buried insulating layer 156 can be omitted, and the channel layer 154 can be formed in a column shape to fill the remainder of the channel hole C150H.

[0044] In one example embodiment, the channel layer 154 may contact the top surface of the substrate 110 at the bottom portion of the channel via C150H. In contrast, a semiconductor layer (not shown) with a specific height may be further formed on the substrate 110 at the bottom portion of the channel via C150H, and the channel layer 154 may be electrically connected to the substrate 110 via this semiconductor layer.

[0045] like Figure 7As shown, the gate insulating layer 152 may have a structure in which a tunneling dielectric layer 152A, a charge storage layer 152B, and a barrier dielectric layer 152C are sequentially included on the outer sidewall of the channel layer 154. The relative thicknesses of the tunneling dielectric layer 152A, the charge storage layer 152B, and the barrier dielectric layer 152C constituting the gate insulating layer 152 are not limited to... Figure 7 The relative thickness shown is not the actual thickness, but can be modified in various ways.

[0046] The tunneling dielectric layer 152A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer 152B may be a region that stores electrons that have passed through the tunneling dielectric layer 152A from the channel layer 154, and may include silicon nitride, boron nitride, silicon boron nitride, or doped polycrystalline silicon. The barrier dielectric layer 152C may include silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. This metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof.

[0047] like Figure 5 and Figure 6 As shown, the first channel hole portion C150H1 and the second channel hole portion C150H2 can have a horizontal cross-section with an elliptical shape (e.g., a non-circular shape) having a major axis. The first channel hole portion C150H1 and the second channel hole portion C150H2 can also have a horizontal cross-section with an elliptical shape having a major axis extending in different directions. For example, the upper end CH1U of the first channel hole in the first channel hole portion C150H1 can have a cross-section with an elliptical shape having a major axis extending in a first horizontal direction (X direction). The upper end CH2U of the second channel hole in the second channel hole portion C150H2 can have a cross-section with an elliptical shape having a major axis extending in a second horizontal direction (Y direction). Furthermore, the lower end CH2L of the second channel hole in the second channel hole portion C150H2 can have a cross-section with an elliptical shape having a major axis extending in the first horizontal direction (X direction).

[0048] In this case, the upper end CH1U of the first channel hole can refer to the portion of the first channel hole portion C150H1 at a height higher than or equal to the height of the uppermost first gate electrode 122, the upper end CH2U of the second channel hole can refer to the portion of the second channel hole portion C150H2 at a height higher than or equal to the height of the uppermost second gate electrode 132, and the lower end CH2L of the second channel hole can refer to the portion of the second channel hole portion C150H2 at a height lower than or equal to the height of the lowermost second gate electrode 132.

[0049] exist Figure 5The diagram shows the horizontal cross-sections of the channel structure C150 at a first vertical height LV1 (at the same height as the uppermost first gate electrode 122), a second vertical height LV2 (at the same height as the lowermost second gate electrode 132), and a third vertical height LV3 (at the same height as the uppermost second gate electrode 132). In other words, in Figure 5 The diagram schematically shows the horizontal cross-section of the upper end CH1U of the first channel hole at the first vertical height LV1 (or the horizontal cross-section of the first channel portion C150_1), the horizontal cross-section of the lower end CH2L of the second channel hole at the second vertical height LV2 (or the horizontal cross-section of the second channel portion C150_2), and the horizontal cross-section of the upper end CH2U of the second channel hole at the third vertical height LV3 (or the horizontal cross-section of the second channel portion C150_2).

[0050] like Figure 5 As shown, at the first vertical height LV1, the upper end CH1U of the first channel hole can have an elliptical cross-section in which the major axis is arranged in the first horizontal direction (X direction) and the minor axis is arranged in the second horizontal direction (Y direction). At the second vertical height LV2, the lower end CH2L of the second channel hole can have an elliptical cross-section in which the major axis is arranged in the first horizontal direction (X direction) and the minor axis is arranged in the second horizontal direction (Y direction). At the third vertical height LV3, the upper end CH2U of the second channel hole can have an elliptical cross-section in which the major axis is arranged in the second horizontal direction (Y direction) and the minor axis is arranged in the first horizontal direction (X direction).

[0051] Figure 6 The arrangement at the connection between the first channel hole portion C150H1 and the second channel hole portion C150H2 is schematically shown. The upper end CH1U of the first channel hole in the first channel hole portion C150H1 may have a first width w11 in a first horizontal direction (X direction) and a second width w12 in a second horizontal direction (Y direction). The second width w12 may be smaller than the first width w11. When the deformation ratio is correspondingly defined as the width of the cross-section with respect to the elliptical shape in the second horizontal direction (Y direction) compared to the width in the first horizontal direction (X direction), the deformation ratio of the upper end CH1U of the first channel hole (i.e., the ratio of the second width w12 to the first width w11) may be less than about 1. For example, the deformation ratio of the upper end CH1U of the first channel hole may be in the range of about 0.5 to about 1.

[0052] The upper end CH2U of the second channel hole portion C150H2 may have a third width w13 in the first horizontal direction (X direction) and a fourth width w14 in the second horizontal direction (Y direction). The fourth width w14 may be greater than the third width w13. In other words, the deformation ratio of the upper end CH2U of the second channel hole (i.e., the ratio of the fourth width w14 to the third width w13) may be greater than about 1. For example, the deformation ratio of the upper end CH2U of the second channel hole may be in the range of about 1 to about 2.

[0053] The lower end CH2L of the second channel hole portion C150H2 may have a fifth width w15 in the first horizontal direction (X direction) and a sixth width w16 in the second horizontal direction (Y direction). The sixth width w16 may be smaller than the fifth width w15. In other words, the deformation ratio of the lower end CH2L of the second channel hole (that is, the ratio of the sixth width w16 to the fifth width w15) may be less than about 1. For example, the deformation ratio of the lower end CH2L of the second channel hole may be in the range of about 0.5 to about 1. The fifth width w15 of the lower end CH2L of the second channel hole may be smaller than the first width w11 of the upper end CH1U of the first channel hole, and the sixth width w16 of the lower end CH2L of the second channel hole may be smaller than the second width w12 of the upper end CH1U of the first channel hole.

[0054] like Figure 6 As shown, the lower end CH2L of the second channel hole can have a deformation ratio of less than about 1, similar to that of the upper end CH1U of the first channel hole, and the lower end CH2L of the second channel hole can be arranged at a substantially uniform separation distance from the upper end CH1U of the first channel hole. For example, the lower end CH2L of the second channel hole and the upper end CH1U of the first channel hole can be spaced apart by a first horizontal distance Dovx in a first horizontal direction (X direction) and by a second horizontal distance Dovy in a second horizontal direction (Y direction). The second horizontal distance Dovy can have a value similar to that of the first horizontal distance Dovx. Therefore, a relatively uniform overlap margin can be ensured in all directions at the connection portion between the upper end CH1U of the first channel hole and the lower end CH2L of the second channel hole, and process defects caused by misalignment of the second channel hole portion C150H2 during the formation of the second channel hole portion C150H2 can be prevented or reduced.

[0055] like Figure 3 As shown, the bit line contact BLC can penetrate the upper insulating layer 160 and contact the conductive plug 158 of the channel structure C150, and the bit line BL that contacts the bit line contact BLC can extend in the second horizontal direction (Y direction) on the upper insulating layer 160.

[0056] In a block, the top two second gate electrodes 132 may be separated into two parts by a string separation insulating layer 174. The string separation insulating layer 174 may extend from the same height as the top surface of the top second insulating layer 134 to a height lower than the bottom surface of the top two second gate electrodes 132. Thus, the top two second gate electrodes 132 may be separated into two parts by the string separation insulating layer 174 in a string selection line cut region SSLC. In another exemplary embodiment, different from that shown in Figure 3 the string separation insulating layer 174 may extend from the same height as the top surface of the top second insulating layer 134 (or the top surface of the second gate stack 130S) to a height lower than the bottom surface of the top second gate electrode 132 and higher than the top surface of the second top second gate electrode 132.

[0057] In a connection region CON, the first gate stack 120S and the second gate stack 130S may extend to form a pad portion PAD. In the connection region CON, the plurality of first gate electrodes 122 and the plurality of second gate electrodes 132 may extend to have lengths that are shorter in a first horizontal direction (X direction) as they are farther from the top surface of the substrate 110. The pad portion PAD may refer to a portion where the first gate electrode 122 and the second gate electrode 132 are arranged in a stepped form. The lower cover insulating layer 136 may be on a portion of the first gate stack 120S that constitutes the pad portion PAD, and the upper cover insulating layer 138 may be on a portion of the second gate stack 130S that constitutes the pad portion PAD. In the connection region CON, pad contacts 172 connected to the first gate electrode 122 or the second gate electrode 132 may be arranged.

[0058] As Figure 2 shown, a plurality of dummy channel structures D150 may penetrate the first gate stack 120S and the second gate stack 130S from the top surface of the substrate 110 in the connection region CON and may extend in a vertical direction (Z direction). The dummy channel structures D150 may be formed to ensure the structural stability of the semiconductor device 100 during the manufacturing process of the semiconductor device 100. Each of the plurality of dummy channel structures D150 may have a structure and a shape similar to those of the plurality of channel structures C150. In one exemplary embodiment, at least some of the plurality of dummy channel structures D150 may have a width larger than that of the plurality of channel structures C150.

[0059] Generally, as the number of gate electrodes stacked in the vertical direction increases, it may become more difficult to form the channel hole with a uniform size and shape over the entire height of the channel hole. Therefore, a method of sequentially forming the first gate stack 120S and the second gate stack 130S can be considered, but it may be difficult to align the second channel hole portion C150H2 such that the second channel hole portion C150H2 penetrating the second gate stack 130S accurately lands on the first channel hole portion C150H1 passing through the first gate stack 120S. In addition, when under-etching (i.e., asymmetric etching) occurs in a specific direction during the process of forming the channel hole C150H adjacent to the word line cut region WLC, the channel hole C150H can have an asymmetric shape in which the shape of the uppermost portion and the shape of the bottom portion are different from each other.

[0060] However, in the semiconductor device 100 according to the above exemplary embodiment, the upper end CH2U of the second channel hole of the second channel hole portion C150H2 can have a horizontal cross-section with an elliptical shape having a major axis in the second horizontal direction (Y direction), and the upper end CH1U of the first channel hole of the first channel hole portion C150H1 can have a horizontal cross-section with an elliptical shape having a major axis in the first horizontal direction (X direction). Therefore, even when the second channel hole portion C150H2 has an asymmetric shape (that is, even when the lower end CH2L of the second channel hole has a horizontal cross-section with an elliptical shape having a major axis in the first horizontal direction (X direction)), a relatively uniform overlap margin can be ensured at the connection portion between the first channel hole portion C150H1 and the second channel hole portion C150H2. Therefore, process defects due to misalignment of the second channel hole portion C150H2 during the formation of the second channel hole portion C150H2 can be prevented or reduced.

[0061] Figure 8 is a top view of a semiconductor device 100A according to an exemplary embodiment. Figure 8 Schematically shows the arrangement at the connection portion between the first channel portion C150_1 and the second channel portion C150_2. In Figure 8 the same reference numerals as those in Figures 1 to 7 denote the same components.

[0062] Refer to Figure 8The first channel portion C150_1 and the second channel portion C150_2 can have a horizontal cross-section with an elliptical shape having a major axis in the same direction but with different deformation ratios. For example, the upper end CH1UA of the first channel hole can have an elliptical cross-section having a major axis extending in the second horizontal direction (Y direction). For example, the length of this major axis can correspond to the second width w12a. For example, the upper end CH2UA of the second channel hole can have an elliptical cross-section having a major axis extending in the second horizontal direction (Y direction). For example, the length of this major axis can correspond to the fourth width w14a. Furthermore, the lower end CH2LA of the second channel hole can have an elliptical cross-section having a major axis extending in the second horizontal direction (Y direction). For example, the length of this major axis can correspond to the sixth width w16a.

[0063] The deformation ratio of the upper end CH1UA of the first channel hole (that is, the ratio of the second width w12a to the first width w11a) can be greater than about 1. The deformation ratio of the upper end CH2UA of the second channel hole (that is, the ratio of the fourth width w14a to the third width w13a) can be greater than about 1, and can be greater than the deformation ratio of the upper end CH1UA of the first channel hole. Furthermore, the deformation ratio of the lower end CH2LA of the second channel hole (that is, the ratio of the sixth width w16a to the fifth width w15a) can be greater than about 1, and can have a value similar to the deformation ratio of the upper end CH1UA of the first channel hole.

[0064] exist Figure 8 The diagram shows that the upper end CH1UA of the first channel hole and the lower end CH2LA of the second channel hole have a long axis extending in the second horizontal direction (Y direction). In another example embodiment, as shown... Figure 8 As shown, each of the upper end CH1UA of the first channel hole and the lower end CH2LA of the second channel hole may have a major axis in a horizontal direction that is inclined from about 0° to about 45° relative to the second horizontal direction (Y direction). Furthermore, the major axis of the lower end CH2LA of the second channel hole may be inclined from about 0° to about 45° relative to the major axis of the upper end CH1UA of the first channel hole.

[0065] According to the above embodiment, the lower end CH2LA of the second channel hole and the upper end CH1UA of the first channel hole can be spaced apart by a first horizontal distance Dovx in the first horizontal direction (X direction), and can be spaced apart by a second horizontal distance Dovy in the second horizontal direction (Y direction). The second horizontal distance Dovy can have a value similar to the first horizontal distance Dovx. Therefore, a relatively uniform overlap margin can be ensured in all directions at the connection portion between the upper end CH1UA of the first channel hole and the lower end CH2LA of the second channel hole, and process defects caused by misalignment of the second channel hole portion C150H2 during the formation of the second channel hole portion C150H2 can be prevented or reduced.

[0066] Figure 9 This is a top view of a semiconductor device 100B according to an example embodiment. Figure 9 The arrangement at the connection between the first channel portion C150_1 and the second channel portion C150_2 is schematically shown. Figure 9 In, with Figures 1 to 8 The same reference numerals in the accompanying drawings indicate the same parts.

[0067] Reference Figure 9 The upper end CH2UB of the second channel hole may have an elliptical horizontal cross-section having a major axis in the second horizontal direction (Y direction), and the upper end CH1UB of the first channel hole may have a substantially circular horizontal cross-section. Furthermore, the lower end CH2LB of the second channel hole may have a substantially circular horizontal cross-section.

[0068] The deformation ratio of the upper end CH1UB of the first channel hole (that is, the ratio of the second width w12b to the first width w11b) can have a value of approximately 1. The deformation ratio of the upper end CH2UB of the second channel hole (that is, the ratio of the fourth width w14b to the third width w13b) can be greater than approximately 1, and can be greater than the deformation ratio of the upper end CH1UB of the first channel hole. The deformation ratio of the lower end CH2LB of the second channel hole (that is, the ratio of the sixth width w16b to the fifth width w15b) can have a value of approximately 1.

[0069] The lower end CH2LB of the second channel hole and the upper end CH1UB of the first channel hole can be spaced apart by a first horizontal distance Dovx in the first horizontal direction (X direction) and by a second horizontal distance Dovy in the second horizontal direction (Y direction). The second horizontal distance Dovy can have a value similar to the first horizontal distance Dovx. Therefore, a relatively uniform overlap margin can be ensured in all directions at the connection portion between the upper end CH1UB of the first channel hole and the lower end CH2LB of the second channel hole, and process defects caused by misalignment of the second channel hole portion C150H2 during its formation can be prevented or reduced.

[0070] In one example implementation, at least some of the plurality of channel structures C150 may have, for example, Figure 6 The horizontal cross-sectional shape shown, and some of the plurality of channel structures C150 may have, for example, the horizontal cross-sectional shape shown. Figure 8 or Figure 9 The horizontal cross-sectional shape shown.

[0071] For example, the first channel structure C150 adjacent to the word line cutting area WLC can have, for example, Figure 6 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 are shown. Furthermore, the second channel structure C150, which is relatively far from the word line cutting area WLC, can have, as shown... Figure 8 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 shown are as follows. Figure 9 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 are shown.

[0072] As another example, the first channel structure C150 adjacent to the edge portion of the memory cell region MCR can have, for instance, the following characteristics. Figure 6 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 are shown. Furthermore, the second channel structure C150, which is relatively far from the edge of the memory cell region MCR, can have, as shown... Figure 8 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 shown are as follows. Figure 9 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 are shown.

[0073] Figure 10 This is a cross-sectional view of a semiconductor device 100C according to an example embodiment. Figure 11 This is a schematic top view showing the arrangement at the connection between the second channel section C150_2 and the third channel section C150_3. Figure 12This is a schematic top view showing the arrangement at the connection between the first channel portion C150_1 and the second channel portion C150_2. Figures 10 to 12 In, with Figures 1 to 9 The same reference numerals in the accompanying drawings can represent the same parts.

[0074] Reference Figures 10 to 12 The semiconductor device 100C may include a first gate stack 120S, a second gate stack 130S, and a third gate stack 140S sequentially stacked on a substrate 110. The third gate stack 140S may include a plurality of third gate electrodes 142 and a plurality of third insulating layers 144 alternately stacked on the second gate stack 130S.

[0075] The plurality of channel structures C150 may include a first channel portion C150_1, a second channel portion C150_2, and a third channel portion C150_3. The first channel portion C150_1 may be in a first channel via portion C150H1 that penetrates the first gate stack for 120 seconds, the second channel portion C150_2 may be in a second channel via portion C150H2 that penetrates the second gate stack for 130 seconds, and the third channel portion C150_3 may be in a third channel via portion C150H3 that penetrates the third gate stack for 140 seconds.

[0076] exist Figure 11 In the diagram, together with the horizontal cross-section of the upper end CH2U of the second channel hole of the second channel hole portion C150H2 at the same third vertical height LV3 as the uppermost second gate electrode 132, the horizontal cross-section of the lower end CH3L of the third channel hole of the third channel hole portion C150H3 at the same fourth vertical height LV4 as the lowermost third gate electrode 142 and the horizontal cross-section of the upper end CH3U of the third channel hole of the third channel hole portion C150H3 at the same fifth vertical height LV5 as the uppermost third gate electrode 142 are shown.

[0077] In one example embodiment, the upper end CH3U of the third channel hole may have an elliptical horizontal cross-section having a major axis in the second horizontal direction (Y direction), and the lower end CH3L of the third channel hole and the upper end CH2U of the second channel hole may also have elliptical horizontal cross-sections having a major axis in the second horizontal direction (Y direction). Furthermore, the deformation ratio of the upper end CH3U of the third channel hole may be greater than the deformation ratio of the lower end CH3L of the third channel hole, and may also be greater than the deformation ratio of the upper end CH2U of the second channel hole.

[0078] For example, the width w21c of the upper end CH3U of the third channel hole in the first horizontal direction (X direction) can be smaller than the width w22c of the upper end CH3U of the third channel hole in the second horizontal direction (Y direction). Furthermore, the width w23c of the lower end CH3L of the third channel hole in the first horizontal direction (X direction) can be smaller than the width w24c of the lower end CH3L of the third channel hole in the second horizontal direction (Y direction). The width w13c of the upper end CH2U of the second channel hole in the first horizontal direction (X direction) can be smaller than the width w14c of the upper end CH2U of the second channel hole in the second horizontal direction (Y direction).

[0079] exist Figure 12 In the diagram, together with the horizontal cross-section of the upper end CH2U of the second channel hole of the second channel hole portion C150H2 at the same third vertical height LV3 as the uppermost second gate electrode 132, the horizontal cross-section of the lower end CH2L of the second channel hole portion C150H2 at the same second vertical height LV2 as the lowermost second gate electrode 132 and the horizontal cross-section of the upper end CH1U of the first channel hole portion C150H1 at the same first vertical height LV1 as the uppermost first gate electrode 122 are shown.

[0080] In one example embodiment, the lower end CH2L of the second channel hole may have an elliptical horizontal cross-section having a major axis in the first horizontal direction (X direction), and the upper end CH1U of the first channel hole may have an elliptical horizontal cross-section having a major axis in the first horizontal direction (X direction). Furthermore, the deformation ratio of the upper end CH2U of the second channel hole may be greater than the deformation ratio of the lower end CH2L of the second channel hole.

[0081] For example, the width w11c of the upper end CH1U of the first channel hole in the first horizontal direction (X direction) can be greater than the width w12c of the upper end CH1U of the first channel hole in the second horizontal direction (Y direction). Furthermore, the width w15c of the lower end CH2L of the second channel hole in the first horizontal direction (X direction) can be greater than the width w16c of the lower end CH2L of the second channel hole in the second horizontal direction (Y direction).

[0082] According to the above-described exemplary embodiment, a relatively uniform overlap margin can be ensured in all directions at the connection portion between the upper end CH1U of the first channel hole and the lower end CH2L of the second channel hole, and a relatively uniform overlap margin can also be ensured in all directions at the connection portion between the upper end CH2U of the second channel hole and the lower end CH3L of the third channel hole. Therefore, process defects caused by misalignment of the second channel hole portion C150H2 and the third channel hole portion C150H3 can be prevented or reduced.

[0083] Figure 13This is a cross-sectional view of a semiconductor device 100D according to an example embodiment. Figure 14 This is a schematic plan view showing the arrangement at the connection portion between the lower pad contact 172L and the upper pad contact 172U. Figure 13 and Figure 14 In, with Figures 1 to 12 The same reference numerals in the accompanying drawings can represent the same parts.

[0084] Reference Figure 13 and Figure 14 The pad contact 172D may include a lower pad contact 172L and an upper pad contact 172U. The lower pad contact 172L may be in a lower contact hole 172H1 that penetrates the lower overlay insulating layer 136, and the upper pad contact 172U may be in an upper contact hole 172H2 that penetrates the upper overlay insulating layer 138 and the upper insulating layer 160.

[0085] exist Figure 14 In the diagram, the horizontal cross-section of the lower contact hole 172H1 at the first vertical height LV1, the horizontal cross-section of the upper contact hole 172H2 at the second vertical height LV2, and the horizontal cross-section at the sixth vertical height LV6 are shown together. In this case, the sixth vertical height LV6 can be the same height as the top surface of the upper pad contact 172U. The horizontal cross-section of the upper contact hole 172H2 at the sixth vertical height LV6 can have an elliptical shape with a major axis in the second horizontal direction (Y direction), the horizontal cross-section of the upper contact hole 172H2 at the second vertical height LV2 can have an elliptical shape with a major axis in the first horizontal direction (X direction), and the horizontal cross-section of the lower contact hole 172H1 at the first vertical height LV1 can have an elliptical shape with a major axis in the first horizontal direction (X direction).

[0086] In another example embodiment, the horizontal cross-sections of the lower contact hole 172H1 and the upper contact hole 172H2 can be respectively similar to... Figure 8 or Figure 9 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 are shown.

[0087] According to the example implementation, a relatively uniform overlap margin can be ensured in all directions at the connection portion of the lower contact hole 172H1 and the upper contact hole 172H2, thus preventing or reducing defects caused by misalignment during the formation of the upper contact hole 172H2.

[0088] Figure 15 This is a top view showing a representative configuration of a semiconductor device 200 according to an example embodiment. Figure 16 It is along Figure 15 The cross-sectional view taken from line A3-A3' in the diagram.Figure 17 This is a top view schematically showing the arrangement at the connection portion between the lower through electrode 270L and the upper through electrode 270U. Figures 15 to 17 In, with Figures 1 to 14 The same reference numerals in the accompanying drawings can represent the same parts.

[0089] Reference Figures 15 to 17 The connection region CON2 can be located on one side of the memory cell region MCR, and the peripheral circuit region PERI2 can be formed at a vertical height lower than the memory cell region MCR and the connection region CON2. The connection region CON2 can be an area in which a plurality of through electrodes 270 are arranged for electrical connection between the memory cell region MCR and the peripheral circuit region PERI2 at a vertical height lower than the memory cell region MCR. Although in Figure 15 The image shows a single connection area CON2, but unlike this, multiple connection areas CON2 can be surrounded by a memory cell area MCR.

[0090] The lower substrate 210 may be located at a lower vertical height than the substrate 110. An active region (not shown) may be defined by a device isolation layer 222 on the lower substrate 210, and a plurality of driving transistors 230T may be formed on the active region. The plurality of driving transistors 230T may include a driving circuit gate structure 232 and impurity regions 212 on both sides of the driving circuit gate structure 232 in a portion of the lower substrate 210.

[0091] On the lower substrate 210, a plurality of wiring layers 242, a plurality of contact plugs 244 connecting each of the plurality of wiring layers 242 or connecting the plurality of wiring layers 242 and the driving transistor 230T, and a peripheral circuit wiring layer 246 at a vertical height higher than the plurality of wiring layers 242 can be disposed. Furthermore, on the lower substrate 210, a lower interlayer insulating layer 250 covering the plurality of wiring layers 242, the plurality of contact plugs 244, and the peripheral circuit wiring layer 246 can be disposed, and the substrate 110 can be disposed on the lower interlayer insulating layer 250.

[0092] On the substrate 110, a first semiconductor layer 162 and a second semiconductor layer 164 may be arranged sequentially, and on the second semiconductor layer 164, a first gate stack 120S and a second gate stack 130S may be arranged sequentially.

[0093] In one example embodiment, the first semiconductor layer 162 may include doped polysilicon or undoped polysilicon, and the second semiconductor layer 164 may also include doped polysilicon or undoped polysilicon. The first semiconductor layer 162 can be used as a common source line extension region and can be... Figure 1The portion corresponding to the common source line CSL in the first semiconductor layer 162. The second semiconductor layer 164 can be used as a support layer to prevent the molded stack from collapsing or falling over during the process of removing the sacrificial layer used to form the first semiconductor layer 162. The common source line 180 can be connected to the first semiconductor layer 162.

[0094] The plurality of channel structures C150 and the plurality of dummy channel structures D150 can penetrate the first semiconductor layer 162 and the second semiconductor layer 164, and can contact the substrate 110. For example... Figure 16 As shown, each dummy channel structure D150 may include a first dummy channel portion D150_1 in the first dummy channel via portion passing through the first gate stack 120S and a second dummy channel portion D150_2 in the second dummy channel via portion passing through the second gate stack 130S. Figure 16 As shown, a portion of the gate insulating layer 152 can be removed at the same height as the first semiconductor layer 162, and the channel layer 154 can contact the extension 162E of the first semiconductor layer 162. Because the gate insulating layer 152 surrounds the bottom surface of the channel layer 154, the channel layer 154 can be electrically connected to the common source line 180 via the first semiconductor layer 162, instead of directly contacting the substrate 110.

[0095] In the connection region CON2, an insulating structure 260 can be arranged in the opening 260H of the penetration substrate 110, the first gate stack 120S, and the second gate stack 130S. The insulating structure 260 may include a lower insulating layer 260L and an upper insulating layer 260U. The lower insulating layer 260L may have a top surface at the same height as the top surface of the first gate stack 120S, and the upper insulating layer 260U may have a top surface at the same height as the top surface of the second gate stack 130S.

[0096] The plurality of through electrodes 270 can penetrate the insulating structure 260 and connect to the peripheral circuit wiring layer 246. Each of the plurality of through electrodes 270 may include a lower through electrode 270L and an upper through electrode 270U. The lower through electrode 270L can be in a lower through hole 270H1 penetrating the lower insulating layer 260L and extends to a height lower than the top surface of the lower interlayer insulating layer 250 to connect to the peripheral circuit wiring layer 246. The upper through electrode 270U can be in an upper through hole 270H2 penetrating the upper insulating layer 260U and can be connected to the lower through electrode 270L.

[0097] exist Figure 17The horizontal cross-sections of the lower through-hole 270H1 at a first vertical height LV1, the upper through-hole 270H2 at a second vertical height LV2, and the upper through-hole 270H2 at a third vertical height LV3 are shown together for comparison. The horizontal cross-section of the upper through-hole 270H2 at the third vertical height LV3 may have an elliptical shape with a major axis in the second horizontal direction (Y direction), the horizontal cross-section of the upper through-hole 270H2 at the second vertical height LV2 may have an elliptical shape with a major axis in the first horizontal direction (X direction), and the horizontal cross-section of the lower through-hole 270H1 at the first vertical height LV1 may have an elliptical shape with a major axis in the first horizontal direction (X direction).

[0098] In another example embodiment, the horizontal cross-sections of the lower through hole 270H1 and the upper through hole 270H2 can be respectively similar to... Figure 8 or Figure 9 The horizontal cross-sections of the first channel portion C150_1 and the second channel portion C150_2 are shown.

[0099] According to the above example implementation, a relatively uniform overlap margin can be ensured in all directions at the connection portion of the lower through hole 270H1 and the upper through hole 270H2. Therefore, defects caused by misalignment in the process of forming the upper through hole 270H2 can be prevented or reduced.

[0100] Figures 18A to 22B This is a schematic diagram of a method for manufacturing a semiconductor device 100 in process sequence according to an example embodiment. Figure 18A , Figure 19A , Figure 20 , Figure 21 and Figure 22A Is along Figure 2 The cross-sectional view corresponding to the section intercepted by line A1-A1' in the diagram. Figure 18B , Figure 19B and Figure 22B It is along Figure 2 The cross-sectional view taken by line A2-A2' in the diagram. Figure 18C It is at the first vertical height and Figure 2 The horizontal cross-sectional view corresponding to region B1 in the diagram. Figure 19C The figure shows the relationship at the second and third vertical heights. Figure 2 The horizontal cross-sectional view corresponding to region B1 in Figure 18. Figure 22B In, with Figures 1 to 17 The same reference numerals in the accompanying drawings can represent the same parts.

[0101] Reference Figures 18A to 18COn the top surface of the substrate 110, a first molding stack 320S can be formed by alternately forming a plurality of first insulating layers 124 and a plurality of first sacrificial layers 322. In an example embodiment, the plurality of first insulating layers 124 may include insulating materials such as silicon oxide and silicon oxide nitride, and the plurality of first sacrificial layers 322 may include silicon nitride, silicon oxide nitride, or polycrystalline silicon doped with impurities.

[0102] Next, the first pad portion PAD1 can be formed by sequentially patterning the first molding stack 320S in the connection area CON. In one example embodiment, the first pad portion PAD1 can be formed as a stepped shape with a difference in the height of the top surface in the first horizontal direction (X direction).

[0103] Next, a lower cover insulating layer 136 can be formed to cover the first pad portion PAD1. The lower cover insulating layer 136 may include insulating materials such as silicon oxide and silicon oxide nitride.

[0104] Subsequently, a mask pattern 310 with an opening 310H can be formed on the first molding stack 320S. By patterning the first molding stack 320S using the mask pattern 310 as an etch mask, the first channel hole portion C150H1 can be formed.

[0105] like Figure 18C As shown, the upper end CH1U of the first channel hole of the first channel hole portion C150H1 can have a horizontal cross section with an elliptical shape having a major axis in the first horizontal direction (X direction).

[0106] Reference Figures 19A to 19C A protective layer 325 can be formed to fill the interior of the first channel hole portion C150H1. In an example embodiment, after the first channel hole portion C150H1 is filled with a conductive material, the protective layer 325 can be formed by planarizing the upper part of the conductive material until the top surface of the first molded stack 320S is exposed. The protective layer 325 can be formed using at least one material, such as metal, polycrystalline silicon, amorphous carbon, and spin-on hard mask (SOH).

[0107] Next, a second molding stack 330S can be formed by alternately forming a plurality of second insulating layers 134 and a plurality of second sacrificial layers 332 on the first molding stack 320S. In one example embodiment, the plurality of second insulating layers 134 may include insulating materials such as silicon oxide and silicon oxide nitride, and the plurality of second sacrificial layers 332 may include silicon nitride, silicon oxide nitride, or polycrystalline silicon doped with impurities.

[0108] Next, the second pad portion PAD2 can be formed by sequentially patterning the second molding stack 330S in the connection area CON. In one example embodiment, the second pad portion PAD2 can be formed as a stepped shape with a difference in the height of the top surface in the first horizontal direction (X direction).

[0109] Next, an upper cover insulating layer 138 can be formed to cover the second pad portion PAD2. The upper cover insulating layer 138 may include insulating materials such as silicon oxide and silicon nitride.

[0110] Subsequently, a mask pattern 315 with an opening 315H can be formed on the second molding stack 330S. By patterning the second molding stack 330S using the mask pattern 315 as an etching mask, the second channel hole portion C150H2 can be formed.

[0111] like Figure 19C As shown, the upper end CH2U of the second channel hole of the second channel hole portion C150H2 can have a horizontal cross-section with an elliptical shape having a major axis in the second horizontal direction (Y direction), while the lower end CH2L of the second channel hole of the second channel hole portion C150H2 can have a cross-section with an elliptical shape having a major axis extending in the first horizontal direction (X direction).

[0112] In one example implementation, during the formation of the second channel hole portion C150H2 adjacent to the word line cutting region WLC, etching can be reduced in a specific direction (i.e., asymmetric etching can occur). In this case, the second channel hole portion C150H2 can have an asymmetric shape in which the horizontal cross-sectional shape of the upper end CH2U of the second channel hole is different from the horizontal cross-sectional shape of the lower end CH2L of the second channel hole.

[0113] Furthermore, the lower end CH2L of the second channel hole can have an elliptical horizontal cross-section similar to the upper end CH1U of the first channel hole, and the overlap margin between the lower end CH2L of the second channel hole and the upper end CH1U of the first channel hole can be relatively uniform in all directions. Therefore, the lower end CH2L of the second channel hole can accurately fall within the region of the upper end CH1U of the first channel hole, and can reduce or prevent misalignment or poor connection between the lower end CH2L of the second channel hole and the upper end CH1U of the first channel hole.

[0114] Reference Figure 20 The protective layer 325 formed in the first channel hole portion C150H1 can be removed (refer to...). Figure 19A ).

[0115] Next, a channel structure C150, including a gate insulating layer 152, a channel layer 154, a buried insulating layer 156 and a conductive plug 158, can be formed on the inner wall of the first channel hole portion C150H1 and the second channel hole portion C150H2.

[0116] Reference Figure 21 A mask pattern (not shown) can be formed on the second molding stack 330S, and a word line cut region WLC can be formed by removing portions of the second molding stack 330S and the first molding stack 320S using the mask pattern as a mask. The top surface of the substrate 110 can be exposed to the bottom portion of the word line cut region WLC.

[0117] Subsequently, the plurality of first sacrificial layers 322 and the plurality of second sacrificial layers 332 exposed on the sidewalls of the word line dicing region WLC can be removed, and a first gate space 122S can be formed at the location where the first sacrificial layer 322 has been removed, and a second gate space 132S can be formed at the location where the second sacrificial layer 332 has been removed. In an example embodiment, the removal process of the plurality of first sacrificial layers 322 and the plurality of second sacrificial layers 332 can be a wet etching process using, for example, a phosphoric acid solution as an etchant.

[0118] Reference Figure 22A and Figure 22B By filling the word line cut region WLC, the first gate space 122S, and the second gate space 132S with metal material and removing the metal material from the word line cut region WLC, the first molding stack 320S can be achieved (see [link to documentation]). Figure 21 The first gate electrode 122 is formed between the insulating layers 124, and can be formed in the second molding stack 330S (see Figure 21 A second gate electrode 132 is formed between the insulating layers 134.

[0119] By implanting impurities into the substrate 110 via the word line cut region WLC, a common source region 112 can be formed in the portion of the substrate 110 located at the bottom portion of the word line cut region WLC.

[0120] Next, insulating spacers 182 and common source lines 180 can be formed in the word line cut area WLC.

[0121] Subsequently, a string separation insulating layer 174 can be formed by removing a portion of the two uppermost second gate electrodes 132 in the memory cell region MCR and filling the space formed by the removal with an insulating material. In another example embodiment, the string separation insulating layer 174 can be formed after removing a portion of two of the uppermost second sacrificial layers 332 and before forming the word line cut region WLC.

[0122] Refer again Figure 3 An upper insulating layer 160 can be formed on the uppermost second insulating layer 134, and a bit line contact BLC that penetrates the upper insulating layer 160 and electrically contacts the channel structure C150 can be further formed. Next, a bit line BL that connects to the bit line contact BLC and extends in the second horizontal direction (Y direction) can be further formed on the upper insulating layer 160.

[0123] Semiconductor device 100 can be manufactured by performing the above process.

[0124] According to the example embodiment, even when the second channel hole portion C150H2 is formed in an asymmetrical shape, a relatively uniform overlap allowance at the connection portion between the first channel hole portion C150H1 and the second channel hole portion C150H2 can be ensured. Therefore, process defects caused by misalignment of the second channel hole portion C150H2 during its formation can be prevented or reduced.

[0125] In summary and review, as the integration density of memory devices increases and the number of gate electrode layers stacked in the vertical direction increases, manufacturing difficulties may arise.

[0126] As described above, the embodiments relate to a semiconductor device including a channel structure extending in a vertical direction and a method of manufacturing the semiconductor device. The embodiments can provide a semiconductor device with a large vertical height and prevent defects during the channel hole formation process. The embodiments can also provide a method of manufacturing a semiconductor device with a large vertical height and prevent defects during the channel hole formation process.

[0127] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

[0128] Korean Patent Application No. 10-2019-0168141, entitled "Semiconductor Device and Method of Manufacturing the Semiconductor Device", filed on December 16, 2019 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first gate stack is disposed on a substrate and includes a plurality of alternating first gate electrodes and a plurality of first insulating layers; The second gate stack is disposed on the first gate stack and includes a plurality of alternately arranged second gate electrodes and a plurality of second insulating layers; as well as Multiple channel structures are arranged in multiple channel vias, the multiple channel vias penetrating the first gate stack and the second gate stack and being spaced apart from each other in a first direction and a second direction parallel to the top surface of the substrate, wherein: Each of the plurality of vias includes a first via portion penetrating the first gate stack and a second via portion penetrating the second gate stack, and The ratio of the second width of the upper end of the first channel hole in the second direction to its first width in the first direction is less than the ratio of the fourth width of the upper end of the second channel hole in the second direction to its third width in the first direction.

2. The semiconductor device of claim 1, wherein the ratio of the sixth width of the lower end of the second channel hole in the second direction to its fifth width in the first direction is less than the ratio of the fourth width of the upper end of the second channel hole in the second direction to its third width in the first direction.

3. The semiconductor device as claimed in claim 2, wherein: The fifth width of the lower end of the second channel hole in the first direction is smaller than the first width of the upper end of the first channel hole in the first direction, and The sixth width of the lower end of the second channel hole in the second direction is less than the second width of the upper end of the first channel hole in the second direction.

4. The semiconductor device of claim 1, further comprising a common source line penetrating the first gate stack and the second gate stack, the common source line being in a word line dicing region and extending in the first direction.

5. The semiconductor device as claimed in claim 1, wherein: The upper end of the second channel hole has an elliptical horizontal cross-section at the same vertical height as the uppermost second gate electrode among the plurality of second gate electrodes, and The length of the major axis of the elliptical shape corresponds to the fourth width, and the length of the minor axis of the elliptical shape corresponds to the third width.

6. The semiconductor device of claim 1, wherein: The upper end of the first channel hole has a horizontal cross-section with an elliptical shape at the same vertical height as the uppermost first gate electrode among the plurality of first gate electrodes, and The length of the major axis of the elliptical shape corresponds to the first width, and the length of the minor axis of the elliptical shape corresponds to the second width.

7. The semiconductor device of claim 1, wherein: The upper end of the first channel hole has a horizontal cross-section with an elliptical shape at the same vertical height as the uppermost first gate electrode among the plurality of first gate electrodes, and The length of the major axis of the elliptical shape corresponds to the second width, and the length of the minor axis of the elliptical shape corresponds to the first width.

8. The semiconductor device of claim 2, wherein: The upper end of the first channel hole has a horizontal cross-section with a circular shape at the same vertical height as the uppermost first gate electrode among the plurality of first gate electrodes, and The lower end of the second channel hole has a circular horizontal cross-section at the same vertical height as the lowermost second gate electrode among the plurality of second gate electrodes.

9. The semiconductor device of claim 1, further comprising a third gate stack disposed on the second gate stack and comprising a plurality of alternately arranged third gate electrodes and a plurality of third insulating layers. Each of the plurality of vias includes a first via portion penetrating the first gate stack, a second via portion penetrating the second gate stack, and a third via portion penetrating the third gate stack.

10. A semiconductor device, comprising: Multiple first gate electrodes are arranged on a substrate and spaced apart from each other in a direction perpendicular to the top surface of the substrate; A plurality of second gate electrodes are disposed on the plurality of first gate electrodes and spaced apart from each other in the direction perpendicular to the top surface of the substrate; Multiple channel structures are formed in multiple channel holes that penetrate the multiple first gate electrodes and the multiple second gate electrodes; as well as A common source line region extends along a first direction parallel to the top surface of the substrate on one side of the plurality of first gate electrodes and the plurality of second gate electrodes, wherein: Each of the plurality of channel holes includes a first channel hole portion penetrating the plurality of first gate electrodes and a second channel hole portion penetrating the plurality of second gate electrodes, and The ratio of the second width of the upper end of the first channel hole in the second direction to its first width in the first direction is less than the ratio of the fourth width of the upper end of the second channel hole in the second direction to its third width in the first direction.

11. The semiconductor device of claim 10, wherein: The ratio of the second width at the upper end of the first channel hole to the first width is in the range of 0.5 to 1, and The ratio of the fourth width to the third width at the upper end of the second channel hole is in the range of 1 to 2.

12. The semiconductor device of claim 10, wherein: Each of the plurality of channel structures includes a first horizontal section at the same height as the uppermost first gate electrode and a second horizontal section at the same height as the uppermost second gate electrode, and The first horizontal cross section has an elliptical shape having a major axis in the first direction, and the second horizontal cross section has an elliptical shape having a major axis in the second direction.

13. The semiconductor device of claim 10, wherein: Each of the plurality of channel structures includes a third horizontal section at the same height as the lowermost second gate electrode, and The third horizontal section has an elliptical shape with a major axis in the first direction.

14. The semiconductor device of claim 10, wherein: Each of the plurality of channel structures includes a first horizontal section at the same height as the uppermost first gate electrode and a second horizontal section at the same height as the uppermost second gate electrode, and The first horizontal section has an elliptical shape having a major axis in the second direction, and the second horizontal section has an elliptical shape having a major axis in the second direction.

15. A semiconductor device, comprising: Multiple first gate electrodes are arranged on a substrate and spaced apart from each other in a direction perpendicular to the top surface of the substrate; A plurality of second gate electrodes are arranged on the plurality of first gate electrodes and spaced apart from each other in the direction perpendicular to the top surface of the substrate; Multiple channel structures are formed in multiple channel holes that penetrate the multiple first gate electrodes and the multiple second gate electrodes; as well as A common source line extends along a first direction parallel to the top surface of the substrate on one side of the plurality of first gate electrodes and the plurality of second gate electrodes, wherein: Each of the plurality of channel structures includes a first horizontal section at the same height as the uppermost first gate electrode and a second horizontal section at the same height as the uppermost second gate electrode, and The first horizontal cross section has an elliptical shape having a major axis in the first direction, and the second horizontal cross section has an elliptical shape having a major axis in a second direction, the second direction being parallel to the top surface of the substrate and perpendicular to the first direction.

16. The semiconductor device of claim 15, wherein: Each of the plurality of channel structures includes a third horizontal section at the same height as the lowermost second gate electrode, and The third horizontal section has an elliptical shape with a major axis in the first direction.

17. The semiconductor device of claim 15, wherein: Each of the plurality of channel holes includes a first channel hole portion penetrating the plurality of first gate electrodes and a second channel hole portion penetrating the plurality of second gate electrodes, and The ratio of the second width of the upper end of the first channel hole in the second direction to its first width in the first direction is less than the ratio of the fourth width of the upper end of the second channel hole in the second direction to its third width in the first direction.

18. The semiconductor device of claim 17, wherein the ratio of the sixth width of the lower end of the second channel hole in the second direction to its fifth width in the first direction is less than the ratio of the fourth width of the upper end of the second channel hole in the second direction to its third width in the first direction.

19. The semiconductor device of claim 18, wherein: The fifth width at the lower end of the second channel hole is smaller than the first width at the upper end of the first channel hole, and The sixth width at the lower end of the second channel hole is smaller than the second width at the upper end of the first channel hole.

20. The semiconductor device of claim 17, further comprising a plurality of third gate electrodes disposed on the plurality of second gate electrodes and spaced apart from each other in a direction perpendicular to the top surface of the substrate. Each of the plurality of channel holes further includes a third channel hole portion that penetrates the plurality of third gate electrodes and is located at a height higher than the second channel hole portion.

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