Memory Subsystem Analysis Based on Threshold Distribution

Abstract

The present application relates to memory subsystem analysis based on threshold distributions. A system is disclosed, comprising: a memory component having a plurality of memory cells capable of being in a plurality of states, each state in the plurality of states corresponding to a value stored by the memory cell; and a processing device operatively coupled to the memory component to perform operations comprising: obtaining a plurality of threshold voltage distributions for the plurality of memory cells, wherein each of the plurality of distributions corresponds to one of the plurality of states; classifying each of the plurality of distributions into one of a plurality of classifications; generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a corresponding one of the plurality of distributions; and processing the generated vector using a classifier to determine a likelihood that the memory component will fail within a target time period.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to analyzing memory subsystems based on threshold distributions. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present application provides a system comprising: a memory component comprising a plurality of memory cells, wherein each of the plurality of memory cells is capable of being in a plurality of states, each of the plurality of states corresponding to a value stored by the memory cell; and a processing device operatively coupled to the memory component to perform operations comprising: obtaining a plurality of threshold voltage distributions for the plurality of memory cells, wherein each of the plurality of distributions corresponds to one of the plurality of states; classifying each of the plurality of distributions into one of a plurality of categories; generating a vector comprising a plurality of components, wherein each of the plurality of components represents the category of a corresponding one of the plurality of distributions; and processing the generated vector using a classifier to determine a likelihood that the memory component will fail within a target time period.

[0004] In another aspect, the present application provides a method comprising: obtaining, by a processing device operatively coupled to a memory component comprising a plurality of memory cells, a plurality of threshold voltage distributions, wherein each of the plurality of distributions corresponds to one of a plurality of states of a memory cell in the plurality of memories, wherein each of the plurality of states corresponds to a value stored by the memory cell; classifying each of the plurality of distributions into one of a plurality of categories; generating a vector comprising a plurality of components, wherein each of the plurality of components represents the category of a corresponding one of the plurality of distributions; and processing the generated vector using a classifier to determine a likelihood that the memory component will fail within a target time period.

[0005] In another aspect, the present application provides a method comprising: obtaining, by a processing device, a training input comprising a plurality of threshold voltage distributions for a memory component, wherein each of the plurality of threshold voltages corresponds to one of a plurality of states, each of the plurality of states corresponding to a value stored by a memory cell of the memory component; obtaining, by the processing device, a target output, wherein the target output comprises a target probability of failure of the memory component within a target time interval; processing the training input by a neural network model comprising a plurality of neurons to obtain, by the processing device, a training output, wherein the training output comprises a predicted probability of failure of the memory component within the target time interval; determining, by the processing device, a difference between the predicted failure probability and the target failure probability; and modifying, by the processing device, parameters of the neural network model based on the determined difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing environment including a memory subsystem is described according to some embodiments of the present disclosure.

[0008] Figure 2 Some embodiments of the present disclosure illustrate a training phase for training a machine learning classifier that can be used to predict the likelihood of potential failure of a memory device.

[0009] Figure 3A Some embodiments of the present disclosure schematically illustrate structured histograms depicting threshold voltage distributions of robust memory cells capable of storing three bits of data.

[0010] Figure 3B Conditional histograms are schematically illustrated according to some embodiments of the present disclosure, depicting the threshold voltage distribution of damaged TLC memory cells.

[0011] Figure 3C Some embodiments according to the present disclosure schematically illustrate unstructured distributed data, such as may be collected by a memory subsystem controller.

[0012] Figure 4 An exemplary classification of various characteristics of threshold voltage distributions is described according to some embodiments of the present disclosure.

[0013] Figure 5A Some embodiments according to the present disclosure illustrate structured histograms depicting actual threshold voltage distributions of robust TLC memory cells, where the various distributions are well separated from each other.

[0014] Figure 5BSome embodiments according to the present disclosure illustrate structured histograms depicting actual threshold voltage distributions of damaged TLC memory cells, with some distributions significantly overlapping each other.

[0015] Figure 5C Some embodiments according to the present disclosure illustrate structured histograms depicting actual threshold voltage distributions of damaged TLC memory cells, some of which are erased.

[0016] Figure 6A Some embodiments according to the present disclosure illustrate classification of some exemplary tail features using a quantile-quantile representation (QQR) of the threshold voltage distribution of a particular state of memory cells corresponding to a target device distribution relative to a control distribution.

[0017] Figure 6B A set of exemplary quantile-quantile representations of seven different threshold voltage distributions for a TLC memory device are described according to some embodiments of the present disclosure.

[0018] Figure 6C Another set of exemplary quantile-quantile representations of seven different threshold voltage distributions for another TLC memory device is described according to some embodiments of the present disclosure.

[0019] Figure 7 A flow chart illustrating an example method for predicting the likelihood of potential failure of a memory device (component) according to some embodiments of the present disclosure.

[0020] Figure 8 A flowchart illustrating an example method for classifying multiple distributions of memory components into one of multiple categories is provided according to some embodiments of the present disclosure.

[0021] Figure 9 A flow chart illustrating an example method of training a machine learning model to determine the likelihood of failure of a memory component according to some embodiments of the present disclosure.

[0022] Figure 10 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0023] Aspects of the present disclosure are directed to analyzing a memory subsystem based on a threshold distribution. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Typically, a host system can utilize a memory subsystem that includes one or more memory components, such as memory devices that store data. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0024] Storing data in certain memory devices with different media types relies on the precise placement of charge within the memory cells of the memory device. The amount of charge placed on the memory cell can be used to represent the value stored by the memory cell. Depending on the amount of charge placed, the current passing through the memory cell may require the application of a value-specific threshold voltage. The readability of the memory cell depends primarily on the specificity of the threshold voltages representing different stored values. Due to the inevitable variations in the size, location, and environment of various memory cells, the threshold voltage corresponding to a given value in various memory cells, even when implemented on the same substrate, will vary and fall within a distribution of voltages. However, as long as the distributions corresponding to different values ​​do not significantly overlap, occasional erroneous stored values ​​can be detected and corrected using error correction codes.

[0025] However, over time and with multiple write / read operations, the distribution can shift, expand, or otherwise distort, potentially compromising the specificity of the representation of different stored values, leading to eventual failure of the memory device. Such memory failures, when unexpected, can lead to loss of critical data and broader system failure. Deterioration of a memory device's distribution often occurs gradually over time and can be detected at an early stage, before catastrophic failure occurs. However, traditional distribution monitoring is time-consuming and relies on human intervention for accurate data analysis.

[0026] Aspects of the present disclosure address the above-mentioned and other deficiencies by including a memory subsystem that includes a trained classifier capable of detecting distribution features (e.g., shifts, tails, erasures, etc.) that may indicate an impending failure. In some embodiments, the classifier may be a trained machine learning model. The classifier may be trained on multiple data sets (e.g., distribution histograms), which may include data sets representing good memory devices (those not at risk of failure) and faulty and / or critical devices (those likely to fail within a specific time period). During the training phase, the classifier may establish a correlation between a set of specific distribution features (e.g., the simultaneous presence of various tails in multiple distributions) and the likelihood of failure. During the detection (identification) phase, the trained classifier may obtain a histogram representing the distribution of voltage thresholds for a subset of memory cells in the memory device being tested, extract the distribution features, and classify the distributions into several categories. Based on the obtained categories, the classifier may determine the likelihood that the memory device will fail in the near future.

[0027] Advantages of the present disclosure include, but are not limited to, the ability to quickly and automatically monitor the acoustics of memory devices in "real time." Traditionally, the use of distribution histograms for product control has been hampered by the significant time required to collect the distribution data and analyze the histograms. Although data collection time has been significantly reduced in hardware accelerated platform solutions, analysis still requires manual engineering input and represents a critical bottleneck in efficient memory device monitoring. Large capacity storage platforms may require large amounts of distribution data to monitor, which can strain the engineers of even large scale memory device manufacturers. Furthermore, for post-sale monitoring of memory devices, smaller customers may have to incur significant expenses to perform such monitoring on a regular basis, or forgo it altogether. In this context, the automatic dynamic real-time detection of problematic memory issues represents a significant technical improvement.

[0028] Figure 1 An example computing system 100 is described according to some embodiments of the present disclosure that includes a memory subsystem 110. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or such combinations.

[0029] The memory subsystem 110 can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0030] Computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0031] The computing system 100 may include a host system 120 that is coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, etc.

[0032] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0033] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize a high-speed NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TTC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. Furthermore, the memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0040] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include the controller 115 and may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0041] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller for media management (e.g., local controller 135) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] Memory subsystem 110 includes a fault prediction component (FPC) 113 capable of determining the condition of one or more memory devices 130 and / or 140 (e.g., the distribution of voltage thresholds) and determining whether a memory device is likely to fail within a certain time interval in the future (e.g., next month, next week, etc.). In some cases, FPC 113 can determine the probability of failure for a given number of future memory operations (e.g., write, erase, reprogram, read, etc.). FPC 113 can further determine when a memory device is likely to fail based on average usage intensity (e.g., the number of write / read operations per time interval). In some embodiments, FPC 113 can initiate testing upon receiving an indication from the ECC (not shown) of controller 115 that the ECC was unable to correct errors in data associated with a write operation performed on a certain partition (page, block) of memory 130 (or 140, or any other memory device not shown). The ECC can be based on Hamming, Reed-Solomon, BCB, low-density parity check (LDPC), or any other error correction algorithm.

[0045] In some embodiments, FPC 113 may receive instructions from host system 120 to perform a check on the memory device. For example, the host system may detect corrupted data received from memory subsystem 110 that the memory subsystem controller 115 was unable to detect and / or correct. In some embodiments, FPC 113 may perform monitoring on the memory device at scheduled intervals even if no instructions to initiate the check are received from the memory subsystem controller 115 or the host system 120. In some embodiments, the monitoring schedule may be stored in local memory 119 (e.g., in an embedded memory of local memory 119).

[0046] In some embodiments, memory subsystem controller 115 includes at least a portion of FPC 113. For example, memory subsystem controller 115 may include processor 117 (processing device) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, FPC 113 is part of memory subsystem 110, an application, or an operating system. In some embodiments, FPC 113 may have configuration data, libraries, and other information stored in memory device 130 (and / or memory device 140).

[0047] FPC 113 may be based on one or more machine learning models. The model may include multiple layers of neurons and may be trained before being installed in memory subsystem 110. In some embodiments, the model may be based on the following Figure 2 The training phase can be performed on a separate computing system (e.g., at the manufacturer), embedded in local memory 119 during the production phase, and called by FPC 113 for planned monitoring and / or unplanned real-time inspections. More details on the operation of FPC 113 are described below.

[0048] Figure 2According to some embodiments of the present disclosure, a training phase 200 for training a machine learning classifier that can be used to predict the likelihood of a potential failure of a memory device (component) is schematically illustrated. To train a machine learning model to detect impending memory device failures, the training phase 200 may generate a training set for training the machine learning model. A training set generator 210 may generate training input 220, for example, by obtaining good device data 220A, failed device data 220B, modified good device data, manual input 220D, and the like. The training input 220 may include voltage distributions for various similar memory devices, such as memory devices having the same number of levels per memory cell as the target device being tested. For example, data related to similar TLC memory devices may be used to train a model intended to test a target TLC memory device that stores up to 8 bits per memory cell. In some embodiments, when used, a TLC memory device may no longer be able to store three bits per cell due to its widened threshold voltage distribution and therefore function as an MLC device (wherein a memory cell only stores 4 bits). Therefore, the training input 220 for such a TLC device may additionally include MLC (or even SLC) training data.

[0049] In some embodiments, the good device data 220A may include threshold distributions for various devices that, after inspection, an engineer (e.g., an engineer) deems unlikely to fail within a target time period (or a target number of memory operations). For example, the good device data 220A may have distributions that approximate a normal (Gaussian) distribution, with each distribution having such a mean and width (standard deviation) that there is insignificant overlap with other (e.g., adjacent) voltage distributions. If the overlap involves rare events (threshold voltages in a single cell) in both distributions that occur with sufficiently low probability, the overlap may be insignificant, e.g., 3 standard deviations, 3.5 standard deviations, etc., so that expected rare errors occurring at the scale of memory devices do not compromise device integrity. The good device data 220A may also include stronger overlap, e.g., 2.5 standard deviations, corresponding to more frequent events that are still correctable by the ECC of the memory subsystem controller 115.

[0050] In some embodiments, the failed device data 220B may include threshold distributions for various devices that have failed or are considered likely to fail within a target time period (or after a target number of operations) after inspection. For example, the failed device data 220B may include distributions that deviate from a well-defined distribution. For example, a distribution may still be normal, but shifted so significantly toward a neighboring distribution that the ECC is unable to correct the resulting errors. This may occur when a read operation returns too many incorrect values ​​(different from the values ​​originally stored in the memory cells). As another example, the failed device data 220B may include distributions that have expanded significantly enough to reach a neighboring distribution, resulting in unacceptable overlap between the two distributions (e.g., 2 standard deviations, 2.5 standard deviations, etc.). As another example, one or more of the distributions may be non-normal and form tails that extend far enough into the neighboring distributions. In some failed devices, if present alone, none of the distributions may have a significant shift / tail / expansion that would result in a failure. However, when considered in their entirety, multiple distributions with smaller deviations may still indicate compromised device integrity and, therefore, may be included in the faulty device data 220B.

[0051] In some embodiments, good device data 220A and failed device data 220B may include distributions for various real (physical) devices. However, because collecting such real data from many physical devices can sometimes be an extremely difficult or expensive task, training input 220 may additionally include modified device data 220C. In some implementations, modified device data 220C may be based on (real or ideal) memory devices that are in good condition, but whose threshold distributions have been artificially modified to resemble those of failed devices or devices that may fail in the future. For example, a set of good distributions may be artificially shifted, enlarged, or equipped with tails that extend further outward to lower (bottom tail) or higher (top tail) threshold voltage values. In some implementations, modified device data 220C may be based on distributions for actual memory devices that have failed (or are considered at risk of failure), but modified in a manner that reduces critical characteristics. For example, some tails may be reduced or even removed entirely, some distributions may be shifted back closer to their normal positions, shrunk, etc.

[0052] The training input 220 may further include human input 220D. In some embodiments, the human input 220D may include classifications of other input data. For example, the human input may rank the good device data 220A and the failed device data 220B by placing various threshold voltage distributions into multiple buckets ranked by the likelihood of failure within a target time after testing. In one exemplary embodiment, the distribution may be ranked by bucket number (using a scale from 0 to 10), where bucket number 0 corresponds to memory devices that have less than a 1% probability of failure within the next month. Bucket 1 may correspond to approximately a 10% probability of failure, bucket 2 may correspond to a 20% probability, and so on, with bucket 10 corresponding to a substantial certainty of failure within the target time. The bucket numbers may be used to Figure 2 and can be processed by the classifier's neural layers to establish an association between the likelihood of a fault and specific features of the training distribution.

[0053] Various training inputs 220 may be selected by a training set generator 210, which may also select target outputs 230, such as likelihood of device failure 232. The training set generator 210 may further establish input-output associations 235 between the training inputs 220 and corresponding target outputs 230. In establishing the input-output associations 235, the training set generator may use a grouping and clustering algorithm, such as the Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm or a similar algorithm. The training set generator 210 may further store the training set, including the training inputs, exited target outputs, and input-output associations, on a computer-readable storage medium (not shown).

[0054] Figures 3A to 3C Various possible threshold voltage distributions of memory devices are described. In some embodiments, Figures 3A to 3C The distribution shown in can correspond to Figure 2 In other embodiments, Figures 3A to 3C The distribution shown in may correspond to the target input of the detection (recognition) stage. In some embodiments, Figures 3A to 3C The distribution shown in FIG can describe the state of a transistor-based memory cell, such as a metal oxide semiconductor field effect transistor (MOSFET) memory cell. The transistor can have a source electrode and a drain electrode through which current passes. The memory cell can further have a control gate electrode to receive a voltage signal V CG To control the magnitude of the current flowing between the source electrode and the drain electrode. In some embodiments, the gate voltage V T (also referred to herein as the “threshold voltage”) CG <V T) can result in low source-drain current. Once the control gate voltage has exceeded the threshold voltage (V CG >V T ), the current can increase significantly. Because the actual geometry of the gate and electrodes of the memory cell (and the memory cell's environment) can vary from cell to cell, the threshold voltage V T Even transistors implemented on the same die may be different. Therefore, transistors of the same memory device can be represented by the distribution of their threshold voltages (P(V T )=dW / dV T ) characterization, where dW=P(V T )dV T Any given transistor has a T ,V T +dV T ] is the probability of the threshold voltage being within .

[0055] In a memory device having a non-volatile memory cell, the cell may further be provided with a conductive island (floating gate) which is electrically isolated from the control gate, source electrode and drain electrode by an insulating layer. In response to a suitably selected positive (relative to the source potential) control gate voltage V CG , the floating gate can receive (via Fowler-Nordheim tunneling or hot electron injection) a negative charge Q that can remain permanently on the floating gate even after power to the memory cell (and therefore the source-drain current) is stopped. T ) compared to the charge q, the presence of the threshold voltage distribution P q (V T ) shift. This is because a stronger positive control gate voltage V CG to overcome the negative potential of the floating gate charge q. If the sequence q k Any charge in the charge (where 1≤k≤2 N ) can be selectively programmed (and later detected during a read operation) into a memory cell, the memory cell can then function as an N-bit memory cell. To properly function as a memory cell, the cell should ideally have adjacent voltage distributions P that are sufficiently separated (e.g., by valley tolerance) q (V T ).

[0056] Figure 3A Some embodiments of the present disclosure schematically illustrate structured histograms depicting threshold voltage distributions of robust memory cells capable of storing three bits of data. Figure 3A Shows the threshold voltage distribution P(V) for 8 different charge states of a triple-level cell (TLC) T). The numbers 0, 1...7 enumerate the various states of TLC. For example, a memory cell programmed to charge state 0 can represent the stored value 111, state 1 can represent the stored value 011, state 2 can represent the stored value 001, and so on. Figure 3A The distribution in illustrates some memory devices that have a robust separation ("good distribution") between the various charge states of the memory cells. Figure 3A The distribution in can (in some cases) be approximated by a normal (Gaussian) distribution.

[0057] Figure 3B Conditional histograms are schematically illustrated according to some embodiments of the present disclosure, depicting the threshold voltage distribution of damaged TLC memory cells. Figure 3B The distribution is described as good 0, 1, 2, 5, 6 and 7, which is consistent with Figure 3A In contrast, distributions 3 and 4 are distorted distributions. Distribution 3 is a “bottom tail” distribution that extends beyond the normal distribution toward the threshold voltage V T Distribution 3 is a “top tail” distribution that extends beyond the normal distribution toward the threshold voltage V T Distribution 3 overlaps significantly with neighboring distribution 2 (and even extends to the V corresponding to distribution 1). T ). Thus, in one illustrative example, a large portion of the device's memory cells cannot reliably distinguish between the stored values ​​101 and 001. Similarly, in one illustrative example, Distribution 4 and Distribution 5 overlap significantly, which can result in a lack of distinction between the stored values ​​100 and 000. (The actual value may depend on the specific encoding scheme used by the memory device being tested.)

[0058] Figure 3A and 3B The distribution depicted in is a "structured" histogram, where different charge states have separately displayed distributions. In contrast, Figure 3C Some embodiments according to the present disclosure schematically illustrate unstructured distributed data, such as may be collected by the memory subsystem controller 115 . Figure 3C The unstructured data depicted in FIG may be the sum of all distributions collected as part of the hardware background check operation. In some embodiments, the memory subsystem controller 115 may perform the separation of the unstructured data into Figure 3A and 3BA set of structured histograms is depicted in [ ]. For example, a machine learning model can be trained using unconditional data. To reduce the number of possibilities for a data element to belong to various distributions (e.g., the top and bottom tails of two adjacent distributions), a window function can be used to extract data belonging to various distributions. This can be used to predict each extracted distribution. Training data can be generated by combining unconditional data with data whose association with a specific distribution is known.

[0059] Figure 4 According to some embodiments of the present disclosure, exemplary classifications of various characteristics of threshold voltage distributions are described. A good distribution (depicted by a dotted line) may be a normal distribution or some other controlled distribution. An enlarged distribution may have the same mean (or median) as the good distribution, but may have a different (larger) width. A shifted distribution may have the same width as the good distribution, but a different mean (or median). In some embodiments, the processing device performing the classification may ignore enlargements that are less than some predetermined threshold (e.g., 0.5 standard deviation, 0.75 standard deviation) and treat the corresponding distribution as a good distribution. Similarly, in some embodiments, shifts that are less than some predetermined threshold shift (e.g., 0.25 standard deviation, 0.5 standard deviation) may be ignored. In some embodiments, the mean and standard deviation of the good distribution may be stored in the memory subsystem 110, for example, in the local memory 119.

[0060] A distribution with a tail extending into high values ​​of the threshold voltage may be classified as a "top tail." A distribution with a tail extending into low values ​​of the threshold voltage may be classified as a "bottom tail." In some embodiments, a weak but long tail corresponding to a rare event (an accidental memory cell) (described below with respect to FIG. Figure 8 In some embodiments, the distribution may be classified into two categories (in the more quantitative sense described herein) and may be ignored. Similarly, strong but short tails that do not deviate far from the mean (or median) may also be ignored. In the case where a distribution has two tails extending towards higher and lower voltages, the processing device performing the classification may classify such a distribution as a "top and bottom tail" distribution. In some embodiments, additional categories of distributions may be implemented. For example, the various tail categories may be subdivided into multiple subcategories that identify the strength of the tails. In some embodiments, the tails may be quantified by calculating the degree of deviation of the mean squared deviation in the actual distribution from the standard deviation of a good distribution. In some embodiments, calculations may be performed on the bottom / top portion of the distribution in order to distinguish between the bottom tail and the top tail. In other embodiments, the processing device may use various other schemes to quantify the tail strength.

[0061] Figures 5A to 5C According to some embodiments of the present disclosure, various threshold voltage distributions of memory devices are described. In some embodiments, Figures 5A to 5C The distribution shown in can correspond to Figure 2 In other embodiments, Figures 5A to 5C The distribution shown in may correspond to the training input. Figure 5A According to some embodiments of the present disclosure, a structured histogram is described that depicts the actual threshold voltage distribution of robust TLC memory cells, where the various distributions are well separated from each other. Figure 5A As depicted in , some distributions (e.g., 1 and 5) may be closer to a normal distribution, while other distributions (e.g., 7) may deviate significantly from a normal distribution. Therefore, robust separation between distributions may be a better indicator of a good memory device than how close a particular distribution is to a normal distribution.

[0062] Figure 5B According to some embodiments of the present disclosure, a structured histogram is described that depicts the actual threshold voltage distributions of damaged TLC memory cells, some of which overlap significantly with each other. Figure 5B As depicted in , distributions 0, 1, 2, and 3 have top tails, with distributions 0 and 1 showing the most pronounced tails. Figure 5B A histogram of may indicate that the distinction between states 0 and 1, 1 and 2, 2 and 3, and (possibly) 3 and 4 is significantly impaired, to the point where ECC may be unable to erroneously correct subsequent hardware failures.

[0063] Figure 5C According to some embodiments of the present disclosure, a structured histogram is described that depicts the actual threshold voltage distribution of damaged TLC memory cells, some of which are erased. Figure 5C , all distributions are essentially indistinguishable from each other. However, in other cases, only some distributions (eg, 5, 6, and 7) may be erased, while other distributions may be good (or have characteristics as described above).

[0064] Figures 6A to 6C The quantile-quantile representation of various threshold voltage distributions relative to a control distribution is illustrated. The control distribution can be the actual distribution of good devices or some model distribution (e.g., a normal distribution) that approximates an ideal memory device. In some embodiments, Figures 6A to 6C The various distributions described in may correspond to Figure 2 In other embodiments, Figures 6A to 6C The distribution shown in may correspond to the training input. Figure 6A According to some embodiments of the present disclosure, the classification of some exemplary tail features is illustrated using a quantile-quantile representation (QQR) of the threshold voltage distribution of a particular state of a memory cell corresponding to a target device distribution relative to a control distribution. The QQR can map the distribution of actual target device threshold voltages P(V) to the control distribution P(V). C(V). The processing device for constructing the QQR can first determine (e.g., by calculating the available points in the available dataset) the quantile Q (e.g., percentile) of the target distribution, P(V) → Q(V). The quantile Q(V) together with its reciprocal V(Q) represents specific threshold voltages V corresponding to various percentiles (e.g., Q = 0.1 can correspond to the 10th percentile of the distribution P(V), Q = 0.84 can correspond to the 84th percentile, etc.). Similarly, the control distribution P C (V) can have its own set of quantiles Q C : P C (V) → Q C (V). The QQR can be (in some embodiments, quasi - continuous) a plot Q(V(Q C )), which indicates the position of the target quantile Q relative to the various quantiles Q C of the control distribution. As shown in Figure 6A , the target distribution consistent with the control distribution is represented by the dashed line Q = Q C .

[0065] Figure 6A Describe various possible deviations (characteristics) of the target distribution P(V) from the control distribution based on the QQR. For example, tail A is the top tail, which indicates a significant deviation from the control distribution starting from approximately +1 standard deviation and represents a possible negative performance of the target memory device. Tail B is the bottom tail, which indicates a significant deviation from the control distribution starting from approximately - 3 standard deviations. In some cases, such tails may indicate relatively insignificant performance issues of the memory device because they are limited to voltage ranges corresponding to relatively rare (as low as 1%) events (in other words, only rare memory cells have threshold voltages within tail B). Therefore, tails B and other tails limited to very low or very high quantiles (e.g., whose occurrence probability is below a certain cutoff value, such as + or - 3 standard deviations) can be ignored. As another example, tail C is the bottom tail, which (unlike tail B) starts from a relatively common event (-1 standard deviation), but in some embodiments, it can similarly be ignored because it does not deviate far enough from the control distribution and is thus less likely to cross into the adjacent state distribution. In some embodiments, the following procedure can be implemented to determine whether a tail is ignored. First, a tail in which all or most points (e.g., more than 80% or 90% of the total tail points) correspond to rare events (|Q| > Q1 (e.g., Q < - 3 standard deviations or Q > 3 standard deviations)) can be ignored. Second, a tail that starts (or whose points are mostly limited) within the region |Q| < Q1 can also be ignored, provided that the tail starts from the line Q = Q CRemain within a second cutoff value Q2 (at least until it reaches the first cutoff value Q1): |ΔQ| < Q2. In various embodiments, the distance ΔQ may be determined along the horizontal direction of the QQR plot, along the vertical direction of the QQR plot, or along the shortest distance direction from the diagonal Q = Q C or otherwise. Those skilled in the art will appreciate that the above are just some exemplary scenarios, and there are almost infinite ways to establish the time when a particular tail can be ignored as it represents 1) a rare event, or 2) an insignificant deviation from the control distribution that will not have a substantial impact on the memory device functionality. In some embodiments, the cutoff values for the top tail and the bottom tail may be selected to be different from each other.

[0066] Figure 6B A set of exemplary quantile - quantile representations of seven different threshold voltage distributions of a TLC memory device is illustrated in accordance with some embodiments of the present disclosure. Distribution 7 is shown to have a valid bottom tail (starting from about - 2 standard deviations), while the tail of distribution 6 can be ignored because although it starts from about - 2.5 standard deviations, it does not deviate significantly from the straight line before it reaches the cutoff value of - 3 standard deviations. Figure 6C Another set of exemplary quantile - quantile representations of seven different threshold voltage distributions of another TLC memory device is illustrated in accordance with some embodiments of the present disclosure. Distribution 7 has a valid bottom tail, while the tail of distribution 6, although significant, is limited to values less than - 3.5 standard deviations. Also, a top tail in distribution 2 that can be ignored is schematically depicted (by the dashed line) because it does not deviate significantly from the straight line before it reaches the cutoff value (e.g., + 3 standard deviations). The dashed tail in distribution 2 illustrates how a well - distributed set (e.g., edited by an engineer) can be modified to diversify a set of available memory device distributions for training a classifier.

[0067] Figure 7 and Figure 8 illustrate method 700 and method 800, respectively. Method 700 or method 800 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device) or a combination thereof. Although shown in a particular order, the order of operations may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations may be performed in a different order, where some operations may be performed in parallel. Additionally, one or more operations may be omitted in various embodiments. Thus, not every embodiment requires all the operations of method 700 or method 800. Other operation flows are possible. In other embodiments, different operations may be used. It may be noted that aspects of the present disclosure may be used for any type of multi - bit memory cell.

[0068] Figure 7 A flowchart illustrating an example method 700 for predicting the likelihood of a potential failure of a memory device (component) according to some embodiments of the present disclosure is provided. In one embodiment, FPC 113 may execute example method 700 based on instructions stored in an embedded memory of local memory 119. In some embodiments, firmware of memory subsystem 110 (or memory device 130) may execute example method 700. In some embodiments, an external processing device, such as a processing device of host system 120, may execute example method 700.

[0069] The method 700 may include obtaining, by a processing device, a plurality of threshold voltage distributions for a memory component (e.g., memory device 130) (operation 710). The processing device (e.g., processor 117) may be operatively coupled to the memory component. The memory component may include a plurality of memory cells. Each or some of the memory cells may have a plurality of states corresponding to various values ​​that the memory cells can store. Each of the plurality of distributions may correspond to one of the states of the memory cell. An SLC memory component may have two distributions, an MLC memory component may have four distributions, a TLC memory component may have eight distributions, a QLC memory component may have sixteen distributions, and so on. In some embodiments, the memory controller 115 may determine the threshold voltage distributions for a representative subset of the memory cells of the memory component. For example, in some embodiments, the subset may include a random sampling of word lines of the memory component. In some embodiments, thousands of memory cells (e.g., a 2 kB memory block) may be sampled. The number of distributions obtained may be equal to the number of different values ​​that can be stored per memory cell of the component. In some embodiments, the number of distributions obtained may be less than the number of storable values. For example, in some embodiments, the lowest distribution (distribution 0) may be omitted. In some embodiments, a processing device executing method 700 may obtain a plurality of threshold voltage distributions in response to an error correction module detecting that a memory component fails to correctly store data during a store (write) operation.

[0070] In operation 720, the processing device executing method 700 may classify each of the plurality of obtained distributions into one of a plurality of categories. In one exemplary embodiment, the j-th distribution may belong to one of the following seven categories: good distribution (C j =0), top tail distribution (C j =1), bottom tail distribution (C j =2), top and bottom tail distribution (C j =3), expand distribution (C j =4), shift distribution (C j =5), and erasure distribution (C j=6). In some embodiments, the number of categories can be reduced, for example, no category is created corresponding to the expanded and / or shifted distribution. In other embodiments, more than seven categories can be used. For example, the top and / or bottom tail distributions can be further subdivided into multiple subcategories specifying the strength of the respective tails.

[0071] At operation 730, the processing device executing method 700 may generate a vector representation of the distribution of the memory component. The vector may have a number of components equal to the number of distributions, for example, C = (C0, C1 = 1, ... C7). The components of vector C may represent the category of the corresponding distribution (memory state). For example, vector C = (0, 0, 1, 6, 0, 3, 0, 0) may represent that distribution 2 has a top tail, distribution 5 has both a top tail and a bottom tail, distribution 3 is erased, and the remaining distributions are good. In some embodiments, vector C may alternatively be represented using the category as an index (label representation). For example, the above distributions may be categorized as follows (where the specific distribution is listed after each category label):

[0072] “Good”: 0, 1, 4, 6, 7;

[0073] "top tail": 2;

[0074] "Bottom tail": –;

[0075] "Top and bottom tail": 5;

[0076] "expand":-;

[0077] “Shift”: –;

[0078] "Erase":3.

[0079] Method 700 may continue at operation 740 by processing the device to analyze the generated vector (or its label representation) using a classifier to determine the likelihood that the memory component will fail within the target time period. In one exemplary representation, the classifier may be a machine learning model trained as described above. In some embodiments, the classifier may be any processor-operated model or code that, once trained, is capable of analyzing the distribution of voltages to determine the likelihood of failure without human input or supervision. In some embodiments, the classifier may be a classifier that uses the vector components C j A formula takes as input, performs a set of mathematical operations on the input vector components, and outputs a value representing the probability of failure. In some embodiments, the value can be between 0 and 10 (between 0 and 100, or within any other set range), where 0 indicates a very unlikely failure and 10 indicates a nearly certain failure. In some embodiments, the output can have an estimated probability of failure (e.g., 65%).

[0080] Figure 8 A flowchart illustrates an example method 800 for classifying multiple distributions of memory components into one of multiple categories, according to some embodiments of the present disclosure. In some embodiments, method 800 may be performed as part of operation 720 of method 700. In one embodiment, FPC 113 may perform example method 800 based on instructions stored in embedded memory of local memory 119. In some embodiments, firmware of memory subsystem 110 (or memory device 130) may perform example method 800. In some embodiments, an external processing device, such as a processing device of host system 120, may perform example method 800.

[0081] Method 800 may include obtaining, by a processing device, a threshold voltage distribution for a given state of memory cells in a second memory component (operation 810). In one exemplary embodiment, the distribution may be Figures 3A-3C , 5A-5C, and 6A-6C. Method 800 may continue with the processing device obtaining a quantile-quantile representation (QQR) of the distribution relative to the control distribution (operation 820). At operation 830, method 800 may continue with the processing device identifying the presence of tails in the QQR of the distribution (the processing device may be able to extract distribution characteristics from the digital QQR without generating an actual plot). The processing device may be able to identify more than one tail, for example, a first tail (which may be a top tail) and a second tail (which may be a bottom tail). In such a case, the described operations may be performed with respect to the first tail and the second tail.

[0082] At decision operation 835, the processing device may determine whether the (first or second) tail corresponds to an event with a probability of occurrence below a first cutoff value (e.g., Q1), as described above with respect to Figures 6A to 6CAs explained. If the tail corresponds to such a rare event, then method 800 may continue to treat the first tail as not existing (operation 840). If the tail corresponds to an event with a probability of occurrence below a first cutoff value Q1, method 800 may continue to decision operation 845, wherein the processing device may determine whether the tail corresponds to a deviation ΔQ from the control distribution below a second cutoff value Q2. If so, then method 800 may continue to perform operation 840 and treat the tail as not existing. When the tail corresponds to an event whose probability of occurrence is at or above the value represented by the second value Q2, the processing device executing method 800 may treat the tail as valid (operation 850). Then, method 800 may continue to identify the tail as one of the top tail or the bottom tail and assign the distribution to the corresponding category of the distribution. Method 800 may also (optionally) continue with the processing device to identify whether the distribution (first and / or second) has moved, expanded, etc. (operation 860). The output of method 800 may be to assign the distribution among multiple categories, as described above. The processing device may repeat method 800 to implement some or all of the resulting threshold voltage distributions.

[0083] Figure 9 According to some embodiments of the present disclosure, a flowchart illustrates an example method 900 for training a machine learning model to determine the likelihood of failure of a memory component. In some embodiments, a processing device of a computing system on the manufacturer side of the memory component may execute example method 900 and implement the training model in memory subsystem 110. In some embodiments, a processing device of host system 120 may execute example method 900. In one embodiment, FPC 113 may execute example method 900. Example method 900 may involve, by a processing device, obtaining a training input comprising a plurality of threshold voltage distributions for a memory component (operation 910). Each of the plurality of threshold voltages may correspond to one of a plurality of states of a memory cell of the memory component. Example method 900 may continue with the processing device obtaining a target output (operation 920). The target output may include a target likelihood (e.g., probability) of failure of the memory component within a target time interval. In some embodiments, the target time interval may be measured in days, weeks, months, etc. In some embodiments, the target time interval may be measured over a plurality of memory operations (read, write, erase, etc.).

[0084] A processing device executing method 900 may process a training input using a neural network model (operation 930). The neural network model may include a plurality of neurons associated with learnable weights and biases. The neurons may be arranged in layers. The neural network model may process the training input using one or more neuron layers and generate a training output. The training output may include a predicted likelihood of a memory component failure occurring within a target time interval. In some embodiments, the predicted likelihood may be a numerical value, such as 20%, 65%, or the like. In other embodiments, the predicted likelihood may be a discrete category, such as "unlikely," "likely," "certain," or the like. At operation 940, the processing device executing method 900 may determine a difference between the predicted failure likelihood and the target failure likelihood. For example, the processing device may determine the difference between two probabilities (the predicted likelihood and the target likelihood). In those embodiments, where discrete prediction categories are used, the difference may include an indication of whether the two possibilities belong to the same category. For example, if both possibilities belong to the "very likely" category, the processing device may not detect any difference. As another example, if the predicted likelihood belongs to the "unlikely" category and the target likelihood is the "likely" category, the processing device may determine the difference to be "underestimated."

[0085] Having determined the likelihood difference, the processing device may modify (adjust) the parameters of the neural network model based on the determined difference (operation 950). In one exemplary embodiment, the modification of the parameters of the neural network model (e.g., weights of neural connections, biases, etc.) may be performed using a backpropagation method. For example, the parameters may be adjusted to minimize the difference between the target output and the predicted output generated by the neural network.

[0086] In some embodiments, the neural network model may include a first neuron sub-network and a second neuron sub-network. The first sub-network may be configured to process training inputs and generate intermediate outputs, which may include a distribution category, and the second sub-network may be configured to determine a predicted fault probability based on the intermediate outputs (distribution category).

[0087] In some embodiments, the second sub-network may perform a clustering (grouping) operation using the plurality of training inputs (distributions) to create a vector group, such as vector C, as described with respect to method 700. For example, the processing device executing method 800 may use one of the following clustering algorithms: a DBSCAN algorithm, an autoencoder (e.g., a variational autoencoder), a K-means clustering, an expectation-maximization algorithm, a mean-shift algorithm, a termination algorithm, a generalization algorithm, a singular value decomposition algorithm, or other suitable algorithms.

[0088] After clusters (groups of vectors C) are determined during the training phase, they can be used during the identification phase. A processing device (e.g., a device executing methods 700 and 800) can compare the values ​​of vector C for the target memory device under test and determine to which cluster the vector belongs. The proximity of a vector to a particular cluster can be estimated using a similarity function (correlation function, similarity metric) or a difference function. For example, the jth cluster may have a specific centroid value for each component of vector C belonging to that cluster. The processing device can determine the correlation between vector C and the jth cluster by calculating the distance (in vector component space) between the target memory device's vector C and each cluster centroid determined during training.

[0089] Clusters (groups) may depend on characteristics of multiple (in some embodiments, all) distributions. For example, a cluster may include distributions (memory devices) characterized by "top tails in distributions 0, 1, and 3, and bottom tails in distributions 5 and 6." Another cluster may include instances of "top tails and bottom tails in at least three distributions." In some embodiments, a cluster may include the context that caused the processing device to seek distribution data (e.g., an operational history that resulted in errors that cannot be corrected by ECC) or the physical context of the memory device (e.g., whether the memory component selected for analysis is fully or partially programmed). For example, a cluster may include "top tails in distributions 5, 6, and 7 after multiple reads on a partially programmed block."

[0090] Figure 10 An example machine illustrating a computer system 1000 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In some embodiments, the computer system 1000 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform operations of the controller (for example, execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0091] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be performed by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0092] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1018, which communicate with each other via a bus 1030.

[0093] Processing device 1002 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. Computer system 1000 may further include a network interface device 1008 for communicating via a network 1020.

[0094] The data storage system 1018 may include a machine-readable storage medium 1024 (also referred to as a non-transitory computer-readable storage medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein. The instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002 during execution of the instructions by the computer system 1000, with the main memory 1004 and the processing device 1002 also constituting machine-readable storage media. The machine-readable storage medium 1024, the data storage system 1018, and / or the main memory 1004 may correspond to Figure 1 Memory subsystem 110.

[0095] In one embodiment, instructions 1026 include instructions to implement the corresponding Figure 1The functionality of the fault prediction component 113 is shown in the example embodiment. Although the machine-readable storage medium 1024 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be taken to include (but not be limited to) solid-state memory, optical media, and magnetic media.

[0096] Some portions of the foregoing detailed description have been presented in terms of symbolic representations of operations on data bits and operations within a computer memory. These algorithmic descriptions and representations are a means used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm or operation is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, or otherwise manipulated. It has proven convenient at times, primarily for reasons of commonality, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0097] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0098] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for a particular purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any other type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0099] The algorithms, operations, and displays presented herein are not inherently related to any particular computer or other device. Based on the teachings herein, various general-purpose systems may be used with the program, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be described below. Additionally, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0100] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0101] The words "example" or "exemplary" are used herein to mean "serving as an example, instance, or illustration." Any aspect or design described herein as an "example" or "exemplary" should not necessarily be construed as preferred or advantageous over other aspects or designs. Rather, the use of the words "example" or "exemplary" is intended to present concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing circumstances. Additionally, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more," unless otherwise specified or clear from the context to be directed to the singular. Furthermore, the use of the terms "embodiment," "one embodiment," "an embodiment," etc., throughout the application is not intended to refer to the same embodiment unless otherwise described. One or more embodiments or embodiments described herein may be combined in a specific embodiment. As used herein, the terms "first," "second," "third," "fourth," etc. are intended to be marks for distinguishing different elements and may not necessarily have ordinal meanings according to their numerical designations.

[0102] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory system comprising: a memory component comprising a plurality of memory cells, wherein each memory cell of the plurality of memory cells is capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell; and a processing device operatively coupled to the memory component to perform operations comprising: obtaining a plurality of threshold voltage distributions for the plurality of memory cells, wherein each of the plurality of threshold voltage distributions corresponds to one of the plurality of states; classifying each of the plurality of threshold voltage distributions into one of a plurality of categories; generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a corresponding one of the plurality of threshold voltage distributions; and The generated vector is processed using a classifier to determine a likelihood that the memory component will fail within a target time period. 2 . The memory system of claim 1 , wherein classifying a first distribution of the plurality of threshold voltage distributions comprises identifying a first tail in a quantile-quantile representation of the first distribution relative to a control distribution. The memory system of claim 2 , wherein the control distribution is a normal distribution.

4. The memory system of claim 2 , wherein classifying the first distribution among the plurality of threshold voltage distributions further comprises: determining that the first tail corresponds to an event with a corresponding probability of occurrence lower than a first cutoff value; and The first tail is considered not to exist.

5. The memory system of claim 2 , wherein classifying the first distribution among the plurality of threshold voltage distributions further comprises: determining that the first tail corresponds to a deviation from the control distribution, wherein the deviation is below a second cutoff value; and The first tail is considered not to exist.

6. The memory system of claim 2 , wherein classifying the first distribution of the plurality of threshold voltage distributions comprises identifying the first tail as one of a top tail and a bottom tail, wherein the top tail corresponds to a threshold voltage that is higher than a mean of the first distribution, and wherein the bottom tail corresponds to a threshold voltage that is lower than the mean of the first distribution. 7 . The memory system of claim 2 , wherein classifying a second distribution of the plurality of threshold voltage distributions comprises identifying a shift of the second distribution relative to the control distribution.

8. The memory system of claim 1, wherein the classifier comprises a machine learning model.

9. The memory system of claim 8 , wherein the machine learning model is trained based on training inputs, target outputs, and associations between the training inputs and the target outputs, wherein the training inputs include training multiple threshold voltage distributions, wherein the training multiple threshold voltage distributions include one of multiple threshold voltage distributions for faulty memory components, multiple threshold voltage distributions for good memory components, or multiple threshold voltage distributions for good memory components modified to simulate faulty memory components.

10. The memory system of claim 9, wherein the target output comprises a probability that a memory component having the trained plurality of threshold voltage distributions will fail within the target time period.

11. The memory system of claim 1 , wherein obtaining the plurality of threshold voltage distributions comprises: Collect unstructured threshold voltage data; and The unstructured threshold voltage data is converted into the plurality of threshold voltage distributions corresponding to each of the plurality of states.

12. The memory system of claim 1, wherein obtaining the plurality of threshold voltage distributions is responsive to an error correction module detecting that the memory component cannot correctly store data after a storage operation.

13. A method for predicting the likelihood of a memory component failing, comprising: obtaining, by a processing device operatively coupled to the memory component comprising a plurality of memory cells, a plurality of threshold voltage distributions, wherein each of the plurality of threshold voltage distributions corresponds to one of a plurality of states of a memory cell of the plurality of memory cells, wherein each state of the plurality of states corresponds to a value stored by the memory cell; classifying each of the plurality of threshold voltage distributions into one of a plurality of categories; generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a corresponding one of the plurality of threshold voltage distributions; and The generated vector is processed using a classifier to determine a likelihood that the memory component will fail within a target time period. 14 . The method of claim 13 , wherein classifying a first distribution of the plurality of threshold voltage distributions comprises identifying a first tail in a quantile-quantile representation of the first distribution relative to a control distribution. The method of claim 14 , wherein the control distribution is a normal distribution.

16. The method of claim 14, wherein classifying the first distribution among the plurality of threshold voltage distributions further comprises: determining that the first tail corresponds to an event with a corresponding probability of occurrence lower than a first cutoff value; and The first tail is considered not to exist.

17. The method of claim 14, wherein classifying the first distribution among the plurality of threshold voltage distributions further comprises: determining that the first tail corresponds to a deviation from the control distribution, wherein the deviation is below a second cutoff value; and The first tail is considered not to exist.

18. The method of claim 14, wherein classifying the first distribution of the plurality of threshold voltage distributions comprises identifying the first tail as one of a top tail and a bottom tail, wherein the top tail corresponds to a threshold voltage above a mean of the first distribution, and wherein the bottom tail corresponds to a threshold voltage below the mean of the first distribution.

19. The method of claim 14, wherein classifying a second distribution of the plurality of threshold voltage distributions comprises identifying a shift of the second distribution relative to the control distribution.

20. The method of claim 13, wherein obtaining the plurality of threshold voltage distributions is responsive to an error correction module detecting that the memory component cannot correctly store data after a storage operation.

21. A method for training a neural network model, comprising: obtaining, by a processing device, a training input comprising a plurality of threshold voltage distributions for a memory component, wherein each of the plurality of threshold voltage distributions corresponds to one of a plurality of states for each of a plurality of memory cells of the memory component, each state of the plurality of states corresponding to a value stored by the plurality of memory cells of the memory component; obtaining, by the processing device, a target output, the target output comprising a target probability of the memory component failing within a target time interval; The training input is processed by the neural network model comprising a plurality of neurons to obtaining the categories of the plurality of threshold voltage distributions by the processing device, and determining a predicted likelihood of failure of the memory component within the target time interval based on the outputted category; determining, by the processing device, a difference between the predicted likelihood of a failure occurring and the target likelihood of a failure occurring; and Parameters of the neural network model are modified, by the processing device, based on the determined differences.

22. The method of claim 21 , wherein the neural network model comprises a first neuron sub-network and a second neuron sub-network, wherein the first neuron sub-network processes the training input and outputs the categories for the plurality of threshold voltage distributions, and wherein the second neuron sub-network determines the predicted likelihood of a failure based on the outputted categories.

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