Semiconductor device and semiconductor package having the same

Abstract

A semiconductor device and a semiconductor package having the same are provided. The semiconductor device includes: a semiconductor chip having a first surface and a second surface opposite to the first surface; a first heat dissipation member located on the second surface of the semiconductor chip, the first heat dissipation member having a first vertical thermal conductivity in a direction perpendicular to the second surface and a first horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being less than the first horizontal thermal conductivity; and a second heat dissipation member including a vertical pattern passing through the first heat dissipation member, the second heat dissipation member having a second vertical thermal conductivity greater than the first vertical thermal conductivity of the first heat dissipation member.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0170815, filed with the Korean Intellectual Property Office on December 19, 2019, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to semiconductor devices and / or semiconductor packages having the same. Background art

[0004] As semiconductor devices such as mobile terminals have become highly integrated and multifunctional, and their power consumption has increased, the heat dissipation ability of semiconductor devices has recently become increasingly important. At the same time, there are spatial limitations for heat dissipation in highly integrated semiconductor devices. Therefore, semiconductor packaging technologies that can dissipate heat efficiently and utilize space suitable for high integration efficiently are needed. Summary of the invention

[0005] Some example embodiments may provide a semiconductor device and / or a semiconductor package having improved heat dissipation characteristics.

[0006] Some example embodiments may provide a method of manufacturing a semiconductor package having improved heat dissipation characteristics.

[0007] According to an example embodiment, a semiconductor device includes: a semiconductor chip having a first surface and a second surface opposite the first surface; a first heat dissipation member located on the second surface of the semiconductor chip, the first heat dissipation member having a first vertical thermal conductivity in a direction perpendicular to the second surface and a first horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being less than the first horizontal thermal conductivity; and a second heat dissipation member including a vertical pattern passing through the first heat dissipation member, the second heat dissipation member having a second vertical thermal conductivity greater than the first vertical thermal conductivity of the first heat dissipation member.

[0008] According to an example embodiment, a semiconductor device includes: a semiconductor chip including a first surface on which connection pads are provided and a second surface opposite the first surface; and a composite heat dissipation layer including: a graphite sheet located on the second surface of the semiconductor chip, and a plurality of metal patterns passing through the graphite sheet.

[0009] According to an exemplary embodiment, a semiconductor package includes: a package substrate including a redistribution layer; a semiconductor chip located on the package substrate, the semiconductor chip including a first surface and a second surface, the first surface including connection pads electrically connected to the redistribution layer, and the second surface being opposite to the first surface; a composite heat dissipation layer including a first heat sink and a vertical pattern, the first heat sink being located on the second surface of the semiconductor chip, the first heat sink having a first vertical thermal conductivity in a direction perpendicular to the second surface and a first horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being less than the first horizontal thermal conductivity, the vertical pattern passing through the first heat sink, and the vertical pattern having a second vertical thermal conductivity greater than the first vertical thermal conductivity of the first heat sink; and a sealing member located on the package substrate and covering the semiconductor chip.

[0010] According to an exemplary embodiment, a method of manufacturing a semiconductor device includes: preparing a wafer having a plurality of semiconductor chips; forming a mask pattern in a second region of one surface of the wafer such that a first region of the one surface of the wafer is exposed; forming a first heat sink in the first region of the one surface of the wafer, the first heat sink having a first vertical thermal conductivity in an interlayer direction perpendicular to the one surface and a first horizontal thermal conductivity in an in-plane direction horizontally parallel to the one surface, the first vertical thermal conductivity being less than the first horizontal thermal conductivity; forming pinholes in the first heat sink by removing the mask pattern to expose the second region of the wafer; forming a vertical pattern in the pinholes of the first heat sink, the vertical pattern having a second vertical thermal conductivity greater than the first vertical thermal conductivity of the first heat sink; and dicing the wafer together with the first heat sink having the vertical pattern formed thereon into a plurality of the semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a side cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0013] Figure 2 is a plan view of a composite heat dissipation layer taken along line II-II' of the semiconductor device along Figure 1 ;

[0014] Figures 3A to 3C is a plan view of various examples of a composite heat dissipation layer that can be employed in a semiconductor device according to an exemplary embodiment;

[0015] Figures 4A to 4E is a side cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment;

[0016] Figure 5 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0017] Figure 6 is taken along line VI-VI'; Figure 5 planar view of the semiconductor package;

[0018] Figures 7A to 7D is a side cross-sectional view showing a method of manufacturing a semiconductor package according to an exemplary embodiment;

[0019] Figure 8 and Figure 9 are side cross-sectional views of various examples of semiconductor packages according to some exemplary embodiments;

[0020] Figure 10A is a side cross-sectional view of a semiconductor package according to an exemplary embodiment, and Figure 10B is along Figure 10A planar view of the composite heat dissipation layer taken along line XB-XB' of the semiconductor package;

[0021] Figure 11A is a side cross-sectional view of a semiconductor package according to an exemplary embodiment, and Figure 11B is taken along line XIB-XIB'; Figure 11A planar view of the semiconductor package;

[0022] Figures 12 to 15 are side cross-sectional views of various examples of semiconductor packages according to some exemplary embodiments;

[0023] Figures 16A to 16C is a side cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment; and

[0024] Figure 17 is a side cross-sectional view of a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] Although the terms "same" or "identical" are used in the description of the exemplary embodiments, it should be understood that there may be some inaccuracies. Therefore, when an element or value is referred to as being the same as another element or value, it should be understood that the element or value is the same as the other element or value within the desired manufacturing or operating tolerances (e.g., ±10%).

[0027] When the terms "about" or "substantially" are used in connection with a numerical value in this specification, it means that the relevant numerical value includes manufacturing or operating tolerances (e.g., ±10%) around the recited numerical value. In addition, when the words "substantially" and "about" are used in connection with a geometric shape, it means that geometric precision is not required, but the variation range of the shape is within the scope of the present disclosure. In addition, whether a numerical value or a shape is modified to be "about" or "substantially", it should be understood that these numerical values and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the recited numerical values or shapes.

[0028] Figure 1 is a side cross-sectional view of a semiconductor device according to an exemplary embodiment, Figure 2 is along Figure 1 a plan view of a composite heat dissipation layer taken along line II-II' of the semiconductor device.

[0029] Based on Figure 1 and Figure 2 , a semiconductor device 10 according to an exemplary embodiment includes: a semiconductor chip 20 having a first surface 20A and a second surface 20B disposed opposite to each other; and a composite heat dissipation layer 50 disposed on the second surface 20B of the semiconductor chip 20.

[0030] The semiconductor chip 20 includes a semiconductor substrate 21 having an active surface and a non-active surface disposed opposite to each other. The active surface and the non-active surface correspond to the first surface 20A and the second surface 20B of the semiconductor chip, respectively. A plurality of active / passive elements (e.g., transistors) and connection pads connected thereto may be disposed on the active surface of the semiconductor substrate 21. For example, the semiconductor substrate 21 may comprise silicon. In another example, the semiconductor substrate 21 may comprise: a semiconductor atom such as germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0031] A passivation film 23 that exposes the connection pads 22 may be disposed on the active surface of the semiconductor substrate 21. For example, the passivation film 23 may be an oxide film or a nitride film, or a bilayer thereof.

[0032] The semiconductor chip 20 employed in the exemplary embodiment may be, for example, a processor chip, such as a central processing unit (e.g., central processing unit (CPU)), a graphics processing unit (e.g., graphics processing unit (GPU)), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc. Specifically, an application processor (AP), but not limited thereto. The semiconductor chip 20 may include a memory chip such as a volatile memory (e.g., dynamic random access memory (DRAM)), a non-volatile memory (e.g., read only memory (ROM)), a flash memory, etc., a logic chip such as an analog-to-digital converter, an application specific integrated circuit (ASIC), etc., or a power management integrated circuit (PMIC).

[0033] The composite heat dissipation layer 50 is disposed on the second surface 20B (i.e., the non-active surface) of the semiconductor chip 20 and includes a first heat dissipation member 52 and a second heat dissipation member 55 having different heat dissipation characteristics from each other.

[0034] The first heat dissipation member 52 is in the form of a sheet and has the following heat dissipation characteristics: the thermal conductivity in the direction perpendicular to the second surface 20B (the z direction) (hereinafter referred to as "vertical thermal conductivity" or in-plane thermal conductivity) is lower than the thermal conductivity in the direction parallel to the second surface 20B (the x-y direction) (hereinafter referred to as "horizontal thermal conductivity" or through-plane thermal conductivity). In this specification, the first heat dissipation member 52 is also referred to as a "heat sink". For example, the first heat dissipation member 52 may include at least one of graphite or graphene.

[0035] The second heat dissipation member 55 has a plurality of vertical patterns 55P passing through the first heat dissipation member 52, and the vertical thermal conductivity of the second heat dissipation member 55 is higher than the vertical thermal conductivity of the first heat dissipation member 52. The second heat dissipation member 55 employed in the present disclosure is disposed on the upper surface of the first heat dissipation member 52 and may further include a heat dissipation layer 55L connecting the plurality of vertical patterns 55P. The second heat dissipation member 55 may include a metal having a relatively high thermal conductivity in all directions. For example, it may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), or nickel (Ni).

[0036] The material of the second heat dissipation member 55 is not limited thereto. In some exemplary embodiments, the material of the second heat dissipation member 55 may include the same material as that of the first heat dissipation member 55, which is configured to provide improved thermal conductivity by changing its growth direction (see Figures 16A to 16C ).

[0037] In an exemplary embodiment, the first heat dissipation member 52 ensures or can effectively dissipate heat in the horizontal direction (x-y direction), but may have poor thermal conductivity in the vertical direction (z direction). To enhance heat dissipation in the vertical direction (z direction), a vertical pattern 55P passing through the first heat dissipation member 52 is introduced. Such a vertical pattern 55P can be configured to be in direct contact with the second surface 20B of the semiconductor chip 20. In the present exemplary embodiment, the heat dissipation layer 55L of the second heat dissipation member 55 is connected to the upper portion of the vertical pattern 55P to more actively or effectively dissipate heat in the vertical direction. As used herein, the term "first heat dissipation member 52" may refer to "the first heat sink". Similarly, the term "heat dissipation layer 55L" may refer to "the second heat sink".

[0038] In some exemplary embodiments, the first heat dissipation member 52 includes graphite, while the second heat dissipation member 55 may be a metal (e.g., Cu). Due to the layer structure, the vertical thermal conductivity of graphite is significantly lower than the horizontal thermal conductivity. For example, the horizontal thermal conductivity of graphite is as high as 1,500 W / m·k to 1,700 W / m·k, while its vertical thermal conductivity is only about 15 W / m·k.

[0039] By forming a vertical pattern 55P passing through the first heat dissipation member 52 in the thickness direction (i.e., the vertical direction) with a metal, vertical heat dissipation can be improved. For example, since the thermal conductivity of Cu is approximately 400 W / m·k in all directions, when the second heat dissipation member 55 is formed of Cu, the low vertical thermal conductivity (about 15 W / m·k) of the first heat dissipation member 52 can be improved.

[0040] In the present exemplary embodiment, the side surface of the composite heat dissipation layer 50 employed can be substantially coplanar with the side surface of the semiconductor chip 20. Specifically, the side surface of the first heat dissipation member 52 and the side surface of the heat dissipation layer 55L of the second heat dissipation member 55 can be substantially coplanar with the side surface of the semiconductor chip 20. Such a coplanar arrangement can be understood as the result obtained through the manufacturing method of the composite heat dissipation layer 50 (see Figures 7A to 7D ).

[0041] The surface area of the second heat dissipation member 55 (e.g., the vertical pattern 55P) can be in contact with the second surface 20B of the semiconductor chip 20 and can account for 1% to 50% of the total surface area of the second surface 20B.

[0042] As Figure 2 shown, the vertical pattern 55P of the second heat dissipation member 55 has a circular shape in a plan view and can be arranged to have a constant distance from each other. Although there is no limitation, the vertical pattern 55P can have various shapes and arrangements.

[0043] Figures 3A to 3CIt is a plan view of various examples of the composite heat dissipation layer 50 (e.g., the vertical pattern 55P) that can be adopted in a semiconductor device according to an exemplary embodiment.

[0044] Figure 3A The plurality of vertical patterns 55P shown may have a rectangular or rod-like shape in a top view. Figure 3B A plurality of vertical patterns 55P having a cross shape are shown. However, the shape of the vertical pattern 55P according to the exemplary embodiment is not limited thereto. The vertical pattern 55P may have various shapes and arrangements.

[0045] As in the above exemplary embodiments ( Figure 1 、 Figure 3A and Figure 3B ), it is desirable that the first heat dissipation member 52 has a monolithic structure such that the heat dissipation path is not interrupted by the closed vertical pattern in the vertical direction.

[0046] In some exemplary embodiments, the vertical pattern 55P may span the first heat dissipation member 52. For example, as Figure 3C shown, the vertical pattern 55P may include a first vertical pattern 55P1 and a second vertical pattern 55P2 that intersect each other, and the first vertical pattern 55P1 may be configured to divide the first heat dissipation member 52 into two regions.

[0047] Meanwhile, the vertical pattern 55P may have various cross-sectional shapes in the thickness direction of the composite heat dissipation layer 50. For example, the cross-section of the vertical pattern 55P may have the shape of a jar, a regular trapezoid, or an inverted trapezoid according to the shape of the mask pattern Figure 4B shown.

[0048] Figures 4A to 4E It is a side cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment. The manufacturing method includes forming a composite heat dissipation layer and can be implemented at the wafer level.

[0049] Based on Figure 4A , a wafer W for a plurality of semiconductor chips is prepared. The wafer W may include silicon, and in another exemplary embodiment, may include a single-element semiconductor such as germanium or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The plurality of semiconductor chips employed in the wafer may be the same as the Figure 1 semiconductor chip 20 shown. For example, a number of active / passive elements (e.g., transistors) and connection pads connected thereto may be formed on the first surface 20A of the wafer W through a series of semiconductor processes. A composite heat dissipation layer may be provided on the second surface 20B (i.e., the non-active surface) of the wafer W through subsequent processes.

[0050] Based onFigure 4B , a mask pattern MP is formed on the second surface 20B of the wafer W.

[0051] A mask pattern MP can be provided such that at least one region of the second surface 20B is exposed. The at least one region defines a region in which the first heat dissipation member ( Figure 4C of 52) is formed, and the mask pattern MP defines a region where the second heat dissipation member ( Figure 4E of 55) contacts the second surface 20B of the wafer W (e.g., a region where a vertical pattern ( Figure 4E of 55P) is formed). In the present exemplary embodiment, the mask pattern MP can be a plurality of segmented mask patterns, and the exposed region can be a plurality of sub-regions connected as one region. The planar shape of the mask pattern MP can define the planar shape of the vertical pattern. For example, in the case of forming the Figure 1 and Figure 2 shown composite heat dissipation layer 50, the mask pattern MP can be a plurality of circular mask patterns.

[0052] Based on Figure 4C , the first heat dissipation member 52 is formed in this one region of the second surface 20B of the wafer W.

[0053] The first heat dissipation member 52 can be formed of a material having a vertical thermal conductivity lower than the horizontal thermal conductivity in the direction perpendicular to the surface direction. For example, the first heat dissipation member 52 can be formed of graphite or graphene. The first heat dissipation member 52 can be formed in the form of a sheet using a film forming process such as a deposition process. As in the present exemplary embodiment, the first heat dissipation member 52 is formed to directly contact the second surface 20B of the wafer W without using additional adhesion. In this way, improved heat dissipation characteristics can be obtained or ensured, and delamination caused by differences in the coefficient of thermal expansion can be reduced.

[0054] In addition, based on Figure 4D , the remaining region of the wafer W can be exposed by removing the mask pattern MP.

[0055] In the present exemplary embodiment, the region where the mask pattern MP is removed can be provided in the hole h of the first heat dissipation member 52. The hole h of the first heat dissipation member 52 can define a region in which a vertical pattern (55P in FIG. 4) is formed. The planar shape of the hole h is defined by the mask pattern MP as described above and can be a closed-type pinhole (a structure surrounded by the first heat dissipation member 52). The planar shape can be achieved by another form of the pinhole (see Figure 3B of 55P).

[0056] Based on Figure 4E , the second heat dissipation member 55 having the vertical pattern 55P can be formed in the remaining region of the wafer W.

[0057] According to an example embodiment, the second heat dissipation member 55 may include a vertical pattern 55P filling the holes h and a heat dissipation layer 55L disposed on the first heat dissipation member 52 and connecting the vertical patterns 55P to each other. The second heat dissipation member 55 may be formed of a material (e.g., graphite) having a higher vertical thermal conductivity than that of the first heat dissipation member 52. For example, the second heat dissipation member 55 may be formed of a metal (e.g., Cu).

[0058] In the present example embodiment, the vertical pattern 55P and the heat dissipation layer 55L may be a metal pattern and a metal layer, respectively. The vertical pattern 55P may be connected to the heat dissipation layer 55L disposed on the first heat dissipation member 52 to form a vertical heat dissipation path, while being in direct contact with the second surface 20B of the wafer W through the holes h of the first heat dissipation member 52. Heat generated from the wafer W may be actively or effectively dissipated in the vertical direction through the vertical heat dissipation path. Accordingly, the low vertical thermal conductivity of the first heat dissipation member 52 may be compensated for by the second heat dissipation member 55 via the vertical heat dissipation path.

[0059] Figure 4E The illustrated wafer W may be cut together with the composite heat dissipation layer 50 into individual chip units to provide Figure 1 the illustrated semiconductor device 10.

[0060] Figure 5 is a side cross-sectional view of a semiconductor package according to an example embodiment, and Figure 6 is a plan view of the semiconductor package taken along line VI-VI'. Figure 5 Based on

[0061] and Figure 5 and Figure 6 a semiconductor package 100 according to the present example embodiment may include: a package substrate 140 including a redistribution layer, a semiconductor device 10 disposed on the package substrate 140, and a sealing member 130 sealing the semiconductor device 10 on the package substrate (or redistribution substrate) 140. The semiconductor device 10 may be Figure 1 and Figure 2 the semiconductor device shown.

[0062] The semiconductor device 10 includes: a semiconductor chip 20 having a first surface 20A including connection pads 22 electrically connected to the redistribution layers (142 and 143) and a second surface 20B disposed opposite to the first surface 20A; and a composite heat dissipation layer 50 disposed on the second surface 20B.

[0063] The sealing member 130 may protect the frame 110 and the semiconductor chip 20. For example, the sealing member 130 may cover the upper surface of the frame 110 and the heat dissipation layer 50 located on the second surface 20B of the semiconductor chip 20.

[0064] In the composite heat dissipation layer 50 adopted in the present exemplary embodiment, it may include: a first heat dissipation layer 52 (also referred to as "the first heat sink") disposed on the second surface 20B of the semiconductor chip 20, a vertical pattern 55P passing through the first heat sink 52, and a second heat sink 55L (also referred to as the "heat dissipation layer" of the second heat dissipation member 55) disposed on the first heat sink 52 and connected to the vertical pattern 55P.

[0065] The first heat sink 52 includes a material whose vertical thermal conductivity in a direction perpendicular to the second surface 20B is less than the horizontal thermal conductivity in a direction parallel to the second surface 20B and the vertical thermal conductivity of the vertical pattern 55P passing through the first heat sink 52. The vertical thermal conductivities of the vertical pattern 55P and the second heat sink 55L are greater than the vertical thermal conductivity of the first heat sink 52 and may include the same material.

[0066] For example, the first heat dissipation layer 52 includes at least one of graphite or graphene, and the vertical pattern 55P and the second heat sink 55L may include a metal. As used herein, the terms "vertical pattern 55P" and "second heat sink 55L" may be referred to as "second heat dissipation member 55".

[0067] The heat generated from the semiconductor chip 20 can be effectively released through the first heat dissipation layer 52 having excellent horizontal thermal conductivity. For example, since the average horizontal thermal conductivity of graphite is as high as 1,500 W / m·k to 1,700 W / m·k, the first heat sink 52 formed on the second surface 20B of the semiconductor chip 20 can promote effective heat dissipation in the lateral direction by providing a horizontal heat dissipation path DH1. However, since the sealing member 130 has a relatively low thermal conductivity and seals the corners (e.g., sides) of the first heat sink 52, sufficient heat dissipation may not be achieved.

[0068] To compensate for the above problems, the composite heat dissipation layer 50 can ensure that the vertical heat dissipation paths passing through both the vertical pattern 55P and the second heat sink 55L have relatively high vertical thermal conductivities. In addition, the semiconductor package 100 in the present exemplary embodiment uses a heat dissipation path 133H and a heat dissipation pattern 132H connected to the composite heat dissipation layer 50 to extend the vertical heat dissipation path DH2.

[0069] For example, the heat dissipation pattern 132H may be disposed on the upper surface of the sealing member 130 and at a position corresponding to the composite heat dissipation layer 50. The heat dissipation path 133H may pass through a part of the sealing member 130 to connect the heat dissipation pattern 132H and the composite heat dissipation layer 50.

[0070] In the present exemplary embodiment, the heat dissipation path 133H may be connected to the second heat sink 55L of the composite heat dissipation layer 50. Such an arrangement may help to provide an extended vertical heat dissipation path DH2 that connects the vertical pattern 55P, the second heat sink 55L, the heat dissipation path 133H, and the heat dissipation pattern 132H. Thus, such a vertical heat dissipation path DH2 may extend toward the outside of the sealing member 130, and thus may be expected to provide more effective heat dissipation compared to the horizontal heat dissipation path DH1.

[0071] The heat dissipation pattern 132H and the heat dissipation path 133H may include a metal having a relatively high thermal conductivity and may be formed of the same material as the materials of the backside redistribution layers 132 and 133. In some exemplary embodiments, the heat dissipation pattern 132H and the heat dissipation path 133H may be the same material (e.g., Cu) as the vertical pattern 55P and the second heat sink 55L.

[0072] The redistribution substrate 140 includes a first surface 140A and a second surface 140B that are disposed opposite to each other. The redistribution substrate 140 may include a three-layer redistribution layer (142 and 143) on a plurality (e.g., three) of insulating layers 141. The redistribution layer (142 and 143) may include a redistribution pattern 142 disposed on the insulating layer 141 and a redistribution path 143 that passes through the insulating layer 141 and connects vertically adjacent redistribution patterns 142. The semiconductor chip 20 is disposed on the first surface 140A of the redistribution substrate 140, and the connection pads 22 located on the first surface 20A of the semiconductor chip 20 may be connected to the redistribution layer (e.g., the redistribution path 143).

[0073] The redistribution substrate 140 employed in the present exemplary embodiment includes three insulating layers 141 and three redistribution layers 142 and 143. However, in some exemplary embodiments, the redistribution substrate 140 may have a single layer, a double layer, or a greater number of layers. The insulating layer 141 may be a photosensitive insulating material such as a photoimageable dielectric (PID) resin. Even when the insulating layer 141 is configured to have multiple layers, the insulating layer 141 may have an indistinct interlayer boundary depending on the material and process of each layer.

[0074] As Figure 5 shown, the semiconductor package 100 may further include a frame 110, backside redistribution layers (RDL) 132 and 133, a first passivation layer 150a and a second passivation layer 150b, an under-bump metal layer 160, and an electrically connecting metal 170.

[0075] The frame 110 is disposed on the first surface 140A of the encapsulation substrate 140 and may include a cavity 110H for accommodating the semiconductor chip 20. The frame 110 includes a wiring structure that provides electrical connection between the upper surface and the lower surface. The wiring structure employed in the present exemplary embodiment may include first to third wiring patterns 112a to 112c and first and second wiring vias 113a and 113b that provide connections between the first to third wiring patterns 112a to 112c, but is not limited thereto. In some exemplary embodiments, the wiring structure may be formed to have a different number of layers and different structures (see Figure 10A ). The wiring structure (e.g., the first wiring pattern 112a) of the frame 110 may be connected to the redistribution layers 142 and 143 of the redistribution substrate 140 to be electrically connected to the semiconductor chip 20.

[0076] In the present exemplary embodiment, the sealing member 130 extends to cover the upper surface of the frame 110. The semiconductor package 100 may further include backside redistribution layers 132 and 133 that are disposed on the sealing member 130 and electrically connected to the wiring structure (e.g., the third wiring pattern 112c). The backside redistribution layers 132 and 133 may include a wiring pattern 132 disposed on the sealing member 130 and a wiring via 133 that passes through a portion of the sealing member 130 to connect the third wiring pattern 112c to the wiring pattern 132.

[0077] As described above, the wiring pattern 132 and the wiring via 133 that constitute the backside redistribution layer may be formed of the same material as the heat dissipation pattern 132H and the heat dissipation via 133H by the same process.

[0078] The frame 110 is a selective structure and may provide improved rigidity in accordance with the specific materials of the semiconductor package 100. As described above, the frame 110 has a wiring structure that provides electrical connection between its upper surface and its lower surface, thereby enabling the semiconductor package 100 to be used as a package-on-package (POP) type package. The semiconductor chip 20 disposed in the cavity 110H of the frame 110 may be spaced apart from the inner sidewall of the frame 110 by a predetermined distance. The side surface area of the semiconductor chip 20 may be surrounded by the frame 110, but is not limited thereto, and may be modified in various forms to correspondingly have different functions.

[0079] As described above, the frame 110 includes: a first insulating layer 111a in contact with the redistribution substrate 140; a first wiring pattern 112a in contact with the redistribution substrate 140 and embedded in the first insulating layer 111a; a second wiring pattern 112b disposed on a second surface of the first insulating layer 111a, the second surface being opposite to a first surface of the first insulating layer 111a in which the first wiring pattern 112a is embedded; a second insulating layer 111b disposed on the first insulating layer 111a and covering the second wiring pattern 112b; and a third wiring pattern 112c disposed on the second insulating layer 111b. The first wiring pattern 112a to the third wiring pattern 112c are electrically connected to the connection pad 22. The first wiring pattern 112a to the third wiring pattern 112c are electrically connected to each other via a first wiring via 113a and a second wiring via 113b that respectively pass through the first insulating layer 111a and the second insulating layer 111b.

[0080] In the present exemplary embodiment, when the first wiring pattern 112a is embedded inside the first insulating layer 111a, the step generated by the thickness of the first wiring pattern 112a can be minimized, so that the insulation distance of the redistribution substrate 140 is more constant. When the first wiring pattern 112a is recessed into the first insulating layer 111a, both the lower surface of the first insulating layer 111a and the lower surface of the first wiring pattern 112a have steps. In this case, since the material for forming the sealing member 130 does not ooze out, contamination of the first redistribution layer 112a can be reduced or prevented. The frame 110 is manufactured to have a sufficiently large thickness by a substrate process or the like, and the redistribution substrate 140 is manufactured to be very thin by a semiconductor process or the like. In this regard, the thickness of each of the first wiring pattern 112a to the third wiring pattern 112a to 112c of the frame 110 can be greater than the thickness of the redistribution layer 142 of the redistribution substrate 140.

[0081] For example, the insulating layers 111a and 111b may include: a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a composite resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler and / or glass fiber (glass cloth or glass fiber fabric). In some exemplary embodiments, the first insulating layer 111a and the second insulating layer 11b may include a prepreg, an Ajinomoto Build-up film (ABF), FR-4, or a bismaleimide triazine (BT).

[0082] The first wiring vias 113a and the second wiring vias 113b that are electrically connected to the first to third wiring layers 112a to 112c formed on different insulating layers 111a and 111b may form a wiring structure having an interlayer connection path within the frame 110. The first wiring vias 113a and the second wiring vias 113b may be formed of the previously described conductive material. In some example embodiments, the first wiring vias 113a and the second wiring vias 113b may be integrally formed with the second wiring pattern 112b and the third wiring pattern 112c by the same process.

[0083] The first passivation layer 150a and the second passivation layer 150b may protect the redistribution substrate 140 and the backside redistribution pattern 132 from external physical or chemical damage, etc., respectively. The first passivation layer 150a and the second passivation layer 150b may include the aforementioned insulating material. In some example embodiments, the first passivation layer 150a and the second passivation layer 150b may include prepreg, ABF, FR-4, BT, solder mask, or PID. The first passivation layer 150a and the second passivation layer 150b may have pinholes PH that partially expose the redistribution pattern 142 and the backside redistribution pattern 132. A surface treatment layer (not shown) may be formed by plating (e.g., noble metal plating) in the exposed area of the backside redistribution pattern 132.

[0084] The under-bump metal layer 160 may be formed in the pinholes of the first passivation layer or the outermost insulating layer of the insulating layer 141 by a known metallization method, but is not limited thereto. The electrical connection metal 170 may electrically connect and / or physically connect the semiconductor package 100 to an external device such as a motherboard of an electronic device. The electrical connection metal 170 may include a metal with a low melting temperature (e.g., solder such as tin (Sn)-aluminum (Al)-copper (Cu)). The electrical connection metal 170 may have multiple layers or a single layer. For example, the multi-layer electrical connection metal may include pillars and solder, while the single-layer connection metal may include tin-silver solder or copper.

[0085] Figures 7A to 7D is a side cross-sectional view showing a method of manufacturing a semiconductor package according to an example embodiment.

[0086] Based on Figure 7A , a frame 110 having a cavity 110H is provided on a first carrier film 210, a semiconductor chip 20 is received in the cavity 110H, and a sealing member 130 is formed on the frame 110 and the semiconductor chip 20.

[0087] As described above, the frame 110 employed in the present exemplary embodiment includes a wiring structure and a first insulating layer 111a and a second insulating layer 111b, and the wiring structure includes three wiring patterns 112a to 112c and wiring vias 113a and 113b that provide connections between the wiring patterns 112a to 112c. A first carrier film 210 is attached to the lower side of the first insulating layer 111a. For example, the first carrier film 210 may be a tape containing epoxy resin.

[0088] The semiconductor chip 20 may be built in the cavity 110H of the frame 110. As described above, the composite heat dissipation layer 50 may be disposed on the second surface 20B of the semiconductor chip 20. The side surface of the composite heat dissipation layer 50 may be substantially coplanar with the side surface of the semiconductor chip 20 (see Figure 4E ). The semiconductor chip 20 is arranged such that the first surface 20A on which the connection pads 22 are formed faces the first carrier film 210. The sealing member 130 seals the semiconductor chip 20 using the aforementioned sealing material. The sealing member 130 may cover the composite heat dissipation layer 50 coated on the semiconductor chip 20 and extend to the upper surface of the frame 110 to cover the third wiring pattern 112c.

[0089] Based on Figure 7B , a second carrier film 220 is attached to the upper surface of the sealing member 130, and the first carrier film 210 is removed to form a redistribution substrate 140 thereon.

[0090] The formation process of the redistribution substrate 140 may include: forming an insulating layer 141 using a lamination or coating method; forming vias on the insulating layer 141; and forming redistribution patterns 142 and redistribution vias 143 by an electrolytic or electroless plating method. When PID is used as the insulating layer, a photolithography method may be used to form vias with a fine pitch.

[0091] In some exemplary embodiments, as Figure 7B shown, a first passivation layer 150a and an under-bump metal layer 160 may be further formed. The first passivation layer 150a is formed on the lower surface 140B of the redistribution substrate 140, and a plurality of pinholes exposing a part of the first redistribution pattern 142 are formed on the first passivation layer 150a. Then, the under-bump metal layer 160 is formed on the first passivation layer 150a to contact the exposed area of the redistribution pattern 142 through the plurality of pinholes.

[0092] Based on Figure 7C , the second carrier film 220 is removed from the sealing member 130, and heat dissipation patterns 132H and heat dissipation vias 133H are formed together with the backside redistribution layers 132 and 133.

[0093] After removing the second carrier film 220, a pinhole is formed in the sealing member 130 such that a part of the third wiring pattern 112c and a part of the composite heat dissipation layer 50 (e.g., the second heat sink 55L) are exposed. This process can be performed by a hole forming process such as a laser drilling process, but is not limited thereto. For example, the sealing member 130 can be formed by a photolithography process when formed as a PID.

[0094] A photoresist pattern that opens the pattern formation area can be formed on the upper surface of the sealing member 130, and a heat dissipation pattern 132H and a heat dissipation path 133H can be formed together with the backside redistribution layers 132 and 133 using a plating process. For example, a wiring pattern 132 and a heat dissipation pattern 132H are formed on the surface of the sealing member 130, and a wiring path 133 that connects the wiring pattern 132 and the third wiring pattern 112c, and a heat dissipation path 133H that connects the second heat sink 55L to the heat dissipation pattern 132H can be formed. In this process, both the wiring path 133 and the heat dissipation path 133H can be formed integrally with the wiring pattern 132 and the heat dissipation pattern 132H. In addition, the heat dissipation pattern 132H and the heat dissipation path 133H are formed by the same plating process and can therefore be formed of the same material as the backside redistribution layers 132 and 133.

[0095] As described above, the heat dissipation pattern 132H and the heat dissipation path 133H are connected to the vertical pattern 55P and the second heat sink 55L, and thus a vertical heat dissipation path DH2 that extends outside the sealing member 130 can be provided. Such a vertical heat dissipation path DH2 can provide an improved heat dissipation effect.

[0096] As Figure 7D shown, a second passivation layer 150b is formed on the sealing member 130 to cover the backside redistribution layers (132 and 133) and the heat dissipation pattern 132H, and a pinhole PH that exposes a part of the wiring pattern 132 is formed on the second passivation layer 150b. Additionally, an electrical connection metal 170 can be formed on the under bump metal layer 160.

[0097] The above-described method of manufacturing a semiconductor package describes the process of manufacturing a single package. In some example embodiments, such a series of processes can be performed at the panel level, and multiple semiconductor packages (e.g., 4×4) can be manufactured simultaneously at the panel level.

[0098] The semiconductor device according to the present example embodiment can be effectively applied to semiconductor packages having different structures. Figure 8 and Figure 9 are side cross-sectional views of semiconductor packages according to various example embodiments.

[0099] Based Figure 8, the semiconductor package 200A according to the exemplary embodiment includes a package substrate 210, a semiconductor device 10' disposed on the package substrate 210, and a sealing member 230 disposed on the package substrate 210 and surrounding the semiconductor device 10'.

[0100] The package substrate 210 may include a body 201, an upper substrate pad 203 located on the upper surface of the body 201, and a lower substrate pad 205 located on the lower surface of the body 201. In addition, the package substrate 210 may have a wiring pattern (not shown) and a connection via (not shown) that jointly provide an electrical connection between the upper substrate pad 203 and the lower substrate pad 205. For example, the package substrate 210 may be a printed circuit board (PCB), but is not limited thereto, and may be various forms of wiring substrates.

[0101] The semiconductor device 10' employed in the present exemplary embodiment includes: a semiconductor chip 20', which has a first surface on which connection pads 22 are formed and a second surface disposed opposite to the first surface; and a composite heat dissipation layer 50, which is disposed on the second surface of the semiconductor chip 20'. As Figure 1 and Figure 2 shown in the exemplary embodiment of, the composite heat dissipation layer 50 includes a first heat dissipation member 52 having a horizontal thermal conductivity higher than the vertical thermal conductivity and being sheet-shaped, and a second heat dissipation member 55 disposed on the first heat dissipation member 52 and having a vertical thermal conductivity higher than the horizontal thermal conductivity. The second heat dissipation member 55 includes a vertical pattern 55P passing through the first heat dissipation member 52 and a heat dissipation layer 55L disposed on the first heat dissipation member 52 and connected to the vertical pattern 55P.

[0102] In the present exemplary embodiment, the semiconductor chip 20' is built on the package substrate 210 such that the first surface of the semiconductor chip 20' faces the upper surface of the package substrate 210. The connection pads 22 of the semiconductor chip 20' may be connected to the upper substrate pads 203 through conductive bumps SB. The composite heat dissipation layer 50 located on the second surface of the semiconductor chip 20' may be disposed facing upward. As Figure 8 shown, the second heat dissipation member 55 of the composite heat dissipation layer 50 may be exposed through the upper surface 230T of the sealing member 230. For example, the upper surface of the composite heat dissipation layer 50L may be substantially coplanar with the upper surface 230T of the sealing member 230.

[0103] Based on Figure 9 , except that the semiconductor device 10″ is connected to the package substrate 210 through wiring 250, the semiconductor package 200B according to the present exemplary embodiment may have a structure that is the same as or substantially similar to the structure Figure 8 shown. Therefore, unless otherwise specified, the description of the exemplary embodiment Figure 8 shown may be applied to the present exemplary embodiment.

[0104] Unlike Figure 8 the semiconductor device 10' shown, the semiconductor device 10″ employed in the present exemplary embodiment may be disposed on the package substrate 210. For example, the semiconductor device 10″ may be disposed on the package substrate 210 such that the first surface on which the connection pads 22 are provided faces upward, and the connection pads 22 of the semiconductor device 10″ are connected to the upper substrate pads 203 through wirings 250. The semiconductor chip 20″ may be constructed in the package substrate 210 such that the composite heat dissipation layer 50 on the second surface of the semiconductor chip 20″ opposite to the first surface of the semiconductor chip 20″ faces the upper surface of the package substrate 210. As Figure 9 shown, the upper surface of the package substrate 210 and the composite heat dissipation layer 50 may be attached to each other through an adhesive layer 220. In some exemplary embodiments, the adhesive layer 220 may be an adhesive material for heat dissipation. For example, the adhesive material for heat dissipation may include a thermal interface material (TIM).

[0105] The composite heat dissipation layer may be modified to have various structures. The vertical patterns have patterns of various shapes in the Figures 3A to 3C shown plan view, but the patterns of various shapes of the vertical patterns in the plan view according to the exemplary embodiment are not limited thereto. In some exemplary embodiments, the vertical patterns may have a single pattern in a large surface area ( Figure 10A and Figure 10B ), or may be positioned along at least one edge of the first heat dissipation member (or the first heat sink) ( Figure 11A and Figure 11B ).

[0106] Figure 10A is a side cross-sectional view of a semiconductor package according to an exemplary embodiment, and Figure 10B is a plan view of the composite heat dissipation layer taken along the line XB-XB' of the semiconductor package of Figure 10A .

[0107] Based on Figure 10A and Figure 10B , except that the vertical pattern 55P of the composite heat dissipation layer 50A has a single structure and the wiring structure of the frame 110' has a different structure, the semiconductor package 100A according to the present exemplary embodiment may have a structure the same as or substantially similar to the structure shown in Figure 5 and Figure 6 . Therefore, unless otherwise indicated, the description of the exemplary embodiments shown in Figure 5 and Figure 6 may be applied to the present exemplary embodiment.

[0108] In the exemplary embodiment employed herein, the composite heat dissipation layer 50A includes a first heat dissipation member 52A in the form of a sheet and a second heat dissipation member 55 disposed on the first heat dissipation member 52A. The second heat dissipation member 55 has a vertical pattern 55P located substantially in the central region and a heat dissipation layer 55L connected thereto. The vertical pattern 55P may have a larger surface area compared to the previously proposed vertical pattern 55P.

[0109] In the exemplary embodiment herein, a plurality of heat dissipation paths 133H connected to the heat dissipation pattern 132H may be connected to the heat dissipation layer 55L. As Figure 10B shown, the plurality of heat dissipation paths 133H may be aligned to closely surround the region overlapping with the vertical pattern 55P.

[0110] The frame 110' employed in the exemplary embodiment herein may have a wiring structure different from that of the frame 110 of the previous exemplary embodiment. For example, the frame 110' may include: a first insulating layer 111a; a first wiring pattern 112a disposed on one surface of the first insulating layer 111a; a second wiring pattern 112b disposed on the other surface of the first insulating layer 111a; a second insulating layer 111b disposed on one surface of the first insulating layer 111a and covering at least a portion of the first wiring pattern 112a; a third wiring pattern 112c disposed on the surface opposite to the side on which the first wiring pattern 112a of the second insulating layer 111b is embedded; a third insulating layer 111c disposed on the other surface of the first insulating layer 111a and covering at least a portion of the second wiring pattern 112b; a fourth wiring pattern 112d disposed on the surface opposite to the side on which the second wiring pattern 112b of the third insulating layer 111c is embedded; a first wiring via 113a passing through the first insulating layer 111a and electrically connecting the first wiring pattern 112a and the second wiring pattern 112b; a second wiring via 113b passing through the second insulating layer 111b and electrically connecting the first wiring pattern 112a and the third wiring pattern 112c; and a third wiring via 113c passing through the third insulating layer 111c and electrically connecting the second wiring pattern 112b and the fourth wiring pattern 112d. Since the frame employed in the exemplary embodiment herein has a larger number of wiring patterns 112a to 112d, the redistribution layer 142 of the redistribution substrate 140 can be more simplified.

[0111] The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to substantially maintain its rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of wiring patterns 112c and 112d. The first insulating layer 111a may contain an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c.

[0112] Figure 11A is a side cross-sectional view of a semiconductor package according to an exemplary embodiment, and Figure 11B is taken along line XIB-XIB'. Figure 11A A plan view of the semiconductor package.

[0113] Based on Figure 11A and Figure 11B , except that the vertical pattern 55P of the composite heat dissipation layer 50B surrounds the first heat dissipation member 52A, the semiconductor package 100B according to the present exemplary embodiment may have a structure that is the same as or substantially similar to the structure shown in Figure 5 and Figure 6 . Therefore, unless otherwise indicated, the description of the exemplary embodiments shown in Figure 5 and Figure 6 can be applied to the present exemplary embodiment.

[0114] The composite heat dissipation layer 50B employed in the present exemplary embodiment includes a first heat dissipation member 52B and a second heat dissipation member 55 disposed on the first heat dissipation member 52B. The first heat dissipation member 52B may be disposed in the remaining area of the second surface of the semiconductor chip 20 except for the edge region. The vertical pattern 55P of the second heat dissipation member 55 is disposed along the edge region of the second surface of the semiconductor chip 20. As shown in Figure 11B , the vertical pattern 55P may be disposed to surround the first heat dissipation member 52B at the edge region of the semiconductor chip 20. A heat dissipation layer 55L is disposed on the upper surface of the first heat dissipation member 52B and is connected to the vertical pattern 55P. In the present exemplary embodiment, the second heat dissipation member 55 may be formed to cover the side surface and the upper surface of the first heat dissipation member 52B.

[0115] In such an arrangement, the first heat dissipation member 52B having a relatively high horizontal thermal conductivity releases heat in the horizontal direction, and the heat can be dissipated in the vertical direction along the vertical pattern 55P in contact with the side surface of the first heat dissipation member 52B and the heat dissipation layer 55L connected to the vertical pattern 55P.

[0116] In the previous exemplary embodiment, the composite heat dissipation layer is shown to have a double-layer structure (an integrated structure of a first heat sink and at least one vertical pattern and a second heat sink), but the exemplary embodiment is not limited thereto. In some exemplary embodiments, the composite heat dissipation layer may be implemented as a single layer. For example, the second heat dissipation member may have a structure that only has a vertical pattern and does not include a second heat sink (e.g., a heat dissipation layer), and the composite heat dissipation layer may be constructed as a first heat dissipation member in the form of a sheet and a vertical pattern passing through the first heat dissipation member. Such a structure is shown in Figures 12 to 14 .

[0117] Based onFigure 12 , except that the composite heat dissipation layer 50C has a single-layer structure and the wiring structure of the frame 110' is different, the semiconductor package 100C according to the present exemplary embodiment may have a structure that is the same as or substantially similar to the structure shown in Figure 5 and Figure 6 . Therefore, unless otherwise indicated, the description of the exemplary embodiments shown in Figure 5 and Figure 6 can be applied to the present exemplary embodiment.

[0118] The composite heat dissipation layer 50C adopted in the present exemplary embodiment has a single-layer structure and may include a first heat dissipation member 52 and a second heat dissipation member having a plurality of vertical patterns 55P passing through the first heat dissipation member. In other words, the composite heat dissipation layer 50C may include: a heat dissipation layer 52 having a horizontal thermal conductivity greater than the vertical thermal conductivity and a plurality of vertical patterns 55P passing through the heat dissipation layer 52 and having a relatively high vertical thermal conductivity. The vertical patterns 55P may have an arrangement as shown in Figure 2 and Figures 3A to 3C . For example, the heat dissipation layer 52 may contain graphite, and the vertical patterns 55P may be metal patterns such as copper patterns.

[0119] The composite heat dissipation layer 50C may be connected to a heat dissipation pattern 132H provided outside the sealing member 130 via a heat dissipation path 133H. As shown in Figure 12 , different from the heat dissipation path in the previous exemplary embodiment, the heat dissipation path 133H may be partially connected to the heat sink 52.

[0120] The frame 110' adopted in the present exemplary embodiment may have the same wiring structure as the wiring structure shown in Figure 10A . Figure 10A The description of the frame 110' of

[0121] Based on Figure 13 , except that the composite heat dissipation layer 50D has a single-layer structure, the semiconductor package 100D according to the present exemplary embodiment may have a structure that is the same as or substantially similar to the structure shown in Figure 5 and Figure 6 . Therefore, unless otherwise indicated, the description of the exemplary embodiments shown in Figure 5 and Figure 6 can be applied to the present exemplary embodiment.

[0122] The composite heat dissipation layer 50D adopted in the present exemplary embodiment has a single-layer structure, but has the same as Figure 12The composite heat dissipation layer 50C shown has different shapes. The composite heat dissipation layer 50D may include a first heat dissipation member 52 in the form of a sheet and a second heat dissipation member having a single vertical pattern 55P passing through a substantially central region of the first heat dissipation member 52. In other words, the composite heat dissipation layer 50D may include a heat sink 52 with a higher horizontal thermal conductivity than vertical thermal conductivity and a vertical pattern 55P with a higher vertical thermal conductivity than the heat sink 52 and passing through the center (or central) region of the composite heat dissipation layer 50D. Such a vertical pattern 55P may have an arrangement as shown in Figure 10B For example, the heat sink 52 contains at least one of graphite and graphene, and the vertical pattern 55P may be a metal pattern such as a copper pattern.

[0123] The composite heat dissipation layer 50D may be connected via a heat dissipation path 133H to a heat dissipation pattern 132H provided outside the sealing member 130. As shown in Figure 13 The heat dissipation path 133H may be connected to the vertical pattern 55P.

[0124] Based on Figure 14 , except that the composite heat dissipation layer 50E has a single-layer structure, the semiconductor package 100E according to the present exemplary embodiment may have a structure the same as or substantially similar to the structures shown in Figure 5 and Figure 6 . Therefore, unless otherwise indicated, the descriptions of the exemplary embodiments shown in Figure 5 and Figure 6 may be applied to the present exemplary embodiment.

[0125] The composite heat dissipation layer 50E employed in the present exemplary embodiment has a single-layer structure, but has a different shape from the composite heat dissipation layer 50C shown in Figure 12 . The composite heat dissipation layer 50E may include a first heat dissipation member 52 in the form of a sheet and a second heat dissipation member having a vertical pattern 55P around an edge region of the first heat dissipation member 52. In other words, the composite heat dissipation layer 50E may include a heat sink 52 with a higher horizontal thermal conductivity than vertical thermal conductivity and a vertical pattern 55P with a higher vertical thermal conductivity than the heat sink 52 and around the edge region of the heat sink 52. Such a vertical pattern 55P may have an arrangement as shown in Figure 11B For example, the heat sink 52 contains at least one of graphite and graphene, and the vertical pattern 55P may be a metal pattern such as a copper pattern.

[0126] The composite heat dissipation layer 50E may be connected via a heat dissipation path 133H to a heat dissipation pattern 132H provided outside the sealing member 130. As shown in Figure 14 The heat dissipation path 133H may be connected to the heat sink 52.

[0127] Figure 15It is a side cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0128] Based on Figure 15 , except that the vertical interconnect portion 110P replaces the frame having a wiring structure ( Figure 5 110), the semiconductor package 100F according to the present exemplary embodiment may have the same or substantially similar structure as that shown in Figure 5 and Figure 6 . Therefore, unless otherwise indicated, the description of the exemplary embodiments shown in Figure 5 and Figure 6 may be applied to the present exemplary embodiment.

[0129] Different from the foregoing exemplary embodiments, the semiconductor package 100F including the composite heat dissipation layer 50F according to the present exemplary embodiment may be a wafer-level package. In the semiconductor package 100F, the interconnecting elements connecting the backside redistribution layers 132 and 133 to the redistribution layers 142 and 143 of the package substrate 140 may be vertical interconnect portions 110P such as metal pillars, rather than the wiring structure of the frame. Such vertical interconnect portions 110P are arranged to pass through the sealing member 130 of the encapsulated semiconductor device 10, thereby electrically connecting the backside redistribution layers 132 and 133 to the redistribution layers 142 and 143 of the package substrate 140. In the present exemplary embodiment, the vertical interconnect portion 110P is directly connected to the wiring vias 133 and 143, but is not limited thereto. In other exemplary embodiments, the vertical interconnect portion 110P may be directly connected to the wiring patterns 132 and 142.

[0130] In the present exemplary embodiment, the heat dissipation via 133H may be connected to the second heat dissipation member 55 of the composite heat dissipation layer 50F. The second heat dissipation member 55 is vertically patterned through the first heat dissipation member 52 and bonded to the semiconductor chip 20, so as to be able to provide a vertical heat dissipation path extending to the outside of the sealing member 130 through the heat dissipation via 133H, the heat dissipation pattern 132H, and the second heat dissipation member 55. The heat dissipation via 133H and the heat dissipation pattern 132H may be metals having a relatively high thermal conductivity and may be formed of the same material as that of the backside redistribution layers 132 and 133.

[0131] The method of manufacturing a semiconductor device having the foregoing composite heat dissipation layer 50 may be performed by different methods. In the previous exemplary embodiments ( Figures 4A to 4E ), the first heat dissipation member 52 and the second heat dissipation member 55 are formed of different materials, but are not limited thereto. In other exemplary embodiments, the material of the second heat dissipation member 55 is the same as that of the first heat dissipation member 52, but has a different growth direction to provide a material having a relatively high vertical thermal conductivity. The manufacturing method of such a semiconductor device may be referred to Figures 16A to 16C for description.

[0132] Based on Figure 16A , an additional mask pattern MP' can be formed on the first heat dissipation member 52.

[0133] The first heat dissipation member 52 shown in the present exemplary embodiment can be understood as Figure 4D a product manufactured in Figure 4C . After removing the mask pattern (MP

[0134] Based on Figure 16B , the second heat dissipation member 55' can be formed in the hole h by slightly tilting the wafer W.

[0135] The second heat dissipation member 55' employed in the present exemplary embodiment has the same material as the first heat dissipation member 52, but is oriented in an orientation different from that of the first heat dissipation member. In a specific example, as Figure 16B shown, the second heat dissipation member filled in the hole h can be formed by growing graphite identical to that of the first heat dissipation member 52 by tilting the second surface 20B of the wafer W at a certain angle θ with respect to the growth direction GD. Therefore, the first heat dissipation member 52 and the second heat dissipation member 55' can be formed of graphite having different orientations due to the tilt angle θ. Since the graphite of the first heat dissipation member 52 maintains a layered structure parallel to the second surface 20B of the wafer, the vertical thermal conductivity of the first heat dissipation member 52 is significantly lower than the horizontal thermal conductivity of the first heat dissipation member 52. However, due to the different growth directions, the second heat dissipation member 55' can have a vertical thermal conductivity higher than that of the first heat dissipation member 52.

[0136] Based on Figure 16C , after removing the mask pattern MP', the wafer W is cut together with the composite heat dissipation layer 50' into individual chip units to provide Figure 17 the semiconductor device 10F shown in

[0137] Figure 17 is a side cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0138] Based on Figure 17 , except that the semiconductor device 10F includes a composite heat dissipation layer 50' in a different form, the semiconductor device 10F according to the present exemplary embodiment can have a structure the same as or substantially similar to the structure shown in Figure 1 and Figure 2 . Therefore, unless otherwise specified, Figure 1 and Figure 2 the description of the exemplary embodiments shown can be applied to the present exemplary embodiment.

[0139] In the exemplary embodiment employed herein, the composite heat dissipation layer 50' is a product manufactured by the previously described process (see Figures 16A to 16C ), and may include a first heat dissipation member 52 and a second heat dissipation member 55' formed of materials (e.g., graphite) having different orientations. For example, the first heat dissipation member 52 is formed of graphite grown (or oriented) in the z direction, while the second heat dissipation member 55 is formed of graphite grown by tilting the growth surface. In this case, the graphite of the second heat dissipation member 55' grows in a direction intersecting the z direction (e.g., a direction close to the x or y direction), and thus may have a different orientation compared to the graphite of the first heat dissipation member 52. Therefore, the second heat dissipation member 55' can obtain a heat dissipation characteristic in which the vertical thermal conductivity is higher than that of the first heat dissipation member 52.

[0140] As described above, the first heat dissipation member 52 provides effective heat dissipation in the horizontal direction, but relatively ineffective heat dissipation in the vertical direction. To enhance heat dissipation in the vertical direction, the second heat dissipation member 55' is formed to pass through the first heat dissipation member 52.

[0141] According to an exemplary embodiment disclosed herein, a composite heat dissipation layer is provided that has improved heat dissipation ability by forming a vertical pattern on a heat sink (e.g., a graphite sheet) having relatively good heat dissipation characteristics in the horizontal direction using a material (e.g., a metal) having a relatively high vertical thermal conductivity. Such a composite heat dissipation layer can be formed on the surface of a semiconductor chip by a wafer-level method, and such a semiconductor chip can be beneficially introduced into various package structures.

[0142] The various advantages and beneficial effects of the present disclosure are not limited to the above description, and can be easily understood during the description of specific exemplary embodiments.

[0143] Although some exemplary embodiments have been shown and described in detail above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A semiconductor chip having a first surface and a second surface opposite to the first surface; And A composite heat dissipation layer, the composite heat dissipation layer comprising: A first heat dissipation member located on the second surface of the semiconductor chip to directly contact the second surface of the semiconductor chip, the first heat dissipation member having a first vertical thermal conductivity in a direction perpendicular to the second surface and a first horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being less than the first horizontal thermal conductivity; and A second heat dissipation member covering the side surface and the upper surface of the first heat dissipation member, and comprising a vertical pattern disposed along an edge region of the second surface of the semiconductor chip and surrounding the first heat dissipation member and a heat dissipation layer disposed on the first heat dissipation member and connected to the vertical pattern, the vertical pattern passing through the first heat dissipation member to directly contact the second surface of the semiconductor chip, the second heat dissipation member having a second vertical thermal conductivity greater than the first vertical thermal conductivity of the first heat dissipation member, Wherein, a side surface of the composite heat dissipation layer is substantially coplanar with a side surface of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein, The vertical pattern includes a plurality of vertical patterns disposed in the first heat dissipation member.

3. The semiconductor device according to claim 1, wherein, The first heat dissipation member has a monolithic structure not separated by the vertical pattern.

4. The semiconductor device according to claim 1, wherein, The first heat dissipation member includes at least one of graphite or graphene.

5. The semiconductor device according to claim 1, wherein, The second heat dissipation member includes a metal.

6. The semiconductor device according to claim 1, wherein, The first heat dissipation member includes graphite oriented in a first direction, and the second heat dissipation member includes graphite oriented in a second direction intersecting the first direction.

7. A semiconductor package, the semiconductor package comprising: A package substrate including a redistribution layer; A semiconductor chip located on the package substrate, the semiconductor chip including a first surface and a second surface, the first surface including connection pads electrically connected to the redistribution layer, and the second surface being opposite to the first surface; A composite heat dissipation layer, the composite heat dissipation layer including a first heat sink and a second heat sink covering the side surface and the upper surface of the first heat sink, the second heat sink including a vertical pattern disposed along an edge region of the second surface of the semiconductor chip and surrounding the first heat sink and a heat dissipation layer disposed on the first heat sink and connected to the vertical pattern, the first heat sink being located on the second surface of the semiconductor chip, the first heat sink having a first vertical thermal conductivity in a direction perpendicular to the second surface and a first horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being less than the first horizontal thermal conductivity, the vertical pattern passing through the first heat sink to directly contact the second surface of the semiconductor chip, and the second heat sink having a second vertical thermal conductivity greater than the first vertical thermal conductivity of the first heat sink; A sealing member, the sealing member being located on the encapsulation substrate and covering the semiconductor chip; A heat dissipation pattern, the heat dissipation pattern being located on the sealing member; And A heat dissipation path, the heat dissipation path passing through the sealing member to connect the heat dissipation pattern to the composite heat dissipation layer.

8. The semiconductor package according to claim 7, wherein, The semiconductor chip is located on the encapsulation substrate such that the first surface faces the encapsulation substrate.

9. The semiconductor package according to claim 7, wherein, The heat dissipation path is connected to the vertical pattern of the composite heat dissipation layer.

10. The semiconductor package according to claim 7, wherein, The heat dissipation path is connected to the second heat sink.

11. The semiconductor package according to claim 7, the semiconductor package further comprising: A vertical interconnect portion, the vertical interconnect portion being electrically connected to the redistribution layer and passing through the sealing member, and A wiring pattern, the wiring pattern being located on the sealing member and electrically connected to the vertical interconnect portion.

12. The semiconductor package according to claim 7, the semiconductor package further comprising: A frame, the frame being located on the encapsulation substrate, the frame including a cavity configured to receive the semiconductor chip, wherein the sealing member covers the upper surface of the frame.

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