Semiconductor structure and method for forming the same

Abstract

Embodiments described herein are directed to methods for mitigating edge capacitance generated by a patterned gate structure. The method includes forming a gate structure on a fin structure disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first portion and a second portion, wherein the first portion and the second portion are separated by the opening. The method also includes forming a filling structure in the opening, wherein forming the filling structure includes depositing a silicon nitride liner in the opening to cover a sidewall surface of the opening, and depositing silicon oxide on the silicon nitride liner. Embodiments of the present application also include a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor structure and a method for forming the same. Background Art

[0002] During the formation of transistors in an integrated circuit (IC), a long gate structure shared between two or more transistors may be patterned to form a shorter gate structure. The space formed by the removed portion of the gate structure is then filled with dielectric material, which affects device performance due to undesirable fringe capacitance. For example, the delay time of a ring oscillator. Summary of the invention

[0003] In some embodiments, the semiconductor structure includes a first fin structure and a second fin structure located on a substrate, a first gate structure disposed on the first fin structure, and a second gate structure disposed on the second fin structure and separated from the first gate structure, so that a first end of the first gate structure faces a second end of the second gate structure. The semiconductor structure also includes a filling structure inserted between the first end and the second end of the corresponding first gate structure and the second gate structure. The filling structure includes a first layer located on the first end and the second end and a second layer filling a space between the first gate structure and the second gate structure, and the dielectric constant of the second layer is lower than that of the first layer.

[0004] In some embodiments, the semiconductor structure includes a first gate structure disposed on a first fin structure above a substrate, and a second gate structure disposed on a second fin structure above the substrate, wherein the second gate structure is spaced apart from the first gate structure so that a first end of the first gate structure faces a second end of the second gate structure. The semiconductor structure also includes a filling structure inserted between the first end and the second end of the corresponding first gate structure and the second gate structure. The filling structure includes a nitride liner located on the first end and the second end, and an oxide filler including a gap. In addition, the semiconductor structure includes an interlayer dielectric material surrounding the first gate structure, the second gate structure, and the filling structure.

[0005] In some embodiments, a method includes forming a gate structure on a fin structure disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first portion and a second portion, wherein the first portion and the second portion are separated by the opening. The method also includes forming a filling structure in the opening, wherein forming the filling structure includes depositing a silicon nitride liner in the opening to cover a sidewall surface of the opening, and depositing silicon oxide on the silicon nitride liner.

[0006] Embodiments of the present application provide a structure for edge capacitance control. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 and Figure 2 is an isometric view of a gate structure according to some embodiments.

[0009] Figure 3 and Figure 4 is an isometric view of a gate structure after forming a cut that divides the gate structure into two parts, according to some embodiments.

[0010] Figure 5 is an isometric view of a fill structure located within a cutout that divides a gate structure into two parts, according to some embodiments.

[0011] Figure 6 is an isometric view of a fill structure with a gap within a cutout that divides a gate structure into two parts, according to some embodiments.

[0012] Figure 7 is a flow chart of a method for forming a filling structure within a cutout that divides a gate structure into two parts, according to some embodiments.

[0013] Figure 8A-B , Figure 9A-9C , Figure 10A-10B , Figure 11A-11B , Figure 12A-12B and Figure 13A-13B is a cross-sectional view illustrating various processing steps for forming a fill structure within a cutout that divides a gate structure into two parts, according to some embodiments.

[0014] Fig.14 is an isometric view of a fill structure with a gap within a cutout that divides a gate structure into two parts, according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] As used herein, the term "nominal" refers to the desired or target value for a characteristic or parameter of a component or process operation, as set during the design phase of a product or process, as well as values ​​above and / or below the desired value. The range of values ​​is usually due to slight variations in manufacturing processes or tolerances.

[0018] In some embodiments, the terms "about" and "substantially" may mean that the value of a given amount varies within 5% of a target value (eg, ±1%, ±2%, ±3%, ±4%, and ±5% of a target value).

[0019] As used herein, the term "vertical" refers to nominally perpendicular to the surface of a substrate.

[0020] The gate structure in a field effect transistor can be extended to two or more transistors. For example, the gate structure can be formed as a long "line" such as a fin that crosses the active area of ​​the substrate. Once the gate structure is formed, the patterning process "cuts" the long gate structure line into shorter parts according to the desired structure. In other words, the patterning process removes the excess portion of the long gate structure to form one or more "cuts" and divides the long line into shorter parts. This process may be referred to as a cutting-metal-gate (CMG) process. Subsequently, a dielectric material, such as silicon nitride having a dielectric constant greater than 3.9, is filled in the cuts formed between the separated portions of the gate structure. Silicon nitride not only electrically isolates the separated gate structure portions, but also protects the exposed gate structure layer from oxygen infiltration.

[0021] Since the gate structure is actually an electrode embedded in one or more dielectric materials, it forms a parasitic capacitor, which in turn generates undesirable parasitic capacitance and edge capacitance in the integrated circuit. The more cuts formed by the CMG process, the greater the accumulation of edge capacitance in the IC. The edge capacitance is further exacerbated by the use of silicon nitride with a dielectric constant (k value) of approximately 7.4 as a filling material at the end (face) of the patterned gate structure. Edge capacitance (and other parasitic capacitances present near the gate structure) may adversely affect the performance of the IC device, such as slowing down the ring oscillator (RO) circuit and adversely affecting the threshold voltage of the manufactured transistor.

[0022] Embodiments described herein relate to a method for mitigating edge capacitance generated by a patterned gate structure. In some embodiments, edge capacitance is reduced by partially replacing silicon nitride isolation material with a low-k dielectric. In some embodiments, the deposition of the low-k dielectric is adjusted to allow gaps or air gaps to be formed between the patterned gate structures to further reduce the effective dielectric constant of the formed filling structure. In some embodiments, the dielectric stack is formed by first depositing a silicon nitride liner in a cutout, followed by a silicon oxide or silicon oxide-based dielectric filling material (e.g., silicon oxycarbide) that fills the cutout. In some embodiments, the dielectric stack in the cutout may include layers other than the silicon nitride liner and the dielectric filling material. The silicon oxide or silicon oxide-based filling material has a dielectric constant equal to or less than 3.9, which can significantly reduce the combined dielectric constant of the filling structure (e.g., to close to about 3.9).

[0023] According to some embodiments, Figure 1 1 is a partial isometric view of a gate structure 100 on a fin structure 110, which is located on a substrate 120. In some embodiments, the gate structure 100 covers the top and side surfaces of the fin structure 110, such as Figure 1 As shown by the dashed line in FIG. 1 , the length direction of the fin structure extends along the x-axis direction. The fin structure 110 may be isolated by the dielectric layer 130. In some embodiments, the epitaxial structure 140 is formed on the top surface of the recessed portion of the fin structure 110 that is not covered by the gate structure 100. In an alternative embodiment, as shown in FIG. Figure 2 As shown, the epitaxial structure 140 may be formed on the top surface and the sidewall surface of the non-recessed fin structure 110. In some embodiments, the gate structure 100 is isolated from the epitaxial structure 140 by a gate spacer 150. Figure 1 and Figure 2 For ease of illustration, the gate structure 100 and the epitaxial structure 140 are surrounded by an interlayer dielectric (ILD) 160 indicated by a dotted line.

[0024] In some embodiments, additional gate structures, such as gate structure 100, may be formed on different fin structures 110 in parallel with gate structure 100. Figure 1 These additional gate structures are not shown in FIG. Figure 1 and Figure 2 Only a portion of the IC structure is shown, where the spacing between the fin structures (eg, fin pitch), the size of the fin structures, and the size of the gate structures may vary. Figure 1 In addition, Figure 1 and Figure 2 The following figures are for illustration purposes only and are not drawn to scale. Figure 1and Figure 2 The following drawings may not reflect the actual structure, features or actual geometry of the film. For the purpose of explanation, some structures, films or geometric figures may have been intentionally enhanced.

[0025] According to some embodiments, the gate structure 100 includes several layers. By way of example and not limitation, the gate structure 100 may include a dielectric stack 100a, a work function stack 100b, and a metal filler 100c, as well as Figure 1 and Figure 2 And other intermediate layers not shown in the subsequent figures. In some embodiments, Figure 1 and 2 As shown, a hard mask layer 170 is formed on the top surface of the gate structure 100. The hard mask layer 170 may include a bottom metal nitride layer 170a (eg, titanium nitride) and a top silicon nitride layer 170b. According to some embodiments, the hard mask layer 170 protects the gate structure 100 during subsequent operations.

[0026] In some embodiments, substrate 120 is a top layer of a bulk semiconductor wafer or a semiconductor-on-insulator (SOI) wafer (e.g., silicon-on-insulator). In addition, substrate 120 may be made of silicon (Si) or another basic semiconductor [such as (i) germanium (Ge); (ii) a compound semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or (iv) a combination thereof]. In some embodiments, substrate 120 has a crystalline microstructure—e.g., it is not amorphous or polycrystalline.

[0027] The substrate 120 may be formed by patterning Figure 1 and Figure 2 The fin structure 110 shown in . For example, the fin structure 110 can be patterned using one or more photolithography processes including double patterning or multiple patterning processes. The double patterning or multiple patterning process can combine photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches than can be obtained using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate (e.g., substrate 120), and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the retained spacers can then be used to pattern the fin structure 110.

[0028] In some embodiments, the fin structure 110 is made of the same or different material as the substrate 120. By way of example and not limitation, the fin structure 110 may be made of Si or another basic semiconductor [e.g., (i) Ge; (ii) a compound semiconductor including SiC, GaAs, GaP, InP, InAs, and / or InSb; (iii) an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or (iv) a combination thereof]. In some embodiments, the fin structure 110 has a crystalline microstructure—e.g., it is not amorphous or polycrystalline.

[0029] According to some embodiments, the dielectric layer 130 is deposited by a flowable chemical vapor deposition process [e.g., flowable chemical vapor deposition (CVD)] to ensure that the dielectric layer 130 fills the space between the fin structures 110 without forming gaps or voids. In some embodiments, the dielectric layer 130 is a silicon oxide based dielectric (e.g., including nitrogen and / or hydrogen). In order to further improve its dielectric and structural properties, the dielectric layer 130 can be wet steam annealed (e.g., 100% water molecules) at a temperature between about 800° C. and 1200° C. During the wet steam annealing, the dielectric layer 130 is densified and its oxygen content can be increased.

[0030] According to some embodiments, epitaxial structure 140 forms source and drain regions of a fin field effect transistor (FET). By way of example and not limitation, depending on the type of transistor (e.g., n-type or p-type), epitaxial structure 140 may include: (i) boron (B)-doped silicon germanium (SiGe), boron (B)-doped germanium (Ge), or boron (B)-doped germanium tin (GeSn) for a p-type transistor; (ii) carbon-doped silicon (Si:C), phosphorus-doped silicon (Si:P), or arsenic-doped silicon (Si:As) for an n-type transistor. In addition, epitaxial structure 140 may include multiple layers (e.g., two, three, or more layers) having different dopant concentrations and / or crystal microstructures, crystallographic orientations, etc.

[0031] refer to Figure 3In accordance with some embodiments, cuts 300 are formed to split gate structure 100 along the y-axis. Once completed, for example, individual transistors, such as transistor 310 and / or a series of transistors such as transistor 320, are formed by utilizing portions of the same original gate structure 100. This approach provides better process control than other manufacturing methods, allowing a large number of shorter gate structures to be formed at one time. As an example and not limitation, forming cuts 300 can eliminate process-related variability (e.g., during patterning, layer deposition, planarization, etc.) when forming multiple shorter gate structures. In addition, by splitting a long gate structure with one or more cuts (e.g., similar to cut 300), a large group of transistors can be formed from portions of the same original gate structure, which can reduce performance differences across the transistors. In some embodiments, additional cuts like cut 300 can be formed in gate structure 100 and / or in additional gate structures of the integrated circuit as needed. These additional cuts are not included in the Figure 3 Shown in.

[0032] In some embodiments, Figure 4 As shown, the cutout 300 is designed to overetch the dielectric layer 130 and form a recess 400 on its top surface. Figure 4 Similar to Figure 3 , except that the epitaxial structure 140 is intentionally omitted so as to make the recess 400 visible. In some embodiments, the depth of the recess 400 measured from the top surface of the dielectric layer 130 is between about 50 nm and about 100 nm. If the depth of the recess 400 is greater than about 100 nm, the processing time required to fill the cutout 300 will increase, thereby increasing the manufacturing cost. If the depth of the recess 400 is less than about 50 nm, the gate material may not be completely removed from the bottom of the cutout 300. Figure 3 and Figure 4 As shown, the cutout 300 is formed in the ILD 160 as an "opening" that exposes the top surface of the dielectric layer 130 and the face of the gate structure 100. Therefore, the dielectric stack 100a, the work function stack 100b, and the metal filler 100c are exposed within the cutout 300. According to some embodiments, a silicon nitride liner is disposed in the cutout 300 to cover the face of the gate structure 100 and protect the exposed layers of the gate structure 100. In some embodiments, the silicon nitride liner is used as a barrier layer to prevent oxygen from diffusing into the layers of the gate structure 100 (e.g., the dielectric stack 100a and the work function stack 100b). The source of oxygen species is, for example, an oxide layer near the gate structure 100. Oxygen diffusion is undesirable because oxygen diffusion can cause unexpected and uncontrollable threshold voltage shifts in the fabricated transistor.

[0033] According to some embodiments, an oxide layer is subsequently deposited on the silicon nitride liner to fill the cutout 300 . Figure 5The final structure is shown in which a silicon nitride liner 500 and an oxide fill 510 are formed to fill the cutout 300 between the transistor 310 and the transistor 320. As described above, additional cutouts (not shown) may be similarly filled with the silicon nitride liner 500 and the oxide fill 510. In some embodiments, the silicon nitride liner 500 and the oxide fill 510 together form a filling structure 520.

[0034] In some embodiments, the fill structure 520 provides several advantages. For example, after the cutout 300 is formed, the fill structure 520 protects the surface of the gate structure 100. In addition, because the dielectric constant of the oxide fill 510 (e.g., about 3.9) is lower than the dielectric constant of the silicon nitride liner 500 (e.g., about 7.4), the fill structure 520 has a combined dielectric constant (k-value) that is closer to the dielectric constant of the oxide fill 510. This is achieved because the volume occupied by the oxide fill 510 in the fill structure 520 is larger than the volume occupied by the silicon nitride liner 500. Therefore, the effect of the fill structure 520 on the edge capacitance is reduced compared to a fill structure with only silicon nitride as the only fill material. In some embodiments, the thinner the silicon nitride liner 500, the lower the dielectric constant of the resulting fill structure 520. In other words, the larger the volume occupied by the oxide fill 510 in the fill structure 520, the smaller the fill structure 520. The lower the combined dielectric constant (k value) of the structure 520. However, the nitride liner 500 needs to have a sufficient thickness to prevent oxygen from diffusing into the layers of the gate structure 100. In some embodiments, the silicon nitride liner 500 has a thickness of about 5 nm and the oxide fill 510 has a thickness of about 25 nm, or the oxide fill 510 has a thickness sufficient to fill the cutout 300. A silicon nitride liner having a thickness less than 5 nm may not be sufficient to prevent oxygen diffusion, which may cause a threshold voltage shift in the transistor. On the other hand, a silicon nitride liner having a thickness greater than 5 nm sufficiently prevents oxygen diffusion, but at the same time increases the dielectric constant and edge capacitance of the filling structure 520. In some embodiments, the thickness ratio between the silicon nitride liner 500 and the oxide fill 510 in the cutout 300 may be between about 1:5 and about 1:9.

[0035] In some embodiments, when air gaps or gaps are formed in the oxide fill 510, the combined dielectric constant (k value) of the filling structure 520 can be further reduced. This is because the dielectric constant of air is about 1, which is lower than the dielectric constants of the oxide fill 510 and the silicon nitride liner 500. In some embodiments, the larger the air gap in the oxide fill 510, the lower the dielectric constant of the filling structure 520. By way of example and not limitation, Figure 6A filling structure 600 having an air gap (or seam) 610 formed in the oxide fill 510 is shown. In some embodiments, the air gap 610 is formed during the deposition of the oxide fill 510 by adjusting, for example, the deposition rate of the oxide fill 510 and / or the profile geometry of the cutout 300. In some embodiments, the air gap 610 is located below the top surface of the gate structure 100 to prevent the slurry from entering the air gap 610 during the subsequent planarization process. The slurry in the air gap may corrode the oxide fill 510 and the silicon nitride liner 500 (e.g., remove the oxide fill 510 and the silicon nitride liner 500) and reach the layers of the gate structure 100, which is undesirable. In some embodiments, it is feasible to intentionally introduce an air gap or seam in the oxide fill 510 as a means of reducing the dielectric constant and edge capacitance of the filling structure 520. In some embodiments, the air gap or seam 610 introduced in the oxide fill 510 has a width along the y-axis between 0 nm and about 3 nm.

[0036] Figure 7 700 is a flow chart describing a manufacturing method 700 for forming a structure having a silicon nitride liner, an oxide fill, and an optional air gap or seam fill according to some embodiments. Other manufacturing processes may be performed between various processes of method 700, which may be omitted for clarity and ease of description. These various operations are included within the scope of the present invention. In addition, not all operations need to be performed in the manner provided herein. In addition, some operations may be performed simultaneously or in different steps. Figure 7 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. For illustrative purposes, reference will be made to Figure 1-6 8-14 are used to describe the method 700. The drawings provided for describing the method 700 are for illustrative purposes only and are not drawn to scale. In addition, these drawings may not reflect the actual geometry of the actual structure, features or films. For the purpose of illustration, some structures, films or geometric figures may have been intentionally enhanced.

[0037] refer to Figure 7 , method 700 begins at operation 710 and a process of depositing and patterning a hard mask over a gate structure. For example, Fig. 8A and Figure 8B (respectively Figure 1 A hard mask 800 is formed and patterned to form an opening 810 in the hard mask material, as shown in a cross-sectional view along lines AB and CD of FIG. Fig. 8A It is a cross section along the direction of the gate structure 100, and is therefore referred to as a “y-cut”. Figure 8Bis a cross section along a direction parallel to the fin structure 110, referred to as an "x-cut". In some embodiments, the hard mask 800 is a photoresist material that is spun onto the structure of the substrate 120 and then patterned. In some embodiments, the hard mask 800 is a silicon nitride layer, or any other suitable material that can be used as an etching mask and prevents the masked areas of the gate structure 100 and the ILD 160 from being etched.

[0038] By way of example and not limitation, Figure 8B As shown, the opening 810 may have a sidewall 810s inclined along the direction of the gate structure 100 (eg, along the y-axis), and as shown in FIG. Fig. 8A The substantially vertical sidewalls along the direction of the fin structure 110 (e.g., along the x-axis) are shown. In some embodiments, the opening 810 exposes the top surface of the hard mask layer 170 (e.g., the top silicon nitride 170b). Note that the opening 810 also extends above the ILD 160. In other words, as shown in FIG. Figure 8B as well as Figure 3 and Figure 4 As shown in the isometric view of , a portion of ILD 160 is exposed by opening 810 .

[0039] refer to Figure 7 , the method 700 continues with operation 720 and a process of forming a cutout in the gate structure through the patterned hard mask, e.g. Figure 3 and Figure 4 Cutout 300 is shown. Fig. 9A and Fig. 9B The cross-sectional views along the y-axis and the x-axis are shown respectively. Fig. 9B In the embodiment, a transistor 320 (such as Figure 3 and Figure 4 The surface of the gate structure 100 (shown in FIG. 1 ) is visible in the background through the cutout 300. In some embodiments, the cutout 300 is formed by dry etching. The etching process may include several etching operations, each etching operation having a suitable etching gas chemistry. In some embodiments, the dry etching process used to form the cutout 300 is an anisotropic etching process. Therefore, the cutout 300 may have substantially vertical sidewalls. However, this is not limiting, and the cutout 300 may have substantially vertical sidewalls. Fig. 9C In some embodiments, the negatively sloped sidewalls may be formed only along the y-axis (eg, a direction parallel to the gate structure 100 ). Further details regarding the sloped sidewalls will be discussed below with respect to operation 740 of method 700 .

[0040] According to some embodiments, the etching process is configured to remove the exposed portion of the hard mask layer 170, the exposed portion of the gate structure 100, and the exposed portion of the ILD 160. In some embodiments, once the gate structure 100 and the ILD 160 are removed, the etching process etches the exposed portion of the dielectric layer 130 as discussed above and forms the recess 400 on the top surface of the dielectric layer 130. In some embodiments, the cutout 300 has a height H between about 140 nm and about 190 nm and a width W along the y-axis of about 18 nm to about 24 nm. Figure 3 and Figure 4 As shown in the isometric view of FIG. 3 , in some embodiments, the width W is a spacing or gap between a portion of the gate structure 100 that forms the transistor 310 and a portion of the gate structure 100 that forms the transistor 320. In some embodiments, the aspect ratio (H / W) of the cutout 300 is in a range of about 8 to about 1. In some embodiments, if the width of the cutout 300 is greater than about 24 nm, the performance of the transistor 310 and the transistor 320 will be adversely affected. In addition, if the length of the cutout 300 is less than about 140 nm, the depth of the groove 400 may be difficult to control.

[0041] refer to Figure 7 The method 700 continues with operation 730 and depositing a silicon nitride liner (eg, Figure 5 and Figure 6 In some embodiments, Fig. 10A and Fig. 10B The liner 500 deposited in the cutout 300 when viewed along the y-axis and the x-axis are shown, respectively. In some embodiments, the silicon nitride liner 500 is deposited by a conformal process [e.g., an atomic layer deposition (ALD) process] at a temperature between about 300 degrees Celsius and about 500 degrees Celsius and a processing pressure between about 10 Toor and about 30 Toor, with a deposition thickness of about 5 nm. As described above, the silicon nitride liner 500 needs to have a sufficient thickness to prevent oxygen from diffusing into the gate structure 100. A silicon nitride liner having a thickness less than 5 nm may not be sufficient to prevent oxygen diffusion, thereby causing a threshold voltage shift in the transistor. On the other hand, a silicon nitride liner having a thickness greater than 5 nm can adequately prevent oxygen diffusion, but it will also increase the dielectric constant and edge capacitance of the filling structure. As described above, the silicon nitride liner 500 may have a thickness less than 5 nm. Fig. 10A and Fig. 10B As shown in the previous Figure 5, the silicon nitride liner 500 does not fill the cutout 300 and does not adequately cover the exposed surface of the gate structure 100. In some embodiments, cracks or thin portions (e.g., less than about 5 nm) of the silicon nitride liner 500 may serve as weak points for oxygen diffusion. By way of example and not limitation, the location of the weak points may be difficult to fill geometries such as corners, voids, cracks, and / or the bottom of the cutout 300. For at least this reason, it is important to deposit the silicon nitride liner 500 using a process (e.g., an ALD-based process) that is capable of producing conformal films.

[0042] refer to Figure 7 The method 700 continues with operation 740 and depositing an oxide fill (eg, Figure 5 The process of oxide filling 510) is shown in an isometric view of FIG. In some embodiments, Fig.11A and Fig. 11B The oxide filler deposited in the cutout 300 is shown when viewed along the y-axis and the x-axis, respectively. In some embodiments, the oxide filler 510 is deposited by a plasma-assisted process [e.g., a plasma-assisted ALD (PEALD) process] to a thickness sufficient to fill the cutout 300, for example, about 25 nm. In some embodiments, the oxide filler 510 is deposited at a lower temperature than the silicon nitride liner 500 (e.g., between about 100° C. and about 300° C.) and a higher process pressure (e.g., between about 1000 Torr and about 5000 Torr). In some embodiments, the deposition rate of the oxide filler 510 can be primarily regulated by the power of the plasma implemented during deposition, which ranges between about 15 Watts and 500 Watts. In some embodiments, a lower plasma power setting (e.g., close to 15 Watts) results in a higher deposition rate than a higher plasma power setting (e.g., close to about 500 Watts). The process temperature and pressure can also be used to adjust the deposition rate of the oxide fill 510; however, the degree of adjustment that can be achieved with the above process parameters is limited compared to the adjustment achieved with the plasma power setting. In other words, the deposition rate of the oxide fill 510 is more sensitive to the plasma power setting than to the process temperature and / or pressure. Figure 5 , Fig.11A and Fig. 11B As discussed above, silicon nitride liner 500 and oxide filler 510 together form filling structure 520. In some embodiments, oxide filler 510 includes silicon oxide (SiO2) having a dielectric constant of about 3.9 or a silicon oxide-based dielectric having a dielectric constant of about 2.6, such as silicon oxycarbide (SiOC).

[0043] In some embodiments, the deposition rate of the oxide filler 510 can be used to form optional gaps or air gaps in the oxide filler 510. For example, a higher deposition rate can form a premature "neck" at the opening of the cut 300, thereby limiting the delivery of reactants at the bottom of the cut 300. Therefore, the top of the cut 300 is "sealed" before the cut 300 is filled with the oxide filler 510. This effect can be assisted or exacerbated by changing the profile geometry of the cut 300 (e.g., creating a re-entrant top profile for the cut 300). By way of example and not limitation, the etching process responsible for forming the cut 300 can be adjusted to form the sidewalls of the cut 300 with a negative slope, such as Fig. 9C As shown in the x-cut of the cut 300, when the sidewall angle θ of the cut 300 is less than about 90°, a negative slope is formed, so that the top opening 300t is smaller than the bottom opening 300b (for example, 300t<300b). In some embodiments, the contour geometry of the cut 300 corresponds to Figure 5 This is because profile changes along the y-cut direction (e.g., in the yz plane) will affect the slope of the surface of the gate structure 100, which may affect the reliability and electrical performance of the manufactured transistor. As an example and not limitation, due to the etching process used to form the cutout 300, the bottom corners of the cutout 300 may be chamfered (e.g., rounded).

[0044] In some embodiments, the deposition rate of oxide fill 510, alone or in combination with the profile geometry of cutout 300, can be used as a means to controllably and reproducibly form gaps or air gaps within oxide fill 510. By way of example and not limitation, Figure 6 An isometric view of the Fig. 12A and Fig. 12B The cross-sectional view shown shows an optional air gap or seam 610 formed within the oxide fill 510 in the fill structure 600. As described above, the air gap or seam 610 can be formed by adjusting (i) the deposition rate of the oxide fill 510, (ii) the profile geometry of the opening 300, or (iii) a combination of both. It should be noted that the position of the seam or air gap 610 needs to be lower than the top surface of the gate structure 100 to prevent the air gap 610 from being exposed during the subsequent planarization process. As described above, the width of the air gap or seam 610 along the y-direction is between 0 nm and about 3 nm. Wider air gaps or seams (e.g., wider than about 3 nm) increase the possibility of exposing the air gap or seam 610 during the subsequent planarization process, which is undesirable.

[0045] In reference Figure 7 When the method 700 continues with operation 750 and FIG. 11A to FIG. 11B and FIG. 12A to FIG. 12B750 . In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process that removes the oxide filler 510, the silicon nitride liner 500, and the hard mask layer 170 from the top surface of each portion of the gate structure 100. In some embodiments, in the planarization process described above, the top of the gate structure 100 is also removed. In other words, the original height of the gate structure 100 can be reduced by the planarization process of operation 750. By way of example and not limitation, FIG. 13A to FIG. 13B The cross-sectional view and Fig.14 The isometric view of FIG. 700 shows the resulting structure after the planarization process of operation 750. In some embodiments, as a result of method 700, more than one discrete (e.g., unjoined) air gap or seam (e.g., air gap or seam 610) may be formed within oxide fill 510. For example, two or three discrete air gaps or seams may be formed within oxide fill 510 along cut 300 in the x-direction.

[0046] As described above, when the planarization process planarizes the filling structure 600, it is necessary to locate the air gap or gap 610 so that the air gap or gap 610 is not exposed. If the planarization process exposes and opens the air gap 610, the slurry from the planarization process will enter the air gap and begin to corrode the oxide filler 510 and the silicon nitride liner 500 within the filling structure 600. In this case, the air gap 610 will increase significantly in an uncontrolled and reproducible manner. In addition, when the oxide filler 510 and the silicon nitride liner 500 are corroded, the slurry can reach the gate structure 100 and continue to "attack" the dielectric stack 100a, the work function stack 100b and the metal filler 100c. In addition, the exposed air gap 610 may be unintentionally filled with materials from a subsequent deposition process, which can significantly increase the edge capacitance and reduce the reliability of the chip.

[0047] Embodiments described herein are directed to methods for mitigating edge capacitance generated by patterned gate structures. In some embodiments, edge capacitance can be reduced by partially replacing silicon nitride isolation materials with lower-k oxides. In some embodiments, the profile of the deposition or cutout of the lower-k oxide can be adjusted respectively to allow gaps or air gaps to be formed within the lower-k oxide to further reduce the effective dielectric constant of the formed filling structure. In some embodiments, a dielectric stack is formed by first depositing a silicon nitride liner in the cutout and then filling the cutout with silicon oxide or a silicon oxide-based dielectric. In some embodiments, the silicon nitride liner has a thickness of about 5nm and the oxide filler has a thickness of about 25nm or more. In some embodiments, the silicon oxide-based or silicon oxide-based filling material has a dielectric constant equal to or less than about 3.9, which can substantially reduce the combined dielectric constant of the filling structure (e.g., to be close to about 3.9). In some embodiments, the deposition rate of the oxide filler can be adjusted by the plasma power in the PEALD process used to deposit the oxide filler. In some embodiments, the higher the deposition rate of the oxide filler, the larger the gap or air gap formed in the filling structure.

[0048] In some embodiments, the semiconductor structure includes a first fin structure and a second fin structure located on a substrate, a first gate structure disposed on the first fin structure, and a second gate structure disposed on the second fin structure and separated from the first gate structure, so that a first end of the first gate structure faces a second end of the second gate structure. The semiconductor structure also includes a filling structure inserted between the first end and the second end of the corresponding first gate structure and the second gate structure. The filling structure includes a first layer located on the first end and the second end and a second layer filling a space between the first gate structure and the second gate structure, and the dielectric constant of the second layer is lower than that of the first layer.

[0049] In some embodiments, the second layer includes an air gap below the top surface of the first gate structure and the second gate structure. In some embodiments, the width of the filling structure corresponds to the distance between the first and second gate structures. In some embodiments, the width of the filling structure ranges between about 18nm and about 24nm. In some embodiments, the first layer includes a nitrogen-containing material and the second layer includes an oxide material. In some embodiments, the first layer is thinner than the second layer. In some embodiments, the filling structure is parallel to the first and second fin structures. In some embodiments, an interlayer dielectric material surrounding the first gate structure, the second gate structure and the filling structure is also included.

[0050] In some embodiments, the semiconductor structure includes a first gate structure disposed on a first fin structure above a substrate, and a second gate structure disposed on a second fin structure above the substrate, wherein the second gate structure is spaced apart from the first gate structure so that a first end of the first gate structure faces a second end of the second gate structure. The semiconductor structure also includes a filling structure inserted between the first end and the second end of the corresponding first gate structure and the second gate structure. The filling structure includes a nitride liner located on the first end and the second end, and an oxide filler including a gap. In addition, the semiconductor structure includes an interlayer dielectric material surrounding the first gate structure, the second gate structure, and the filling structure.

[0051] In some embodiments, the top surfaces of the filling structure, the first gate structure, and the second gate structure are coplanar. In some embodiments, the length of the filling structure is perpendicular to the length of the first gate structure and the second gate structure. In some embodiments, the thickness ratio between the nitride liner and the oxide filling ranges between about 1:5 and about 1:9. In some embodiments, the bottom surface of the filling structure is below the bottom surface of the first gate structure and the second gate structure.

[0052] In some embodiments, a method includes forming a gate structure on a fin structure disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first portion and a second portion, wherein the first portion and the second portion are separated by the opening. The method also includes forming a filling structure in the opening, wherein forming the filling structure includes depositing a silicon nitride liner in the opening to cover a sidewall surface of the opening, and depositing silicon oxide on the silicon nitride liner.

[0053] In some embodiments, depositing a silicon nitride liner includes conformally depositing a silicon nitride liner such that a thickness ratio between the silicon nitride liner and silicon oxide ranges from about 1:5 to about 1:9. In some embodiments, depositing silicon oxide includes depositing silicon oxide using a plasma assisted process, and a deposition rate of the plasma assisted process can be adjusted by a plasma power of the plasma assisted process. In some embodiments, depositing silicon oxide includes filling an opening with silicon oxide. In some embodiments, depositing silicon oxide includes forming an air gap in the silicon oxide. In some embodiments, wherein forming the air gap includes adjusting a deposition rate of silicon oxide. In some embodiments, forming an opening includes forming an opening having sidewalls having a negative slope along a plane parallel to a width of the gate structure.

[0054] It should be understood that the "Detailed Description" section, rather than the "Abstract of the Disclosure" section, is intended to be used to interpret ownership issues. As intended by the inventor, the Abstract of the Disclosure section may set forth one or more but not all possible embodiments of the disclosure contemplated by the inventor, and therefore, may not limit the dependent claims in any way.

[0055] The above disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A first fin structure and a second fin structure are located on a substrate; A first gate structure, disposed on the first fin structure; a second gate structure disposed on the second fin structure and spaced apart from the first gate structure, wherein a first end of the first gate structure faces a second end of the second gate structure; A filling structure, inserted between the first end and the second end of the corresponding first gate structure and second gate structure, comprising: A first layer is located on the first end and the second end; and a second layer fills the space between the first gate structure and the second gate structure, wherein the dielectric constant of the second layer is lower than that of the first layer, wherein the second layer includes an air gap, and the second layer has a vertical sidewall profile from bottom to top along the length direction of the first gate structure and the second gate structure, and has a sidewall profile with a negative slope along the length direction of the first fin structure and the second fin structure, so that the top width of the second layer is shorter than the bottom width of the second layer.

2. The semiconductor structure according to claim 1, wherein: The air gap is located below top surfaces of the first gate structure and the second gate structure.

3. The semiconductor structure according to claim 1, wherein: The width of the filling structure corresponds to the distance between the first gate structure and the second gate structure.

4. The semiconductor structure according to claim 3, wherein: The width of the filling structure ranges between 18 nm and 24 nm.

5. The semiconductor structure according to claim 1, wherein: The first layer includes a nitrogen-containing material, and the second layer includes an oxide material.

6. The semiconductor structure according to claim 1, wherein: The first layer is thinner than the second layer.

7. The semiconductor structure according to claim 1, wherein: The filling structure is parallel to the first fin structure and the second fin structure. 8 . The semiconductor structure of claim 1 , further comprising an interlayer dielectric material surrounding the first gate structure, the second gate structure, and the filling structure.

9. A semiconductor structure comprising: A first gate structure is disposed on the first fin structure above the substrate; a second gate structure disposed on a second fin structure above the substrate and spaced apart from the first gate structure, wherein a first end of the first gate structure faces a second end of the second gate structure; a filling structure inserted between the first and second ends of the respective first and second gate structures and comprising: a nitride liner located on the first end and the second end; and an oxide filling including a gap, wherein the oxide filling has a vertical sidewall profile from bottom to top in a length direction along the first gate structure and the second gate structure, and has a negative slope profile sidewall in a length direction along the first fin structure and the second fin structure, so that a top width of the oxide filling is shorter than a bottom width of the oxide filling; and An interlayer dielectric material surrounds the first gate structure, the second gate structure and the filling structure.

10. The semiconductor structure according to claim 9, wherein: Top surfaces of the filling structure, the first gate structure, and the second gate structure are coplanar.

11. The semiconductor structure according to claim 9, wherein: A length direction of the filling structure is perpendicular to length directions of the first gate structure and the second gate structure.

12. The semiconductor structure according to claim 9, wherein: A thickness ratio between the nitride liner and the oxide filler ranges between 1:5 and 1:

9.

13. The semiconductor structure according to claim 9, wherein: A bottom surface of the filling structure is below bottom surfaces of the first and second gate structures.

14. A method of forming a semiconductor structure, comprising: forming a gate structure on a fin structure disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first portion and a second portion, wherein the first portion and the second portion are separated by the opening, wherein the opening has a vertical opening sidewall profile from bottom to top in a length direction of the gate structure and has a negatively sloped opening sidewall profile in a length direction of the fin structure so that the top of the opening is shorter than the bottom of the opening; and forming a filling structure in the opening, wherein forming the filling structure comprises: depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening; and depositing silicon oxide on the silicon nitride liner; Wherein, depositing the silicon oxide includes forming air gaps in the silicon oxide.

15. The method according to claim 14, wherein: Depositing the silicon nitride liner includes conformally depositing the silicon nitride liner such that a thickness ratio between the silicon nitride liner and the silicon oxide ranges from 1:5 to 1:

9.

16. The method according to claim 14, wherein: Depositing the silicon oxide includes depositing the silicon oxide using a plasma assisted process, wherein a deposition rate of the plasma assisted process can be adjusted by a plasma power of the plasma assisted process.

17. The method according to claim 16, wherein: Depositing the silicon oxide includes filling the opening with the silicon oxide.

18. The method according to claim 14, wherein: The width of the air gap along the length direction of the gate structure is between 0 nm and 3 nm.

19. The method according to claim 14, wherein: Forming the air gap includes adjusting a deposition rate of the silicon oxide.

20. The method according to claim 14, wherein: The bottom corners of the opening are chamfered.

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