Multistage power amplifier with low voltage drive stage and apparatus

Abstract

An amplifier includes a driver stage amplifier transistor and a final stage amplifier transistor integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance. The final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to radio frequency (RF) amplifiers, and more specifically, to power transistor devices and amplifiers, as well as methods of manufacturing such devices and amplifiers. Background Technology

[0002] Wireless communication systems increasingly require higher efficiency to reduce operating and system costs. In wireless communication system transmitters, radio frequency (RF) power amplifiers are among the most power-consuming components, and typically have the greatest impact on the total power dissipation. Therefore, amplifier and transmitter designers strive to develop RF power amplifiers that reduce power consumption and power loss while maintaining or improving efficiency and RF bandwidth. Summary of the Invention

[0003] This invention provides an amplifier, comprising:

[0004] A driver-stage amplifier transistor, the driver-stage amplifier transistor being integrated in a semiconductor die and having a driver-stage input, a driver-stage output, and an output impedance, wherein the driver-stage amplifier transistor is configured to operate using a first bias voltage at the driver-stage output; and

[0005] A final-stage amplifier transistor, the final-stage amplifier transistor being integrated in the semiconductor die and having a final-stage input, a final-stage output, and an input impedance, wherein the final-stage input is electrically coupled to the driver stage output, and the final-stage amplifier transistor is configured to operate using a second bias voltage at the final-stage output, wherein the second bias voltage is at least twice the size of the first bias voltage.

[0006] According to one or more embodiments, the driver stage amplifier transistor has an output impedance; the final stage amplifier transistor has an input impedance; the ratio of the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier transistor is less than 10:1; and the amplifier further includes an interstage impedance matching circuit electrically coupled between the driver stage output and the final stage input, wherein the interstage impedance matching circuit is configured to perform impedance transformation from the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier.

[0007] According to one or more embodiments, the output impedance of the driver stage amplifier is less than 10 ohms; and the second impedance is less than 5 ohms.

[0008] According to one or more embodiments, the driver stage amplifier transistor is characterized by a first drain-source on-resistance; and the final stage amplifier transistor is characterized by a second drain-source on-resistance greater than the first drain-source resistance.

[0009] According to one or more embodiments, the driver stage amplifier transistor is characterized by a first breakdown voltage; and the final stage amplifier transistor is characterized by a second breakdown voltage that is at least 100% higher than the first breakdown voltage.

[0010] According to one or more embodiments, the driver stage amplifier transistor is characterized by a first power density; and the final stage amplifier transistor is characterized by a second power density that is at least 200% greater than the first power density.

[0011] According to one or more embodiments, the semiconductor die is a silicon-based die, the drive amplifier transistor is a first laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET), and the final stage amplifier is a second LDMOS FET.

[0012] According to one or more embodiments, the driver stage amplifier transistor has a first transistor finger, the first transistor finger including a first gate structure having a first sidewall, a first drain region, and a first drift region extending from the first sidewall to the first drain region, and wherein the driver stage amplifier transistor is characterized by a first drain-source on-resistance; and the final stage amplifier transistor has a second transistor finger, the second transistor finger including a second gate structure having a second sidewall, a second drain region, and a second drift region extending from the second sidewall to the second drain region, and wherein the final stage amplifier transistor is characterized by a second drain-source on-resistance greater than the first drain-source resistance.

[0013] According to one or more embodiments, the first drift region and the second drift region have one or more different characteristics selected from different doping degrees, different drift region widths, different drift region depths, and different drift region lengths.

[0014] According to one or more embodiments, the first drift region has a first length between the first sidewall and the first drain region; and the second drift region has a second length between the second sidewall and the second drain region, wherein the second length is at least 50% greater than the first length.

[0015] According to a second aspect of the present invention, an amplifier is provided, comprising:

[0016] A driver-stage field-effect transistor (FET), the FET being integrated in a semiconductor die and having a driver-stage input, a driver-stage output, and an output impedance, wherein the driver-stage amplifier transistor is characterized by a first breakdown voltage;

[0017] A final-stage FET, said final-stage FET being integrated in the semiconductor die and having a final-stage input, a final-stage output, and an input impedance, and said final-stage amplifier transistor being characterized by a second breakdown voltage at least 100% higher than the first breakdown voltage; and

[0018] An interstage impedance matching circuit electrically coupled between the driver stage output and the final stage input, wherein the interstage impedance matching circuit is configured to perform impedance transformation from the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier.

[0019] According to one or more embodiments, the ratio of the output impedance to the input impedance is less than 10:1.

[0020] According to one or more embodiments, the output impedance of the driver stage FET is less than 10 ohms; and the input impedance of the final stage FET is less than 5 ohms.

[0021] According to one or more embodiments, the driving stage FET is characterized by a first power density; and the final stage FET is characterized by a second power density that is at least 200% greater than the first power density.

[0022] According to one or more embodiments, the driving stage FET is characterized by a first drain-source on-resistance; and the final stage FET is characterized by a second drain-source on-resistance greater than the first drain-source on-resistance.

[0023] According to one or more embodiments, the amplifier further includes: an amplifier substrate; and a power amplifier module coupled to the amplifier substrate, wherein the power amplifier module includes the semiconductor die in which the driver stage FET and the final stage FET are integrated; a first connector coupled to the substrate and configured to receive a first bias voltage; a second connector coupled to the substrate and configured to receive a second bias voltage; a first conductive path coupled between the first connector and the driver stage output; and a second conductive path coupled between the second connector and the final stage output.

[0024] According to one or more embodiments, the amplifier further includes: a preamplifier module coupled to the substrate; and a third conductive path coupled between the first connector and the preamplifier module.

[0025] According to a third aspect of the present invention, a method is provided for operating an amplifier including a driver stage amplifier transistor and a final stage amplifier transistor coupled in series and integrated in a semiconductor die, the method comprising:

[0026] Provide a first bias voltage to the output of the driver stage amplifier transistor; and

[0027] A second bias voltage is provided to the output of the final stage amplifier transistor, wherein the second bias voltage is at least twice the first bias voltage.

[0028] According to one or more embodiments, the first bias voltage is less than 10 volts; and the second bias voltage is greater than 20 volts.

[0029] According to one or more embodiments, the driver stage amplifier transistor and the final stage amplifier transistor are implemented in a power amplifier module coupled to a substrate, the amplifier further including a preamplifier module coupled to the substrate, and the method further including: providing the first bias voltage to the preamplifier module. Attached Figure Description

[0030] A more complete understanding of the subject matter can be obtained by considering the following figures, and by referring to the detailed embodiments and claims, in which similar reference numerals are used throughout the figures to refer to similar elements.

[0031] Figure 1 This is a schematic circuit diagram of a power amplifier circuit according to an example embodiment;

[0032] Figure 2 This is a top view of a two-stage power amplifier integrated circuit (IC) according to an example embodiment;

[0033] Figure 3 According to the embodiments Figure 2 A cross-sectional side view of a portion of the driver amplifier transistor;

[0034] Figure 4 According to the embodiments Figure 2 A cross-sectional side view of a portion of the final stage amplifier transistor;

[0035] Figure 5 This is a simplified schematic diagram of a Doherty power amplifier according to an example embodiment;

[0036] Figure 6 This is a top view of the Dougherty amplifier module according to an example embodiment;

[0037] Figure 7 This is a perspective view of the transceiver module according to an example embodiment; and

[0038] Figure 8 This is a flowchart of a method for operating an amplifier according to an example embodiment. Detailed Implementation

[0039] An embodiment of an amplifier includes a driver-stage amplifier transistor and a final-stage amplifier transistor integrated in a semiconductor die. The driver-stage amplifier transistor has a driver-stage input, a driver-stage output, and an output impedance, and is configured to operate using a first bias voltage at the driver-stage output. The final-stage amplifier transistor has a final-stage input, a final-stage output, and an input impedance, wherein the final-stage input is electrically coupled to the driver-stage output. The final-stage amplifier transistor is configured to operate using a second bias voltage at the final-stage output, and the second bias voltage is at least twice the first bias voltage.

[0040] According to another embodiment, the driver stage amplifier transistor has an output impedance, the final stage amplifier transistor has an input impedance, and the ratio of the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier transistor is less than 10:1. According to yet another embodiment, the amplifier further includes an interstage impedance matching circuit electrically coupled between the driver stage output and the final stage input, the interstage impedance matching circuit being configured to perform impedance transformation from the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier. According to yet another embodiment, the output impedance of the driver stage amplifier is less than 10 ohms, and the second impedance is less than 5 ohms. According to yet another embodiment, the driver stage amplifier transistor is characterized by a first drain-source on-resistance, and the final stage amplifier transistor is characterized by a second drain-source on-resistance greater than the first drain-source resistance. According to yet another embodiment, the driver stage amplifier transistor is characterized by a first breakdown voltage, and the final stage amplifier transistor is characterized by a second breakdown voltage at least 100% higher than the first breakdown voltage. According to yet another embodiment, the driver stage amplifier transistor is characterized by a first power density, and the final stage amplifier transistor is characterized by a second power density at least 200% higher than the first power density. According to another embodiment, the semiconductor die is a silicon-based die, the driver amplifier transistor is a first laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET), and the final stage amplifier is a second LDMOS FET. According to yet another embodiment, the driver amplifier transistor has a first transistor finger, the first transistor finger including a first gate structure having a first sidewall, a first drain region, and a first drift region extending from the first sidewall to the first drain region, wherein the driver amplifier transistor is characterized by a first drain-source on-resistance; and the final stage amplifier transistor has a second transistor finger, the second transistor finger including a second gate structure having a second sidewall, a second drain region, and a second drift region extending from the second sidewall to the second drain region, wherein the final stage amplifier transistor is characterized by a second drain-source on-resistance greater than the first drain-source resistance. According to yet another embodiment, the first drift region and the second drift region have one or more different characteristics selected from different doping degrees, different drift region widths, different drift region depths, and different drift region lengths. According to another embodiment, the first drift region has a first length between the first sidewall and the first drain region, and the second drift region has a second length between the second sidewall and the second drain region, wherein the second length is at least 50% greater than the first length.

[0041] Another embodiment of an amplifier includes a driver-stage field-effect transistor (FET) and a final-stage FET integrated in a semiconductor die. The driver-stage FET has a driver-stage input, a driver-stage output, and an output impedance, and the driver-stage amplifier transistor is characterized by a first breakdown voltage. The final-stage FET has a final-stage input, a final-stage output, and an input impedance, and the final-stage amplifier transistor is characterized by a second breakdown voltage at least 100% higher than the first breakdown voltage. The amplifier further includes an interstage impedance matching circuit electrically coupled between the driver-stage output and the final-stage input, wherein the interstage impedance matching circuit is configured to perform impedance transformation from the output impedance of the driver-stage amplifier transistor to the input impedance of the final-stage amplifier.

[0042] According to another embodiment, the ratio of output impedance to input impedance is less than 10:1. According to yet another embodiment, the output impedance of the driver stage FET is less than 10 ohms, and the input impedance of the final stage FET is less than 5 ohms. According to yet another embodiment, the driver stage FET is characterized by a first power density, and the final stage FET is characterized by a second power density at least 200% greater than the first power density. According to yet another embodiment, the driver stage FET is characterized by a first drain-source on-resistance, and the final stage FET is characterized by a second drain-source on-resistance greater than the first drain-source on-resistance. According to yet another embodiment, the amplifier further includes: an amplifier substrate; and a power amplifier module coupled to the amplifier substrate, wherein the power amplifier module includes a semiconductor die integrating the driver stage FET and the final stage FET; a first connector coupled to the substrate and configured to receive a first bias voltage; a second connector coupled to the substrate and configured to receive a second bias voltage; a first conductive path coupled between the first connector and the driver stage output; and a second conductive path coupled between the second connector and the final stage output. According to another embodiment, the amplifier further includes a preamplifier module coupled to the substrate, and a third conductive path coupled between the first connector and the preamplifier module.

[0043] An embodiment of a method for operating an amplifier including a driver-stage amplifier transistor and a final-stage amplifier transistor series-coupled and integrated in a semiconductor die, the method comprising the steps of: providing a first bias voltage to the output of the driver-stage amplifier transistor; and providing a second bias voltage to the output of the final-stage amplifier transistor, wherein the second bias voltage is at least twice the first bias voltage. According to another embodiment, the first bias voltage is less than 10 volts and the second bias voltage is greater than 20 volts. According to yet another embodiment, the driver-stage amplifier transistor and the final-stage amplifier transistor are implemented in a power amplifier module coupled to a substrate, the amplifier further including a preamplifier module coupled to the substrate, and the method further includes providing a first bias voltage to the preamplifier module.

[0044] The embodiments of RF power amplifier architectures disclosed herein include a low-voltage driver stage (e.g., 5 volts (V)) and a high-voltage final stage (e.g., 28-32 V), wherein a “low-voltage driver stage” means a power amplifier transistor configured to operate at a relatively low output bias voltage (e.g., drain bias voltage), and a “high-voltage final stage” means a power amplifier transistor configured to operate at a relatively high output bias voltage (e.g., drain bias voltage). The RF power amplifier architectures disclosed herein can have several potential advantages compared to conventional two-stage amplifiers that bias the outputs of their driver and final stages at the same relatively high voltage (e.g., 28 V or higher).

[0045] For example, given the relatively low output bias voltage, the low-voltage driver stage embodiments disclosed herein can be designed to have a much lower output impedance (e.g., Z1, or the impedance to the drain of the driver stage transistor) than a conventional high-voltage driver stage that biases its output at a higher voltage (e.g., 28V or higher). For example, the low-voltage driver stage embodiments can have an output impedance of less than 10 ohms, while a conventional high-voltage driver stage can have an output impedance of 60 ohms or higher. Considering that the input impedance of the final stage (e.g., Z2, or the impedance to the gate of the final stage transistor) can be only a few ohms (e.g., 2-5 ohms or less), it is evident that the embodiments of the interstage impedance matching network between the low-voltage driver stage output and the high-voltage final stage input can be characterized by a significantly reduced impedance transformation ratio compared to the impedance transformation ratio required by a conventional two-stage amplifier (i.e., the ratio of the driver stage output impedance to the final stage input impedance). For example, for a conventional two-stage power amplifier, a 28V drive stage may require an impedance transformation ratio of about 30:1 to 50:1 (e.g., from about 60-100 ohms Z1 to about 2 ohms Z2), while an embodiment of a low-voltage drive stage may only require an impedance transformation ratio of less than 10:1 (e.g., about 2.5:1 to 5:1, corresponding to an impedance transformation ratio from about 5-10 ohms Z1 to about 2 ohms Z2).

[0046] Because only a relatively low impedance transformation ratio is required, the interstage impedance matching networks used in various embodiments can be relatively simple (e.g., fewer impedance matching stages and passive components). Therefore, the losses of the interstage impedance matching network can be significantly reduced during operation (e.g., by 3 dB or more) compared to the losses caused by a conventional two-stage amplifier.

[0047] For example, assuming a 3dB reduction in interstage matching losses, the required output power from the low-voltage driver stage can also be reduced by 3dB. Therefore, the DC power consumption of the low-voltage driver stage embodiment can be further reduced compared to a conventional high-voltage driver stage. In other words, the DC power consumption of the low-voltage driver stage embodiment discussed herein can be significantly less than that of a conventional driver stage. Essentially, with relatively fewer matching stages and components, the power dissipated in the interstage matching network embodiment is significantly reduced compared to a conventional two-stage power amplifier, thereby further contributing to improved efficiency.

[0048] Furthermore, for wireless infrastructure applications, power amplifiers typically need to operate at an average power level that is approximately 8-9 dB back from peak power. While the final stage operates in the back-off state, and the driver stage operates in the back-off state even further, this is generally inefficient. Therefore, the reduction in DC power consumption achieved using embodiments of the subject matter of this invention can actually be several times the drive output power, resulting in a significant improvement in overall lineup efficiency. Additionally, according to various embodiments, implementations using relatively simple interstage impedance matching networks can produce a wider RF bandwidth than that achievable using conventional two-stage amplifiers.

[0049] The driver-stage transistors and the final-stage transistors can be integrally formed on a single semiconductor substrate (e.g., both the driver and final stages are silicon-based transistors integrated into a single semiconductor chip), with the driver-stage transistors tailored for low-voltage operation and the final-stage transistors tailored for high-voltage operation. This allows for a more integrated lineup, resulting in cost-effective and high-throughput solutions that are attractive and suitable for massively multi-input / multi-output (MIMO) applications.

[0050] Furthermore, embodiments of the present invention can fully utilize standard, available low-voltage power supplies (e.g., 5V), which can also be used to power other RF subsystems of the RF transmitter or transceiver (e.g., transmitter power amplifier pre-drivers, transmit / receive switches, duplexers, and / or receiver low-noise amplifiers). Therefore, low-voltage power supplies do not impose unique requirements that would additionally increase system costs.

[0051] According to various example embodiments, Figure 1This is a schematic circuit diagram of a power amplifier circuit 100, including a low-voltage drive stage and a high-voltage final stage. Figure 2 It is to achieve Figure 1 A top view of the two-stage power amplifier integrated circuit (IC) 200 of the power amplifier circuit 100. For clarity and brevity, they will be described together below. Figure 1 and 2 .

[0052] like Figure 2 As best illustrated, a number of components of IC 200 corresponding to the components of circuit 100 can be coupled to or integrally formed with a single semiconductor die 290, which is mounted to the mounting surface of a main substrate 292. For example, as combined with Figure 6 In more detail, the main substrate 292 may be a small printed circuit board (PCB), but the main substrate 292 may alternatively be a conductive package flange or other suitable substrate. (As will also be combined...) Figure 6 In more detail, the main substrate 292 may include an embedded, conductive and thermally conductive coin 294 or a thermal via, the coin 294 or thermal via being configured to provide a ground reference voltage and act as a heat sink, and the semiconductor die 290 may be mounted to the conductive coin 294 or thermal via.

[0053] In the embodiment, power amplifier circuit 100 and power amplifier IC 200 each include RF inputs 102 and 202, input impedance matching circuits 110 and 210, driver stage transistors 130 and 230, interstage impedance matching circuits 140 and 240, final stage transistors 160 and 260, first and second input (gate) bias circuits 120, 170, 220, and 270, first and second output (drain) bias circuits 150, 180, 250, and 280, and RF outputs 104 and 204. It should be noted that in... Figure 2 In one embodiment, the second output (drain) bias circuit 280 is actually implemented off-chip (i.e., circuit 280 is electrically coupled to IC 200, but not integrally formed with IC 200). In an alternative embodiment, similar to the implementations of bias circuits 220, 250, and 270, the second output (drain) bias circuit 280 can be implemented on-chip.

[0054] RF inputs 102, 202 and RF outputs 104, 204 may each include a conductor configured to electrically couple circuitry 100 and IC 200 to an external circuitry system (not shown). For example, as Figure 2 As depicted, the RF input 202 includes conductive bonding pads exposed on the top surface of the die 290 and configured for attaching a set of one or more bonding wires (e.g., Figure 2The bonding wire array 201. Conversely, the RF output 204 is electrically coupled to the output / drain terminal 264 of the final stage transistor 260 (or the same conductive structure as the output / drain terminal 264), which may also be a conductive bonding pad exposed on the top surface of the die 290. The first set of bonding wires 201 is configured to transmit the input RF signal from an external circuit system (e.g., Figure 7 The preamplifier 730) is fed to the RF input 202, and the second set of bonding lines 203 is configured to transmit the output RF signal from the RF output 204 to an external circuit system (e.g., Figure 7 (760 duplexer).

[0055] Input impedance matching circuits 110 and 210 are electrically coupled between RF inputs 102 and 202 and the input / gate terminals 132 and 232 of driver stage transistors 130 and 230. Additionally, interstage impedance matching circuits 140 and 240 are electrically coupled between the output / drain terminals 134 and 234 of driver stage transistors 130 and 230 and the input / gate terminals 162 and 262 of final stage transistors 160 and 260. The output / drain terminals 164 and 264 of final stage transistors 160 and 260 are electrically coupled to RF outputs 104 and 204 (or have the same conductivity structure as RF outputs 104 and 204).

[0056] Each transistor 130, 160, 230, 260 is characterized by its input impedance and output impedance, wherein the output impedance (Z1) of transistors 130 and 230 and the input impedance (Z2) of transistors 160 and 260 are most relevant to the subject matter of this invention, as will be discussed in detail below. Input and interstage impedance matching circuits 110 and 210 are each configured to perform desired impedance transformation to, from, or between the input and output impedances of transistors 130, 160, 230, 260.

[0057] For example, input impedance matching circuits 110, 210 are configured to raise the impedance of circuit 100 or IC 200 to a higher (e.g., intermediate or higher) impedance level (e.g., in the range from about 2 ohms to about 50 ohms or higher). According to an embodiment, input impedance matching circuits 110, 210 include parallel inductors 112, 212 and series capacitors 114, 214. The parallel inductors 112, 212 have a first terminal electrically coupled to RF inputs 102, 202, and a second terminal electrically coupled to a ground reference node (e.g., electrically coupled to...). Figure 3 , 4The conductive layer 380 is electrically coupled to a through-hole (TSV) or through-doped deposition region in the substrate. Series capacitors 114 and 214 have a first terminal (or electrode) electrically coupled to RF inputs 102 and 202, and a second terminal (or electrode) electrically coupled to the input / gate terminals 132 and 232 of transistors 130 and 230. According to an embodiment, the inductance values ​​of inductor elements 112 and 212 can range from about 0.1 nanohenry (nH) to about 10 nH, and the capacitance values ​​of capacitors 114 and 214 can range from about 0.1 picofarads (pF) to about 30 pF, but the component values ​​of each of these components can also be lower or higher than the given ranges.

[0058] Interstage impedance matching circuits 140 and 240 are configured to match the output impedance (Z1) of the driver stage transistors 130 and 230 with the input impedance (Z2) of the final stage transistors 160 and 260. According to an embodiment, the interstage impedance matching circuits 140 and 240 include series inductors 142 and 242, series capacitors 144 and 244, and parallel inductors 152 and 252. The series inductors 142 and 242 and the series capacitors 144 and 244 are coupled in series with each other between the output / drain terminals 134 and 234 of the driver stage transistors 130 and 230 and the input / gate terminals 162 and 262 of the final stage transistors 160 and 260, with an intermediate node 143 between the two series-coupled components. More specifically, series inductors 142 and 242 have a first terminal electrically coupled to the output / drain terminals 134 and 234 of the driver stage transistors 130 and 230, and a second terminal electrically coupled to the intermediate node 143. Series capacitors 144 and 244 have a first terminal (or electrode) electrically coupled to the intermediate node 143, and a second terminal (or electrode) electrically coupled to the input / gate terminals 162 and 262 of the final stage transistors 160 and 260. Parallel inductors 152 and 252 have a first terminal electrically coupled to the intermediate node 143, and a second terminal electrically coupled to a ground reference node (e.g., through capacitors 154 and 254). According to the embodiment, the inductance values ​​of inductor elements 142 and 242 can be in the range of about 0.1nH to about 10nH, the capacitance values ​​of capacitors 144 and 244 can be in the range of about 0.1pF to about 30pF, and the inductance values ​​of inductor elements 152 and 252 can be in the range of about 0.1nH to about 10nH, but the component values ​​of each of these components can also be lower or higher than the given ranges.

[0059] like Figure 2As shown, inductors 112, 142, 152, 212, 242, 252 and capacitors 114, 144, 214, 244 can be integrally formed in semiconductor die 290. For example, inductors 112, 142, 152, 212, 242, 252 can be implemented as a stack of layers of die 290 (e.g., ...). Figure 3 , 4 The spiral inductor is formed by patterned conductive portions of layer 304, and capacitors 114, 144, 214, and 244 can be implemented as metal-insulator-metal (MIM) capacitors formed in the stacked layers of die 290. In an alternative embodiment, some or all of the inductor elements 112, 142, 152, 212, 242, and 252 and capacitors 114, 144, 214, and 244 can be implemented as surface-mount, "chip" assemblies physically coupled to the top surface of die 290 and electrically coupled via bonding pads or other contacts (not shown) exposed on the top surface of die 290. Additionally, in other alternative embodiments, some or all of the inductor elements 112, 142, 152, 212, 242, and 252 can be implemented as bonding wires.

[0060] The driver and final stage transistors 130, 160, 230, and 260 are the primary active components of circuit 100 and IC 200. Each of transistors 130, 160, 230, and 260 is configured to amplify RF signals conducted through transistors 130, 160, 230, and 260. As used herein, the term "transistor" refers to a field-effect transistor (FET) or another suitable type of transistor. For example, "FET" can be a metal-oxide-semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), an enhancement-mode or depletion-mode high electron mobility transistor (HEMT), or another type of FET. The description herein refers to each transistor as including an input terminal (or control terminal) and two conductive terminals. For example, using the terminology associated with FET, "input terminal" refers to the gate terminal of the transistor, and the first and second conductive terminals refer to the drain and source terminals of the transistor (or vice versa).

[0061] Driver stage transistors 130, 230 include an input terminal 132 (e.g., gate terminal 232), a first conductive terminal 134 (e.g., "output" or drain terminal 234), and a second conductive terminal 135 (e.g., Figure 2 (Source terminal not shown). Similarly, final-stage transistors 160, 260 include an input terminal 162 (e.g., gate terminal 262), a first conductive terminal 164 (e.g., output / drain terminal 264), and a second conductive terminal 165 (e.g., source terminal). Figure 2 (Source extremes not shown in the image).

[0062] In a specific embodiment, each transistor 130, 160, 230, 260 includes an active region disposed between its input / gate terminals 132, 162, 232, 262 and its output / drain terminals 134, 164, 234, 264. For example... Figure 2-4 As best shown, the active regions of transistors 230 and 260 each include multiple elongated, parallel-aligned, and interdigitated drain regions (e.g., Figure 3 , 4 (Examples of multiple parallel alignments of drain regions 340, 440) and source regions (e.g., Figure 3 , 4 Examples of multiple parallel alignments of source regions 330, 430), wherein each drain region and each source region are formed on a base semiconductor substrate (e.g., Figure 3 The doped semiconductor region in the substrate 302).

[0063] There are variable conductivity channel regions and drain drift regions between adjacent source and drain regions (e.g., Figure 3 , 4 The drift regions 350, 450). Conductive (e.g., polysilicon or metal) gate structures (e.g., Figure 3 , 4 The gate structures 310, 410) extend above and along the elongated channel region. The gate structure of transistor 230 is electrically coupled to a first gate manifold, and the gate structure of transistor 260 is electrically coupled to a second gate manifold. Each of the gate manifolds of transistors 230, 260 is tightly electrically coupled to its respective input / gate terminal 232, 262. Similarly, the drain region of transistor 230 is electrically coupled to a first drain manifold, and the drain region of transistor 260 is electrically coupled to a second drain manifold. Each of the drain manifolds of transistors 230, 260 is tightly electrically coupled to its respective output / drain terminal 234, 264. Due to their elongated shape, the gate structures of each pair of adjacent drain and source regions and the channel region overlying the adjacent drain and source regions (e.g., Figure 3 , 4 The gate structures 310, 410 can be referred to as "transistor fingers". Each transistor 130, 160, 230, 260 includes multiple parallel transistor fingers in the active region of the transistor.

[0064] In various embodiments, amplifier circuit 100 and amplifier IC 200 each include DC bias circuits 120, 150, 170, 180, 220, 250, 270, 280, which are configured to provide DC bias voltages to the input / gate terminals 132, 162, 232, 262 and the output / drain terminals 134, 164, 234, 264 of transistors 130, 160, 230, 260. Each of the input DC bias circuits 120, 170, 220, and 270 is configured as a "parallel inductor" (or parallel L) circuit, which includes inductor elements 122, 172, 222, and 272 and capacitors 124, 174, 224, and 274 connected in series between the transistor input / gate terminals 132, 162, 232, and 262 and the ground reference voltage, with intermediate nodes or contacts 105, 107, 205, and 207 between each inductor / capacitor pair. Similarly, each of the output DC bias circuits 150, 180, 250, and 280 is configured as a "parallel inductor" (or parallel L) circuit, comprising inductor elements 152, 182, 252, and 282 and capacitors 154, 184, 254, and 284 connected in series between the transistor output / drain terminals 134, 164, 234, and 264 and a ground reference voltage, with intermediate nodes or contacts 106, 108, 206, and 208 between each inductor / capacitor pair. According to an embodiment, contacts 205, 206, and 207 (corresponding to nodes 105-107) are implemented as conductive bonding pads exposed on the top surface of die 290 and configured for attaching one or more bonding wires. Conversely, contact 208 (corresponding to node 108) is implemented as part of a patterned conductive layer on the top surface of substrate 292 and is also configured for attaching one or more bonding wires (e.g., Figure 2 Bonding line 282).

[0065] According to an embodiment, inductor elements 222, 252, 272 and capacitors 224, 254, 274 are integrally formed in semiconductor die 290. For example, each of inductors 222, 252, 272 can be implemented as a stack of layers of die 290 (e.g., Figure 3 , 4The spiral inductor is formed by patterned conductive portions of layer 304, and each of capacitors 224, 254, and 274 can be implemented as a metal-insulator-metal (MIM) capacitor formed in a stacked layer of die 290. In an alternative embodiment, some or all of the inductor elements 222, 252, and 272 and capacitors 224, 254, and 274 can be implemented as surface-mount, "chip" assemblies physically coupled to the top surface of die 290 or substrate 292, and electrically coupled through bonding pads or other contacts (not shown) exposed on the top surface of die 290 or substrate 292. Additionally, in other alternative embodiments, some or all of the inductor elements 222, 252, and 272 can be implemented as bonding wires. For example, in Figure 2 In one embodiment, the inductor 282 is implemented as a set of bonding lines electrically coupled between the output / drain terminals 264 of the final stage transistor 260 and the contact 208, and the capacitor 284 is implemented as a chip capacitor coupled to the top surface of the substrate 292.

[0066] like Figure 2 As shown, the output / drain terminal 264 is configured to allow multiple bonding wire arrays 203, 282 to be oriented with an angular offset (e.g., vertical) to the output / drain terminal 264. More specifically, the output / drain terminal 264 has an elongated first conductive bonding pad 265 to which the bonding wire array 203 is connected, and an elongated second conductive bonding pad 266 (or “side pad”) to which the bonding wire array 282 is connected. For the sake of… Figure 6 For reasons that will be obvious in the discussion, the output / drain end 264 may also include an elongated third conductive bonding pad 267 (or “side pad”) to which another bonding wire array can be connected. In any case, the second and third conductive side pads 266, 267 may be coupled or connected to the opposite ends of the elongated first conductive bonding pad 265, and in embodiments, the longest dimension of the second and third conductive side pads 266, 267 may be oriented perpendicular to the longest dimension of the first conductive bonding pad.

[0067] According to the embodiment, the capacitance value of each of capacitors 124, 154, 174, 184, 224, 254, 274, and 284 is sufficiently high (e.g., greater than about 60 pF) to ensure that each node / contact 105, 106, 107, 108, 205, 206, 207, and 208 corresponds to an RF low-impedance point (e.g., an "RF cold spot" or "pseudo-RF cold spot"). In other words, each node / contact 105, 106, 107, 108, 205, 206, 207, and 208 represents a low-impedance point in the circuit used for RF signals. This ensures minimal RF signal energy loss through the bias circuits 120, 150, 170, 180, 220, 250, 270, and 280.

[0068] To provide bias voltages to the input / gate terminals 132, 162, 232, 262 and output / drain terminals 134, 164, 234, 264 of transistors 130, 160, 230, 260, external gate or drain DC bias voltage power supplies 126, 156, 176, 186 ( Figure 2 (Not shown) is connected to each node / contact 105, 106, 107, 108, 205, 206, 207, 208. More specifically, driver stage gate power supply 126 is connected to nodes / contacts 105, 205 to provide DC bias voltage to the input / gate terminals 132, 232 of driver stage transistors 130, 230; driver stage drain power supply 156 is connected to nodes / contacts 106, 206 to provide DC bias voltage to the output / drain terminals 134, 234 of driver stage transistors 130, 230; final stage gate power supply 176 is connected to nodes / contacts 107, 207 to provide DC bias voltage to the input / gate terminals 162, 262 of final stage transistors 160, 260; and final stage drain power supply 186 is connected to nodes / contacts 108, 208 to provide DC bias voltage to the output / drain terminals 164, 264 of final stage transistors 160, 260. The driver stage gate power supply and the final stage gate power supply 126, 176 can each provide a DC gate bias voltage in the range of about 0.5V to about 3.5V, but the DC gate bias voltage can also be lower or higher.

[0069] According to an embodiment, the driver-stage drain power supply and the final-stage drain power supplies 156 and 186 provide substantially different DC drain bias voltages to transistors 130 and 230 and 160 and 260, respectively. More specifically, the driver-stage drain power supply 156 provides a much lower DC drain bias voltage to nodes / contacts 106 and 206 (and therefore to the outputs / drains 134 and 164 of the driver transistors 130 and 230) than the DC drain bias voltage provided by the final-stage drain power supply 186 to nodes / contacts 108 and 208 (and therefore to the outputs / drains 164 and 264 of the final-stage transistors 160 and 260). Therefore, the driver-stage drain power supply 156 can be referred to as the driver-stage low-voltage (LV) power supply, and the driver-stage transistors 130 and 230 can be referred to as the low-voltage driver stage, while the final-stage drain power supply 186 can be referred to as the final-stage high-voltage (HV) power supply, and the final-stage transistors 160 and 260 can be referred to as the high-voltage final stage.

[0070] In a specific embodiment, the driver stage drain power supply 156 provides a DC bias voltage of less than about 10V, and in a more specific embodiment, the driver stage drain power supply 156 provides a DC bias voltage of about 5V. (As can be combined with...) Figure 7 In more detail, the drain power supply 156 of the driver stage is preferably supplied by other circuitry in the RF system (e.g., by...). Figure 7 The DC bias voltage utilized by the preamplifier 730, duplexer 760, and / or low-noise amplifier (LNA) 750 of the transmitter or transceiver 700. For example, the driver stage drain power supply 156 may be a commercially available (or standard) power supply, but it may also be a custom power supply. Conversely, in specific embodiments, the DC bias voltage provided by the final stage drain power supply 186 is at least twice the DC bias voltage of the driver stage drain power supply 156. For example, the final stage drain power supply 186 may provide a DC bias voltage greater than about 20V (e.g., in the range of 28-32V or higher). In various embodiments, the ratio of the DC bias voltage provided by the final stage drain power supply 186 to the DC bias voltage provided by the driver stage drain power supply 156 is greater than 2 (e.g., in the range between 2 and 10). In a more specific embodiment, the ratio is between about 5.6 and about 6.4 when the DC bias voltage provided by the final stage drain power supply 186 is about 28-32V and the DC bias voltage provided by the driver stage drain power supply 156 is about 5V.

[0071] According to an embodiment, the driver stage transistors 130, 230 and the final stage transistors 160, 260 are configured differently from each other to operate effectively at relatively low and relatively high DC drain bias voltages, respectively. Essentially, the driver stage transistors 130, 230 are configured to have a much lower power density and drain-source on-resistance (RDSon) than the final stage transistors 160, 260 (i.e., the total resistance between drain terminal 134 and source terminal 135 when transistors 130, 230 are fully turned on). For example, the power density of the driver stage transistors 130 and 230 can be in the range of about 0.1 W / mm to about 0.2 W / mm, while the power density of the terminal stage transistors 160 and 260 can be in the range of about 0.9 W / mm to about 1.3 W / mm (e.g., the power density of the terminal stage transistors 160 and 260 is at least 200% (i.e., 3 times) greater than that of the driver stage transistors 130 and 230, and may be 10 times or more greater than that of the driver stage transistors 130 and 230). Additionally, the RDSon of the driving stage transistors 130 and 230 can be in the range of about 5 ohms / mm to about 10 ohms / mm, while the RDSon of the final stage transistors 160 and 260 can be in the range of about 10 ohms / mm to about 15 ohms / mm (for example, the RDSon of the final stage transistors 160 and 260 is greater than the Rdson of the driving stage transistors 130 and 230, and in some cases is three times greater than the RDSon of the driving stage transistors 130 and 230).

[0072] Because the driver stage transistors 130 and 230 are configured to operate at a relatively low DC drain bias voltage, they can be configured to have optimized performance (e.g., lower on-resistance (RDSon)). To achieve this optimization, the driver stage transistors 130 and 230 can be designed to have a breakdown voltage much lower than that of the final stage transistors 160 and 260. Although the difference in breakdown voltage can be achieved in various ways, according to a specific embodiment, the difference can be achieved by configuring the driver stage transistors 130 and 230 to have a significantly shorter drift region between the gate and drain within each transistor finger. For illustration, Figure 3 and 4 Depicting according to the embodiment Figure 2 A cross-sectional side view of portions of the driver amplifier transistor 230 and the final stage amplifier transistor 260. More specifically, Figure 3 and 4 Each of them is depicted through the drive amplifier transistor 230 ( Figure 3 ) and final stage amplifier transistor 260 ( Figure 4 A cross-sectional side view of a single transistor within a )

[0073] Drive amplifier transistor 230 ( Figure 3 ) and final stage amplifier transistor 260 ( Figure 4 All of these are integrally formed with the semiconductor die 290. More specifically, the semiconductor die 290 includes a base semiconductor substrate 302 and a plurality of stacked layers 304 above the top surface 303 of the base semiconductor substrate 302. Figure 3 and 4 Only the lower portion of stacked layer 304 is shown to avoid unnecessary detail. In a specific example embodiment, the base semiconductor substrate 302 is a high-resistivity silicon substrate (e.g., a silicon substrate with a bulk resistivity in the range of about 1,000 ohms / cm to about 100,000 ohms / cm or greater). Alternatively, the base semiconductor substrate may be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a bulk resistivity up to 10...). 8 The base semiconductor substrate can be a GaAs substrate with a resistivity of ohms / cm or another suitable high-resistivity substrate. In yet another alternative embodiment, the base semiconductor substrate can be any of several variations of a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate (e.g., to accommodate a GaN epitaxial layer, for example, grown on SiC), or other III-V semiconductor substrates. The advantage of using a high-resistivity substrate is that such a substrate can allow for relatively low losses in the circuitry of various on-die components compared to amplifier dies that do not utilize a high-resistivity substrate. However, in other embodiments, a substrate with lower resistivity (or higher conductivity) can be used.

[0074] In embodiments where substrate 302 is a high-resistivity substrate, a substrate through-via (TSV, not shown) can be used to form a conductive path between the conductive back-side contacts 380 on the top surface 303 of substrate 302 and the bottom surface of substrate 305. Alternatively, for substrates with lower resistivity (or higher conductivity), a low-resistivity sink region can be used at least partially to form a conductive path between the top surface 303 and the back-side contacts 380. In any case, when die 290 is integrated into a larger electrical system, the back-side contacts 380 can be connected to ground (e.g., to...). Figure 2 The coin 294 or heat through-hole), and the TSV (or settling region) can be used to connect source regions 330, 430 and other components (e.g., Figure 2 The inductor 212 and capacitors 224, 254, and 274 are electrically connected to ground.

[0075] Each transistor 230, 260 includes a gate structure 310, 410 supported by a top surface 303 of a semiconductor substrate 302, and doped source regions 330, 430 and drain regions 340, 440 (or more generally, "current-carrying regions") extending from the top surface 303 into the substrate 302 on both sides of the gate structure 310, 410. Each source region 330, 430 and drain region 340, 440, or a portion thereof, may have a dopant concentration sufficient to establish an ohmic contact with electrodes or interconnects 336, 436 and 342, 442.

[0076] According to the embodiment, each source region 330, 430 may be disposed along or aligned with the first sidewall 320, 420 of the gate structure 310, 410. In addition, each drain region 340, 440 may be laterally separated from the second opposing sidewall 318, 418 of the gate structure 310, 410 on the surface 303 of the substrate 302, and drift regions 350, 450 extend laterally from each drain region 340, 440 to each gate structure 310, 410.

[0077] Each transistor 230, 260 also includes a well region or diffusion region 332, 432 in the semiconductor substrate 302 below the gate structures 310, 410. During operation, a DC bias voltage (e.g., by applying a DC bias voltage to the conductive portion of the gate structures 310, 410) is applied. Figure 1 The driving stage LV drain power supply 156 or the final stage HV drain power supply 186 is applied to form a channel or channel region in the well regions 332 and 432 at the surface 303 of the semiconductor substrate 302. As previously discussed, during operation, the drain region 340 of the driving stage transistor 230 is biased with a bias voltage much lower than the bias voltage applied to the drain region 440 of the final stage transistor 260.

[0078] The die 290 may include one or more passivation layers 370 covering surface 303. One or more shielding plates 322, 422, 424 may be disposed between adjacent dielectric or passivation layers 370. Figure 3 and 4 As indicated, the configurations of shields 322, 422, and 424 may differ for the driver stage transistor 230 (which includes only a single shield 322) and the final stage transistor 260 (which includes two shields 422, 424). In any case, shields 322, 422, and 424 help protect the gate dielectric from damage or degradation caused by charge carriers (i.e., “hot carriers”) accelerated under the electric field generated by the drain-source voltage. Shields 322, 422, and 424 also help reduce the maximum electric field in drift regions 350, 450. Shields 322, 422, and 424 may be grounded or otherwise biased to prevent the injection of such hot carriers into the oxide or other dielectric material below the gate structures 310, 410 and / or above the oxide or other dielectric material of the drift regions 350, 450.

[0079] According to an embodiment, the length 360 of the drift region 350 in the driver stage transistor 230 (i.e., the dimension from the sidewall 318 of the gate 310 to the drain region 340) is significantly shorter than the length 460 of the drift region 450 in the final stage transistor 260 (i.e., the dimension from the sidewall 418 of the gate 410 to the drain region 440). This results in the RDSon and breakdown voltage of the driver stage transistor 230 being much lower than those of the final stage transistor 260. In some embodiments, for example, the length 360 of the drift region 350 in the driver stage transistor 230 may be in the range of about 0.5 micrometers to about 1.5 micrometers (e.g., about 1.0 micrometer), while the length 460 of the drift region 450 in the final stage transistor 260 may be in the range of about 2.0 micrometers to about 3.5 micrometers (e.g., about 2.8 micrometers). In other words, the length 460 of the drift region 450 in the final stage transistor 260 is at least 50% larger than the length 360 of the drift region 350 in the driver stage transistor 230 (e.g., in a first range of about 50% to about 600%, or in a second range of about 100% to about 200%). It should be noted that the lengths 360 and 460 can also be smaller or larger than the given ranges. Essentially, establishing a much shorter length 360 for the drift region 350 in the driver stage transistor 230 compared to the length 460 of the drift region 450 in the final stage transistor 260 makes the RDSon of the driver stage transistor 230 much lower than that of the final stage transistor 260 (e.g., at least about 40-50% lower), and makes the breakdown voltage of the driver stage transistor 230 much lower than that of the final stage transistor 260 (e.g., at least about 50-60% lower). In other words, the breakdown voltage of the final stage transistor 260 can be much higher than the breakdown voltage of the driver stage transistor 230 (e.g., at least about 100-150%). For example, the breakdown voltage of the driver stage transistor 230 can be in the range of about 25V to about 40V (e.g., about 32V), and the breakdown voltage of the final stage transistor 250 can be in the range of about 65V to about 80V (e.g., about 71V).

[0080] In addition to having a lower RDSon, the lower power density of driver stage transistors 130 and 230 allows driver stage transistor 230 to be designed with a power density per unit width ( Figure 2 The driver stage transistor 230 (in its horizontal dimension) has more transistor fingers than the final stage transistor 260. By providing more transistor fingers per unit width in the driver stage transistor 230, the RDSon of the driver stage transistor 230 can be further reduced relative to the RDSon of the final stage transistor 260 without consuming a significant amount of additional die area. In this embodiment, the reduced RDSon of the driver stage transistor 230 allows for optimization of the frequency response and efficiency of the driver stage transistor 230 for lower voltage operation.

[0081] Although in the embodiments described above, the breakdown voltage and RDSon difference are achieved at least in part by implementing a drift region 350 in the driver stage transistor 230 having a length 360 shorter than the length 460 of the drift region 450 implemented in the final stage transistor 260, the breakdown voltage and RDSon difference can also be achieved in other ways. For example, they can also be achieved by using different doping degrees and different drift region widths ( Figure 3 , 4 Page dimensions), different drift zone depths ( Figure 3 , 4 The breakdown voltage and RDSon difference are achieved through various combinations of vertical dimensions, different drift region lengths, and / or other characteristics of the driver stage transistor 230 and the final stage transistor 260 configured in different ways. In other words, drift regions 350 and 450 have one or more different characteristics selected from different doping degrees, different drift region widths, different drift region depths, and different drift region lengths.

[0082] Refer again Figure 1 and 2 Furthermore, considering the characteristics of the driver stage transistors and final stage transistors 130, 160, 230, 260 described above, and the relatively low output bias voltage provided to the driver stage transistors 130, 230, the output impedance of the low-voltage driver transistors 130, 230 (e.g., Z1 or the impedance entering the drain of the driver stage transistors 130, 230) can be much lower than the output impedance of conventional high-voltage driver transistors (e.g., in conventional systems where the driver transistors are biased at a higher voltage, such as 28V or higher). For example, the output impedance of an embodiment of the low-voltage driver stage transistors 130, 230 can be less than 10 ohms (e.g., from 5-10 ohms), while the output impedance of a conventional high-voltage driver stage can be 60-100 ohms or higher. In contrast, the input impedance of the final stage transistors 160, 260 (e.g., Z2, or the impedance entering the gate of the final stage transistors 160, 260) can be only a few ohms (e.g., from 1-3 ohms). Therefore, in the embodiments, the output impedance Z1 of the low-voltage drive stage transistors 130, 230 (e.g., less than about 10 ohms) can be matched with the input impedance Z2 of the final stage transistors 160, 260 (e.g., between about 1 ohm and 3 ohms), thereby promoting a low conversion ratio and easily achievable impedance matching between the output of the low-voltage drive stage transistors 130, 230 and the input of the final stage transistors 160, 260.

[0083] As previously discussed, circuits 100 and IC 200 each include interstage impedance matching networks 140 and 240 electrically coupled between the output / drain terminals 134 and 234 of low-voltage driver stage transistors 130 and 230 and the input / gate terminals 162 and 262 of high-voltage final stage transistors 160 and 260. The interstage impedance matching networks 140 and 240 are configured to match the output impedance (Z1) of the driver stage transistors 130 and 230 with the input impedance (Z2) of the final stage transistors 160 and 260. As discussed above, because the output impedance (Z1) of the driver stage transistors 130 and 230 is much lower than that of conventional driver stage transistors, the interstage impedance matching networks 140 and 240 can be characterized by a significantly reduced impedance transformation ratio compared to that required by a conventional two-stage amplifier. For example, a conventional two-stage power amplifier might require an impedance transformation ratio of approximately 30:1 to 50:1 for a 28V drive stage (e.g., from approximately 60-100 ohms Z1 to approximately 2 ohms Z2), while embodiments of a low-voltage drive stage might only require an impedance transformation ratio of less than approximately 10:1 (e.g., a ratio between approximately 2.5:1 and approximately 5:1, corresponding to an impedance transformation ratio from approximately 5-10 ohms Z1 to approximately 2 ohms Z2). Because a relatively low impedance transformation ratio can be guaranteed when implementing embodiments of the subject matter of this invention, the circuit topology of the interstage impedance matching networks 140, 240 can be relatively simpler (e.g., fewer impedance matching stages and / or passive components) compared to the circuit topology of the interstage impedance matching networks of conventional amplifiers that require relatively high impedance transformation. Therefore, during operation, the losses due to the interstage impedance matching networks 140, 240 can be significantly reduced (e.g., reduced by 3 dB or more) compared to the losses due to the interstage impedance matching networks of conventional two-stage amplifiers.

[0084] Although transistors 130, 160 and various elements of the input impedance matching circuit and interstage impedance matching circuits 110, 140 are shown as single components, this depiction is for ease of explanation only. Those skilled in the art will understand based on the description herein that certain elements of transistors 130, 160 and / or input impedance matching circuit 110 and interstage impedance matching circuit 140 may each be implemented as multiple components (e.g., connected in parallel or series with each other).

[0085] Figure 1 and 2The RF amplifier circuit 100 and IC 200 can be used as single-path amplifiers, receiving RF signals at RF inputs 102 and 202, amplifying signals through transistors 130, 160, 230, and 260, and generating amplified RF signals at RF outputs 104 and 204. Alternatively, multiple instances of the RF amplifier circuit 100 or IC 200 can be used to provide multipath amplifiers, such as Dougherty power amplifiers or other types of multipath amplifier circuits.

[0086] For example, Figure 5 This is a simplified schematic diagram of a Dougherty power amplifier 500 according to an example embodiment, which may include two instances of RF amplifier circuitry 100 or IC 200. The Dougherty amplifier 500 includes an input node 502, an output node 504, a power divider 506 (or splitter), a main amplifier path 520 with two main amplifier stages 522 (including a driver stage amplifier 530 and a final stage amplifier 560), a peaking amplifier path 521 with two peaking amplifier stages 523 (including a driver stage amplifier 531 and a final stage amplifier 561), and a combination node 580. A load 590 may be coupled to the combination node 580 (e.g., via an impedance transformer, not shown) to receive amplified RF signals from the amplifier 500.

[0087] Power divider 506 is configured to split the power of the input RF signal received at input node 502 into a main portion and a peaked portion of the input signal. The main input signal is provided to the main amplifier path 520 at power divider output 508, and the peaked input signal is provided to the peaked amplifier path 521 at power divider output 509. During full-power mode operation, when both the main amplifier path and the peaked amplifier paths 520, 521 supply current to the load 590, power divider 506 distributes the input signal power between amplifier paths 520, 521. For example, power divider 506 may distribute the power equally, such that approximately half of the input signal power is provided to each path 520, 521 (e.g., for a symmetrical Dougherty amplifier configuration). Alternatively, power divider 506 may distribute the power unequally (e.g., for an asymmetrical Dougherty amplifier configuration). Essentially, the power divider 506 distributes the input RF signal supplied at input node 502, and the distributed signal is amplified along the main amplifier path and peaking amplifier paths 520 and 521, respectively. The amplified signals are then combined in phase at the combining node 580.

[0088] Amplifier 500 is designed to maintain phase coherence between the main amplifier path and peak amplifier paths 520, 521 in the relevant frequency band, ensuring that the amplified main signal and peaked signal arrive in phase at the combination node 580, thereby ensuring proper operation of the Dougherty amplifier. More specifically, Dougherty amplifier 500 has a “non-inverting” load network configuration. In the non-inverting configuration, the input circuitry is configured such that the input signal supplied to peaked amplifier path 521 at the operating center frequency f0 of amplifier 500 is delayed by 90 degrees relative to the input signal supplied to main amplifier path 520. To ensure that the main input RF signal and the peaked input RF signal are supplied to the main amplifier path and peaked amplifier path 520, 521 with a phase difference of approximately 90 degrees, which is the basis for proper Dougherty amplifier operation, phase delay element 582 applies a phase delay of approximately 90 degrees to the peaked input signal (i.e., the signal generated at power divider output 509). For example, phase delay element 582 may include a quarter-wavelength transmission line, or another suitable type of delay element having an electrical length of about 90 degrees.

[0089] A 90-degree phase delay difference at the inputs of the main amplifier path and peaking amplifier paths 520, 521 is used to compensate for a 90-degree phase delay in the signal applied to the output of the main amplifier 522 and the combination node 580. This is achieved by an additional delay element 584 between the output of the main amplifier 522 and the combination node 580. The additional delay element 584 can also be configured to perform impedance inversion, and therefore element 584 can be referred to as a "phase delay and impedance inversion" element or structure.

[0090] Each of the main amplifier path 520 and the peaking amplifier path 521 includes series-coupled input impedance matching networks 510, 511 (input MNm and input MNp) and multi-stage power amplifiers 522, 523 (e.g., Figure 1 , 2 An example of amplifier 100 implemented using amplifier IC 200. Input impedance matching networks 510, 511 may be implemented between the power divider outputs 508, 509 and the inputs of the main amplifier and peaking amplifiers 522, 523 (e.g., the gates of the main driver stage amplifier and peaking driver stage amplifiers 530, 532). In each case, matching networks 510, 511 may be used to gradually increase the circuit impedance to the load impedance and source impedance. All or part of the input impedance matching networks 510, 511 may be connected to the IC including the main amplifier and / or peaking amplifiers 522, 523 (e.g., ...). Figure 2 The IC 200 is integrated with it. For example, input impedance matching networks 510 and 511 can be integrated with the IC, along with input impedance matching network 210. Figure 2Similarly, all or part of the input impedance matching networks 510 and 511 can be implemented on the PCB or other substrate to which the IC is mounted.

[0091] Multistage power amplifiers 522, 523 (e.g., Figure 1 , 2 An example of amplifier 100 implemented using amplifier IC 200 is configured to amplify RF signals conducted through the main amplifier path and peaking amplifier paths 520, 521. According to various embodiments, the main driver stage amplifier and peaking driver stage amplifiers 530, 532, as well as the final stage amplifiers 560, 561, may each use, for example, field-effect transistors (e.g.,...). Figure 2 The FETs 530 and 260 are used for implementation. As discussed in detail above, each driver stage amplifier 530 and 531, or more specifically, the FET corresponding to each driver stage amplifier 530 and 531, can be configured to operate at a relatively low output bias voltage (e.g., drain bias voltage). To provide a relatively low output bias voltage to the driver stage amplifiers 530 and 531, the Dougherty amplifier 500 includes a driver stage low-voltage (LV) drain power supply 540 (e.g., ...). Figure 1 The driver stage LV drain power supply 540 provides an output bias voltage to the driver stage amplifiers 530 and 531. As previously discussed, the driver stage LV drain power supply 540 can be configured to provide a DC bias voltage of less than about 10V to the driver stage amplifiers 530 and 531, and in a more specific embodiment, the driver stage LV drain power supply 540 can be configured to provide a DC bias voltage of about 5V to the driver stage amplifiers 530 and 531.

[0092] Conversely, each of the final stage amplifiers 560, 561, or more specifically, the FET corresponding to each of the final stage amplifiers 560, 561, can be configured to operate at a relatively high output bias voltage (e.g., drain bias voltage). To provide a relatively high output bias voltage to the final stage amplifiers 560, 561, the Dougherty amplifier 500 includes a final stage high voltage (HV) drain power supply 542 (e.g., Figure 1 The final-stage HV drain power supply 542 (186) provides an output bias voltage to the final-stage amplifier. As previously discussed, the final-stage HV drain power supply 542 can be configured to provide a DC bias voltage of 20V or higher to the final-stage amplifiers 560 and 561, and in a more specific embodiment, the final-stage HV drain power supply 542 can be configured to provide a DC bias voltage in the range of 28-32V or higher to the final-stage amplifiers 560 and 561.

[0093] During operation of the Dougherty amplifier 500, the main amplifier 522 is biased to operate in Class AB mode, and the peaking amplifier 523 is biased to operate in Class C mode. At low power levels, where the power of the input signal at node 502 is lower than the turn-on threshold level of the peaking amplifier 523, amplifier 500 operates in low-power (or back-off) mode, where the main amplifier 522 is the only amplifier supplying current to the load 590. When the power of the input signal exceeds the threshold level of the peaking amplifier 523, amplifier 500 operates in high-power mode, where both the main amplifier 522 and the peaking amplifier 523 supply current to the load 590. At this time, the peaking amplifier 523 provides active load modulation at the combined node 580, thereby allowing the current of the main amplifier 522 to increase linearly and continuously.

[0094] Also refer to Figure 2 In one embodiment, a first instance of the power amplifier IC 200 can be used to implement the main amplifier 522, wherein the driver stage transistor 230 corresponds to the driver stage amplifier 530, and the final stage transistor 260 corresponds to the final stage amplifier 560. Similarly, a second instance of the power amplifier IC 200 can be used to implement the peaking amplifier 523, wherein the driver stage transistor 230 corresponds to the driver stage amplifier 531, and the final stage transistor 260 corresponds to the final stage amplifier 561.

[0095] Practical implementations of the Dougherty amplifier 500 or portions thereof can be implemented in discrete, packaged power amplifier modules and devices. For example, Figure 6 This is a top view of a Dougherty amplifier module 600 according to an example embodiment, wherein the first amplifier die and the second amplifier dies 632, 652 (e.g., Figure 2 Two examples of the amplifier die 200 are used to provide the main amplifier and peaking amplifier of the Dougherty amplifier.

[0096] The Dougherty amplifier module 600 includes a substrate 601 and a power splitter 620 (e.g., Figure 5 The power splitter 506), the main amplifier die 632 (e.g., with...) Figure 5 Corresponding to the main amplifier 522), peaking amplifier die 652 (e.g., with Figure 5 Corresponding to the peaking amplifier 523), phase delay and impedance inverting structure 670 (e.g., Figure 5 The phase delay and impedance inversion structure 584, along with various other circuit elements, will be discussed in more detail below. According to embodiments, the main amplifier die 632 and the peaking amplifier die 652 may be structurally identical to each other, except for the configuration of the RF outputs 634 and 654, and may be combined with... Figure 2 The amplifier IC 200 is described in detail.

[0097] The Dougherty amplifier module 600 can be implemented as, for example, a planar grid array (LGA) module. Therefore, substrate 601 has a component mounting surface 602 and a planar surface (not numbered) on the side of substrate 601 opposite to the component mounting surface 602. Conductive landing pads 610-617 of the LGA are exposed at the planar surface and are electrically connected via substrate 601 to overlying conductive features (e.g., contacts 608, 609, 690, etc.). Although module 600 is depicted as an LGA module, module 600 can alternatively be packaged as a leaded grid array module, a square flat no-lead (QFN) module, or another type of package. In either case, component mounting surface 602 and components mounted to said surface 602 can optionally be covered with encapsulation material to create a form suitable for integration into a larger electrical system (e.g., Figure 7 The surface mount device (e.g., transceiver module 700) in the transceiver module 700) Figure 7 (Power amplifier device 740). In an alternative embodiment, the component mounted to surface 602 may be housed in an air chamber defined by various structures (not shown) covering the mounting surface 602.

[0098] The power splitter 620 coupled to the mounting surface 602 includes an input terminal 622 (e.g., Figure 5 The input 502) and two output terminals 624, 626 (e.g., Figure 5 Outputs 508 and 509. Input 622 is electrically coupled to landing pad 610 via bonding wires and conductive contact 690, which is configured to receive the input RF signal. Outputs 624 and 626 are electrically coupled (e.g., via additional bonding wires) to the main amplifier path and peaking amplifier path, respectively. Power splitter 620 is configured to split the power of the input RF signal received through input 622 into a first RF signal and a second RF signal (e.g., the main signal and the peaking signal) generated at outputs 624 and 626. Additionally, power splitter 620 may include one or more phase shift elements configured to impart an approximately 90-degree phase difference between the first RF signal and the second RF signal provided at outputs 624 and 626 (e.g., to implement the phase shifting effect of the phase shifting effect). Figure 5 The phase shift applied by the phase delay element 582.

[0099] The first RF signal generated at output terminal 624 is amplified through the main amplifier path. The main amplifier path includes input circuit 627 and main amplifier die 632 (e.g., Figure 2 Examples of IC 200), and phase delay and impedance inversion structure 670 (e.g., Figure 5The phase delay and impedance inverting element 584). Input circuit 627 is configured to provide appropriate impedance matching between the first power splitter output 624 and the input to the main amplifier die 632. Input circuit 627 is electrically coupled (e.g., with...) Figure 2 The bonding wire 201 corresponding to the bonding wire 660) is connected to the RF input terminal 633 of the main amplifier die 632 (e.g., Figure 2 The RF input 202 provides an RF signal for amplification to the main amplifier die 632.

[0100] The main amplifier die 632 embodies a two-stage amplifier, which is essentially similar to the two-stage amplifier embodied in amplifier IC 200. For the sake of simplicity, the combination will not be repeated here. Figure 2 The details of amplifier IC 200 are discussed, but these details are also intended to apply to the main amplifier die 632. In simple terms, the electrical components of the main amplifier die 632 include RF input 633, input matching network (e.g., ... Figure 2 Input matching network 210), driver-level transistors (e.g., Figure 2 The driver stage transistor 230), inter-stage matching network (e.g., Figure 2 Interstage matching network 240), output or final stage transistor (e.g., Figure 2 The final stage transistor 260) and the RF output terminal 634 (e.g., Figure 2 The RF output terminal 204. The driver stage transistor and the final stage transistor are coupled in series between the input terminal and the output terminals 633 and 634. The driver stage transistor is configured to apply a relatively low gain to the main signal, and the final stage transistor is configured to apply a relatively high gain to the main signal after initial amplification by the driver stage transistor.

[0101] According to an embodiment, the main amplifier die 632 further includes a first DC bias circuit 650 (e.g., Figure 2 The bias circuit 250 passes through the conductive landing pad 611 and the bonding pad on the die 632 (e.g., Figure 2 The bonding pad 206 receives a relatively low bias voltage. The first DC bias circuit 650 transfers the relatively low DC bias voltage from the landing pad 611 to the output (e.g., the drain terminal) of the driver stage transistor, as described above. Figure 2 It is discussed in detail.

[0102] In an embodiment, the second DC bias circuit 680 (e.g., Figure 2 The bias circuit 280 is implemented off-chip, and the second DC bias circuit 680 receives a relatively high DC bias voltage through the landing pad 612. The second DC bias circuit 680 may include conductive contacts 608 on the mounting surface 602 (e.g., Figure 2The contact 608 and bonding wire 642 electrically couple the contact 608 to the RF output terminal 634 (therefore, electrically connecting the pad 612 to the output of the final stage transistor of the main amplifier die 632). A second DC bias circuit 680 transfers a relatively high bias voltage from the pad 612 to the output (e.g., the drain terminal) of the final stage transistor, as described above. Figure 2 This is discussed in detail. In addition to the drain bias circuits 650 and 680, module 600 may also include an additional main amplifier bias circuit that provides gate bias voltage to the driver stage transistors and final stage transistors of the main amplifier die 632.

[0103] Such as combination Figure 2 As discussed, each of the first DC bias circuit 650 and the second DC bias circuit 680 can be configured as a parallel L-circuit, wherein each circuit includes an inductor and a capacitor connected in series between the transistor output and a ground reference voltage, with an intermediate node or contact between each inductor / capacitor pair. The inductor / capacitor pair associated with DC bias circuit 650 can be integrally formed with die 632, and the inductor / capacitor pair associated with DC bias circuit 680 can include bonding wire 642, contact 608, and capacitor 684. A first end (or electrode) of capacitor 684 is coupled to contact 608, and a second end of capacitor 684 can be coupled to a ground reference via landing pad 613.

[0104] The main amplifier die 632 generates an amplified main signal at the RF output terminal 634. The amplified main signal is then transmitted to the RF output terminal 654 of the peaking amplifier die 652 via a phase delay and impedance inversion structure 670. More specifically, the phase delay and impedance inversion structure 670 comprises a series combination of a first bonding line array 661, an inverter line 672 connected to the substrate 601, and a second bonding line array 663. In an embodiment, the phase delay and impedance inversion structure 670 has an electrical length of approximately 90 degrees.

[0105] As will be discussed in more detail below, the output terminal 654 of the peaking amplifier die 652 acts as the combination node 690 of the Dougherty amplifier (e.g., Figure 5 The combination node 580), and the phase delay and impedance inversion structure 670 are used to phase align the amplified RF main signal with the amplified RF peaked signal generated by the peaked amplifier die 652.

[0106] Returning to power splitter 620, the second RF signal generated at output 626 is amplified via a peaking amplifier path. The peaking amplifier path includes input circuitry 628 and peaking amplifier die 652 (e.g., ...). Figure 2(Example of IC 200). Input circuit 628 is configured to provide appropriate impedance matching between the second power splitter output 626 and the input to the peaking amplifier die 652. Input circuit 628 is electrically coupled (e.g., to...) Figure 2 The bonding wire 201 corresponding to the bonding wire 665) is connected to the RF input terminal 653 of the peaking amplifier die 652 (e.g., Figure 2 The RF input 202 is used to provide an RF signal for amplification to the peaking amplifier die 652.

[0107] The peaking amplifier die 652 embodies a two-stage amplifier, which is essentially similar to the two-stage amplifier embodied in amplifier IC 200. For the sake of simplicity, the connection will not be repeated here. Figure 2 The details of amplifier IC 200 are discussed, but these details are also intended to apply to peaking amplifier die 652. In simple terms, the electrical components of peaking amplifier die 652 include RF input 653, input matching network (e.g., ... Figure 2 Input matching network 210), driver-level transistors (e.g., Figure 2 The driver stage transistor 230), inter-stage matching network (e.g., Figure 2 Interstage matching network 240), output or final stage transistor (e.g., Figure 2 The final stage transistor 260) and the RF output terminal 654 (e.g., Figure 2 Output / drain extreme 264).

[0108] The driver stage transistor and the final stage transistor are coupled in series between the input and output terminals 653 and 654. The driver stage transistor is configured to apply a relatively low gain to the peaked signal, and the final stage transistor is configured to apply a relatively high gain to the peaked signal after initial amplification by the driver stage transistor.

[0109] According to an embodiment, the peaking amplifier die 652 further includes a first DC bias circuit 651 (e.g., Figure 2 The bias circuit 250 passes through the conductive landing pad 614 and the bonding pad on the die 652 (e.g., Figure 2 The bonding pad 206 receives a relatively low bias voltage. A first DC bias circuit 651 transfers the relatively low DC bias voltage from the landing pad 614 to the output (e.g., the drain terminal) of the driver stage transistor, as described above. Figure 2 It is discussed in detail.

[0110] In an embodiment, the second DC bias circuit 681 (e.g., Figure 2The bias circuit 280 is implemented off-chip, and the second DC bias circuit 681 receives a relatively high DC bias voltage via a landing pad 615. The second DC bias circuit 681 may include conductive contacts 609 on the mounting surface 602 (e.g., ...). Figure 2 The contact 609 is connected to the RF output terminal 654 (and thus electrically connected to the pad 615 and the output of the final stage transistor of the peaking amplifier die 652). A second DC bias circuit 681 transfers a relatively high bias voltage from the pad 615 to the output (e.g., the drain terminal) of the final stage transistor, as described above. Figure 2 The details are as follows. In addition to the drain bias circuits 651 and 681, module 600 may also include additional peaking amplifier bias circuitry to provide gate bias voltages to the driver stage transistors and final stage transistors of peaking amplifier die 652.

[0111] Such as combination Figure 2 As discussed, each of the first DC bias circuit 651 and the second DC bias circuit 681 can be configured as a parallel L-circuit, wherein each circuit includes an inductor and a capacitor connected in series between the transistor output and a ground reference voltage, with an intermediate node or contact between each inductor / capacitor pair. The inductor / capacitor pair associated with DC bias circuit 651 can be integrally formed with die 652, and the inductor / capacitor pair associated with DC bias circuit 681 can include bonding wire 646, contact 609, and capacitor 685. A first end (or electrode) of capacitor 685 is coupled to contact 609, and a second end of capacitor 685 can be coupled to a ground reference via landing pad 616.

[0112] Peaking amplifier die 652 generates an amplified peaked signal at RF output 654. In this embodiment, and as mentioned above, RF output 654 also receives the amplified main signal through a phase delay and impedance inversion structure 670, and RF output 654 acts as a combination node 690 (e.g., Figure 5 The amplified main signal and the amplified peaked signal are combined in phase at the combination node 690 (combination node 580).

[0113] According to an embodiment, the RF output terminal 654 (and therefore the combination node 690) is electrically coupled to the conductive output converter line 692 at the mounting surface 602 via a bonding wire array 664. In this embodiment, an output impedance matching network 694 and / or a decoupling capacitor 696 may be coupled along the output converter line 692. The output impedance matching network 694 is used to present an appropriate load impedance to the combination node 690. Although Figure 6Details are not shown, but the output impedance matching network 694 may include various discrete and / or integrated components (e.g., capacitors, inductors, and / or resistors) to provide the required impedance matching. Finally, the output converter line 692 is electrically coupled to the conductive landing pad 617 via the substrate 601. The landing pad 617 serves as the RF output node for module 600.

[0114] Modules including one or more instances of amplifier 100 and / or amplifier IC 200 (e.g., Figure 6 Embodiments of the Dougherty amplifier module 600 or another device or module can be further integrated into a larger electrical system. For example, the Dougherty amplifier module 600 (or another amplifier device including an amplifier die) can be included in a transmitter lineup of RF transmitters or RF transceivers.

[0115] For example, Figure 7 This is a perspective view of a transceiver module 700 according to an exemplary embodiment. Essentially, the transceiver module 700 houses an array of transmitters and an array of receivers. Components of the transceiver module 700 are mounted on (or coupled to) a system substrate 710, which may be, for example, a multilayer PCB or other type of substrate.

[0116] The transmitter array includes a series-coupled RF transmit (TX) input connector 720, a preamplifier device 730, a power amplifier device 740, a duplexer 760 (e.g., a circulator in the illustrated embodiment), and an RF transmit / receive (TX output / RX input) connector 724. The RF transmit input connector 720 is configured to couple to an external RF signal source, such as a transmission processor (not shown), which generates an analog, modulated RF transmit signal to be amplified and transmitted to a remote receiver. The RF transmit input connector 720 receives the RF transmit signal from the RF signal source and transmits the signal to a first substrate transmission line between the RF transmit input connector 720 and the preamplifier device 730. The preamplifier device 730 acts as a first amplification stage, applying a first gain to the RF transmit signal. The preamplified RF transmit signal is then transmitted through a second substrate transmission line between the preamplifier device 730 and the power amplifier device 740.

[0117] For example, the power amplifier device 740 may be a Dougherty amplifier module (e.g., Figure 6 The power amplifier device 740 may alternatively include a single-path amplifier or another type of amplifier, such as the Dougherty amplifier module 600. In any case, the power amplifier device 740 includes an amplifier with a low-voltage drive stage (e.g., Figure 1 , 2The driver stage transistors 130, 230, 530, and 531) and the high-voltage final stage amplifier (e.g., Figure 1 , 2 An amplifier comprising at least one of the final stage transistors 160, 260, 560, and 561.

[0118] Power amplifier device 740 acts as the final amplification stage to apply additional gain to the RF transmission signal, and then transmits the amplified RF transmission signal through a third substrate transmission line between power amplifier device 740 and duplexer 760. Duplexer 760 is used to isolate the transmitter and receiver. In various embodiments, duplexer 760 may include a circulator (as shown), an active transmit / receive switch, or another type of duplexer. In any case, duplexer 760 transmits the amplified RF transmission signal to a fourth substrate transmission line between duplexer 760 and RF transmit / receive connector 724.

[0119] RF transmit / receive connector 724 is configured to couple to a load, such as an antenna, for transmitting an amplified RF transmit signal to a remote receiver (e.g., to radiate the amplified RF transmit signal over an air interface). RF transmit / receive connector 724 is also configured to receive RF receive signals from a load (e.g., from an antenna, and ultimately from a remote transmitter) and transmit the RF receive signals to a receiver array.

[0120] The receiver array includes a series-coupled RF transmit / receive connector 724, a duplexer 760, a low-noise amplifier (LNA) device 750, and an RF receive (RX) output connector 722. Once an RF signal is received from a load (e.g., an antenna), the RF transmit / receive connector 724 transmits the RF signal to the duplexer 760 via a fourth board transmission line. The duplexer 760 then transmits the RF signal to the LNA device 750 via a fifth board transmission line. The LNA device 750 amplifies the RF signal and transmits the amplified RF signal to a sixth board transmission line between the LNA device 750 and the RF receive output connector 722. The RF receive output connector 722 is configured to couple to a receiver processor (not shown) that processes (e.g., demodulates, converts to digital, and otherwise processes) the RF signal.

[0121] In addition to the circuitry described above, the transceiver module 700 also includes a low-voltage power connector 770, a high-voltage power connector 780, and potentially additional power connectors (not discussed below). The low-voltage power connector 770 and the high-voltage power connector 780 are configured to couple to a low-voltage power source (e.g., Figure 1 , 5 The driver stage LV drain power supply 156, 540) and high voltage power supply (e.g., Figure 1 , 5 The final stage HV drain power supply 186, 542). As previously described, the low-voltage power supply (not shown) can supply a relatively low DC voltage (e.g., less than 10V, such as 5V, or another relatively low voltage), and the high-voltage power supply (not shown) can supply a relatively high DC voltage (e.g., 28-32V or another relatively high voltage).

[0122] In an embodiment, a low-voltage power connector 770 is coupled to a low-voltage substrate conductor 772, which conducts the low-voltage DC power received through the low-voltage power connector 770 to the preamplifier 730, amplifier module 740, and LNA 750. Essentially, the low-voltage substrate conductor 772 forms part of a conductive path between the low-voltage power connector 770 and the preamplifier 730, amplifier module 740 (and more specifically, the output / drain of the driver stage amplifier transistors in amplifier module 740), and LNA 750. Therefore, the transceiver module 700 is configured such that the preamplifier 730, amplifier module 740, and LNA 750 can operate using the same low-voltage power supply. When the duplexer 760 is implemented as an active device (e.g., an active transmit / receive switch), the duplexer 760 can also receive and utilize the low-voltage DC power for operation. In the amplifier module 740 (e.g., Figure 6 In the amplifier module 600), the contacts coupled to the low-voltage substrate conductor 772 (e.g., Figure 6 Contacts 611, 614) are biased by a circuit (e.g., Figure 6 The bias circuits 650 and 651) transfer low-voltage DC power to the driver stage transistors (e.g., Figure 1 , 2 Transistors 130 and 230 were not in Figure 6 The output / drain endpoints (e.g., numbered) Figure 1 , 2 Terminals 134 and 234 were not in Figure 6 (Chinese number).

[0123] A high-voltage power connector 780 is coupled to a high-voltage substrate conductor 782, which conducts the high-voltage DC power received through the high-voltage power connector 780 to the amplifier module 740. Essentially, the high-voltage substrate conductor 782 forms part of a conductive path between the high-voltage power connector 780 and the amplifier module 740 (and more specifically, the output / drain of the final-stage amplifier transistors within the amplifier module 740). In the amplifier module 740 (e.g., Figure 6 In the amplifier module 600), the contacts coupled to the high-voltage substrate conductor 782 (e.g., Figure 6 Contacts 612 and 615) are biased by a bias circuit (e.g., Figure 6 The bias circuits 680 and 681) transfer the high-voltage DC power to the final stage transistor (e.g., Figure 1 , Figure 2 Transistors 160 and 260 were not in Figure 6 The output / drain endpoints (e.g., numbered) Figure 1 , 2 6 (ends 164, 264, 634, 654).

[0124] As noted above, embodiments of the subject matter of this invention can fully utilize the use of a single low-voltage power supply (e.g., a standard 5V power supply) to power multiple RF subsystems of an RF transmitter or transceiver (e.g., preamplifier module 730, power amplifier module 740, duplexer 760, and / or LNA module 750). Therefore, the system costs associated with some or all of the unique power supplies for these subsystems can be avoided.

[0125] Figure 8 This is a flowchart of a method for operating an amplifier having a low-voltage drive stage amplifier and a high-voltage final stage amplifier, according to an example embodiment. A power amplifier (e.g., Figure 1 , 2 Amplifiers 100, 200), Dougherty amplifiers or amplifier modules (e.g., Figure 5 , 6 Amplifier 500 and module 600) and / or transmitter or transceiver (e.g., as in Figure 7 The method is performed using various embodiments of the transceiver module 700 implemented in the system.

[0126] The method may begin at step 802 by biasing a multi-stage power amplifier or amplifier module (e.g., ...) by providing a relatively low DC voltage (e.g., below 10V, such as about 5V). Figure 1 , 2 Amplifiers 100, 200, 500 or modules 600, 740 (5-7) drive amplification stages / transistors (e.g., Figure 1-3 The output (e.g., drain terminal) of the stage / transistor 130, 230, 530, 531). Step 802 may also include sending to a transmitter or transceiver system (e.g., Figure 7 Additional components of the transceiver module 700 can provide a relatively low DC voltage. For example, as previously discussed, a preamplifier (e.g., Figure 7 Preamplifier module 730), duplexer, LNA (e.g., Figure 7The LNA750 and / or other system components provide a relatively low DC voltage, and these system components are configured to operate using the same relatively low DC voltage supplied to drive the amplification stage / transistor. For example, when additional components are included in a single module (e.g., Figure 7 When the transceiver module 700 is configured to supply a relatively low DC voltage, a first DC voltage power supply can be coupled to the module (e.g., ...). Figure 7 The first power connector of connector 770), and the conductor (e.g., Figure 7 Conductor 772) can be used to deliver DC voltage to an amplifier module that includes a drive amplification stage / transistor (e.g., Figure 7 (Module 740) and transmit to additional components.

[0127] In step 804, a relatively high DC voltage (e.g., about 28-32V or higher) is provided to bias a multi-stage power amplifier or amplifier module (e.g., Figure 1 , 2 The final amplification stage / transistor (e.g., amplifiers 100, 200, 500 or modules 600, 740) of 5-7 Figure 1-3 The output (e.g., drain terminal) of the 5th stage / transistor (160, 260, 560, 561). For example, when the final amplification stage / transistor is included in the module (e.g., Figure 7 When in the transceiver module 700, a second DC voltage power supply configured to supply a relatively high DC voltage can be coupled to the module (e.g., Figure 7 The second power connector of connector 780), and the conductor (e.g., Figure 7 Conductor 782) can be used to deliver DC voltage to an amplifier module that includes the final amplification stage / transistor (e.g., Figure 7 (Module 740). Additional bias voltages (e.g., input / gate bias voltages) can also be provided via additional connectors and conductors.

[0128] In step 806, when a preamplifier (e.g., is included) is used... Figure 7 When the preamplifier 730 is used, the power amplifier (e.g., Figure 1 , 2 Amplifiers 100, 200, 500 or modules 600, 740 (5-7) are provided (e.g., via...) Figure 1 , 2 The power amplifier continues to amplify the received RF signals (102, 202, 502, 633, 653, 720) input from points 5-7. In step 808, the amplified RF signal is then provided to a load (e.g., an antenna or other load), and the method ends.

[0129] The foregoing specific embodiments are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the foregoing technical field, background art, or specific embodiments.

[0130] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of the subject matter. Furthermore, certain terms may be used herein for reference only, and therefore these terms are not intended to be limiting, and unless the context explicitly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0131] As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes can be implemented using a single physical element (and although received or output at a common node, two or more signals can still be multiplexed, modulated, or distinguished).

[0132] The foregoing description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly connected to) another element, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly connected to) another element electrically or otherwise, and not necessarily mechanically. Therefore, while the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0133] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. An amplifier characterized by, comprises: a driver stage amplifier transistor integrated in a semiconductor die and having a driver stage input, a driver stage output, and an output impedance, wherein the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output; and a final stage amplifier transistor integrated in the semiconductor die and having a final stage input, a final stage output, and an input impedance, wherein the final stage input is electrically coupled to the driver stage output, and the final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage, wherein the semiconductor die is a silicon-based die, the driver stage amplifier transistor is a first laterally diffused metal oxide semiconductor (LDMOS) field effect transistor (FET), and the final stage amplifier transistor is a second LDMOS FET, and wherein the driver stage amplifier transistor has a first transistor finger comprising a first gate structure having a first sidewall, a first drain region, and a first drift region extending from the first sidewall to the first drain region, and wherein the driver stage amplifier transistor is characterized by a first drain-source on-resistance; and the final stage amplifier transistor has a second transistor finger comprising a second gate structure having a second sidewall, a second drain region, and a second drift region extending from the second sidewall to the second drain region, and wherein the final stage amplifier transistor is characterized by a second drain-source on-resistance that is greater than the first drain-source resistance.

2. The amplifier of claim 1, wherein: the driver stage amplifier transistor has an output impedance; the final stage amplifier transistor has an input impedance; a ratio of the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier transistor input is less than 10: 1; and the amplifier further comprises an inter-stage impedance matching circuit electrically coupled between the driver stage output and the final stage input, wherein the inter-stage impedance matching circuit is configured to perform an impedance transformation from the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier.

3. The amplifier of claim 1, wherein: the output impedance of the driver stage amplifier is less than 10 ohms; and the second impedance is less than 5 ohms.

4. The amplifier of claim 1, wherein: the driver stage amplifier transistor is characterized by a first drain-source on-resistance; and the final stage amplifier transistor is characterized by a second drain-source on-resistance that is greater than the first drain-source resistance.

5. The amplifier of claim 1, wherein: the driver stage amplifier transistor is characterized by a first breakdown voltage; and the final stage amplifier transistor is characterized by a second breakdown voltage that is at least 100% higher than the first breakdown voltage.

6. The amplifier of claim 1, wherein: The driver stage amplifier transistor is characterized by a first power density; and The final stage amplifier transistor is characterized by a second power density that is at least 200% greater than the first power density.

7. An amplifier characterized by, Comprise: a driver stage field effect transistor (FET) integrated in a semiconductor die and having a driver stage input, a driver stage output, and an output impedance, wherein the driver stage FET is characterized by a first breakdown voltage; a final stage FET integrated in the semiconductor die and having a final stage input, a final stage output, and an input impedance, and the final stage FET is characterized by a second breakdown voltage that is at least 100% higher than the first breakdown voltage; and an inter-stage impedance matching circuit electrically coupled between the driver stage output and the final stage input, wherein the inter-stage impedance matching circuit is configured to perform an impedance transformation from the output impedance of the driver stage FET to the input impedance of the final stage FET, wherein the semiconductor die is a silicon-based die, the driver stage FET is a first laterally diffused metal oxide semiconductor (LDMOS) field effect transistor (FET), and the final stage FET is a second LDMOS FET, and wherein the driver stage FET has a first transistor finger comprising a first gate structure having a first sidewall, a first drain region, and a first drift region extending from the first sidewall to the first drain region, and wherein the driver stage FET is characterized by a first drain-source on-resistance; and the final stage FET has a second transistor finger comprising a second gate structure having a second sidewall, a second drain region, and a second drift region extending from the second sidewall to the second drain region, and wherein the final stage FET is characterized by a second drain-source on-resistance that is greater than the first drain-source resistance.

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