Fixed Frequency Buck-Boost Power Converter Control

Abstract

The present disclosure provides a processing element, which is configured to be coupled to a first ramp generator and a second ramp generator, and to control the first ramp generator when a power converter operates in a buck-boost operation mode to generate a first ramp signal (805) starting from a first value and increasing to a second value during a first clock cycle, and to generate the first ramp signal (815) starting from the first value and increasing to a third value during a second clock cycle immediately following the first clock cycle, and to control the second ramp generator when the power converter operates in the buck-boost operation mode to generate a second ramp signal (810) starting from a fourth value and decreasing to a fifth value during the first clock cycle, and to generate the second ramp signal (820) starting from the fourth value and decreasing to a sixth value during the second clock cycle.

Description

Summary of the invention

[0001] Various aspects of the present disclosure provide a circuit. In some examples, the circuit includes a first ramp generator, a second ramp generator, and a processing element. The processing element is configured to couple to the first ramp generator and the second ramp generator, and is configured to control the first ramp generator when the power converter is operating in a buck-boost mode of operation to generate a first ramp signal starting from a first value and increasing to a second value during a first clock cycle, and to generate the first ramp signal starting from the first value and increasing to a third value during a second clock cycle immediately following the first clock cycle. The processing element is further configured to control the second ramp generator when the power converter is operating in the buck-boost mode of operation to generate a second ramp signal starting from a fourth value and decreasing to a fifth value during the first clock cycle, and to generate the second ramp signal starting from the fourth value and decreasing to a sixth value during the second clock cycle.

[0002] Other aspects of the present disclosure provide a method. In some examples, the method includes controlling a power converter to operate in a buck mode of operation, including controlling a buck ramp generator to generate a buck ramp signal having a value starting from 0 and increasing to an input voltage (Vin) divided by a scaling constant (K), wherein the buck ramp signal is reset to 0 once per clock cycle, and controlling a boost ramp generator to generate a boost ramp signal having a value starting from Vin / K+output voltage (Vout) divided by K and decreasing to X1*Vin / K, wherein the boost ramp signal is reset to Vin / K+Vout / K once per clock cycle. The method also includes controlling the power converter to operate in a buck-boost operation mode, including controlling the buck ramp generator to alternately generate the buck ramp signal, the buck ramp signal having a value starting from 0 and increasing to X3*Vin / K and having a value starting from 0 and increasing to X4*Vin / K, and controlling the boost ramp generator to alternately generate the boost ramp signal, the boost ramp signal having a value starting from Vin / K+Vout / K and decreasing to X1*Vin / K+Vout / K, and having a value starting from Vin / K+Vout / K and decreasing to X2*Vin / K+Vout / K. The method also includes controlling the power converter to operate in a boost operation mode, including controlling the buck ramp generator to generate the buck ramp signal having a value starting from 0 and increasing to X4*Vin / K, and controlling the boost ramp generator to generate the boost ramp signal having a value starting from Vin / K+Vout / K and decreasing to Vin / K.

[0003] Other aspects of the present disclosure provide a system including a power converter including a plurality of transistors and a controller coupled to the power converter. In some examples, the controller includes a first ramp generator, a second ramp generator, and a processing element. The processing element is configured to be coupled to the first ramp generator and the second ramp generator, and is configured to control the first ramp generator when the power converter is operating in a buck-boost mode of operation to generate a first ramp signal starting from a first value and increasing to a second value during a first clock cycle, and to generate the first ramp signal starting from the first value and increasing to a third value during a second clock cycle immediately following the first clock cycle. The processing element is further configured to control the second ramp generator when the power converter is operating in the buck-boost mode of operation to generate a second ramp signal starting from a fourth value and decreasing to a fifth value during the first clock cycle, and to generate the second ramp signal starting from the fourth value and decreasing to a sixth value during the second clock cycle.

[0004] Other aspects of the present disclosure provide a circuit. In some examples, the circuit includes a first ramp generator, a second ramp generator, and a processing element. The processing element is configured to couple to the first ramp generator and the second ramp generator, and is configured to control the first ramp generator to generate a first ramp signal starting from a first value and increasing to a second value when the power converter operates in a first operating mode, and the first ramp signal is reset to the first value once per clock cycle. The processing element is further configured to control the second ramp generator to generate a second ramp signal starting from a third value and decreasing to a fourth value when the power converter operates in the first operating mode, and the second ramp signal is reset to the third value once per clock cycle.

[0005] Other aspects of the present disclosure provide a circuit including a processing element. In some examples, the processing element is configured to implement a state machine for controlling a buck-boost power converter, monitor an internal control signal to determine whether the internal control signal crosses a buck ramp or a boost ramp during a clock cycle, and transition to a buck-boost state of the state machine when the internal control signal does not cross the buck ramp or the boost ramp during the clock cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a detailed description of various embodiments, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 shows a block diagram of an illustrative switched mode power supply (SMPS) according to various examples;

[0008] Figure 2shows a schematic diagram of an illustrative buck-boost power converter according to various examples;

[0009] Figure 3 presents illustrative state diagrams according to various examples;

[0010] Figure 4 presents illustrative waveform diagrams according to various examples;

[0011] Figure 5 presents illustrative waveform diagrams according to various examples;

[0012] Figure 6 Flowcharts showing illustrative methods according to various examples;

[0013] Figure 7 Flowcharts showing illustrative methods according to various examples; and

[0014] Figure 8 Flowcharts of illustrative methods according to various examples are shown. DETAILED DESCRIPTION

[0015] A switch mode power supply (SMPS) delivers power from an input power source to a load by switching one or more power transistors coupled through a switch node / terminal to an energy storage element (e.g., an inductor / transformer and / or capacitor) that can be coupled to the load. The power transistor may be included in a power converter that includes or can be coupled to the energy storage element. The SMPS may include an SMPS controller to provide one or more gate drive signals to the power transistor. In some architectures (e.g., buck-boost), the SMPS includes or can be coupled to an output / bulk capacitor in parallel with the load, and the SMPS controller switches the power transistor to form a circuit arrangement with an energy storage element to supply a load current to the load and / or to the output / bulk capacitor to maintain a regulated output voltage (e.g., by filtering the switched load current). For example, a power transistor may be coupled through a switch node / terminal to an energy storage inductor that is switched between charge and discharge cycles by the SMPS controller to supply an inductor current (e.g., current through the energy storage inductor) to the load and the output / bulk capacitor to filter the inductor current to maintain a regulated output voltage. In some examples, a SMPS may be configured to operate as a constant current source with an energy storage element but without an output / bulk capacitor.

[0016] The power transistors may be implemented as metal oxide semiconductor field effect transistors (MOSFETs) or any other suitable solid-state transistor devices (e.g., bipolar junction transistors (BJTs)). During an operating mode of a power converter (e.g., a buck-boost power converter) where the value of the input voltage (Vin) is close to the value of the output voltage (Vout), sometimes referred to as a buck-boost operating region, the power converter may oscillate between operating in a buck operating mode and operating in a boost operating mode to provide Vout. In at least some instances, these oscillations may adversely affect the operation of the power converter. For example, the oscillations may waste energy, thereby reducing the operating efficiency of the power converter. In at least some other instances, the oscillations may introduce frequency components to Vout at undesirable and / or undesirable frequencies, thereby reducing the accuracy of Vout produced by the power converter.

[0017] At least some aspects of the present disclosure relate to a controller suitable for controlling a power converter, such as in an SMPS. In at least one example, the controller includes an element suitable for modifying a buck voltage ramp and / or a boost voltage ramp, so that the element of the controller modifies the maximum and / or minimum value of the ramp at least during some time periods. In at least some examples, the controller includes a ramp generator for generating a buck ramp, a ramp generator for generating a boost ramp, and a processing element that at least partially controls the ramp generator. In at least some examples, the processing element controls the ramp generator to modify the maximum and / or minimum value of the ramp generated by the ramp generator. For example, the processing element controls the ramp generator so that during the buck-boost region of operation, the operating points of the buck ramp and the boost ramp are manipulated so that the controller can automatically determine the optimal region for the power converter operation according to a defined rule set that minimizes and / or eliminates the risk of subharmonic oscillations between operating regions.

[0018] Reference now Figure 1, a block diagram of an illustrative SMPS 100 is shown. In at least one example, the SMPS 100 includes a controller 105 and a power converter 110. The power converter 110 is, for example, a buck-boost power converter capable of operating in a buck-boost region. In other examples, the power converter 110 is any other type of power converter, such as a buck power converter, a boost power converter, or a hybrid power converter. In at least one example, the controller 105 includes or is configured to be coupled to a loop controller 115, a processing element 120, a ramp generator 125, a ramp generator 130, and a gate driver 135. At least one example of the SMPS 100 includes at least some aspects of the controller 105 and the power converter 110 in the same semiconductor die and / or in the same component package, while in other examples, the controller 105 and the power converter 110 can be manufactured separately and configured to be coupled together. For example, at least some aspects of the controller 105 can be manufactured separately and coupled together. Thus, although illustrated as including the gate driver 135 , in at least one example, the controller 105 does not include the gate driver 135 , but is instead configured to be coupled to the gate driver 135 .

[0019] In at least one example, the SMPS 100 is configured to receive Vin from an input power source (not shown) and provide Vout at an output terminal based at least in part on an input voltage received by the SMPS 100 and a reference voltage (Vref). Vref may be received from any suitable device (not shown), such as a processor, a microcontroller, or any other device that exerts control on the SMPS 100 to control the value of Vout, and may be or represent a predetermined (e.g., user desired, target, preconfigured, programmed, etc.) value of Vout. In at least one example, the SMPS 100 provides Vout to a load 140 coupled to the SMPS 100 (e.g., coupled to the SMPS 100 at the output of the power converter 110). In at least one example, the controller 105 receives one or more signals from the power converter 110. For example, the controller 105 may receive Vout and / or a value representing an inductor current (IL) of the power converter 110 from the power converter 110. In various examples, the value representing IL may be a value measured directly from an inductor (not shown) of power converter 110 (or a terminal of another component of power converter 110 to which the inductor is also coupled) or a value sensed from a sensing element (not shown) of power converter 110. The sensing element is, for example, a sense resistor, a transistor, or any other component or combination of components capable of measuring IL of power converter 110 and providing a value representing IL to controller 105.

[0020] In at least one example, the loop controller 115 is coupled to the gate driver 135 and the power converter 110 and is configured to receive Vref and Vout, for example, at least in part for controlling the gate driver 135. In another example, the loop controller 115 further receives a value representing IL from a sensing element of the power converter 110 for further use in controlling the gate driver 135. In yet another example, the loop controller 115 includes the processing element 120, the ramp generator 125, and the ramp generator 130. The processing element 120 controls the ramp generator 125 and the ramp generator 130 to generate a ramp signal (for example, controlling the ramp generator 125 to generate a buck ramp and controlling the ramp generator 130 to generate a boost ramp) for the loop controller 115 to use in controlling the gate driver 135. In at least some examples, although not described in detail, the loop controller 115 may be used to control the gate driver 135. Figure 1 , but the processing element 120 is further configured to couple to at least some other components of the SMPS 100 and receive one or more of Vref, Vout, and / or IL.

[0021] Based on the received inputs (e.g., Vin, Vout, a value representing IL, and / or Vref) and outputs of the ramp generators 125 and 130, the loop controller 115 controls the gate driver 135 to control the power transistors (not shown) of the power converter 110 to generate Vout. In at least one example, when the internal control signal (e.g., determined according to Vin, Vout, a value representing IL, and / or Vref) exceeds the value of the buck ramp, the loop controller 115 controls the gate driver 135 to control the power converter 110 to operate in the buck operation mode, and when the internal control signal exceeds the value of the boost ramp, the gate driver 135 is controlled to control the power converter 110 to operate in the boost operation mode. In at least one example, the internal control signal is a scaled representation of Vout. In other examples, the internal control signal is the result determined by a differential amplifier that receives a representation of IL as an input, and the result determined by another differential amplifier that receives a scaled representation of Vref and Vout as an input. In at least some instances, processing element 120 additionally or alternatively provides control measurements to gate driver 135 to control control of power converter 110. Thus, in at least some instances, although not in Figure 1 , but the processing element 120 is configured to receive at least some of Vin, Vout, a value representing IL, and / or Vref.

[0022] For example, in at least one embodiment, the loop controller 115 compares Vout (or a scaled version of Vout, such as by scaling with a voltage divider) to Vref. The result of the comparison is compared to a value representing IL. For example, the result of the comparison is an internal control signal where a buck ramp is compared to a boost ramp. In various examples, the loop controller 115 includes any suitable circuit or component for controlling the gate driver 135 to control the power converter 110 at a fixed (e.g., constant) switching frequency (fsw), as disclosed herein.

[0023] In at least one example, the loop controller 115 may include one or more comparators (not shown). In another example, the loop controller 115 may further include or be coupled to a voltage divider (not shown) that can scale the value of Vout. In another example, the loop controller 115 may further include one or more supporting components (not shown), such as resistors, capacitors, diodes, and the like, the scope of which is not limited herein. In at least some examples, the ramp generator 125 and the ramp generator 130 may each be, for example, a resistor-capacitor (RC) timer or other form of timer, the scope of which is not limited herein. In at least some examples, the resistor (not shown) and / or the capacitor (not shown) of the RC timer are controllable to control the resistance value of the resistor or the capacitance value of the capacitor, for example, to manipulate and / or change the value of the buck ramp and / or the boost ramp, as discussed herein. Typically, the ramp generator 125 and the ramp generator 130 each include any suitable element suitable for generating a controllable ramp signal. In some examples, loop controller 115 can provide any number of control signals to gate driver 135 to control gate driver 135 .

[0024] In various examples, gate driver 135 is any suitable driver, component, or combination of components for controlling power converter 110 (e.g., by coupling to and exerting control over gate terminals of power transistors of power converter 110). In at least one example, gate driver 135 includes at least one driver (not shown) configured to generate a high current control gate drive signal based on a received input signal. For example, when gate driver 135 receives a first input signal from loop controller 115, gate driver 135 may control a first subset of power transistors of power converter 110 to turn on (or remain) while controlling the remaining portion of power transistors of power converter 110 to remain (or turn off). When gate driver 135 receives a second input signal from loop controller 115, gate driver 135 may control a second subset of power transistors of power converter 110 to turn on (or remain), and the remaining portion of power transistors of power converter 110 to remain (or turn off). When the power converter 110 operates in the buck-boost region (e.g., alternating between one clock operation cycle in buck mode (buck cycle) and one clock operation cycle in boost mode (boost cycle), and repeating), in some instances, the gate driver 135 may control the power converter 110 to generate a trapezoidal inductor current waveform, for example based on control applied to the gate driver 135 by the loop controller 115.

[0025] Reference now Figure 2 , showing a schematic diagram of an illustrative buck-boost power converter 200. In at least one example, the buck-boost power converter 200 is suitable for use in the above-discussed Figure 1Implementation of power converter 110 of SMPS 100 of the embodiment of the present invention. In one example, buck-boost power converter 200 includes a plurality of metal oxide semiconductor field effect transistors (MOSFETs) 205, 210, 215 and 220, and at least one energy storage device (illustrated as inductor 225 in this example). In another example, buck-boost power converter 200 further includes a second inductor (not shown) and / or a flying capacitor (not shown). In one example, MOSFETs 205 and 220 are implemented as p-type MOSFETs (PMOS), and MOSFETs 210 and 215 are implemented as n-type MOSFETs (NMOS). In at least one example, buck-boost power converter 200 further includes a sensing element 230 suitable for sensing IL of inductor 225. Sensing element 230 is, for example, a MOSFET, a resistor, or any other suitable device for sensing, measuring or detecting IL. In at least one example, sensing element 230 is implemented by one of MOSFETs 205 , 210 , 215 , or 220 , such that sensing element 230 is not a separate additional component of buck-boost power converter 200 .

[0026] In one example architecture, the source terminal of MOSFET 205 is configured to receive Vin, the drain terminal of MOSFET 205 is coupled to node 235, and the gate terminal of MOSFET 205 is coupled to a controller (e.g., as discussed above). Figure 1100 of the SMPS 100). The drain terminal of the MOSFET 210 is coupled to the node 235, the source terminal of the MOSFET 210 is coupled to the ground node 240, and the gate terminal of the MOSFET 210 is coupled to the controller. A first terminal of the inductor 225 is coupled to the node 235, and a second terminal of the inductor 225 is coupled to the node 245. In at least one example, the sensing element 230 is coupled in series between the node 235 and the first terminal of the inductor 225. In another example, the drain terminal of the MOSFET 215 is coupled to the node 245, the source terminal of the MOSFET 215 is coupled to the ground node 240, and the gate terminal of the MOSFET 215 is coupled to the controller. The drain terminal of MOSFET 220 is coupled to ground node 240, the source terminal of MOSFET 220 provides Vout from buck-boost power converter 200 (e.g., such that the source terminal of MOSFET 220 is configured to be coupled to a load (not shown)), and the gate terminal of MOSFET 220 is coupled to a controller. In at least one example, inductor 225 is implemented as an external component such that buck-boost power converter 200 does not include inductor 225, but is configured to be coupled to inductor 225 between node 235 and node 245. In at least one example, buck-boost power converter 200 is configured to be coupled to capacitor 250 (e.g., a filter capacitor) between the source terminal of MOSFET 220 and ground node 240.

[0027] In one example, the MOSFETs 205, 210, 215, and / or 220 are controlled to be turned on (e.g., conduct current between their respective drain terminals and source terminals) and / or turned off (e.g., stop conducting current between their respective drain terminals and source terminals) based on signals received at their respective gate terminals. For example, based on a signal (e.g., a control signal) received from a controller, one or more of the MOSFETs 205, 210, 215, and / or 220 are controlled to be turned on or off. The MOSFETs 205, 210, 215, and / or 220 may be turned on (or off) based on values ​​or relationships between values ​​present at one or more respective gate terminals and / or source terminals of the MOSFETs 205, 210, 215, and / or 220.

[0028] like Figure 2As further described in at least one example, the buck-boost power converter 200 is configured to operate in a buck cycle or a boost cycle. The buck cycle includes a buck-on phase (as described as Buck) and a buck-off phase (as described as ToffBuck), and the boost cycle includes a boost-on phase (as described as TonBoost) and a boost-off phase (as described as ToffBoost).

[0029] During TonBoost, MOSFETs 205 and 215 are controlled by the controller to be turned on, while MOSFETs 210 and 220 are controlled by the controller to be turned off. During TonBoost, a path from Vin to ground is formed through MOSFET 205, inductor 225, and MOSFET 215, thereby enabling inductor 225 to charge from Vin. During ToffBuck, MOSFETs 205 and 215 are controlled by the controller to be turned off, while MOSFETs 210 and 220 are controlled by the controller to be turned on. During ToffBuck, a path from ground node 240 to a node of buck-boost power converter 200 to which a load can be coupled to receive Vout (e.g., the source terminal of MOSFET 220) is formed through MOSFET 210, inductor 225, and MOSFET 220, thereby enabling inductor 225 to discharge to provide Vout. During ToffBoost and TonBuck, MOSFETs 205 and 220 are controlled by the controller to be turned on, and MOSFETs 210 and 215 are controlled by the controller to be turned off. During ToffBoost and TonBuck, Vin and Vout have approximately the same value, so that the voltage difference across inductor 225 is minimized. When the voltage difference across inductor 225 is minimized, in at least one example, inductor 225 can approximately act as a short circuit between Vin and Vout and have minimal impact on the value of Vout.

[0030] Now go to Figure 3 , showing an illustrative state diagram 300. In at least some examples, the state diagram 300 illustrates Figure 1100 of the SMPS 100 (and thus implemented by it in at least some examples). In at least some examples, the state diagram 300 indicates rules and / or conditions for controlling a power converter (e.g., the power converter 110 of the SMPS 100) to operate in a buck mode of operation, a boost mode of operation, or a buck-boost mode of operation. For purposes of description, it is assumed that Vin is greater than Vout, and thus operation according to the state diagram 300 begins at state 305. However, when operation according to the state diagram 300 begins, if Vin is less than Vout, then operation according to the state diagram 300 will begin at state 310.

[0031] When in state 305, the power converter is controlled to operate in buck mode. When operating in the buck mode of operation, the signal BUBO is set to a low value to indicate that the power converter is not operating in the buck-boost mode of operation. When the controller detects that the power converter performs a buck operation cycle when in state 305, the controller controls the power converter to continue operating according to state 305. When the controller detects that a gap detection has occurred, the controller controls the power converter to operate according to state 310. In at least some examples, the gap detection is defined as the internal control signal of the power converter not crossing the ramp generated by the ramp generator 125 of the SMPS 100 or the ramp generated by the ramp generator 130 of the SMPS 100, while the clock signal (CLK) has a logic level low value (e.g., the internal control signal has a value that exists in the gap between the ramp generated by the ramp generator 125 and the ramp generated by the ramp generator 130, and CLK has a logic level low value). When the controller detects that the power converter performs a boost cycle while in state 305, the controller controls the power converter to operate according to state 310.

[0032] When in state 310, the power converter is controlled to operate in the buck-boost mode of operation. When operating in the buck-boost mode of operation, BUBO is set to a high value to indicate that the power converter is operating in the buck-boost mode of operation. When the controller detects that the power converter performs two consecutive buck operation cycles when in state 310, the controller controls the power converter to return to operation according to state 305. When the controller detects that the power converter performs two consecutive boost operation cycles when in state 310, the controller controls the power converter to operate according to state 315.

[0033] When in state 315, the power converter is controlled to operate in the boost mode of operation. When operating in the boost mode of operation, BUBO is set to a low value to indicate that the power converter is not operating in the buck-boost mode of operation. When the controller detects that the power converter performs a boost operation cycle when in state 315, the controller controls the power converter to continue operating according to state 315. When the controller detects that a gap detection has occurred, the controller controls the power converter to operate according to state 310. When the controller detects that the power converter performs a buck cycle when in state 315, the controller controls the power converter to operate according to state 310.

[0034] In at least some instances, when operating according to state diagram 300, the controller is subject to a plurality of operating rules to provide efficient operation in buck, boost, and buck-boost operating modes while avoiding subharmonic oscillations between operating modes. For example, as discussed herein, the rules provide for manipulation of the ramp generated by ramp generator 125 and the ramp generated by ramp generator 130, and control of internal signals that facilitate control of the power converter. In at least some instances, state diagram 300 and associated rules represent a control scheme in a fixed frequency system where CLK has a fixed frequency. In at least some instances, each cycle of CLK has a high phase of 50 nanoseconds (ns). In other instances, the high phase of CLK has any suitable value determined by the desired operation of the controller and / or power converter.

[0035] In at least some examples, when CLK has a high value, the buck ramp and the boost ramp are each reset (e.g., the buck ramp is reset to 0 and the boost ramp is reset to approximately Vin / K, where K is a scaling constant). When CLK has a low value, the buck ramp increases in value from 0 to approximately Vin / K when in state 305, and from 0 to approximately 0.8*Vin / K when in state 315. When in state 310 and CLK has a low value, if operation proceeds from state 305 to state 310, the buck ramp increases in value from 0 to approximately 0.8*Vin / K, and if operation proceeds from state 315 to state 310, the buck ramp increases in value from 0 to approximately 1.1*Vin / K. Similarly, when CLK has a low value, the value of the boost ramp decreases from about Vin / K+Vout / K to about Vin / K when in state 315, and from about Vin / K+Vout / K to about 1.2*Vin / K when in state 305. When in state 310 and CLK has a low value, the value of the boost ramp decreases from about Vin / K+Vout / K to about 0.9*Vin / K if operation proceeds from state 305 to state 310, and the value of the boost ramp decreases from about Vin / K+Vout / K to about 1.2*Vin / K if operation proceeds from state 315 to state 310. In at least some examples, the scaling constant K has any suitable value dictated by the implementation of the controller and / or power converter, and in at least some examples, K is 2.

[0036] In at least some instances, state signal BUH_BOL has a high value after a buck operation cycle and has a low value after a boost operation cycle. For example, when operating in state 305, BUH_BOL remains high, when operating in state 315, BUH_BOL remains low, and when operating in state 310, BUH_BOL alternates between a high value and a low value. Generally speaking, during a buck cycle, the internal control signal crosses the buck ramp, and during a boost cycle, the internal control signal crosses the boost ramp. When the internal control signal crosses neither the buck ramp nor the boost ramp, the controller determines that gap detection has occurred and the signal GAP_DETECT has a high value for one clock cycle. When GAP_DETECT has a high value and BUH_BOL has a low value, the controller controls the power converter to enforce a minimum buck off-time, which starts from the next rising edge of CLK after the rising edge of GAP_DETECT. When GAP_DETECT has a high value and BUH_BOL has a high value, the controller controls the power converter to enforce a minimum boost on-time, which starts from the next rising edge of CLK after the rising edge of GAP_DETECT. When BUBO has a low value, a rising edge of GAP_DETECT causes a corresponding rising edge to occur in BUBO, and a falling edge to occur in BUBO after two consecutive buck cycles occur or after two consecutive boost cycles occur.

[0037] Now go to Figure 4 , a diagram 400 of an illustrative waveform is shown. In at least some examples, the diagram 400 graphically illustrates the Figure 3 The state diagram 300 and its associated rule-operated system (eg Figure 1 For example, diagram 400 illustrates operation starting from state 305 (e.g., Vout is less than Vin), transitioning to state 310 (e.g., Vout is approximately equal to Vin), and finally transitioning to state 315 (e.g., Vout is greater than Vin) while operating within the range of parameters set in the rules associated with state diagram 300 to create regular, predictable operation while in state 310.

[0038] As shown in diagram 400, when operating in state 305, buck ramp 405 increases from approximately 0 volts (V) to approximately Vin / 2V, and Vout crosses buck ramp 405 when CLK is low during each clock cycle. During this same period, the controller scales boost ramp 410 so that the minimum value of boost ramp 410 is greater than Vin / 2, and no overlap occurs between boost ramp 410 and buck ramp 405. Furthermore, when operating in state 305, whenever the internal control signal (Ctrl) crosses buck ramp 405 when CLK is low, BUH_BOL has a high value, BUBO has a low value, and GAP_DETECT has a low value. At time t1, a gap detection is detected where the internal control signal does not cross buck ramp 405 or boost ramp 410, indicating a transition from state 305 to state 310 operation according to state diagram 300.

[0039] When operating in state 310, as shown in graph 400, the controller controls buck ramp 405 to alternate between a maximum value greater than Vin / 2 and a maximum value less than Vin / 2 with each clock cycle, while controlling boost ramp 410 to alternate between a minimum value greater than Vin / 2 and a minimum value less than Vin / 2 with each clock cycle. In this manner, the controller's manipulation of buck ramp 405 and boost ramp 410 creates a predictable pattern of alternating buck cycles and boost cycles when operating in state 310, thereby mitigating operational oscillations and uncertainties that were previously common in the buck-boost operating mode of the power converter. Furthermore, as shown in diagram 400 and discussed previously, BUH_BOL alternates in value during operation in state 310, indicating the immediately previous mode of operation (e.g., BUH_BOL has a low value after a boost cycle and a high value after a buck cycle), and BUBO has a high value to indicate that operation according to state 310 is being performed (e.g., a buck-boost mode of operation that continuously alternates between buck and boost cycles). In at least some instances, rising edges in GAP_DETECT that occur while BUBO has a high value are ignored. At time t2, for the second of two consecutive clock cycles, the internal control signal crosses the boost ramp 410, resulting in a falling edge in BUBO and indicating a transition from state 310 to state 315 according to state diagram 300.

[0040] When operating in state 315, the boost ramp 410 decreases from approximately Vin / 2+Vout / 2V to approximately Vin / 2V, and the internal control signal crosses the boost ramp 410 when CLK is low during each clock cycle. During this same period, the controller scales the buck ramp 405 so that the maximum value of the buck ramp 405 is less than Vin / 2, and no overlap occurs between the buck ramp 405 and the boost ramp 410. In addition, when operating in state 315, whenever the internal control signal crosses the boost ramp 410 when CLK is low, BUH_BOL has a low value, BUBO has a low value, and GAP_DETECT has a low value.

[0041] As shown in Figure 400, the above Figure 3 The described state diagram 300 and its associated rules for manipulating the buck ramp 405, the boost ramp 410, and controlling the values ​​of GAP_DETECT, BUH_BOL, and BUBO provide orderly, predictable, and standardized regular operation by the power converter to enter the buck-boost mode, operate in the buck-boost operating mode, and exit the buck-boost operating mode to prevent or mitigate unpredictable behavior and / or oscillations between power converter operating modes.

[0042] Although Vin / K Figure 4 , but in practice, Vin / K will change as Vin changes (e.g., as Vin increases and / or decreases). Figure 4 4 and 4. The voltage drop ramp 405 and the voltage increase ramp 410 are illustrated as consistent straight lines in order to facilitate explanation and understanding of the control and manipulation of the voltage drop ramp 405 and the voltage increase ramp 410 with respect to Vin / K.

[0043] Now go to Figure 5 , showing a graph 500 of illustrative waveforms. In at least some examples, graph 500 graphically illustrates the Figure 3 The state diagram 300 and its associated rule-operated system (eg Figure 1 For example, diagram 500 illustrates operation starting from state 315 (e.g., Vout is greater than Vin), transitioning to state 310 (e.g., Vout is approximately equal to Vin), and finally transitioning to state 305 (e.g., Vout is less than Vin) while operating within the range of parameters set in the rules associated with state diagram 300 to create regular, predictable operation while in state 310.

[0044] As shown in diagram 500, when operating in state 315, boost ramp 505 decreases from about Vin / 2+Vout / 2V to about Vin / 2V, and the internal control signal (Ctrl) crosses the boost ramp 505 when CLK is low during each clock cycle. During this same period, the controller scales the buck ramp 510 so that the maximum value of the buck ramp 510 is less than Vin / 2, and no overlap occurs between the buck ramp 510 and the boost ramp 505. Furthermore, when operating in state 315, whenever the internal control signal crosses the boost ramp 505 when CLK is low, BUH_BOL has a low value, BUBO has a low value, and GAP_DETECT has a low value. At time t1, a gap detection is detected, where the internal control signal does not cross the boost ramp 505 or the buck ramp 510, indicating an operational transition from state 315 to state 310 according to state diagram 300.

[0045] When operating in state 310, as shown in graph 500, the controller controls the boost ramp 505 to alternate between a minimum value greater than Vin / 2 and a minimum value less than Vin / 2 with each clock cycle, while controlling the buck ramp 510 to alternate between a maximum value greater than Vin / 2 and a maximum value less than Vin / 2 with each clock cycle. In this manner, the controller's manipulation of the boost ramp 505 and the buck ramp 510 creates a predictable pattern of alternating buck cycles and boost cycles when operating in state 310, thereby mitigating the operational oscillations and uncertainties previously common to the buck-boost operating mode of the power converter. Furthermore, as shown in diagram 500 and discussed previously, BUH_BOL alternates in value during operation in state 310, indicating the immediately prior mode of operation (e.g., BUH_BOL has a low value after a boost cycle and a high value after a buck cycle), and BUBO has a high value to indicate that operation according to state 310 is being performed (e.g., a buck-boost mode of operation that continuously alternates between buck and boost cycles). In at least some instances, rising edges in GAP_DETECT that occur while BUBO has a high value are ignored. At time t2, for the second of two consecutive clock cycles, the internal control signal crosses buck ramp 510, resulting in a falling edge in BUBO and indicating a transition from state 310 to state 305 according to state diagram 300.

[0046] When operating in state 305, the buck ramp 510 increases from approximately 0V to approximately Vin / 2V, and the internal control signal crosses the buck ramp 510 when CLK is low during each clock cycle. During this same period, the controller scales the boost ramp 505 so that the minimum value of the boost ramp 505 is greater than Vin / 2, and no overlap occurs between the boost ramp 505 and the buck ramp 510. Furthermore, when operating in state 305, whenever the internal control signal crosses the buck ramp 510 when CLK is low, BUH_BOL has a high value, BUBO has a low value, and GAP_DETECT has a low value.

[0047] As shown in Figure 500, the above Figure 3 The described state diagram 300 and its associated rules for manipulating the boost ramp 505, the buck ramp 510, and controlling the values ​​of GAP_DETECT, BUH_BOL, and BUBO provide orderly, predictable, and standardized regular operation by the power converter to enter the buck-boost mode, operate in the buck-boost operating mode, and exit the buck-boost operating mode to prevent or mitigate unpredictable behavior and / or oscillations between power converter operating modes.

[0048] Although Vin / K Figure 5 , but in practice, Vin / K will change as Vin changes (e.g., as Vin increases and / or decreases). Figure 5 5 and 6. The voltage regulator 500 is illustrated as a consistent straight line in order to facilitate explanation and understanding of the control and manipulation of the boost ramp 505 and the buck ramp 510 with respect to Vin / K.

[0049] Now go to Figure 6 , a flow chart of an illustrative method 600 is shown. In at least some examples, method 600 represents the operation of a controller that controls a power converter according to state diagram 300 and its associated rules for manipulating buck ramp 405, boost ramp 410, boost ramp 505, and / or buck ramp 510, and for controlling the values ​​of GAP_DETECT, BUH_BOL, and BUBO, as described above with respect to Figure 3 , Figure 4 and / or Figure 5 For the purpose of discussion, it is assumed that at the beginning of the operation of method 600, Vin is greater than Vout, and through the operation of method 600, Vin is reduced to be less than Vout. However, in some examples, at the beginning of the operation of method 600, Vin may instead be less than Vout, and through the operation of method 600, Vin is increased to be greater than Vout. In such examples, the operation of method 600 may be substantially reversed, as may be understood from the previous discussion of state diagrams 300, 400, and 500.

[0050] At operation 605, the controller controls the power converter to operate in a buck mode of operation (e.g., where a buck cycle is followed by another buck cycle). When operating in the buck mode of operation, in at least some instances, the controller manipulates the boost ramp of the controller such that the minimum value of the boost ramp increases. Figure 7 , a flow chart of an illustrative method 700 for controlling a power converter when operating in a buck operating mode is shown. In at least some instances, method 700 is a sub-method describing the operation of a controller during operation 605 of method 600. At operation 705, when the power converter is operating in a first operating mode, the controller controls a first ramp generator (e.g., a buck ramp generator) to generate a first ramp signal starting from a first value and increasing to a second value, the first ramp signal being reset to the first value once per clock cycle. In at least some instances, the first value is approximately 0 and the second value is approximately Vin / K. At operation 710, when the power converter is operating in the first operating mode, the controller controls a second ramp generator (e.g., a boost ramp generator) to generate a second ramp signal starting from a third value and decreasing to a fourth value, the second ramp signal being reset to the third value once per clock cycle. In at least some instances, when the controller determines that the power converter is in the buck operating mode, after operation 710, the controller starts again at operation 705 and repeats method 700. In at least some examples, the third value is approximately Vin / K+Vout / K, and the fourth value is greater than approximately Vin / K.

[0051] In at least some examples, the controller controls the boost ramp generator to modify the boost ramp such that the minimum value of the boost ramp is greater than Vin / K, and during operation 710, the boost ramp decreases each clock cycle from approximately Vin / K+Vout / K to approximately X1*Vin / K, where X1 is a value greater than 1. In addition, the controller controls the buck ramp generator such that during operation 705, the buck ramp increases each clock cycle from approximately 0 to approximately Vin / K. Returning now to Figure 6, when operating in the buck mode of operation, the controller additionally controls the value of the BUH_BOL signal to have a high value, controls the value of the BUBO signal to have a low value, and controls the value of the GAP_DETECT signal to have a low value, unless the controller determines that the internal control signal crosses neither the buck ramp nor the boost ramp when CLK has a low value. In at least one example, the controller controls the power converter to continue operating in the buck mode of operation until an exit condition occurs. The exit condition includes, for example, the occurrence of a gap detection (e.g., as indicated by a rising edge in the GAP_DETECT signal) or the detection of a boost cycle occurring while operating in the buck mode of operation. For example, if a large value and / or a sudden or abrupt change occurs in Vin or the load receiving Vout while operating in the buck mode of operation, the loop controller may directly control the power converter to perform a boost cycle despite the controller indicating operation in the buck mode of operation for one additional clock cycle. When the exit condition occurs, the method 600 proceeds from operation 605 to operation 610.

[0052] At operation 610, the controller controls the power converter to operate in a buck-boost mode of operation (e.g., where a buck cycle is followed by a boost cycle, followed by a buck cycle, and repeats). When operating in the buck-boost mode of operation, in at least some examples, the controller manipulates the boost ramp such that the minimum value of the boost ramp alternates between greater than and less than approximately Vin / K, and manipulates the buck ramp such that the maximum value of the buck ramp alternates between less than and greater than approximately Vin / K. Figure 8 , a flow chart of an illustrative method 800 for controlling a power converter when operating in a buck-boost mode of operation is shown. In at least some instances, method 800 is a sub-method describing the operation of a controller during operation 610 of method 600. At operation 805, the controller controls a first ramp generator (e.g., a buck ramp generator) to generate a first ramp signal starting from a first value and increasing to a second value during a first clock cycle. At operation 810, the controller controls a second ramp generator (e.g., a boost ramp generator) to generate a second ramp signal starting from a fourth value and decreasing to a fifth value during the first clock cycle. At operation 815, the controller controls the first ramp generator to generate a first ramp signal starting from a first value and increasing to a third value during a second clock cycle. At operation 820, the controller controls the second ramp generator to generate a second ramp signal starting from a fourth value and decreasing to a sixth value during the second clock cycle. In at least some instances, the second clock cycle is immediately after the first clock cycle (e.g., the first clock cycle and the second clock cycle are continuous in the clock signal). In at least some examples, when the controller determines that the power converter is in the buck-boost mode of operation, after the second clock cycle (after operation 820 ), the controller starts again at operation 805 and repeats method 800 .

[0053] In at least some examples, the controller controls the boost ramp generator to modify the boost ramp such that the minimum value of the boost ramp decreases from about Vin / K+Vout / K to about X1*Vin / K during operation 810, and decreases from about Vin / K+Vout / K to about X2*Vin / K during operation 820, where X2 is less than 1. In addition, in at least some examples, the controller controls the buck ramp generator to modify the buck ramp such that the maximum value of the boost ramp increases from about 0 to about X3*Vin / K during a first clock cycle, and increases from about 0 to about X4*Vin / K during a second clock cycle, where X3 is greater than 1 and X4 is less than 1. In various examples, X1, X2, X3, and X4 can each be any suitable value within the parameters provided herein, however, in at least one example, X1 is 1.2, X2 is 0.9, X3 is 1.1, and X4 is 0.8. In various examples, the exact values ​​of X1, X2, X3, and / or X4 may vary within the parameters described herein and be selected according to the capabilities of the power converter being utilized. For example, using a gate driver capable of high speed operation may cause X1, X2, X3, and / or X4 to be closer to 1, thereby reducing the size of the buck-boost operating region that exists between the minimum value of the boost ramp and the maximum value of the buck ramp.

[0054] Now return to Figure 6 , when operating in the buck operating mode, the controller additionally controls the value of the BUH_BOL signal to alternate in value, the BUH_BOL value during the current clock cycle representing the operation of the power converter in the immediately previous clock cycle (BUH_BOL has a high value for the clock cycle immediately following the power converter buck cycle and has a low value for the clock cycle immediately following the power converter boost cycle), controls the value of the BUBO signal to have a high value, and controls the value of the GAP_DETECT signal to have a low value unless the controller determines that the internal control signal crosses neither the buck ramp nor the boost ramp when CLK has a low value. In at least one example, the controller controls the power converter to continue operating in the buck-boost operating mode until an exit condition occurs. The exit condition includes, for example, the occurrence of a boost cycle in two consecutive clock cycles (e.g., without an intervening buck cycle or a rising edge of GAP_DETECT) or the occurrence of a buck cycle in two consecutive clock cycles (e.g., without an intervening boost cycle or a rising edge of GAP_DETECT). When the exit condition occurs, the method 600 returns to operation 605 when the exit condition is two consecutive buck cycles, and the method 600 exits to operation 615 when the exit condition is two consecutive boost cycles.

[0055] At operation 615, the controller controls the power converter to operate in a boost mode of operation (e.g., a boost cycle followed by another boost cycle). When operating in the boost mode of operation, in at least some instances, the controller manipulates the buck ramp of the controller such that the maximum value of the buck ramp decreases. In at least some instances, Figure 7 Method 700 also illustrates control of a power converter when operating in a boost mode of operation. In at least some instances, method 700 is a sub-method describing operation of a controller during operation 615 of method 600, wherein the first value is approximately 0, the second value is less than approximately Vin / K, the third value is approximately Vin / K+Vout / K, and the fourth value is less than approximately Vin / K. For example, the controller controls the buck ramp generator such that the maximum value of the buck ramp is less than Vin / K, and the buck ramp increases each clock cycle from approximately 0 to approximately X4*Vin / K. In addition, the controller controls the boost ramp generator such that the boost ramp decreases each clock cycle from approximately Vin / K+Vout / K to approximately Vin / K. In addition, when operating in the boost mode of operation, the controller controls the value of the BUH_BOL signal to have a low value, controls the value of the BUBO signal to have a low value, and controls the value of the GAP_DETECT signal to have a low value, unless the controller determines that the internal control signal crosses neither the buck ramp nor the boost ramp when CLK has a low value. In at least one example, the controller controls the power converter to continue operating in the boost mode of operation until an exit condition occurs. The exit condition includes, for example, the occurrence of a gap detection (e.g., as indicated by a rising edge in the GAP_DETECT signal) or the detection of a buck cycle occurring while operating in the boost mode of operation. For example, if a large value and / or a sudden or abrupt change occurs in Vin or the load receiving Vout while operating in the boost mode of operation, the loop controller may directly control the power converter to perform a buck cycle despite the controller indicating operation in the boost mode of operation for one additional clock cycle. When the exit condition occurs, the method 600 returns from operation 605 to operation 610.

[0056] In addition, in the foregoing discussion, the terms "include" and "comprise" are used in an open manner and should therefore be interpreted as "including but not limited to ...". In addition, the term "coupled" is intended to mean an indirect or direct wired or wireless connection. Therefore, if a first device, element or component is coupled to a second device, element or component, the coupling may be by direct coupling or by indirect coupling via other devices, elements or components and connections. Similarly, a device, element or component coupled between a first component or position and a second component or position may be directly connected or indirectly connected via other devices, elements or components and / or couplings. A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform a function when manufactured by a manufacturer and / or may be configured (or reconfigured) by a user after manufacturing to perform a function and / or other additional or alternative functions. The configuration may be implemented by firmware and / or software programming of the device, by the construction and / or layout of hardware components and interconnections of the device, or a combination thereof. In addition, a circuit or device referred to as including certain components may be configured to couple to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be configured to couple to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0057] Although certain components are described herein as components of a particular process technology (e.g., field effect transistors (FETs), metal oxide semiconductor FETs (MOSFETs), n-type, p-type, etc.), these components may be exchanged for components of other process technologies (e.g., replacing FETs and / or MOSFETs with bipolar junction transistors (BJTs), replacing n-type with p-type, or vice versa, etc.), and the circuits including the replaced components reconfigured to provide the desired functionality at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, components described as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the described resistor. Furthermore, the use of the phrase "ground voltage potential" in the foregoing discussion is intended to include chassis ground, ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of the present disclosure. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0058] The above discussion is intended to illustrate the principles and various examples of the present disclosure. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. It is hoped that the present disclosure will be interpreted as including all such changes and modifications.

Claims

1. A circuit, wherein include: a first ramp generator; a second ramp generator; and a processing element configured to be coupled to the first ramp generator and the second ramp generator and configured to: controlling the first ramp generator to generate a first ramp signal starting from a first value and increasing to a second value during a first clock cycle when the power converter is operating in a buck-boost mode of operation, and to generate the first ramp signal starting from the first value and increasing to a third value during a second clock cycle immediately following the first clock cycle; and The second ramp generator is controlled when the power converter operates in the buck-boost operating mode to generate a second ramp signal starting from a fourth value and decreasing to a fifth value during the first clock cycle, and to generate the second ramp signal starting from the fourth value and decreasing to a sixth value during the second clock cycle.

2. The circuit of claim 1 , wherein the processing element is further configured to: controlling the first ramp generator to generate the first ramp signal starting from the first value and increasing to a seventh value when the power converter operates in a buck mode of operation; and When the power converter operates in the buck operating mode, the second ramp generator is controlled to generate the second ramp signal starting from the fourth value and decreasing to the fifth value.

3. The circuit of claim 2, wherein the processing element is further configured to: controlling the BUH_BOL signal to have a high value after a step-down cycle of the power converter and to have a low value after a step-up cycle of the power converter; controlling a BUBO signal to have a low value during the buck mode of operation and during a boost mode of operation of the power converter; and When the internal control signal does not cross the first ramp signal or the second ramp signal during a low phase of the first clock cycle or the second clock cycle, the GAP_DETECT signal is controlled to have a high value, and when the internal control signal crosses the first ramp signal or the second ramp signal during the low phase of the first clock cycle or the second clock cycle, the GAP_DETECT signal is controlled to have a low value.

4. The circuit of claim 1 , wherein the processing element is further configured to: controlling the first ramp generator to generate the first ramp signal starting from the first value and increasing to the third value when the power converter operates in a boost mode of operation; and When the power converter operates in the boost operating mode, the second ramp generator is controlled to generate the second ramp signal starting from the fourth value and decreasing to a seventh value.

5. The circuit of claim 1 , wherein the first value is 0, wherein the second value is greater than an input voltage Vin divided by a scaling constant K, wherein the third value is less than Vin / K, wherein the fourth value is Vin / K+output voltage Vout divided by K, wherein the fifth value is greater than Vin / K, and wherein the sixth value is less than Vin / K.

6. The circuit of claim 1 , wherein the processing element is further configured to couple to the power converter and control a plurality of switches of the power converter according to the first ramp signal and the second ramp signal to switch an input voltage Vin to a load via at least some of the plurality of switches of the power converter.

7. A method for a power converter, the method include: Controlling the power converter to operate in a buck mode of operation, comprising: controlling the step-down ramp generator to generate a step-down ramp signal having a value starting from 0 and increasing to an input voltage Vin divided by a scaling constant K, wherein the step-down ramp signal is reset to 0 once per clock cycle; and controlling a boost ramp generator to generate a boost ramp signal having a value starting from Vin / K+output voltage Vout divided by K and decreasing to X1*Vin / K, wherein the boost ramp signal is reset to Vin / K+Vout / K once per clock cycle; Controlling the power converter to operate in a buck-boost operation mode, comprising: controlling the step-down ramp generator to alternately generate the step-down ramp signal, the step-down ramp signal having a value starting from 0 and increasing to X3*Vin / K and having a value starting from 0 and increasing to X4*Vin / K; and controlling the boost ramp generator to alternately generate the boost ramp signal having a value starting from Vin / K+Vout / K and decreasing to X1*Vin / K+Vout / K and having a value starting from Vin / K+Vout / K and decreasing to X2*Vin / K+Vout / K; and Controlling the power converter to operate in a boost mode of operation, comprising: controlling the step-down ramp generator to generate the step-down ramp signal having a value starting from 0 and increasing to X4*Vin / K; and The boost ramp generator is controlled to generate the boost ramp signal having a value starting from Vin / K+Vout / K and decreasing to Vin / K. 8 . The method of claim 7 , wherein K is an arbitrary integer value, X1 is a value greater than 1, X2 is a value less than 1, X3 is a value greater than 1, and X4 is a value less than 1.

9. The method of claim 8, wherein K is 2, X1 is 1.2, X2 is 0.9, X3 is 1.1, and X4 is 0.

8.

10. The method of claim 7, wherein the buck operating mode comprises a plurality of buck cycles of the power converter, wherein the boost operating mode comprises a plurality of boost cycles of the power converter, and wherein the buck-boost operating mode comprises a series of alternating buck cycles of the power converter and boost cycles of the power converter.

11. The method according to claim 10, further comprising: include: controlling the BUH_BOL signal to have a high value for a clock cycle following a buck cycle of the power converter in the buck operating mode and to have a low value for a clock cycle following a boost cycle of the power converter in the boost operating mode; controlling a BUBO signal to have a low value during the buck mode of operation and the boost mode of operation, and to have a high value during the buck-boost mode of operation; and The GAP_DETECT signal is controlled to have a high value when the internal control signal does not first cross the step-down ramp signal or the step-up ramp signal, and is controlled to have a low value when the internal control signal crosses the step-down ramp signal or the step-up ramp signal.

12. The method according to claim 11, further comprising: include: upon detecting a rising edge of GAP_DETECT during operation in the buck mode of operation or during a boost cycle of the power converter occurring while operating in the buck mode of operation, after operating in the buck mode of operation, controlling the power converter to operate in the buck-boost mode; and Upon detecting the rising edge of GAP_DETECT during operation in the boost mode of operation or during a step-down cycle of the power converter occurring while operating in the boost mode of operation, the power converter is controlled to operate in the buck-boost mode after operating in the boost mode of operation.

13. The method according to claim 11, further comprising: include: controlling the power converter to operate in the buck mode of operation after operating in the buck-boost mode of operation when two consecutive buck cycles of the power converter are detected; and When two consecutive boost cycles of the power converter are detected, the power converter is controlled to operate in the boost mode of operation after operating in the buck-boost mode of operation.

14. The method of claim 7, further comprising controlling a plurality of switches of the power converter according to the buck ramp signal and the boost ramp signal to switch Vin to a load via at least some of the plurality of switches of the power converter.

15. A circuit system, wherein include: a power converter comprising a plurality of transistors; and a controller coupled to the power converter and comprising: a first ramp generator; a second ramp generator; and a processing element configured to be coupled to the first ramp generator and the second ramp generator and configured to: controlling the first ramp generator to generate a first ramp signal starting from a first value and increasing to a second value during a first clock cycle when the power converter is operating in a buck-boost mode of operation, and to generate the first ramp signal starting from the first value and increasing to a third value during a second clock cycle immediately following the first clock cycle; and The second ramp generator is controlled when the power converter operates in the buck-boost operating mode to generate a second ramp signal starting from a fourth value and decreasing to a fifth value during the first clock cycle, and to generate the second ramp signal starting from the fourth value and decreasing to a sixth value during the second clock cycle.

16. The circuit system of claim 15, wherein the processing element is further configured to: controlling the first ramp generator to generate the first ramp signal starting from the first value and increasing to a seventh value when the power converter operates in a buck mode of operation; and When the power converter operates in the buck operating mode, the second ramp generator is controlled to generate the second ramp signal starting from the fourth value and decreasing to the fifth value.

17. The circuit system of claim 16, wherein the processing element is further configured to: controlling the BUH_BOL signal to have a high value after a step-down cycle of the power converter and to have a low value after a step-up cycle of the power converter; controlling a BUBO signal to have a low value during the buck mode of operation and during a boost mode of operation of the power converter; and When the internal control signal does not cross the first ramp signal or the second ramp signal during a low phase of the first clock cycle or the second clock cycle, the GAP_DETECT signal is controlled to have a high value, and when the internal control signal crosses the first ramp signal or the second ramp signal during the low phase of the first clock cycle or the second clock cycle, the GAP_DETECT signal is controlled to have a low value.

18. The circuit system of claim 15, wherein the processing element is further configured to: controlling the first ramp generator to generate the first ramp signal starting from the first value and increasing to the third value when the power converter operates in a boost mode of operation; and When the power converter operates in the boost operating mode, the second ramp generator is controlled to generate the second ramp signal starting from the fourth value and decreasing to a seventh value.

19. The circuit system of claim 18, wherein the seventh value is an input voltage Vin divided by a proportionality constant K.

20. The circuit system of claim 15, wherein the first value is 0, wherein the second value is greater than the input voltage Vin divided by a scaling constant K, wherein the third value is less than Vin / K, wherein the fourth value is Vin / K+output voltage Vout divided by K, wherein the fifth value is greater than Vin / K, and wherein the sixth value is less than Vin / K.

21. The circuit system of claim 15, wherein the processing element is further configured to couple to the power converter and control a plurality of switches of the power converter according to the first ramp signal and the second ramp signal to switch an input voltage Vin to a load via at least some of the plurality of switches of the power converter.

22. A circuit, wherein include: a first ramp generator; a second ramp generator; and a processing element configured to be coupled to the first ramp generator and the second ramp generator and configured to: controlling the first ramp generator to generate a first ramp signal starting from a first value and increasing to a second value when the power converter operates in a first operation mode, the first ramp signal being reset to the first value once per clock cycle; controlling the second ramp generator to generate a second ramp signal starting from a third value and decreasing to a fourth value when the power converter operates in the first operation mode, the second ramp signal being reset to the third value once per clock cycle; controlling the first ramp generator to generate the first ramp signal starting from the first value and increasing to a fifth value during a first clock cycle when the power converter is operating in a buck-boost mode of operation, and to generate the first ramp signal starting from the first value and increasing to a sixth value during a second clock cycle immediately following the first clock cycle; and The second ramp generator is controlled when the power converter operates in the buck-boost operating mode to generate the second ramp signal starting from the third value and decreasing to the fourth value during the first clock cycle, and to generate the second ramp signal starting from the third value and decreasing to a seventh value during the second clock cycle.

23. The circuit of claim 22, wherein the first operating mode is a buck operating mode, wherein the first ramp is a buck ramp, wherein the second ramp is a boost ramp, wherein the first value is 0, wherein the second value is an input voltage Vin divided by a scaling constant K, wherein the third value is Vin / K+output voltage Vout divided by K, and wherein the fourth value is greater than Vin / K.

24. The circuit of claim 22, wherein the first operating mode is a boost operating mode, wherein the first ramp is a buck ramp, wherein the second ramp is a boost ramp, wherein the first value is 0, wherein the second value is less than an input voltage Vin divided by a scaling constant K, wherein the third value is Vin / K+output voltage Vout divided by K, and wherein the fourth value is Vin / K.

25. The circuit of claim 22, wherein the first ramp is a step-down ramp, wherein the second ramp is a step-up ramp, wherein the fifth value is greater than an input voltage Vin divided by a proportionality constant K, wherein the sixth value is less than Vin / K, and wherein the seventh value is less than Vin / K.

26. A circuit, wherein include: A processing element configured to: implementing a state machine for controlling a buck-boost power converter; monitoring an internal control signal to determine whether the internal control signal crosses a step-down ramp signal or a step-up ramp signal during a clock cycle; and transitioning to a buck-boost state of the state machine when the internal control signal does not cross the buck ramp signal or the boost ramp signal during the clock cycle, wherein the processing element, in the buck-boost state of the state machine, is configured to: controlling the first ramp generator to generate the step-down ramp signal starting from a first value and increasing to a second value during a second clock cycle, and to generate the first ramp signal starting from the first value and increasing to a third value during a third clock cycle immediately following the second clock cycle; and The second ramp generator is controlled to generate the boost ramp signal starting from a fourth value and decreasing to a fifth value during the second clock cycle, and to generate the second ramp signal starting from the fourth value and decreasing to a sixth value during the third clock cycle.

27. The circuit of claim 26, wherein the first value is 0, wherein the second value is greater than the input voltage Vin divided by a scaling constant K, wherein the third value is less than Vin / K, wherein the fourth value is Vin / K+output voltage Vout divided by K, wherein the fifth value is greater than Vin / K, and wherein the sixth value is less than Vin / K.

28. The circuit of claim 26, wherein the processing element is further configured to couple to the buck-boost power converter and control a plurality of switches of the buck-boost power converter according to the buck ramp signal and the boost ramp signal to switch an input voltage Vin to a load via at least some of the plurality of switches of the buck-boost power converter.

Images