Storage device and operating method thereof, and operating method of storage system host

Abstract

The present disclosure relates to a storage device based on key-value storage data, an operating method thereof, a storage system, and an operating method of a host. The storage device generates and stores a key stream and a value stream by extracting a plurality of keys and a plurality of values respectively corresponding to the plurality of keys from data. The storage device includes a controller and a non-volatile memory. The controller receives information about an invalid key included in the key stream and a compression command from a host, and performs a compression operation on the key stream in response to the compression command. The non-volatile memory stores the key stream and the value stream. The controller merges the key stream with other key streams based on the information about the invalid key in the compression operation.

Description

TECHNICAL FIELD

[0001] The inventive concept(s) described herein relate to a storage device and an operating method thereof. More particularly, the inventive concept(s) described herein relate to a storage device that stores data based on a key value and an operating method thereof. BACKGROUND

[0002] Recently, various types of electronic devices have been developed for use. Some electronic devices are capable of storing data and operating based on the stored data. To this end, the electronic devices can include a storage device or a storage system for storing data. The electronic devices can also or instead read data or otherwise operate while communicating with an external storage device or storage system.

[0003] Storage devices can be classified in various ways. As an example of classification of storage devices, storage devices can be classified as non-volatile memory-based storage or volatile memory-based storage. Non-volatile memory-based storage can not lose data even when power is not supplied. On the other hand, data stored in volatile memory-based storage can be lost when power is interrupted, but volatile memory-based storage can operate faster than non-volatile memory-based storage.

[0004] As another example of classification of storage devices, storage devices can be classified as block storage, file storage, or object storage. Block storage manages data based on physical locations, and file storage manages data based on logical sequences. On the other hand, object storage can manage data based on unique identifiers. Block storage and file storage are useful when the amount of text data is large, and object storage is an effective choice when the amount of atypical data such as sound data and video data is large. One example of object storage is key value storage that stores data based on key values. SUMMARY

[0005] The inventive concept(s) described herein include a storage device that performs a compression operation on a key stream based on information about invalid keys, and a storage system including the same.

[0006] According to an aspect of the inventive concept(s) described herein, a storage device includes a controller and a non-volatile memory. The storage device generates and stores a key stream and a value stream by extracting a plurality of keys and a plurality of values respectively corresponding to the plurality of keys from data. The controller receives information about invalid keys included in the key stream and a compression command from a host, and performs a compression operation on the key stream in response to the compression command. The non-volatile memory stores the key stream and the value stream. The controller merges the key stream with other key streams based on the information about the invalid keys in the compression operation.

[0007] According to another aspect of the inventive concept(s) described herein, a storage device stores a key stream and a value stream generated by extracting a plurality of keys and a plurality of values respectively corresponding to the plurality of keys from data. An operation method of the storage device includes receiving a compression command and information about invalid keys included in the key stream from a host, performing a compression operation by merging the key stream with other key streams based on the information about the invalid keys, and storing the merged key stream in a non-volatile memory.

[0008] According to another aspect of the inventive concept(s) described herein, a storage system stores a key stream and a value stream generated by extracting a plurality of keys and a plurality of values respectively corresponding to the plurality of keys from data. The storage system includes a host and a storage device. The host is configured to transmit a compression command for the key stream and information about invalid keys included in the key stream. The storage device is configured to receive the compression command, perform a compression operation by merging the key stream with other key streams based on the information about the invalid keys, and store the merged key stream. BRIEF DESCRIPTION OF DRAWINGS

[0009] Embodiments of the present disclosure will become more fully understood from the detailed description and accompanying drawings, wherein:

[0010] Figure 1 is a block diagram illustrating a storage system according to an embodiment;

[0011] Figure 2 is a block diagram illustrating a storage device according to an embodiment;

[0012] Figure 3 is a block diagram illustrating a storage device according to an embodiment;

[0013] Figure 4 is a flowchart illustrating an operation method of a storage device according to an embodiment;

[0014] Figure 5 is a circuit diagram illustrating a memory block included in a memory cell array according to an embodiment;

[0015] Figure 6 is a perspective view illustrating a memory block in Figure 5 ; ;

[0016] Figure 7 is a conceptual diagram illustrating an operation of a key-value manager according to an embodiment;

[0017] Figure 8 is a conceptual diagram illustrating an operation of a key-value manager according to an embodiment;

[0018] Figure 9 is a flowchart for explaining an operation method of a key-value manager according to an embodiment;

[0019] Figure 10 is a diagram illustrating a key table according to an embodiment;

[0020] Figure 11 is a flowchart for explaining an operation method of a key-value manager according to an embodiment;

[0021] Figure 12A is a diagram illustrating a block according to an embodiment;

[0022] Figure 12B is a diagram illustrating a multi-label table according to an embodiment;

[0023] Figure 13 is a flowchart illustrating an operation method of a storage device according to an embodiment;

[0024] Figure 14 is a diagram illustrating an operation of a storage system over time according to an embodiment;

[0025] Figure 15 is a diagram illustrating an operation of a storage system over time according to an embodiment;

[0026] Figure 16A is a block diagram illustrating a storage system according to an embodiment;

[0027] Figure 16B is a block diagram illustrating a storage system according to an embodiment;

[0028] Figure 17 is a block diagram illustrating a storage device according to an embodiment;

[0029] Figure 18 is a block diagram illustrating a storage device according to an embodiment;

[0030] Figure 19 is a block diagram illustrating a storage device according to an embodiment;

[0031] Figure 20 is a block diagram illustrating a storage system according to an embodiment;

[0032] Figure 21 is a block diagram illustrating an electronic device according to an embodiment;

[0033] Figure 22 is a diagram illustrating a mobile system to which a memory device according to an embodiment is applied; and

[0034] Figure 23 is a diagram illustrating a mobile hub to which a memory device according to an embodiment is applied. DETAILED DESCRIPTION

[0035] Figure 1 is a block diagram illustrating a storage system 10 according to an embodiment.

[0036] Referring to Figure 1 , the storage system 10 can include a storage device 100 and a host 200, and the storage device 100 can include a controller 110, a data buffer 130, and an NVM (non-volatile memory) 140. The host 200 can communicate with the storage device 100 via various interfaces. For example, the host 200 can be implemented as, by, or using an application processor (AP) or a system on chip (SoC). The controller 110 can include a memory storing instructions, and a processor executing the instructions to implement some or all aspects of processes implemented by or using the controller 110.

[0037] In some embodiments described herein, the storage device 100 can be an object storage device including a key-value storage device or store (e.g., a key-value solid state drive (SSD)). The key-value storage device is a device that quickly and simply processes data by using a key-value pair. In this case, the "key-value pair" can be one pair consisting of a unique key and a value that is data corresponding to the key, and can be referred to as a "tuple" or a "key-value tuple." The unique key can uniquely identify or otherwise correspond to the value. Also, the key-value pair can refer to a data storage paradigm designed for management of storage and retrieval of related arrays, which are data structures called dictionaries and hashes. In the key-value pair, the key can be represented by an arbitrary string such as a file name, a uniform resource identifier (URI), a field, or a hash, and the value can be any kind of data such as an image, a user preferred file, and a document. In this case, the size of the key and the value can vary. For example, the size of the value can vary according to data included in the value. As used herein, the term "key-value pair" can refer to a single pair of a key KEY and a value VALUE, or each of a plurality of pairs of a key KEY and a value VALUE.

[0038] Hereinafter, the description of the storage device 100 mainly includes embodiments in which the storage device 100 is a key-value storage device. In these embodiments, the storage device 100 can be substantially synonymous with a key-value storage device or a key-value store. However, the storage device 100 is not limited to a key-value storage device or a key-value store. The storage device 100 can be or include any object cache system or any object storage system that manages data in units of objects. Accordingly, the storage device 100 can manage data in units of objects by using a method other than a key-value pair.

[0039] The host 200 can transmit a key-value command CMD_KV (e.g., a write request command or a put command) including a key-value pair of a key KEY - value VALUE to the storage device 100 for writing data. The key-value pair included in the key-value command CMD_KV can include a plurality of keys KEY and a plurality of values VALUE corresponding to the plurality of keys KEY. The storage device 100 can write the value VALUE to the NVM 140 in response to the key-value command CMD_KV. In an embodiment, the host 200 can transmit a key-value command CMD_KV (e.g., a read request command or a get command) including a key KEY to the storage device 100. The storage device 100 can read a value VALUE corresponding to the key KEY from the NVM 140 in response to the key-value command CMD_KV.

[0040] The host 200 can transmit a compression command CMP_CP for performing a compression operation on the key-value pair to the storage device 100. The storage device 100 can perform a compression operation on a plurality of keys KEY stored in the NVM 140 in response to the compression command CMP_CP. In this specification, the compression operation can refer to an operation of generating a key stream by using only valid keys KEY among the plurality of keys KEY stored in the NVM 140 without using one or more of invalid keys KEY among them. The compression operation can result in generating a key stream having overall fewer keys KEY than otherwise by causing invalid keys KEY among the plurality of keys KEY stored in the NVM 140 not to be included in the generated key stream.

[0041] According to an aspect of the inventive concept(s) described herein, the host 200 can transmit information Info_IK about invalid keys to the storage device 100 together with the compression command CMP_CP. The storage device 100 can perform the compression operation based on the information Info_IK about invalid keys.

[0042] The controller 110 can write a value VALUE to the NVM 140 in response to a write request from the host 200. Alternatively, the controller 110 can control the NVM 140 so that a value VALUE stored in the NVM 140 is read in response to a read request from the host 200.

[0043] The controller 110 can include a key-value manager 120. The key-value manager 120 can receive a key-value pair included in the key-value command CMD_KV, and separate a key KEY and a value VALUE from the key-value pair. The key-value pair included in the key-value command CMD_KV can include a plurality of keys KEY and a plurality of values VALUE corresponding to the plurality of keys KEY. The key-value manager 120 can extract the plurality of keys KEY included in the key-value pair, and store the plurality of keys KEY in the data buffer 130. The key-value manager 120 can extract the plurality of values VALUE included in the key-value pair, and store the plurality of values VALUE in the data buffer 130.

[0044] When a certain number of data, such as a predetermined threshold number of data, or a certain amount of data, such as a predetermined threshold amount of data, of the plurality of keys KEY are stored in the data buffer 130, the key-value manager 120 can store the stored plurality of keys KEY as a key stream in the NVM 140. When a certain number of data, such as a predetermined threshold number of data, or a certain amount of data, such as a predetermined threshold amount of data, of the plurality of values VALUE are stored in the data buffer 130, the key-value manager 120 can store the stored plurality of values VALUE as a value stream. In an embodiment, each of the value stream and the key stream can be stored in different areas of the NVM 140 from each other.

[0045] In addition, the key-value manager 120 can read the plurality of key streams from the NVM 140 in response to the compression command CMP_CP, delete one or more invalid keys KEY among the plurality of key streams, and perform a compression operation of generating a new key stream by using valid keys KEY. According to an embodiment, the key-value manager 120 can determine which key KEY of the plurality of key streams is valid based on information Info_IK about invalid keys received from the host 200. The key-value manager 120 can generate a new key stream by merging only valid keys KEY of the plurality of key streams.

[0046] In an embodiment, the information Info_IK about invalid keys can include index information corresponding to the invalid keys KEY. In another embodiment, the information Info_IK about invalid keys can include address information in the NVM 140 in which the invalid keys KEY are stored.

[0047] In this specification, although an example in which the key-value manager 120 receives information Info_IK about invalid keys from the host 200 and performs a compression operation by using the received information is shown, this is only one embodiment. In another embodiment, the key-value manager 120 can receive information about valid keys KEY from the host 200, and perform a compression operation by using the received information about valid keys.

[0048] The data buffer 130 can include at least one memory element for storing the key KEY and the value VALUE. In an example, the data buffer 130 can include a volatile memory element such as a dynamic random access memory (RAM) (DRAM) and a static RAM (SRAM).

[0049] The NVM 140 can include a memory cell array MCA, and the memory cell array MCA can include memory blocks (BLK1 to BLKz). The first memory block BLK1 can include a plurality of pages (PG1 to PGk). In this case, z and k can each be a positive integer, and various changes can be made according to embodiments. For example, the memory block can be a unit of erasing, and the page can be a unit of writing and reading. In some embodiments, the memory cell array MCA can include a plurality of planes, a plurality of dies, or a plurality of chips. In an embodiment, the NVM 140 can include a flash memory device, for example, a NAND flash memory device. However, the inventive concept(s) described herein are not limited thereto, and the NVM 140 can include resistive memory devices such as resistive RAM (rRAM), phase change RAM (PRAM), and magnetic RAM (MRAM).

[0050] In an embodiment, the key stream generated by using the key KEY and the value stream generated by using the value VALUE can be stored in different memory blocks (BLK1 to BLKz), or different pages (PG1 to PGk) of one same memory block (e.g., the first block BLK1).

[0051] The storage system 10 can be implemented as, by, with, or in, for example, a personal computer (PC), a data server, a network-attached storage device, an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device can include a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital camcorder, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an electronic book, a wearable device, etc.

[0052] In some embodiments, the storage device 100 can include or can be an internal memory embedded in an electronic device. For example, the storage device 100 can include or can be an embedded Universal Flash Storage (UFS) memory device or an embedded Multi Media Card (eMMC). In some embodiments, the storage device 100 can include or can be an external memory removable from the electronic device. For example, the storage device 100 can include or can be a UFS memory card, a Compact Flash (CF) memory card, a Secure Digital (SD) card, a microSD card, a miniSD card, an extreme Digital (xD) card, or a memory stick.

[0053] Figure 2 is a block diagram illustrating a storage device 100 according to an embodiment. Figure 2 An operation method in a case when the storage device 100 receives a key-value command CMD_KV for storing a key KEY and a value VALUE is illustrated.

[0054] Reference Figure 2 The storage device 100 can include a key-value manager 120, a data buffer 130, and an NVM 140. The key-value manager 120 can include a key-value extractor 121 and a compression module 122. The key-value extractor 121 and the compression module 122 can be implemented, for example, using separate software algorithms executed by a processor such as a microprocessor. The key-value extractor 121 can extract the key KEY and the value VALUE included in the key-value command CMD_KV. The key-value extractor 121 can store the extracted key KEY in a key buffer 131 of the data buffer 130 and store the extracted value VALUE in a value buffer 132 of the data buffer 130. In an embodiment, the key buffer 131 and the value buffer 132 can be configured with separate memory elements, such as physically separate memory elements. In another embodiment, the key buffer 131 and the value buffer 132 can be configured as different regions in the data buffer 130, such as physically separate regions.

[0055] In an embodiment, the key-value extractor 121 can manage a physical address of the key KEY stored in the key buffer 131 by using a mapping table. For example, the mapping table can be generated as a hash table storing a hash key corresponding to the key KEY as a mapping index of the key KEY.

[0056] When the amount of keys KEY stored in the key buffer 131 is equal to or greater than a certain amount of data, such as a data amount of a predetermined threshold, the key-value extractor 121 can generate a key stream ST_KEY based on the plurality of keys KEY. In an embodiment, the key-value extractor 121 can generate the key stream ST_KEY by sequentially arranging the plurality of keys KEY. In another embodiment, the key-value extractor 121 can generate the key stream ST_KEY by combining the plurality of keys KEY with indexes respectively corresponding to values VALUE of the plurality of keys KEY. That is, in the latter embodiment, for each key-value pair, each key KEY can be combined with an index corresponding to the value VALUE, such that the plurality of keys KEY collectively are combined with the indexes corresponding to the values VALUE to generate the key stream ST_KEY. The key-value extractor 121 can store the generated key stream ST_KEY in the first area AR1 of the NVM 140.

[0057] In an embodiment, the key-value extractor 121 can manage the physical address of the first area AR1 of the stored key stream ST_KEY by using a key table. In an embodiment, the key table can be generated as a hash table storing a hash key corresponding to each key KEY of the key stream ST_KEY as a mapping index of the key KEY.

[0058] When the amount of values VALUE stored in the value buffer 132 is equal to or greater than a certain amount of data, such as a data amount of a predetermined threshold, the key-value extractor 121 can generate a value stream ST_VAL based on the plurality of values VALUE. For example, the key-value extractor 121 can generate the value stream ST_VAL by sequentially arranging the plurality of values VALUE. The key-value extractor 121 can store the generated value stream ST_VAL in the second area AR2 of the NVM 140. In an embodiment, the key-value extractor 121 can manage the physical address of the second area AR2 of the stored value stream ST_VALUE by using a value table.

[0059] Figure 3 is a block diagram illustrating a storage device according to an embodiment. Figure 3 An operation method in a case where the storage device 100 receives a compression command CMD_CP for a compression operation is illustrated. The previously described Figure 2 description given with reference to

[0060] Reference Figure 3 , the storage device 100 can include a key-value manager 120, a data buffer 130, and an NVM 140. The key-value manager 120 can include a key-value extractor 121 and a compression module 122.

[0061] The compression module 122 can perform a compression operation on a plurality of key streams including the first key stream ST_KEY1 and the second key stream ST_KEY2 stored in the NVM 140 in response to the compression command CMD_CP. For example, the compression operation can refer to an operation of compressing data in a data structure based on a long structured merge (LSM) tree. In the compression operation, invalid keys KEY can be deleted in the keys KEY in the first key stream ST_KEY1 and the second key stream ST_KEY2 read from the NVM 140.

[0062] The compression module 122 can read the first key stream ST_KEY1 and the second key stream ST_KEY2 from the NVM 140 and can determine invalid keys KEY in the first key stream ST_KEY1 and the second key stream ST_KEY2 based on information Info_IK about invalid keys received together with the compression command CMD_CP. In an example, the invalid keys KEY can include keys KEY corresponding to values VALUE for which a delete command has been received from the host 200. In some embodiments, the information Info_IK about invalid keys can include a plurality of notifications of invalid keys KEY, and thus based on the information Info_IK about invalid keys, a plurality of invalid keys KEY are removed in the first key stream ST_KEY1 and the second key stream ST_KEY2 read from the NVM 140.

[0063] The compression module 122 can generate a merged key stream ST_MK by merging only valid keys KEY included in the first key stream ST_KEY1 and the second key stream ST_KEY2. The compression module 122 can write the merged key stream ST_MK in the NVM 140.

[0064] When performing the compression operation, the storage device 100 can perform the compression operation by reading only the first key stream ST_KEY1 and the second key stream ST_KEY2 without reading values VALUE having a relatively large amount of data. Accordingly, the amount of data access to the NVM 140 can be reduced. In addition, according to embodiments of the present disclosure, the storage device 100 can reduce the time and operating memory required for the compression operation by performing the compression operation based on information Info_IK about invalid keys received from the host 200 without analyzing one or more tables (e.g., a key table KT or a value table) stored in the data buffer 130.

[0065] The compression module 122 can update the validity of the invalid key KEY targeted by the compression operation. In an embodiment, the compression module 122 can read the key table KT including information about the invalid key KEY from the data buffer 130, and can update the key table KT based on the information Info IK about the invalid key. The compression module 122 can store the updated key table KT_udt in the data buffer 130. Based on the compression operation, the invalid key KEY can be omitted from the updated key table KT_udt in the data buffer 130. In some embodiments, a plurality of invalid keys KEY can be deleted from the key table KT for one or more compression operations based on one or more instances of the information Info IK about the invalid key.

[0066] Figure 4 is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0067] Referring to Figure 3 and Figure 4 , the storage device 100 can receive a compression command CMD CP and information Info IK about an invalid key (S110). The storage device 100 can perform a compression operation based on the received information Info IK about the invalid key (S120). In an embodiment, the storage device 100 can determine a plurality of invalid keys KEY based on information about the invalid keys KEY among a plurality of keys KEY included in a first key stream ST KEY1 and a second key stream ST KEY2 stored in the NVM 140. The storage device 100 can generate a merged key stream ST MK by merging only valid keys KEY from the first key stream ST KEY1 and the second key stream ST KEY2, and excluding one or more invalid keys KEY based on the information Info IK about the invalid key.

[0068] The storage device 100 can store the merged key stream ST MK generated by the compression operation in the NVM 140 (S130). In an embodiment, the storage device 100 can delete the first key stream ST KEY1 and the second key stream ST KEY2 targeted by the compression operation from the NVM 140 after storing the merged key stream ST MK. The merged key stream ST MK can include valid keys KEY without including one or more invalid keys KEY omitted based on one or more compression operations. The merged key stream ST MK can include data updated or corrected to reflect the information Info IK about the invalid key, compared to data of the first key stream ST KEY1 and the second key stream ST KEY1.

[0069] Figure 5 is a circuit diagram illustrating a memory block included in a memory cell array according to an embodiment.

[0070] refer to Figure 5 Memory cell array (e.g., Figure 1 The MCA in this context can be a vertical NAND flash memory cell array. The memory cell array can include multiple memory blocks. Each memory block BLK0 can include multiple NAND cell strings (NS11 to NS33), multiple word lines (WL1 to WL8), multiple bit lines (BL1 to BL3), multiple ground select lines (GSL1 to GSL3), multiple cell string select lines (SSL1 to SSL3), and a common source line CSL. In this case, the number of NAND cell strings, word lines WL, bit lines BL, ground select lines GSL, and cell string select lines SSL can vary depending on the embodiment.

[0071] NAND cell strings (NS11, NS21, and NS31) can be located between the first bit line BL1 and the common source line CSL. NAND cell strings (NS12, NS22, and NS32) can be located between the second bit line BL2 and the common source line CSL. NAND cell strings (NS13, NS23, and NS33) can be located between the third bit line BL3 and the common source line CSL. Each NAND cell string (e.g., NS11) may include a series-connected cell string selection transistor SST, multiple memory cells (MC1 to MC8), and a ground selection transistor GST.

[0072] Strings of cells connected to a single bit line can form a column. For example, strings of cells connected to the first bit line BL1 (NS11, NS21, and NS31) can correspond to the first column. Strings of cells connected to the second bit line BL2 (NS12, NS22, and NS32) can correspond to the second column. Strings of cells connected to the third bit line BL3 (NS13, NS23, and NS33) can correspond to the third column.

[0073] Strings connected to a single string select line can form a row. For example, strings (NS11, NS12, and NS13) connected to the first string select line SSL1 can correspond to the first row. Strings (NS21, NS22, and NS23) connected to the second string select line SSL2 can correspond to the second row. Strings (NS31, NS32, and NS33) connected to the third string select line SSL3 can correspond to the third row.

[0074] A cell string selection transistor SST can be connected to a corresponding cell string selection line (SSL1 to SSL3). A plurality of memory cells (MC1 to MC8) can be connected to a corresponding word line (WL1 to WL8), respectively. A ground selection transistor GST can be connected to a corresponding ground selection line (GSL1 to GSL3). A cell string selection transistor SST can be connected to a corresponding bit line (BL1 to BL3). A ground selection transistor GST can be connected to a common source line CSL.

[0075] Word lines at the same level (e.g., WL1) can be commonly connected to each other. Cell string selection lines (SSL1 to SSL3) are separated from each other. Ground selection lines (GSL1 to GSL3) are separated from each other in the memory block BLK0, although the ground selection lines (GSL1 to GSL3) can be commonly connected to each other outside the memory block BLK0. For example, when memory cells connected to the first word line WL1 and belonging to cell strings (NS11, NS12, and NS13) are programmed, the first word line WL1 and the first cell string selection line SSL1 can be selected.

[0076] The storage device 100 according to an embodiment of the disclosure can store a key KEY and a value VALUE in different regions of the memory cell array MCA. In an example, the key KEY can be stored in a first page connected to the first word line WL1 of the memory block BLK0. The value VALUE can be stored in a second page connected to the fourth word line WL4 of the memory block BLK0.

[0077] Figure 6 is a perspective view illustrating the memory block BLK0 in Figure 5 .

[0078] Referring to Figure 6 , each memory block included in the memory cell array (e.g., the MCA in Figure 1 ) can be formed in a vertical direction with respect to the substrate SUB. Figure 6 In , the memory block BLK0 is illustrated as including two selection lines (GSL and SSL), eight word lines (WL1 to WL8), and three bit lines (BL1 to BL3), although the number thereof can actually be more or less than these numbers.

[0079] The substrate SUB can be of a first conduction type (e.g., p-type). The common source lines CSL can extend in a first direction (e.g., Y direction) therein and can be of a second conduction type (e.g., n-type). The plurality of insulating layers IL can be sequentially arranged in a third direction (e.g., Z direction). The plurality of insulating layers are arranged in a region of the substrate SUB between two adjacent common source lines CSL in a second direction (e.g., X direction) and respectively extend in the first direction. The plurality of insulating layers IL can be spaced apart from each other by a same distance or at least a minimum predetermined threshold distance in the third direction. For example, the plurality of insulating layers IL can include an insulating material such as silicon oxide.

[0080] The plurality of pillars P can be sequentially arranged in a region of the substrate SUB in the second direction. The plurality of pillars P respectively extend in the third direction and are arranged between two adjacent common source lines CSL in the second direction. The plurality of pillars P penetrate the plurality of insulating films IL in the third direction. For example, the plurality of pillars P can contact the substrate SUB through the plurality of insulating layers IL. The surface layer S of each pillar P can include a silicon material of a first type and can function as a channel region. The inner layer I of each pillar P can include an insulating material such as silicon oxide or an air gap.

[0081] A charge storage layer CS can be provided along the exposed surfaces of the insulating layers IL, the pillars P, and the substrate SUB in a region between two adjacent common source lines CSL. The charge storage layer CS can include a gate insulating layer (which can be alternatively referred to as a tunnel insulating layer), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS can have an oxide-nitride-oxide (ONO) structure. In addition, the gate electrode GE can include the selection lines GSL and SSL and the word lines (WL1 to WL8) and can be provided in the region between two adjacent common source lines CSL on the exposed surfaces of the charge storage layer CS.

[0082] A drain or drain contact DR can be provided on each of the plurality of pillars P. For example, the drain or drain contact DR can include a silicon material doped with impurities of the second conduction type. Bit lines (BL1 to BL3) extending in the second direction can be provided on the drains DR. The bit lines (BL1 to BL3) are spaced apart from each other by a same distance or at least a minimum predetermined threshold distance in the first direction.

[0083] Figure 7 FIG. 1 is a conceptual diagram illustrating an operation of a key-value manager 120 according to an embodiment. Figure 7 An operation in which the key-value manager 120 generates a key stream ST_KEY and a value stream ST_VAL based on a key-value command CMD_KV is illustrated.

[0084] Reference Figure 2 and Figure 7The key-value manager 120 can receive a key-value pair KVP and separate a key KEY included in the key-value pair KVP from a value VALUE. The key-value manager 120 can combine an index Idx corresponding to the value VALUE with the key KEY, and store the key KEY combined with the index Idx in the data buffer 130. Also, the key-value manager 120 can generate a key stream ST_KEY by merging a plurality of keys KEY each combined with a corresponding index Idx of a corresponding value VALUE. The key-value manager 120 can store the generated key stream ST_KEY in a first area AR1 of the NVM 140.

[0085] In Figure 7 , one key stream ST_KEY is shown as corresponding to one index Idx, but this is for ease of description. The key stream ST_KEY according to an embodiment of the disclosure can include a plurality of index-key pairs in which an index Idx is combined one-to-one with a corresponding key KEY.

[0086] The key-value manager 120 can generate a key table KT by using a physical page number (PPN) in which the key stream ST_KEY is stored in the NVM 140. In other words, the key table KT can store the key stream ST_KEY, a physical address of the NVM 140 in which the key stream ST_KEY is stored, and one or more indexes Idx corresponding to the key stream ST_KEY. In an embodiment, the key table KT can further include a validity bit indicating whether the key stream ST_KEY is valid.

[0087] The key-value manager 120 can store the value VALUE separated from the key-value pair KVP in the data buffer 130, generate a value stream ST_VAL by merging a plurality of values VALUE stored in the data buffer 130, and store the generated value stream ST_VAL in the NVM 140.

[0088] The key-value manager 120 can generate a value table VT by using a PPN in which the value stream ST_VAL is stored in the NVM 140. In other words, the value table VT can store the value stream ST_VAL and a physical address of the NVM 140 in which the value stream ST_VAL is stored. In an embodiment, the value table VT can further include a validity bit indicating whether the value VALUE is valid.

[0089] Figure 8 is a conceptual diagram showing an operation of the key-value manager 120 according to an embodiment. Figure 8 A diagram showing that the key-value manager 120 performs a compression operation is shown.

[0090] Referring to Figure 3 and Figure 8, the key-value manager 120 can perform an operation including reading an invalid key stream ST_IK from the first area AR1 of the NVM 140. The invalid key stream ST_IK can represent a key stream including an invalid key KEY. In an embodiment, the key-value manager 120 can receive information Info_IK about an invalid key from the host (200) in the main memory 110. Figure 1

[0091] In an example, the information Info_IK about an invalid key can include index information Idx_IK corresponding to the invalid key. The key-value manager 120 can determine the invalid key KEY from the key table KT by using the index information Idx_IK corresponding to the invalid key.

[0092] The key-value manager 120 can generate at least one merged key stream ST_MK by merging the read invalid key stream ST_IK. In an example, the key-value manager 120 can generate the merged key stream ST_MK by deleting the invalid key KEY based on the information Info_IK about the invalid key and extracting only valid keys. Accordingly, the merged key stream ST_MK can include a key stream ST_KEY including only valid keys KEY.

[0093] The key-value manager 120 can write the merged key stream ST_MK in the first area AR1 of the NVM 140. In addition, the key-value manager 120 can delete the invalid key stream ST_IK after writing the merged key stream ST_MK, and update the validity bit corresponding to the invalid key stream ST_IK in the key table KT to an updated validity bit.

[0094] The key-value manager 120 can update the value table VT by using the invalid value VALUE corresponding to the invalid key KEY. In an embodiment, the key-value manager 120 can update the value table VT by converting the validity bit corresponding to the invalid value VALUE of the value table VT to an updated validity bit representing that the corresponding value VALUE is invalid.

[0095] In an embodiment, the key-value manager 120 can perform a garbage collection operation on the invalid value VALUE based on the validity bit of the value table VT. When the garbage collection operation is performed based on the value table VT, the invalid value VALUE can be deleted from the second area AR2.

[0096] The key-value manager 120 according to an embodiment of the disclosure can minimize an operation for determining an invalid key KEY by using information Info_IK about an invalid key received from the host when a compression operation is performed. Accordingly, a data input / output speed required for the compression operation can be increased.

[0097] ​Figure 9 is a flowchart illustrating an operation method of the key-value manager 120 according to an embodiment. Figure 9 An operation method in which the key-value manager 120 performs a compression operation is illustrated.

[0098] Referring to Figure 3 and Figure 9 , the key-value manager 120 can read a plurality of key streams ST_KEY from the NVM 140 (S210). In an embodiment, the read plurality of key streams ST_KEY can include at least one invalid key KEY. The key-value manager 120 can generate a new key stream ST_KEY by merging the plurality of key streams ST_KEY based on information Info_IK about the invalid key (S220). In an example, the key-value manager 120 can receive index information Info_IK corresponding to the invalid key from the host 200 as index information Idx_IK corresponding to the invalid key. The key-value manager 120 can determine the invalid key KEY based on the index information Idx_IK corresponding to the invalid key. In addition, the key-value manager 120 can generate a merged key stream ST_MK by removing the invalid key KEY included in the plurality of key streams ST_KEY and merging only valid keys KEY.

[0099] The key-value manager 120 can store the merged key stream ST_MK in the NVM 140 (S230). After storing the merged key stream ST_MK, the key-value manager 120 can delete the invalid key stream ST_KEY from the NVM 140 (S240). In an embodiment, the key-value manager 120 can update the key table KT so that the validity bit corresponding to the invalid key stream ST_IK indicates invalidity. In addition, the key-value manager 120 can update the value table VT by using the value VALUE corresponding to the invalid key KEY.

[0100] Figure 10 is a diagram illustrating a key table KT according to an embodiment.

[0101] Referring to Figure 3 and Figure 10 , the key table KT can include a key KEY, an index Idx, a physical address ADDR (e.g., PPN1, PPN2, PPN3, or PPN4) in which the key KEY is stored, and a validity bit Vld. In an example, a first key KEY1 can be given "1" as the index Idx and can be stored at a first physical address PPN1 of the NVM 140. In addition, when a value VALUE corresponding to the first key KEY1 is determined to be valid, the first key KEY1 can have "1" as the validity bit Vld.

[0102] The second key KEY2 can be assigned "2" as the index Idx, and can be stored at a second physical address PPN2 of the NVM 140. Also, when the value VALUE corresponding to the second key KEY2 is determined to be valid, the second key KEY2 can have "1" as the validity bit Vld.

[0103] The third key KEY3 can be assigned "3" as the index Idx, and can be stored at a third physical address PPN3 of the NVM 140. Also, when the value VALUE corresponding to the third key KEY3 is determined to be invalid, the third key KEY3 can have "0" as the validity bit Vld.

[0104] The fourth key KEY4 can be assigned "4" as the index Idx, and can be stored at a fourth physical address PPN4 of the NVM 140. Also, when the value VALUE corresponding to the fourth key KEY4 is determined to be valid, the fourth key KEY4 can have "1" as the validity bit Vld.

[0105] In an example, the key-value manager 120 can receive the compression command CMP_CP from the host 200 and receive "2" as the index information Idx_IK corresponding to the invalid key. The key-value manager 120 can update the validity bit Vld corresponding to the second key KEY2 having "2" as the index Idx to "0". The key-value manager 120 can perform a compression operation to delete the second key KEY2 and the third key KEY3.

[0106] Figure 11 is a flowchart for explaining an operation method of the key-value manager 120 according to an embodiment.

[0107] Referring to Figure 3 and 11 The key-value manager 120 can receive the index information Idx_IK corresponding to the invalid key from the host 200 (S310). The key-value manager 120 can update the key table KT based on the received index information Idx_IK corresponding to the invalid key (S320). In an example, the key-value manager 120 can update the validity bit Vld corresponding to the invalid key KEY to the updated validity bit Vld indicating that the key KEY is the invalid key KEY based on the index information Idx_IK corresponding to the invalid key.

[0108] The key-value manager 120 can perform a compression operation based on the updated key table KT_udt (S330). In an example, the key-value manager 120 can generate a merged key stream ST_MK by merging valid keys KEY and excluding invalid keys KEY based on the validity bits Vld included in the updated key table KT_udt. The key-value manager 120 can store the merged key stream ST_MK in the NVM 140.

[0109] Figure 12A is a diagram illustrating a block BLK according to an embodiment. Figure 12B is a diagram illustrating a multi-map table MMT according to an embodiment. In an example, Figure 12B The multi-map table MMT of Figures 1-11 may represent the key table KT or the value table VT described above with reference to

[0110] With reference to Figure 12A , the block BLK can include a plurality of memory units each having a different PPN (represented by a square in Figure 12A ). The plurality of memory units can store valid data VD or invalid data ID. In an embodiment, the valid data VD or the invalid data ID can include the key KEY or the value VALUE described above with reference to Figures 1-11 . Further, the valid data VD can represent a value VALUE for which a delete command has not been received from a host (200 in Figure 1 ) or a key KEY corresponding to the value VALUE for which the delete command has not been received from the host (200 in Figure 1 ). The invalid data ID can represent a value VALUE for which a delete command has been received from the host 200 or a key KEY corresponding to the value VALUE for which the delete command has been received.

[0111] The block BLK can store a plurality of pieces of data, and at least some of them can be written continuously. In an example of Figure 12A , three pieces of data can be written continuously to a first physical address PPN1, three pieces of data can be written continuously to a second physical address PPN2, three pieces of data can be written continuously to a third physical address PPN3, and three pieces of data can be written continuously to a fourth physical address PPN4.

[0112] With reference to Figure 12B , the key KEY or the value VALUE can be identified by using the multi-map table MMT. Figure 12AThe multi-map table MMT can include an address ADDR (e.g., a physical address PPN) in which the first data of the plurality of consecutive data is stored, and a first validity bit VD1, a second validity bit VD2, and a third validity bit VD3 indicating validity of the plurality of consecutive data stored in the address ADDR. In addition, the multi-map table MMT can include an index Idx corresponding to the plurality of data written. In an example, the first validity bit VD1, the second validity bit VD2, and the third validity bit VD3 can include "1" when data corresponding thereto is valid, and "0" when data corresponding thereto is invalid. In an embodiment, the key-value manager 120 can update the multi-map table MMT based on the information Info_IK about the invalid key received from the host 200.

[0113] Referring again to Figure 12A and Figure 12B Since the plurality of consecutive data stored in the first physical address PPN1 can include valid data VD, invalid data ID, and valid data VD in order, the multi-map table MMT can include "1", "0", and "1" as the first validity bit VD1, the second validity bit VD2, and the third validity bit VD3 corresponding to the first physical address PPN1, respectively. Since the plurality of consecutive data stored in the second physical address PPN2 are all valid data VD, the multi-map table MMT can include all "1" as the first validity bit VD1, the second validity bit VD2, and the third validity bit VD3 corresponding to the second physical address PPN2.

[0114] Since the plurality of consecutive data stored in the third physical address PPN3 are all invalid data ID, the multi-map table MMT can include all "0" as the first validity bit VD1, the second validity bit VD2, and the third validity bit VD3 corresponding to the third physical address PPN3. Since the plurality of consecutive data stored in the fourth physical address PPN4 can be valid data VD, valid data VD, and invalid data ID in order, the multi-map table MMT can include "1", "1", and "0" as the first validity bit VD1, the second validity bit VD2, and the third validity bit VD3 corresponding to the fourth physical address PPN4, respectively.

[0115] In an embodiment, the key-value manager 120 can include a multi-map table MMT in which a plurality of data written in the first memory 110 is stored. The multi-map table MMT can include an address ADDR (e.g., a physical address PPN) in which the first data of the plurality of consecutive data is stored, and a first validity bit VD1, a second validity bit VD2, and a third validity bit VD3 indicating validity of the plurality of consecutive data stored in the address ADDR. In addition, the multi-map table MMT can include an index Idx corresponding to the plurality of data written. In an example, the first validity bit VD1, the second validity bit VD2, and the third validity bit VD3 can include "1" when data corresponding thereto is valid, and "0" when data corresponding thereto is invalid. In an embodiment, the key-value manager 120 can update the multi-map table MMT based on the information Info_IK about the invalid key received from the host 200. Figure 2The key-value manager 120 can perform a compression operation by using the multi-map table MMT. In an example, the key-value manager 120 can update the multi-map table MMT based on the index information received from the host 200. When one or more keys stored in the contiguous address ADDR are invalid, the key-value manager 120 can perform a compression operation based on the updated multi-map table MMT. For example, when all the keys stored in the contiguous address ADDR are invalid, the key-value manager 120 can perform a compression operation based on the updated multi-map table MMT.

[0116] In an embodiment, the key-value manager 120 can perform a garbage collection operation by using the multi-map table MMT. In other words, the key-value manager 120 can determine which data (e.g., the key stream ST_KEY or the value stream ST_VAL) is valid by using the multi-map table MMT. The key-value manager 120 can ensure that the valid space of the NVM 140 is valid by performing a garbage collection operation on the valid data VD. Figure 2 Figure 20

[0117] Figure 13 is a flowchart illustrating an operation method of the storage device 100 according to an embodiment.

[0118] Referring to Figure 1 and Figure 13 , the storage device 100 can receive data capacity information about the value VALUE corresponding to the invalid key KEY from the host 200 (S410). In an example, the data capacity information about the value VALUE can correspond to a physical size occupied by the value VALUE in the NVM 140.

[0119] The storage device 100 can perform a garbage collection operation based on the received data capacity information (S420). The storage device 100 can perform a garbage collection operation for deleting the value VALUE based on the received data capacity information. The value VALUE deleted in the garbage collection operation corresponds to the key KEY that has been deleted in the compression operation and is deleted based on the received data capacity information.

[0120] Figure 14 is a graph illustrating an operation of the storage system 10 over time according to an embodiment. Figure 14 The graph illustrates an embodiment in which the storage system 10 receives a write command.

[0121] Referring to Figure 14 ​​The storage system 10 may include a host 200, a controller 110, and an NVM 140. The host 200 may output a first command CMD1 for writing a first key KEY1 and a first value VAL1 to the controller 110 (T110). The controller 110 may separate the first key KEY1 and the first value VAL1 from the first command CMD1 (T120).

[0122] Controller 110 can use data buffers that have been previously stored ( Figure 2 The controller 110 can generate the key stream ST_KEY by using the first key KEY1 and the second key KEY2 from the data buffer (130). Figure 1 The value stream ST_VAL (T130) is generated from the first value VAL1 and the second value VAL2 in (T130). In an embodiment, the controller 110 can generate a key stream ST_KEY. The controller 110 can first generate the key stream ST_KEY by combining the first index idx1 corresponding to the first value VAL1 with the first key KEY1 and combining the second index idx2 corresponding to the second value VAL2 with the second key KEY2. The controller 110 can then generate the key stream ST_KEY by combining the first key KEY1 and the first index idx1 and the second key KEY2 and the second index idx2.

[0123] The controller 110 can store the generated key stream ST_KEY and value stream ST_VAL in the NVM 140 (T140). The NVM 140 can store the first key KEY1 at the first physical address PPN1 and the second key KEY2 at the second physical address PPN2 (T150). Additionally, the NVM 140 can store the first value VAL1 at the third physical address PPN3 and the second value VAL2 at the fourth physical address PPN4 (T150). In this embodiment, the first physical address PPN1 and the second physical address PPN2 can be physically adjacent to each other, and the third physical address PPN3 and the fourth physical address PPN4 can also be physically adjacent to each other. Furthermore, the first physical address PPN1 and the second physical address PPN2 can be located in a different region than the third physical address PPN3 and the fourth physical address PPN4.

[0124] The controller 110 can update the key table KT (T160) by assigning the storage location of the first key KEY1 to the first physical address PPN1 in the key table KT and assigning the storage location of the second key KEY2 to the second physical address PPN2 in the key table KT.

[0125] The controller 110 can write the third physical address PPN3 into the value table VT such that the third address PPN3 corresponds to the first index idxl corresponding to the first value VALl. In addition, because the first value VALl and the second value VAL2 written at consecutive addresses are valid, the controller 110 can update the value table VT by writing a "1" as the validity bit corresponding thereto (T170).

[0126] Figure 15 is a graph illustrating the operation of the storage system 10 over time according to an embodiment. Figure 15 is a graph illustrating an embodiment in which the storage system 10 receives a compress command.

[0127] Referring to Figure 15 , the storage system 10 can include the host 200, the controller 110, and the NVM 140. The host 200 can output a second command CMD2 for a compress operation on a second key KEY2 and a second value VAL2 to the controller 110 (T210). In an embodiment, the host 200 can transmit a second index Idx2 corresponding to the second key KEY2 together with the second command CMD2 to the controller 110.

[0128] In response to the second command CMD2, the controller 110 can update a validity bit corresponding to the second key KEY2 as an updated validity bit in the key table KT. The validity bit corresponding to the second key KEY2 can be updated as "0" to indicate that the second key KEY2 is invalid (T220). Although not shown, the controller 110 can also update a second validity bit of the value table VT as an updated second validity bit in response to the second command CMD2. The second validity bit can indicate whether the second value VAL2 is valid. In addition, although not shown, the controller 110 can read the first key stream ST_KEY1 and the second key stream ST_KEY2 including the second key KEY2 corresponding to the second index Idx2 from the NVM 140 to perform the compress operation.

[0129] The controller 110 can generate a merged key stream ST_MK by removing at least one key KEY including the invalid second key KEY2 from the first key stream ST_KEY1 and the second key stream ST_KEY2 based on the received second index Idx2 and merging valid keys KEY (T230). In an example, the controller 110 can generate the merged key stream ST_MK by deleting the second key KEY2 corresponding to the second command CMD2 and using at least the first key KEY1 included in the first key stream ST_KEY1 and the third key KEY3 included in the second key stream ST_KEY2.

[0130] The controller 110 can store the merged key stream ST MK in the NVM 140 (T240), and the NVM 140 can store the merged key stream ST MK at the sixth physical address PPN6 (T250). Next, the controller 110 can delete the first key stream ST KEY1 and the second key stream ST KEY2 stored in the NVM 140 after storing the merged key stream ST MK (T260). The NVM 140 can delete the first key stream ST KEY1 and the second key stream ST KEY2 by performing an erase operation at the first physical address PPN1 at which the first key stream ST KEY1 is stored, at the second physical address PPN2 at which the second key stream ST KEY2 is stored, and at the fifth physical address PPN5 (T270).

[0131] According to an aspect of the inventive concept(s) described herein, the controller 110 can perform a compression operation by using information about the second index Idx2 received from the host 200. Accordingly, it can not be necessary to input / output data in / from the data buffer 130 in order to determine the valid key KEY, and the compression operation can be efficiently performed. Figure 1

[0132] Figure 16A FIG. 1 is a block diagram illustrating a storage system according to an embodiment. Figure 16A An embodiment of the storage device 100 that receives information Info VK about a valid key from the host 200 is illustrated. The description given previously with reference to FIG. 1 is omitted. Figures 1-15

[0133] Referring to Figure 16A , the storage system 10a can include the storage device 100 and the host 200, and the storage device 100 can include the controller 110, the data buffer 130, and the NVM 140. Unlike the embodiment described above with reference to FIG. 1, the storage device 100 can receive information Info VK about a valid key and a compression command CMD CP from the host 200. Figures 1-15

[0134] In an embodiment of the disclosure, the storage device 100 can perform a compression operation of merging only a valid key KEY among a plurality of key streams ST KEY based on information Info VK about the valid key. In an example, the information Info VK about the valid key can include index information about the valid key KEY and address information about the valid key KEY.

[0135] Figure 16B FIG. 1 is a block diagram illustrating a storage system according to an embodiment. Figure 16B ​​​An embodiment of the storage device 100 that receives information Info_IV about invalid values from the host 200 is shown. The previously described embodiments are omitted Figures 1-15 The description given above.

[0136] Referring to Figure 16B , the storage system 10b can include the storage device 100 and the host 200, and the storage device 100 can include the controller 110 and the NVM 140. Unlike the embodiments described above with reference to Figures 1-15 , the storage device 100 can receive information Info_IV about invalid values and a compression command CMD_CP from the host 200.

[0137] In an embodiment of the disclosure, the storage device 100 can determine an invalid key KEY based on the information Info_IV about invalid values and at least one table stored in the data buffer 130. The storage device 100 can perform a compression operation of merging only valid keys KEY among the plurality of key streams ST_KEY by using information about the determined invalid key. In an example, the information Info_IV about invalid values can include index information about an invalid value VALUE and address information about the invalid value VALUE.

[0138] Figure 17 is a block diagram showing a storage device 100a according to an embodiment.

[0139] Referring to Figure 17 , the storage device 100a can include a controller 110a, a VM 130a (volatile memory), and an NVM 140. In addition, the controller 110a can include a processor 111, a memory 112, a host interface (IF) 113, an NVM IF 114, a VM IF 115, an ECC (Error-Correcting Code) engine 116, and an AES (Advanced Encryption Standard) engine 117, which can communicate with each other via a bus 118.

[0140] The processor 111 can include a central processing unit (CPU), a microprocessor, etc., and can control the overall operation of the controller 110a. The processor 111 can execute software instructions stored in the memory 112 and retrieved from the memory 112 and / or received from the outside of the controller 110a. The memory 112 can operate under the control of the processor 111 and can serve as an operation memory, a buffer memory, a cache memory, etc. For example, the memory 112 can be implemented as a VM such as DRAM and SRAM, or an NVM such as PRAM and flash.

[0141] The key-value manager 120a can be implemented in firmware or software. The key-value manager 120a can be loaded onto the memory 112. In an embodiment, the key-value manager 120a can be implemented in a flash translation layer (FTL), and can be loaded onto the memory 112. However, the present embodiment is not limited thereto, and the key-value manager 120a can be implemented in hardware. The above-described operations can be performed by the processor 111 by using the key-value manager 120a. Figures 1-16B The above-described operations can be performed by the processor 111 by using the key-value manager 120a.

[0142] The host IF 113 can provide an IF between the host 200 and the controller 110a according to, for example, a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect (PCI) Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), or the like. In an embodiment of the disclosure, the information Info_IK about the invalid key and the compression command CMD_CP can be provided to the key-value manager 120a via the host IF 113.

[0143] The NVM IF 114 can provide an IF between the controller 110a and the NVM 140. For example, the key stream ST_KEY or the value stream ST_VAL can be transceived between the controller 110a and the NVM 140 via the NVM IF 114. The NVM IF 114 can be implemented to comply with a standard agreement such as Toggle or ONFI.

[0144] The VM IF 115 can provide an IF between the controller 110a and the VM 130a. For example, the key KEY, the value VALUE, and the mapping table MT can be transceived between the controller 110a and the VM 130a. The VM IF 115 can be implemented to comply with a standard agreement such as Toggle or ONFI.

[0145] The VM 130a can store the mapping table MT. For example, the VM 130a can further store the key KEY and the value VALUE, similar to the data buffer 130 in Figure 2 . To this end, the VM 130a can be implemented in DRAM. The mapping table MT can include any one of the multi-mapping table, the key table KT, and the value table VT described above with reference to Figures 1-16B

[0146] ​The ECC engine 116 can perform an error detection and correction function on read data read from the non-volatile memory 140. Specifically, the ECC engine 116 can generate parity bits for write data to be written to the non-volatile memory 140, and the parity bits generated as described above are stored together with the write data. When data is read from the non-volatile memory 140, the ECC engine 116 can correct errors in read data using the parity bits read from the non-volatile memory 140 together with the read data, and output the read data in which the errors are corrected. In one embodiment, the ECC engine 116 can include an ECC encoder (not shown) that generates parity bits for write data and / or an ECC decoder (not shown) that corrects errors in read data.

[0147] The AES engine 117 can perform at least one of an encryption operation and a decryption operation on data input to the controller 110a. In one embodiment, the AES engine 117 can perform at least one of the encryption operation and the decryption operation using a symmetric key algorithm. In one embodiment, the AES engine 117 can include an encryption module (not shown) that performs the encryption operation and / or a decryption module (not shown) that performs the decryption operation.

[0148] Each of the ECC engine 116 and the AES engine 117 can be implemented as firmware or software, and can be loaded into the memory 112. However, the present disclosure is not limited thereto, and each of the ECC engine 116 and the AES engine 117 can be implemented as hardware, or can be implemented as a combination of software and hardware.

[0149] According to an aspect of the inventive concept(s) described herein, the key-value manager 120a can perform various operations (e.g., a compression operation and a garbage collection operation) on key-value pairs without intervention of the host 200 or an operating system (OS). Accordingly, data processing speed can be improved.

[0150] Figure 18 is a block diagram illustrating a storage device according to an embodiment.

[0151] Referring to Figure 17 and Figure 18 , the storage device 300 can include a controller 310 and a non-volatile memory 320. The storage device 300 can support a plurality of channels CH1 to CHm, and the controller 310 and the non-volatile memory 320 can be connected through the plurality of channels CH1 to CHm. The controller 310 can correspond to the controllers 110 and 110a described above in Figures 1-17 , and the non-volatile memory 320 can correspond to the non-volatile memory 140 described above in Figures 1-17 .

[0152] The nonvolatile memory 320 can include a plurality of nonvolatile memory devices NVM11 to NVMmn. Each of the nonvolatile memory devices NVM11 to NVMmn can be connected to one of the plurality of channels CH1 to CHm by a corresponding manner. For example, the nonvolatile memory devices NVM11 to NVM1n are connected to the first channel CH1 by paths W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n are connected to the second channel CH2 by paths W21 to W2n.

[0153] The controller 310 can transmit and receive signals to and from the nonvolatile memory 320 through the plurality of channels CH1 to CHm. For example, the controller 310 transmits commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the nonvolatile memory 320 through the channels CH1 to CHm. Alternatively, data DATAa to DATAm can be received from the nonvolatile memory 320.

[0154] The controller 310 can select one of the nonvolatile memory devices connected to a corresponding channel through each channel and transmit and receive signals with the selected nonvolatile memory device. For example, the controller 310 can select the nonvolatile memory device NVM11 from among the nonvolatile memory devices NVM11 to NVM1n connected to the first channel CH1. The controller 310 transmits a command CMDa, an address ADDR a, and data DATAa to the selected nonvolatile memory device NVM11 through the path W11 or receives data DATAa from the selected nonvolatile memory device NVM11 through the path W11.

[0155] Figure 19 is a block diagram illustrating a storage device according to an embodiment.

[0156] Referring to Figure 18 and Figure 19 The storage device 400 can include a controller 410 and a nonvolatile memory 420. The nonvolatile memory 420 can correspond to one of the nonvolatile memory devices NVM11 to NVMmn that communicates with the controller 310 based on Figure 18 The controller 410 can correspond to the controller 310. Figure 18

[0157] ​The controller 410 can include first to eighth pins P21 to P28 and a controller interface circuit 411. The nonvolatile memory 420 can include first to eighth pins P11 to P18, a memory interface circuit 421, a control logic circuit 423, and a memory cell array 425. The first to eighth pins P21 to P28 can correspond to the first to eighth pins P11 to P18.

[0158] The controller interface circuit 411 can transmit a chip enable signal nCE to the nonvolatile memory 420 through the first pin P21. The controller interface circuit 411 can transmit and receive signals to and from the nonvolatile memory 420 selected by the chip enable signal nCE through the second to eighth pins P22 to P28.

[0159] The controller interface circuit 411 transmits a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the nonvolatile memory 420 through the second to fourth pins P22 to P24. The controller interface circuit 411 can transmit a read enable signal nRE to the nonvolatile memory 420 through the fifth pin P25. The controller interface circuit 411 can receive a data strobe signal DQS from the nonvolatile memory 420 through the sixth pin P26 or transmit the data strobe signal DQS to the nonvolatile memory 420 through the sixth pin P26.

[0160] The controller interface circuit 411 can transmit or receive a data signal DQ to or from the nonvolatile memory 420 through the seventh pin P27. A command CMD, an address ADDR, and data DATA can be transmitted through the data signal DQ. For example, the data signal DQ can be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 can include a plurality of pins corresponding to a plurality of data signals. The memory interface circuit 421 can transmit a ready / busy output signal nR / B to the controller 410 through the eighth pin P28.

[0161] The control logic circuit 423 can generally control various operations of the nonvolatile memory 420. The control logic circuit 423 can receive a command / address CMD / ADDR obtained from the memory interface circuit 421. The control logic circuit 423 can generate various control signals for programming or reading data DATA to or from the memory cell array 425 according to the received command / address CMD / ADDR.

[0162] Figure 20 is a block diagram illustrating a storage system 10b according to another embodiment. The descriptions given previously with reference to Figure 1 are omitted.

[0163] Referring to Figure 18 , the storage system 10b can include a storage device 100b and a host 200b, and the host 200b can include a key-value manager 220b. The key-value manager 220b can perform the operations described above with reference to Figures 1-17 The storage system 10b can be configured as an open-channel SSD in which the host 200b directly controls the storage device 100b without a separate controller.

[0164] The key-value manager 220b can read a plurality of key streams ST_KEY from the storage device 100b, delete invalid keys KEY from the plurality of key streams ST_KEY, and perform a compression operation to generate a new key stream ST_KEY by using valid keys KEY. According to an embodiment, the key-value manager 220b can store information Info_IK about invalid keys, determine which key KEY in the plurality of key streams ST_KEY is valid based on the stored information, and generate a new key stream ST_KEY by merging only valid keys KEY in the plurality of key streams ST_KEY.

[0165] Figure 21 is a block diagram illustrating an electronic device 1000 according to an embodiment.

[0166] Referring to Figure 21 , the electronic device 1000 can include a processor 1100, a memory device 1200, a storage device 1300, a modem 1400, an input / output (I / O) device 1500, and a power supply 1600. In an embodiment, the storage device 1300 can be implemented by using the embodiments described above with reference to Figures 1-20

[0167] In an embodiment, in the compression operation, the storage device 1300 can determine invalid keys KEY by using information Info_IK about invalid keys received from a host (e.g., the processor 1100). The storage device 1300 can perform a compression operation for generating a merged key stream ST_MK by merging a key stream ST_KEY including invalid keys KEY with a key stream ST_KEY different therefrom. Accordingly, the amount of data accessed by the VM device in the compression process of the storage device 1300 can be reduced, and the data processing speed can be improved.

[0168] Figure 22 is a diagram illustrating a mobile system 2000 to which a memory device is applied according to an embodiment.

[0169] Referring to Figure 22 ​The mobile system 2000 can include a camera 2100, a display 2200, an audio processing unit 2300, a modem 2400, DRAMs (2500a and 2500b), flash devices (2600a and 2600b), I / O devices (2700a and 2700b), and an AP 2800.

[0170] The mobile system 2000 can be implemented with a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the mobile system 2000 can be implemented with a server or a personal computer.

[0171] The camera 2100 can capture a still image or a video image according to a user's control. The mobile system 2000 can obtain specific information by using the still image / video image captured by the camera 2100. Alternatively, the mobile system 2000 can convert the still image / video image into other types of data, such as text, and store it. Alternatively, the mobile system 2000 can recognize a character string included in the still image / video image captured by the camera 2100 and provide a text or an audio translation corresponding to the character string. In this way, the use field of the camera 2100 in the mobile system 2000 has become increasingly diverse. In an embodiment, the camera 2100 can transmit data such as a still image / video image to the AP 2800 according to a D-Phy or C-Phy interface based on a Mobile Industry Processor Interface (MIPI) standard.

[0172] The display 2200 can be implemented in various types, such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an Active Matrix Organic Light Emitting Diode (AM-OLED) display, a Plasma Display Panel (PDP), a Field Emission Display (FED), and an electronic paper display. In an embodiment, the display 2200 can also function as an input device of the mobile system 2000 by providing a touch screen function. In addition, the display 2200 can be provided integrally with a fingerprint sensor or the like. The display 2200 can provide a security function of the mobile system 2000. In an embodiment, the AP 2800 can transmit image data to be displayed on the display 2200 to the display 2200 according to a D-Phy or C-Phy interface based on a MIPI standard.

[0173] The audio processing unit 2300 can process audio data stored in the flash memory device (2600a or 2600b) or audio data included in content received from the outside via the modem 2400 or the I / O device (2700a or 2700b). For example, the audio processing unit 2300 can perform various processes such as encoding / decoding, amplification, noise filtering, etc. of the audio data.

[0174] The modem 2400 can modulate and transmit a signal to transceive wired / wireless data, while can modulate and restore an original signal received from the outside. The I / O device (2700a and 2700b) can be a device that provides digital input and output. The I / O device (2700a and 2700b) can include a port connectable to an external recording medium, an input device such as a touch screen or a mechanical button key, an output device capable of outputting vibration in a tactile manner or the like, etc. In some examples, the I / O device (2700a and 2700b) can be connected to the external recording medium via a port such as a USB, a lightning cable, an SD card, a micro SD card, a DVD, and a network adapter.

[0175] The AP 2800 can control the overall operation of the mobile system 2000. The AP 2800 can control the display 2200 so that a part of content stored in the flash memory device (2600a and 2600b) is displayed on the screen. In addition, when a user input is received via the I / O device (2700a and 2700b), the AP 2800 can perform a control operation corresponding to the user input.

[0176] The AP 2800 can be provided as a system on chip (SoC) that drives an application program, an operating system (OS), etc. Further, the AP 2800 can be included in one semiconductor package together with other devices included in the mobile system 2000, for example, the DRAM 2500a, the flash memory 2620, and / or the memory controller 2610. For example, the AP 2800 and at least one other device can be provided in a package form such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), system in package (SIP), multi-chip package (MCP), wafer level package (WFP), and wafer level processing package (WSP). The kernel of the operating system running on the AP 2800 can include an I / O scheduler and a device driver for controlling the flash memory device (2600a and 2600b). The device driver can control the access performance of the flash memory device (2600a and 2600b) by referring to the number of synchronization queues managed by the I / O scheduler, or can control a CPU mode, a dynamic voltage and frequency scaling (DVFS) level, etc. inside the SoC.

[0177] In an embodiment, the AP 2800 can include a processor block for performing a computing operation or driving an application and / or an operating system, and various peripheral components connected thereto via the processor block and a system bus. The peripheral components can include a memory controller, an internal memory, a power management block, an error detection block, a monitoring block, etc. The processor block can include one or more cores, and when a plurality of cores is included in the processor block, each of the plurality of cores can include a cache memory, and a common cache shared by the plurality of cores can be included in the processor block.

[0178] In an embodiment, the AP 2800 can include an accelerator block 2820, which is a dedicated circuit for artificial intelligence (AI) data computation. Alternatively, according to an embodiment, a separate accelerator chip can be provided separately from the AP 2800, and the DRAM 2500b can be additionally connected to the accelerator block 2820 or the accelerator chip. The accelerator block 2820 can be a functional block that professionally performs a specific function of the AP 2800, and can include a graphic processing unit (GPU) for professionally performing graphic data processing, a neural processing unit (NPU) for professionally performing AI data computation and inference, a data processing unit (DPU) dedicated to data transmission, etc.

[0179] According to an embodiment, the mobile system 2000 can include a plurality of DRAMs (2500a and 2500b). In an embodiment, the AP 2800 can include a controller 2810 for controlling the DRAMs (2500a and 2500b), and the DRAM 2500a can be directly connected to the AP 2800.

[0180] The AP 2800 can control the DRAM by setting a command and a mode register set (MRS) conforming to a Joint Electron Device Engineering Council (JEDEC) standard. Alternatively, the AP 2800 can communicate by setting a specification and a function required for the mobile system 2000 (e.g., low voltage, high speed, and reliability) and a DRAM interface protocol for cyclic redundancy check / error check and correction (CRC / ECC). For example, the AP 2800 can communicate with the DRAM 2500a via an interface conforming to a JEDEC standard such as low power double data rate (LPDDR) 4 (LPDDR4) and LPDDR5. Alternatively, the AP 2800 can communicate by setting a new DRAM interface protocol so that the DRAM 2500b for an accelerator, which has a higher bandwidth than the DRAM 2500a, is controlled by the accelerator block 2820 or an accelerator chip provided separately from the AP 2800.

[0181] Although in Figure 22DRAMs (2500a and 2500b) are illustrated, but the configuration of the mobile system 2000 is not necessarily limited thereto, and other memories other than the DRAMs (2500a and 2500b) can be included in the mobile system 2000 according to the bandwidth, response speed, voltage conditions, etc. of the AP 2800 or the accelerator block 2820. For example, the controller 2810 and / or the accelerator block 2820 can control various memories such as PRAM, SRAM, MRAM, RRAM, FRAM, and hybrid RAM. The DRAMs (2500a and 2500b) can have a relatively smaller latency and a higher bandwidth compared to the I / O devices (2700a and 2700b) or the flash memory devices (2600a and 2600b). The DRAMs (2500a and 2500b) can be initialized at a boot-up time point of the mobile system 2000, and can be used as a temporary storage location of an operating system and application data when the operating system and application data are loaded, or as an execution space of various software codes.

[0182] In the DRAMs (2500a and 2500b), data of addition / subtraction / multiplication / division arithmetic operations and vector operations, address operations, or fast Fourier transform (FFT) operations can be stored. In another embodiment, the DRAMs (2500a and 2500b) can be provided as processing in a memory (PIM) equipped with a computing function. For example, in the DRAMs (2500a and 2500b), a function for performance to be used in an inference operation can be executed. In this case, the inference operation can be performed by using a deep learning algorithm using an artificial neural network. The deep learning algorithm can include a training operation of learning a model using various data and an inference operation of recognizing data using the learned model. For example, the function for the inference operation can include a hyperbolic tangent function, a sigmoid function, a rectified linear unit (ReLU) function.

[0183] In an embodiment, an image captured by a user using the camera 2100 can be signal-processed and stored in the DRAM 2500b. The accelerator block 2820 or the accelerator chip can perform AI data computation of recognizing data by using data stored in the DRAM 2500b and a function used in an inference operation.

[0184] According to an embodiment, the mobile system 2000 can include a plurality of storage devices or a plurality of flash memory devices (2600a and 2600b) having a larger data capacity (data storage capacity) than the DRAMs (2500a and 2500b).

[0185] The flash memory device (2600a and 2600b) can include a memory controller 2610 and a flash memory 2620. The memory controller 2610 can receive a control command, data, etc. from the AP 2800 and write data in response to the control command to the flash memory 2620, or read data stored in the flash memory 2620 and transmit the read data to the AP 2800.

[0186] The flash memory device (2600a and 2600b) can include a memory device according to various embodiments of the disclosure described above with reference to FIGS. 1 to 25. Figures 1-20 When performing a read operation and / or a program verify operation, the flash memory device (2600a and 2600b) can delay a time point at which a read pass voltage is input to at least one of a plurality of unselected word lines to a time point after a setup period of the unselected word line. As a result, the flash memory device (2600a and 2600b) can prevent occurrence of soft erase and ensure reliability by controlling a degree to which a channel of an unselected cell string is boosted to a certain voltage level such as a predetermined minimum voltage level. In addition, the flash memory device (2600a and 2600b) can reduce power consumption and an increase in size of a power supply device by selectively applying a pre-pulse voltage to any one of an unselected string selection line and an unselected ground selection line connected to the unselected cell string during the read operation and / or the program verify operation.

[0187] According to an embodiment, the accelerator block 2820 or the accelerator chip can perform a training operation and an AI data calculation by using the flash memory device (2600a and 2600b). In an embodiment, a block capable of performing a specific operation can be implemented inside the flash memory device (2600a and 2600b), and the corresponding block can alternatively perform at least a part of the training operation and the inference AI data calculation performed by the AP 2800 and / or the accelerator block 2820 by using data stored in the flash memory 2620.

[0188] In an embodiment, the AP 2800 can include an interface 2830, and thus the flash memory device (2600a and 2600b) can be directly connected to the AP 2800. For example, the AP 2800 can be implemented as an SoC, the flash memory device 2600a can be implemented as a chip separate from the AP 2800, and the AP 2800 and the flash memory device 2600a can be implemented as one package. However, embodiments of the disclosure are not limited thereto, and a plurality of flash memory devices (2600a and 2600b) can be electrically connected to the mobile system 2000 via a connection.

[0189] The flash memory devices (2600a and 2600b) can store data such as still images and videos captured by the camera 2100, or data received via communication networks and / or ports included in the I / O devices (2700a and 2700b). For example, the flash memory devices (2600a and 2600b) can store augmented reality (AR) / virtual reality (VR), high-definition (HD), or ultra-high-definition (UHD) content.

[0190] In the embodiments, the above references can be used. Figures 1-20 The described embodiments implement flash memory devices (2600a and 2600b). In these embodiments, during compression operations, the flash memory devices (2600a and 2600b) can determine an invalid key KEY using information Info_IK received from host 200 regarding the invalid key. The flash memory devices (2600a and 2600b) can perform a compression operation to generate a merged key stream ST_MK by merging a key stream ST_KEY that includes the invalid key KEY and a key stream ST_KEY that is different from it. Therefore, the amount of data accessed by the VM device during compression in the flash memory devices (2600a and 2600b) can be reduced, and data processing speed can be improved.

[0191] Figure 23 This is a diagram illustrating a data center 3000 with a memory device applied according to an embodiment.

[0192] refer to Figure 23 Data center 3000 can be a facility that collects various types of data and provides services, and can also be called a data storage center. Data center 3000 may include application servers (3100 to 3100n) and storage servers (3200 to 3200m). The number of application servers (3100 to 3100n) and the number of storage servers (3200 to 3200m) can be selected differently depending on the embodiment, and the number of application servers (3100 to 3100n) and the number of storage servers (3200 to 3200m) can be different from each other.

[0193] The application server 3100 and the storage server 3200 can include at least one of a processor (3110 and 3210) and a memory (3120 and 3220), respectively. Taking the storage server 3200 as an example, the processor 3210 can control the overall operation of the storage server 3200, access the memory 3220, and execute commands and / or data loaded in the memory 3220. According to an embodiment, the number of processors 3210 and the number of memories 3220 included in the storage server 3200 can be variously selected. In an embodiment, the processor 3210 and the memory 3220 can provide a processor-memory pair. In an embodiment, the number of processors 3210 and the number of memories 3220 can be different from each other. The processor 3210 can include a single core processor or a multi-core processor. The above description of the storage server 3200 can be similarly applied to the application server 3100. According to an embodiment, the application server 3100 can not include the storage device 3150. The storage server 3200 can include at least one of the storage device 3250. The number of storage devices 3250 included in the storage server 3200 can be variously selected according to an embodiment.

[0194] The application servers (3100 to 3100n) and the storage servers (3200 to 3200m) can communicate with each other via the network 3300. The network 3300 can be implemented by using a fiber channel (FC) or Ethernet. In this case, the FC can be a medium for relatively high-speed data transmission, and an optical switch providing high performance / high availability can be used. According to an access method of the network 3300, the storage servers (3200 to 3200m) can be provided as file storage, block storage, or object storage.

[0195] Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. The description of the application server 3100 can be applied to the other application servers (e.g., 3100n), and the description of the storage server 3200 can be applied to the other storage servers (e.g., 3200m).

[0196] The application server 3101 can store data requested by a user or a client to be stored in one of the storage servers (3200 to 3200m) via the network 3300. In addition, the application server 3100 can obtain data requested by a user or a client to be read from one of the storage servers (3200 to 3200m) via the network 3300. For example, the application server 3100 can be implemented as a web server or a database management system (DBMS).

[0197] The application server 3101 can access the memory 3120n or the storage device 3150n included in the application server 3100n via the network 3300, or can access the memory (3220 to 3220m) or the storage device (3250 to 3250m) included in the storage server (3200 to 3200m) server 3101n via the network 3300. Thus, the application server 3100 can perform various operations on data stored in the application servers (3100 to 3100n) and / or the storage servers (3200 to 3200m). For example, the application server 3100 can execute a command for moving or copying data between the application servers (3100 to 3100n) and / or the storage servers (3200 to 3200m). In this case, the data can be moved from the storage device (3250 to 3250m) of the storage server (3200 to 3200m), via the memory (3220 to 3220m) of the storage server (3200 to 3200m) or directly to the memory (3120 to 3120n) of the application server (3100 to 3100n).

[0198] Taking the storage server 3200 as an example, the I / F 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface controller (NIC) 3240 and the controller 32511. For example, the I / F 3254 can be implemented in a direct attached storage (DAS) method in which the storage device 3250 is directly connected to a dedicated cable. In addition, for example, the I / F 32541 can be implemented in various interface methods such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnect (PCI), PCI Express (PCIe), node version manager (NVM) Express (NVMe), IEEE 1394, universal serial bus (USB), secure digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), universal flash memory (UFS), and compact flash (CF) card.

[0199] The storage server 3200 can further include a switch 3230 and a NIC 3240. The switch 3230 can selectively connect the processor 3210 to the storage device 3250 under the control of the processor 3210. Alternatively, the switch 3230 can selectively connect the NIC 3240 to the storage device 3250.

[0200] In an embodiment, the NIC 3240 can include a network interface card, a network adapter, and the like. The NIC 3240 can be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, and the like. The NIC 3240 can include an internal memory, a digital signal processor (DSP), a host bus interface, and the like, and can be connected to the processor 3210 and / or the switch 3230 via the host bus interface. The host bus interface can be implemented as one of the above-described I / F 3254. In an embodiment, the NIC 3240 can be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0201] In the storage server (3200 to 3200m) or the application program server (3100 to 3100n), the processor (3110 to 3110n and 3210 to 3210m) can program or read data by sending a command to the storage device (3130 to 3130n and 3250 to 3250m) or the memory (3120 to 3120n and 3220 to 3220n). In this case, the data can be error corrected data processed by an error check and correction (ECC) engine. The data can be data processed by data bus inversion (DBI) or data masking (DM), and can include cyclic redundancy code (CRC) information.

[0202] The storage device (3150 to 3150m and 3250 to 3250m) can send a control signal and a command / address signal to the NAND flash device (3252 to 3252m) in response to a read command received from the processor (3110 to 3110n and 3210 to 3210m). Accordingly, when data is read from the NAND flash device (3252 to 3252m), a read enable (RE) signal can be input as a data output control signal, and data can be output to a data signal (DQ) bus. A data strobe (DQS) can be generated by using the RE signal. The command and address signals can be latched in a page buffer according to a rising edge or a falling edge of a write enable (WE) signal.

[0203] In an embodiment, the above-described data bus inversion (DBI) and data masking (DM) can be used to reduce power consumption of the storage device (3250 to 3250m) and the NAND flash device (3252 to 3252m). Figures 1-20The described embodiments implement a storage device (3150 to 3150m). In an embodiment, in a compression operation, the storage device (3150 to 3150m) can determine an invalid key KEY by using information Info_IK about the invalid key received from the host 200. The storage device (3150 to 3150m) can perform a compression operation for generating a merged key stream ST_MK by merging a key stream ST_KEY including the invalid key KEY and a key stream ST_KEY different therefrom. Accordingly, the amount of data accessed by the VM device in the compression process of the storage device (3150 to 3150m) can be reduced, and the data processing speed can be improved.

[0204] The controller 3251 can control the overall operation of the storage device 3250. In an embodiment, the controller 3251 can include an SRAM. The controller 3251 can write data to the NAND flash device 3252 in response to a write command. Alternatively, the controller 3251 can read data from the NAND flash device 3252 in response to a read command. For example, the write command and / or the read command can be provided by the processor 3210 in the storage server 3200, the processor 3210m in another storage server 3200m, or the processor (3110 to 3110n) in the application server (3100 to 3100n).

[0205] While the inventive concepts described herein have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: The controller is configured to generate a key stream and a value stream by extracting multiple keys provided by a host and multiple values ​​corresponding to the multiple keys respectively, receive information from the host about specific invalid keys included in the key stream and a compression command, and perform a compression operation on the key stream in response to the compression command; and Non-volatile memory that stores the key stream and the value stream. In the compression operation, the controller merges the key stream with other key streams into a merged key stream based on information about the invalid key.

2. The storage device according to claim 1, wherein, The controller is configured to generate the key stream by merging each of the plurality of keys with an index corresponding to a value among the plurality of values.

3. The storage device according to claim 2, wherein, The controller receives from the host an index corresponding to the invalid key as information about the invalid key.

4. The storage device according to claim 1, wherein, The controller generates a first key stream by combining at least some of the plurality of keys, generates a second key stream by combining at least some of the plurality of keys, generates a third key stream by merging the first key stream and the second key stream based on information about the invalid key, and stores the generated third key stream in the non-volatile memory.

5. The storage device according to claim 4, wherein, Based on information about the invalid keys, the controller identifies invalid keys among a plurality of keys included in the first key stream and the second key stream, and generates the third key stream by combining valid keys included in the first key stream and the second key stream. The invalid key corresponds to the value among the plurality of values ​​for which a delete command has been received from the host.

6. The storage device according to claim 1, further comprising: A volatile memory that stores a key table including the physical addresses of the non-volatile memory and a value table including the physical addresses of the non-volatile memory for the value stream.

7. The storage device according to claim 6, wherein, The key table stores validity bits corresponding to the value stream, such that valid keys correspond to keys corresponding to the plurality of values.

8. The storage device according to claim 6, wherein, When the compression operation is performed, the controller updates the key table by adding the address of the key stream used for the merging to the key table.

9. The storage device according to claim 1, wherein, The controller also receives data capacity information from the host regarding values ​​corresponding to a plurality of invalid keys, including the invalid key, and performs garbage collection operations on the values ​​using the data capacity information.

10. The storage device according to claim 1, wherein, The controller receives the address of the invalid key stored in the non-volatile memory as information about the invalid key.

11. A method of operating a storage device, the storage device storing a key stream and a value stream generated by extracting a plurality of keys and a plurality of values ​​corresponding to the plurality of keys from data, the method comprising: Receive compression commands and information about specific invalid keys included in the key stream from the host; Compression is performed based on the compression command by merging the key stream with other key streams into a merged key stream based on information about the invalid key; and The merged key stream is stored in non-volatile memory.

12. The operating method according to claim 11, further comprising: Generate indexes for the plurality of values ​​corresponding to the plurality of keys respectively; and The key stream is generated by associating the index with the plurality of keys.

13. The operating method according to claim 12, wherein, Information about the invalid key includes index information corresponding to multiple invalid keys, and The compression operation includes excluding the plurality of invalid keys from the key stream based on the index information, and merging only the valid keys of the key stream with other key streams.

14. The operating method according to claim 13, further comprising: Generate a key table, the key table including information about the storage location of the key stream in the non-volatile memory and a validity bit corresponding to the key stream; and The validity bit is updated based on the information about the invalid key.

15. The operating method according to claim 14, wherein, The compression operation includes generating the merged key stream by extracting valid keys from multiple keys included in the key stream and the other key streams based on the validity bits.

16. A storage system that stores a key stream and a value stream generated by extracting a plurality of keys and a plurality of values ​​corresponding to the plurality of keys from data, the storage system comprising: The host is configured to send compression commands for the key stream and information about specific invalid keys included in the key stream; and A storage device is configured to receive the compression command, merge the key stream with other key streams into a merged key stream based on information about the invalid key, perform a compression operation based on the compression command, and store the merged key stream.

17. The storage system according to claim 16, wherein, The storage device generates the key stream by combining each of the plurality of keys with an index corresponding to a corresponding value among the plurality of values, and Information about the invalid key includes index information corresponding to multiple invalid keys, including the invalid key.

18. The storage system according to claim 17, wherein, The storage device generates a first key stream by combining at least some of the plurality of keys, generates a second key stream by combining at least some of the plurality of keys that are not in the first key stream, generates a third key stream by merging the first key stream and the second key stream based on the index information, and stores the generated third key stream in non-volatile memory.

19. The storage system according to claim 18, wherein, The key table stores a validity bit corresponding to each of the plurality of values ​​to correspond to the key corresponding to the plurality of values.

20. The storage system according to claim 16, wherein, The storage device also receives data capacity information from the host regarding values ​​corresponding to a plurality of invalid keys, including the invalid key, and performs garbage collection operations on the values ​​using the data capacity information.

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