Semiconductor package

Abstract

A semiconductor package includes a package substrate, a lower semiconductor device disposed on the package substrate and including a first through electrode, a first lower connection bump disposed between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrode, a connection substrate disposed on the package substrate and including a second through electrode, a second lower connection bump disposed between the package substrate and the connection substrate and electrically connecting the package substrate to the second through electrode, and an upper semiconductor device disposed on the lower semiconductor device and electrically connected to the first through electrode and the second through electrode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0174286, filed on December 24, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The apparatus, devices, methods and articles of manufacture consistent with this disclosure relate to semiconductor packages, and more specifically, to semiconductor packages having improved heat dissipation characteristics. Background Technology

[0004] Semiconductor packages are typically formed by performing packaging processes on semiconductor chips, which are then formed by performing various semiconductor processes on wafers. Recently, various semiconductor chips have been packaged within a single semiconductor package, and these chips are electrically interconnected, allowing them to operate as a system. However, excessive heat can be generated during semiconductor chip operation, which can degrade the performance of the semiconductor package. Summary of the Invention

[0005] One aspect is to provide a semiconductor package with improved heat dissipation characteristics.

[0006] According to one aspect of an exemplary embodiment, a semiconductor package is provided, the semiconductor package comprising: a package substrate; a lower semiconductor device disposed on the package substrate and including a plurality of first through electrodes; a plurality of first lower connection bumps disposed between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the plurality of first through electrodes; a connection substrate disposed on the package substrate and including a plurality of second through electrodes; a plurality of second lower connection bumps disposed between the package substrate and the connection substrate and electrically connecting the package substrate to the plurality of second through electrodes; and an upper semiconductor device disposed on the lower semiconductor device and electrically connected to the plurality of first through electrodes and the plurality of second through electrodes.

[0007] According to another aspect of an exemplary embodiment, a semiconductor package is provided, the semiconductor package comprising: a lower semiconductor device including a plurality of first through electrodes; a connection substrate including a plurality of second through electrodes; an upper semiconductor device stacked on an upper surface of the lower semiconductor device and an upper surface of the connection substrate, the upper semiconductor device being electrically connected to the plurality of first through electrodes and electrically connected to the plurality of second through electrodes; and a redistribution structure disposed on a lower surface of the lower semiconductor device and a lower surface of the connection substrate, the redistribution structure being electrically connected to the plurality of first through electrodes and electrically connected to the plurality of second through electrodes.

[0008] According to another aspect of an exemplary embodiment, a semiconductor package is provided, the semiconductor package comprising: a package substrate; a memory chip disposed on the package substrate and including a plurality of first through electrodes; a connection substrate disposed on the package substrate and including a plurality of second through electrodes, the second width of each of the plurality of second through electrodes being greater than the first width of each of the plurality of first through electrodes; and a logic chip disposed on an upper surface of the memory chip and an upper surface of the connection substrate, the logic chip being electrically connected to the plurality of first through electrodes and the plurality of first through electrodes. A second through electrode; a heat dissipation component located on the logic chip; a redistribution structure disposed on the lower surface of the memory chip and the lower surface of the connection substrate, the redistribution structure including a plurality of first lower bump pads electrically connected to the plurality of first through electrodes, and a plurality of second lower bump pads electrically connected to the plurality of second through electrodes; a plurality of first lower connection bumps located between the plurality of first lower bump pads and the packaging substrate; and a plurality of second lower connection bumps located between the plurality of second lower bump pads and the packaging substrate. The memory chip includes: a first substrate, the first substrate including a first surface facing the logic chip and a second surface opposite to the first surface; and a first semiconductor device layer located on the first surface of the first substrate. The logic chip includes: a second substrate, the second substrate including a third surface facing the memory chip and a fourth surface opposite to the third surface; and a second semiconductor device layer, the second semiconductor device layer being located on the third surface of the second substrate, wherein the planar area of ​​the logic chip is greater than the sum of the planar area of ​​the memory chip and the planar area of ​​the connecting substrate. Attached Figure Description

[0009] These and other aspects will become clearer from the following detailed description taken in conjunction with the accompanying drawings:

[0010] Figure 1 This is a cross-sectional view showing a semiconductor package according to various exemplary embodiments;

[0011] Figure 2 It shows Figure 1 An enlarged cross-sectional view of region II of the semiconductor package shown in the figure;

[0012] Figure 3 It shows Figure 1 An enlarged cross-sectional view of region III of the semiconductor package is shown in the figure;

[0013] Figure 4 It shows Figure 1 The image shows an enlarged cross-sectional view of region IV of the semiconductor package.

[0014] Figure 5 It shows Figure 1 The image shows an enlarged cross-sectional view of region V of the semiconductor package.

[0015] Figures 6A to 6C This is a top view showing an exemplary layout of the lower semiconductor device and the interconnect substrate in a semiconductor package according to various exemplary embodiments;

[0016] Figure 7 This shows a cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0017] Figure 8 This shows a cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0018] Figure 9 This shows a cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0019] Figure 10 This shows a cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0020] Figure 11 This shows a cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0021] Figure 12 This shows a cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0022] Figure 13 This shows a cross-sectional view of a semiconductor package according to an exemplary embodiment;

[0023] Figures 14A to 14MThis is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment; and

[0024] Figures 15A to 15C This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment. Detailed Implementation

[0025] In the following description, various exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout, and for the sake of brevity, the previously given descriptions will be omitted.

[0026] Figure 1 This is a cross-sectional view of a semiconductor package 10 according to various exemplary embodiments. Figure 2 It shows Figure 1 Enlarged cross-sectional view of region II in the diagram. Figure 3 It shows Figure 1 Enlarged cross-sectional view of region III in the image. Figure 4 It shows Figure 1 Enlarged cross-sectional view of region IV in the diagram. Figure 5 It shows Figure 1 An enlarged cross-sectional view of region V in the diagram.

[0027] Reference Figures 1 to 5 The semiconductor package 10 may include a lower semiconductor device 110, an upper semiconductor device 120, a connecting substrate 130, a first molding layer 163, and a first redistribution structure 140.

[0028] The upper semiconductor device 120 may be stacked on top of the lower semiconductor device 110. The planar area (or footprint) of the upper semiconductor device 120 may be larger than the planar area (or footprint) of the lower semiconductor device 110. Viewed from above, the lower semiconductor device 110 may be arranged to overlap the upper semiconductor device 120 in the vertical direction (e.g., the Z direction). See example Figures 6A to 6C .

[0029] Additionally, the semiconductor device 120 can be stacked on the interconnect substrate 130, which is horizontal (e.g., Figure 1 In the example shown, the upper semiconductor device 120 is spaced apart from the lower semiconductor device 110 in the X direction. The planar area of ​​the upper semiconductor device 120 may be greater than the sum of the planar areas of the lower semiconductor device 110 and the connecting substrate 130. Viewed from above, the lower semiconductor device 110 and the connecting substrate 130 may be arranged to overlap the upper semiconductor device 120 in the vertical direction.

[0030] In some exemplary embodiments, when a power signal is supplied to the lower semiconductor device 110 and the upper semiconductor device 120, the heat generated by the upper semiconductor device 120 may be greater than the heat generated by the lower semiconductor device 110. To dissipate heat on the upper semiconductor device 120, in some exemplary embodiments, a heat dissipation component such as a heat sink (e.g., see reference 120) is used. Figure 12 The 180) may be arranged on the upper semiconductor device 120, and / or in other exemplary embodiments, at least a portion of the surface of the upper semiconductor device 120 may be exposed to the outside.

[0031] In an exemplary embodiment, the lower semiconductor device 110 may include a memory chip. For example, the lower semiconductor device 110 may include a volatile memory chip and / or a non-volatile memory chip. The volatile memory chip may be, for example, dynamic random access memory (DRAM), high-bandwidth memory (HBM) DRAM, static RAM (SRAM), thyristor RAM (TRAM), zero-capacitance RAM (ZRAM), or dual-transistor RAM (TTRAM). Alternatively, the non-volatile memory chip may be, for example, flash memory, magnetic RAM (MRAM), spin-torque MRAM (STT-MRAM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM, or insulator phase-change memory.

[0032] In an exemplary embodiment, the upper semiconductor device 120 may include a logic chip. The upper semiconductor device 120 may include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. For example, the upper semiconductor device 120 may include a control chip for controlling the lower semiconductor device 110.

[0033] The lower semiconductor device 110 may include a first semiconductor substrate 111, a first semiconductor device layer 113, a first through electrode 115, a first upper bump pad 117, and a first back protective layer 119.

[0034] The first semiconductor substrate 111 may include a first surface 111F and a second surface 111B opposite to each other. The first surface 111F of the first semiconductor substrate 111 may be an active surface of the first semiconductor substrate 111, and the second surface 111B of the first semiconductor substrate 111 may be a passive surface of the first semiconductor substrate 111. In an exemplary embodiment, the lower semiconductor device 110 may be arranged such that the first surface 111F of the first semiconductor substrate 111 faces the upper semiconductor device 120.

[0035] In some exemplary embodiments, the first semiconductor substrate 111 may include, for example, silicon (Si). Alternatively, in some exemplary embodiments, the first semiconductor substrate 111 may include semiconductor elements such as germanium (Ge), or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Alternatively, in some exemplary embodiments, the first semiconductor substrate 111 may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate 111 may include a buried oxide (BOX) layer. The first semiconductor substrate 111 may include conductive regions, such as impurity-doped wells or impurity-doped structures. Additionally, the first semiconductor substrate 111 may have various device isolation structures, such as shallow trench isolation (STI) structures.

[0036] The first semiconductor device layer 113 is formed on the first surface 111F of the first semiconductor substrate 111, and may include a front-end process (FEOL) structure and a back-end process (BEOL) structure.

[0037] For example, the first semiconductor device layer 113 may include multiple individual devices of various types and interlayer insulating layers. The multiple individual devices of various types may include various microelectronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor (CMOS) transistors, image sensors such as system-on-large-scale integration (LSI) or CMOS imaging sensors (CIS), microelectromechanical systems (MEMS), active components, and passive components.

[0038] For example, the first semiconductor device layer 113 may include a wiring structure for connecting a plurality of individual devices to other wiring formed on the first semiconductor substrate 111. The wiring structure may include a metal wiring layer 1131 and a via plug 1133 formed in an insulating layer 1135. The metal wiring layer 1131 and the via plug 1133 may include a wiring barrier layer and a wiring metal layer. The wiring barrier layer may include at least one material selected from Ti, TiN, Ta, or TaN. The wiring metal layer may include at least one metal selected from tungsten (W), aluminum (Al), or copper (Cu). The metal wiring layer 1131 and the via plug 1133 may be formed of the same material. Alternatively, in some exemplary embodiments, at least a portion of the metal wiring layer 1131 and the via plug 1133 may include different materials.

[0039] The first through electrode 115 can pass through the first semiconductor substrate 111. The first through electrode 115 can be used for signal transmission between an external device and the lower semiconductor device 110, such as the transmission of input / output data signals and power signals. The first through electrode 115 can also be used for signal transmission between an external device and the upper semiconductor device 120, such as the transmission of input / output data signals and power signals.

[0040] Each first through electrode 115 may include a first core conductive material 1151, a first barrier layer 1153, and a first through dielectric layer 1155.

[0041] The first conductive material 1511 may include one or more of, for example, aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), magnesium (Mg), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tin (Sn), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr).

[0042] The first barrier layer 1153 may contact and surround the side surface of the first core conductive material 1151. The first barrier layer 1153 may include a conductive layer with low wiring resistance. For example, the first barrier layer 1153 may include a single layer or multiple layers, which may include at least one of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB. For example, the first barrier layer 1153 may include multiple layers formed of TaN / W, TiN / W, or WN / W. The first barrier layer 1153 may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0043] The first dielectric layer 1155 may surround the side surface of the first barrier layer 1153 and may insulate the first conductive core material 1151 from the first semiconductor substrate 111. The first dielectric layer 1155 may include an oxide layer, a nitride layer, a carbide layer, a polymer layer, or a combination of the above materials. The first dielectric layer 1155 may be formed by CVD.

[0044] Figure 1 and Figure 2 The diagram shows a first through electrode 115 extending from the lower surface 110LS of the lower semiconductor device 110 to the first surface 111F of the first semiconductor substrate 111. However, exemplary embodiments are not limited thereto. For example, in some exemplary embodiments, a portion of the first through electrode 115 may further extend into or through the first semiconductor device layer 113.

[0045] A first upper bump pad 117 may be disposed on a first semiconductor device layer 113. The first upper bump pad 117 may be electrically connected to a first through electrode 115. For example, the first upper bump pad 117 may be electrically connected to the first through electrode 115 through a wiring structure in the first semiconductor device layer 113. For example, the first upper bump pad 117 may comprise Al, Cu, Ni, W, Pt, Au, or a combination of these metals.

[0046] A first back-side protective layer 119 may be formed on a second surface 111B of a first semiconductor substrate 111. The first back-side protective layer 119 may surround a side surface of a first through electrode 115 protruding from the second surface 111B of the first semiconductor substrate 111. The first back-side protective layer 119 may include, for example, an inorganic insulating layer or an organic insulating layer.

[0047] The upper semiconductor device 120 may include a second semiconductor substrate 121, a second semiconductor device layer 123, a first bump pad 125, and a second bump pad 127.

[0048] The second semiconductor substrate 121 may include a first surface 121F and a second surface 121B opposite to each other. The first surface 121F of the second semiconductor substrate 121 may be an active surface of the second semiconductor substrate 121, and the second surface 121B of the second semiconductor substrate 121 may be a passive surface of the second semiconductor substrate 121. In an exemplary embodiment, the upper semiconductor device 120 may be arranged such that the first surface 121F of the second semiconductor substrate 121 faces the upper surface 110US of the lower semiconductor device 110. Because the second semiconductor substrate 121 may be the same as or similar to the first semiconductor substrate 111, its detailed description will not be given for the sake of brevity.

[0049] The second semiconductor device layer 123 may be formed on the first surface 121F of the second semiconductor substrate 121. The second semiconductor device layer 123 may include FEOL structure and BEOL structure. Because the second semiconductor device layer 123 may be the same as or similar to the first semiconductor device layer 113, it will not be described in detail for the sake of brevity.

[0050] The first bump pad 125 and the second bump pad 127 may be disposed on the second semiconductor device layer 123. The first bump pad 125 and the second bump pad 127 may be electrically connected to the wiring structure in the second semiconductor device layer 123. The first bump pad 125 and the second bump pad 127 may comprise, for example, Al, Cu, Ni, W, Pt, or Au, or combinations of these metals.

[0051] Each of the connecting substrates 130 may include a base layer 131, a second through electrode 133, and a second upper bump pad 135.

[0052] The substrate layer 131 may be formed of a semiconductor material or an insulating material. For example, the substrate layer 131 may include at least one of Si, Ge, SiGe, GaAs, glass, or ceramic.

[0053] The second through electrode 133 can penetrate the substrate layer 131. Each second through electrode 133 may include a second core conductive material 1331, a second barrier layer 1333 surrounding the side surface of the second core conductive material 1331, and a second pass dielectric layer 1335 surrounding the side surface of the second barrier layer 1333. Because the second core conductive material 1331, the second barrier layer 1333, and the second pass dielectric layer 1335 may be the same as or similar to the first core conductive material 1151, the first barrier layer 1153, and the first pass dielectric layer 1155, respectively, for the sake of brevity, their detailed description will not be given.

[0054] The second upper bump pad 135 may be disposed on the upper surface 130US of the semiconductor device 120 facing the substrate 130. The second upper bump pad 135 may be electrically connected to the second through electrode 133. For example, the second upper bump pad 135 may include Al, Cu, Ni, W, Pt or Au, or a combination of these metals.

[0055] Between the upper semiconductor device 120 and the lower semiconductor device 110, a first upper connection bump 151 may be arranged for electrically connecting the upper semiconductor device 120 to the lower semiconductor device 110. The lower portion of the first upper connection bump 151 may be attached to the first upper bump pad 117 of the lower semiconductor device 110, and the upper portion of the first upper connection bump 151 may be attached to the first bump pad 125 of the upper semiconductor device 120. The first upper semiconductor device 120 may be electrically connected to the first through electrode 115 via the first upper connection bump 151. The first upper connection bump 151 may be used for signal transmission between the upper semiconductor device 120 and the lower semiconductor device 110 or between an external device and the upper semiconductor device 120.

[0056] Between the upper semiconductor device 120 and the connection substrate 130, a second upper connection bump 153 may be arranged for electrically connecting the upper semiconductor device 120 to a second through electrode 133 of the connection substrate 130. The lower portion of the second upper connection bump 153 may be attached to a second upper bump pad 135 of the connection substrate 130, and the upper portion of the second upper connection bump 153 may be attached to a second bump pad 127 of the upper semiconductor device 120. The second upper connection bump 153 may be used for signal transmission between an external device and the upper semiconductor device 120.

[0057] An insulating adhesive layer 161 may be disposed between the upper semiconductor device 120 and the lower semiconductor device 110, and between the upper semiconductor device 120 and the connection substrate 130. The insulating adhesive layer 161 may surround a first upper connection bump 151 between the upper semiconductor device 120 and the lower semiconductor device 110, and may surround a second upper connection bump 153 between the upper semiconductor device 120 and the connection substrate 130. The insulating adhesive layer 161 may include, for example, a non-conductive film (NCF).

[0058] A first molding layer 163 may be formed on the lower surface 120LS of the upper semiconductor device 120 and may mold the lower semiconductor device 110 and the interconnect substrate 130. The first molding layer 163 may surround the side surfaces of the lower semiconductor device 110 and the interconnect substrate 130. The first molding layer 163 may contact the side surfaces of the lower semiconductor device 110 and the interconnect substrate 130. In some exemplary embodiments, the first molding layer 163 may not cover the lower surface 110LS of the lower semiconductor device 110 facing the first redistribution structure 140 and the lower surface 130LS of the interconnect substrate 130 facing the first redistribution structure 140. Alternatively, the first molding layer 163 may cover a portion of the lower surface 120LS of the upper semiconductor device 120. The first molding layer 163 may protect the lower semiconductor device 110 and the interconnect substrate 130 from the influence of the external environment.

[0059] For example, the first molding layer 163 may include an epoxy-based molding resin or a polyimide-based molding resin. In an exemplary embodiment, the first molding layer 163 may include an epoxy molding compound (EMC).

[0060] The first redistribution structure 140 may be disposed on the lower surface 110LS of the lower semiconductor device 110, the lower surface 130LS of the connecting substrate 130, and the lower surface of the first molding layer 163. The first redistribution structure 140 may include a first redistribution pattern 142 and a first redistribution insulating layer 149.

[0061] The first redistribution insulating layer 149 may contact the lower surface 110LS of the lower semiconductor device 110, the lower surface 130LS of the connecting substrate 130, and the lower surface of the first molding layer 163. The first redistribution insulating layer 149 may electrically insulate various components included in the first redistribution structure 140 from each other. The first redistribution insulating layer 149 may include a photo-imageable dielectric (PID) insulating material that can be used in a photolithography process. For example, the first redistribution insulating layer 149 may be formed of photosensitive polyimide. Alternatively, in some exemplary embodiments, the first redistribution insulating layer 149 may include silicon oxide or silicon nitride.

[0062] The first redistribution pattern 142 can electrically connect the first lower connecting bump 155 to the first through electrode 115 of the lower semiconductor device 110, and can connect the second lower connecting bump 157 to the second through electrode 133 of the connecting substrate 130. For example, the first redistribution pattern 142 may include a conductive line pattern 141 extending in the horizontal direction and a conductive path pattern 143 extending in the vertical direction. The conductive path pattern 143 can electrically connect the conductive line pattern 141 to the first through electrode 115, can electrically connect the conductive line pattern 141 to the second through electrode 133, can electrically connect the conductive line pattern 141 to the first lower connecting bump 155, or can electrically connect the conductive line pattern 141 to the second lower connecting bump 157. In addition, in Figure 1 In the diagram, the conductive line pattern 141 is shown as a single layer. However, in some exemplary embodiments, multiple conductive line patterns 141 forming multiple layers may be disposed in the first redistributed insulating layer 149, and conductive path patterns 143 may be electrically connected to conductive line patterns 141 that are adjacent to each other in the vertical direction.

[0063] In an exemplary embodiment, the first redistribution pattern 142 may include a first lower bump pad 145 and a second lower bump pad 147, with a first lower connecting bump 155 attached to the first lower bump pad 145 and a second lower connecting bump 157 attached to the second lower bump pad 147. At least a portion of the first lower bump pad 145 and at least a portion of the second lower bump pad 147 may protrude from the lower surface of the first redistribution insulating layer 149.

[0064] In an exemplary embodiment, the upper semiconductor device 120 can receive the power required for its operation via the second through electrode 133 of the connecting substrate 130. More specifically, power supplied by an external device can be supplied to the upper semiconductor device 120 via the second lower connecting bump 157, the first redistribution pattern 142 of the first redistribution structure 140, the second through electrode 133, and the second upper connecting bump 153.

[0065] like Figure 2 and Figure 3 As shown, the width of each second through electrode 133 may be greater than the width of each first through electrode 115. For example, in a first direction (e.g., the X or Y direction) parallel to the upper surface 110US of the lower semiconductor device 110, the horizontal width 133W of each second through electrode 133 may be greater than the horizontal width 115W of each first through electrode 115. In an exemplary embodiment, the horizontal width 133W of each second through electrode 133 may be between approximately 10 μm and approximately 20 μm. In an exemplary embodiment, the horizontal width 115W of each first through electrode 115 may be between approximately 1 μm and approximately 7 μm.

[0066] In an exemplary embodiment, the width of each second through electrode 133 may be greater than the width of each first through electrode 115, thus power can be stably supplied to the upper semiconductor device 120. Furthermore, since the second through electrodes 133 can be formed using inexpensive processes, the manufacturing cost of the semiconductor package 10 can be reduced.

[0067] In an exemplary embodiment, the width of each second upper connection bump 153 connected to the second through electrode 133 may differ from the width of each first upper connection bump 151 connected to the first through electrode 115. For example, the width of each second upper connection bump 153 connected to the second through electrode 133 may be greater than the width of each first upper connection bump 151 connected to the first through electrode 115. For example, in a first direction parallel to the upper surface 110US of the lower semiconductor device 110, the maximum horizontal width 153W of each second upper connection bump 153 may be greater than the maximum horizontal width 151W of each first upper connection bump 151.

[0068] In an exemplary embodiment, the width of each second upper bump pad 135 connected to the second upper connection bump 153 may be greater than the width of each first upper bump pad 117 connected to the first upper connection bump 151. For example, in a first direction parallel to the upper surface 110US of the lower semiconductor device 110, the horizontal width 135W of each second upper bump pad 135 may be greater than the horizontal width 117W of each first upper bump pad 117. Additionally, the width of each second bump pad 127 of the upper semiconductor device 120 connected to the second upper connection bump 153 may be greater than the width of each first bump pad 125 of the upper semiconductor device 120 connected to the first upper connection bump 151. For example, in a first direction parallel to the upper surface 110US of the lower semiconductor device 110, the horizontal width 127W of each second bump pad 127 may be greater than the horizontal width 125W of each first bump pad 125.

[0069] In an exemplary embodiment, the width of each second lower connecting bump 157 connected to the second through electrode 133 may be different from the width of each first lower connecting bump 155 connected to the first through electrode 115. For example... Figure 4 and Figure 5 As shown, the width of each second lower connecting bump 157 connected to the second through electrode 133 can be greater than the width of each first lower connecting bump 155 connected to the first through electrode 115. For example, in a first direction parallel to the upper surface 110US of the lower semiconductor device 110, the maximum horizontal width 157W of each second lower connecting bump 157 can be greater than the maximum horizontal width 155W of each first lower connecting bump 155.

[0070] In an exemplary embodiment, the width of each second lower bump pad 147 connected to the second lower connection bump 157 may differ from the width of each first lower bump pad 145 connected to the first lower connection bump 155. For example, the width of each second lower bump pad 147 connected to the second lower connection bump 157 may be greater than the width of each first lower bump pad 145 connected to the first lower connection bump 155. For example, in a first direction parallel to the upper surface 110US of the lower semiconductor device 110, the horizontal width 147W of each second lower bump pad 147 may be greater than the horizontal width 145W of each first lower bump pad 145.

[0071] In various exemplary embodiments, when the upper semiconductor device 120 is a logic chip and the lower semiconductor device 110 is a memory chip, the heat dissipation characteristics of the semiconductor package 10 can be improved because the logic chip is positioned on the upper side of the semiconductor package 10, which facilitates heat dissipation. Furthermore, since power can be supplied to the logic chip using the wide second through electrode 133 of the connecting substrate 130, power can be stably supplied to the logic chip.

[0072] Figures 6A to 6C This is a top view showing an exemplary layout of the lower semiconductor device 110 and the interconnect substrate 130 in the semiconductor package 10.

[0073] Reference Figure 6A as well as Figure 1 The lower semiconductor device 110 and two connecting substrates 130 can be disposed on the lower surface 120LS of the upper semiconductor device 120. The lower semiconductor device 110 can be disposed at the center of the lower surface 120LS of the upper semiconductor device 120, and the two connecting substrates 130 can be spaced apart from each other by the lower semiconductor device 110 between them. The two connecting substrates 130 can extend along two opposite edges of the lower semiconductor device 110, respectively. Figure 6A The diagram shows two interconnect substrates 130 arranged in a semiconductor package 10. However, the exemplary embodiments are not limited to this, and in some exemplary embodiments, three or more interconnect substrates 130 may be arranged in the semiconductor package 10.

[0074] Reference Figure 6B On the lower surface 120LS of the upper semiconductor device 120, a lower semiconductor device 110 and two connecting substrates 130 are arranged, and the two connecting substrates 130 can extend along two adjacent edges of the lower semiconductor device 110, respectively.

[0075] Reference Figure 6COn the lower surface 120LS of the upper semiconductor device 120, a lower semiconductor device 110 and a connecting substrate 130 can be disposed. The connecting substrate 130 can extend along two adjacent edges of the lower semiconductor device 110 and can be bent. For example, as Figure 6C As shown, the connecting substrate 130 may have an L-shape.

[0076] Figure 7 This is a cross-sectional view of a semiconductor package 10a according to various exemplary embodiments.

[0077] Except for the first molding layer 163 exposing a portion of the side surface of the connecting substrate 130a. Figure 7 The semiconductor package 10a shown can be used with Figure 1 The semiconductor package 10 shown is the same as or similar to that described below. The following description will primarily focus on... Figure 7 The semiconductor package 10a shown in the figure and Figure 1 The differences between the semiconductor packages 10 shown in the figure.

[0078] Reference Figure 7 The first molding layer 163 may cover certain portions of the side surface of the connecting substrate 130a or may not cover other portions of the side surface of the connecting substrate 130a. For example, the second side surface of the connecting substrate 130a opposite to the first side surface facing the lower semiconductor device 110 may not be covered by the first molding layer 163. In some exemplary embodiments, the second side surface of the connecting substrate 130a may be coplanar with the side surface of the upper semiconductor device 120.

[0079] Figure 8 This is a cross-sectional view of a semiconductor package 10b according to various exemplary embodiments.

[0080] Except for omitting the connecting substrate 130 ( Figure 1 Furthermore, the lower semiconductor device 110a includes a second through electrode 133 respectively connected to the substrate 130. Figure 1 In addition to the third through electrode 116 corresponding to ) Figure 8 The semiconductor package 10b shown can be used with Figure 1 The semiconductor package 10 shown is the same as or similar to that described below. The following description will primarily focus on... Figure 8 The semiconductor package 10b shown in the figure and Figure 1 The differences between the semiconductor packages 10 shown in the figure.

[0081] Reference Figure 8 The planar area of ​​the lower semiconductor device 110a can be equal to the planar area of ​​the upper semiconductor device 120. In this case, the side surface of the lower semiconductor device 110a can be coplanar with the side surface of the upper semiconductor device 120.

[0082] The lower semiconductor device 110a may include a first through electrode 115 and a third through electrode 116.

[0083] The first through electrode 115 may be disposed in, for example, the central portion of the lower semiconductor device 110a. The first through electrode 115 may be electrically connected to a first lower connecting bump 155 and a first upper connecting bump 151, respectively, and may be electrically connected to the upper semiconductor device 120 through the first upper connecting bump 151. In an exemplary embodiment, the first through electrode 115 may be used for signal transmission between an external device and the lower semiconductor device 110a or between an external device and the upper semiconductor device 120.

[0084] The third through electrode 116 may be disposed, for example, in the edge portion of the lower semiconductor device 110a. The third through electrode 116 may be electrically connected to the second lower connecting bump 157 and the second upper connecting bump 153, respectively, and may be electrically connected to the upper semiconductor device 120 through the second upper connecting bump 153. In an exemplary embodiment, the third through electrode 116 may be used to supply power to the upper semiconductor device 120.

[0085] The width of each third through electrode 116 may be greater than the width of each first through electrode 115. For example, in a first direction parallel to the upper surface 110US of the lower semiconductor device 110a, the horizontal width of each third through electrode 116 may be greater than the horizontal width of each first through electrode 115.

[0086] Additionally, the lower semiconductor device 110a may include a first upper bump pad 117 and a third upper bump pad 118, with first upper connection bumps 151 respectively attached to the first upper bump pad 117 and second upper connection bumps 153 respectively attached to the third upper bump pads 118. In an exemplary embodiment, the width of each third upper bump pad 118 connected to the second upper connection bump 153 may be greater than the width of each first upper bump pad 117 connected to the first upper connection bump 151.

[0087] In an exemplary embodiment, Figure 8 The semiconductor package 10b shown can be formed by a wafer-to-wafer bonding process between a lower wafer including a lower semiconductor device 110a and an upper wafer including an upper semiconductor device 120. When the lower wafer and the upper wafer are bonded by a direct wafer bonding method, the insulating adhesive layer 161, the first upper connection bump 151 and the second upper connection bump 153 can be omitted.

[0088] Figure 9 This is a cross-sectional view showing a semiconductor package 10c according to various exemplary embodiments.

[0089] In addition to the semiconductor package 10c, it also includes a second redistribution structure 170. Figure 9 The semiconductor package 10c shown can be used with Figure 1 The semiconductor package 10 shown is the same as or similar to that shown. In the following text, it will be mainly described... Figure 9 The semiconductor package 10c shown in the figure and Figure 1 The differences between the semiconductor packages 10 shown in the figure.

[0090] Reference Figure 9 The planar area of ​​the upper semiconductor device 120 can be similar to that of the lower semiconductor device 110. For example, in some exemplary embodiments, the planar area of ​​the upper semiconductor device 120 can be smaller than that of the lower semiconductor device 110. The second redistribution structure 170 can be disposed between the upper semiconductor device 120 and the lower semiconductor device 110, and between the upper semiconductor device 120 and the interconnect substrate 130. The second redistribution structure 170 may include a second redistribution pattern 172 and a second redistribution insulating layer 179.

[0091] The second redistribution insulating layer 179 can contact the lower surface 120LS of the upper semiconductor device 120 and the lower surface of the molding layer 165 surrounding the side surface of the upper semiconductor device 120. The second redistribution insulating layer 179 can electrically insulate the various components included in the second redistribution structure 170 from each other.

[0092] The second redistribution pattern 172 can electrically connect the first pad 128 of the upper semiconductor device 120 to the first upper connection bump 151, and can electrically connect the second pad 129 of the upper semiconductor device 120 to the second upper connection bump 153. For example, the second redistribution pattern 172 may include a conductive line pattern 171 extending in the horizontal direction and a conductive path pattern 173 extending in the vertical direction.

[0093] Additionally, the second redistribution pattern 172 may include a fourth upper bump pad 175 and a fifth upper bump pad 177, with first upper connecting bumps 151 respectively attached to the fourth upper bump pad 175 and second upper connecting bumps 153 respectively attached to the fifth upper bump pad 177. At least a portion of the fourth upper bump pad 175 and at least a portion of the fifth upper bump pad 177 may protrude from the lower surface of the second redistribution insulating layer 179. In an exemplary embodiment, the width of each fifth upper bump pad 177 connected to the second upper connecting bump 153 may be greater than the width of each fourth upper bump pad 175 connected to the first upper connecting bump 151.

[0094] Figure 10 This is a cross-sectional view of a semiconductor package 10d according to various exemplary embodiments.

[0095] In addition to the lower semiconductor device 110 being flipped, Figure 10 The semiconductor package 10d shown can be used with Figure 1 The semiconductor package 10 shown is the same as or similar to that described below. The following description will primarily focus on... Figure 10 The semiconductor package 10d shown in the figure is... Figure 1 The differences between the semiconductor packages 10 shown in the figure.

[0096] Reference Figure 10 The lower semiconductor device 110 can be arranged such that the first surface 111F of the first semiconductor substrate 111 faces the first redistribution structure 140 and the second surface 111B of the first semiconductor substrate 111 faces the second upper semiconductor device 120. A first semiconductor device layer 113 located on the first surface 111F of the first semiconductor substrate 111 can be located in the lower portion of the lower semiconductor device 110 adjacent to the first redistribution structure 140, and a first back cover protective layer 119 located on the second surface 111B of the first semiconductor substrate 111 can be located in the upper portion of the lower semiconductor device 110 adjacent to the upper semiconductor device 120. Because the first semiconductor device layer 113 is disposed in the lower portion of the lower semiconductor device 110, the length of the signal transmission path between the external device and the lower semiconductor device 110 can be reduced.

[0097] Figure 11 This is a cross-sectional view of a semiconductor package 10e according to various exemplary embodiments.

[0098] Except for omitting the first upper connecting bump 151 and the second upper connecting bump 153, and including the third redistribution structure 190, Figure 11 The semiconductor package 10e shown can be used with Figure 1 The semiconductor package 10 shown is the same as or similar to that described below. The following description will primarily focus on... Figure 11 The semiconductor package 10e shown in the figure and Figure 1 The differences between the semiconductor packages 10 shown in the figure.

[0099] Reference Figure 11 The third redistribution structure 190 may be disposed on the top surface 110US of the lower semiconductor device 110, the upper surface 130US of the connecting substrate 130, and the first molding layer 163. The first molding layer 163 may surround the side surfaces of the lower semiconductor device 110 and the side surfaces of the connecting substrate 130. The third redistribution structure 190 may include a third redistribution pattern 192 and a third redistribution insulating layer 199.

[0100] The third redistribution insulating layer 199 may cover the upper surface 110US of the lower semiconductor device 110, the upper surface 130US of the connecting substrate 130, and the upper surface of the first molding layer 163. The third redistribution insulating layer 199 may electrically insulate the various components included in the third redistribution structure 190 from each other.

[0101] The third redistribution pattern 192 can electrically connect the lower semiconductor device 110 to the upper semiconductor device 120, and can electrically connect the second through electrode 133 of the connecting substrate 130 to the upper semiconductor device 120. For example, the third redistribution pattern 192 may include a conductive line pattern 191 extending in the horizontal direction and a conductive path pattern 193 extending in the vertical direction.

[0102] On the third redistribution structure 190, an upper semiconductor device 120 and a molding layer 167 covering at least a portion of the upper semiconductor device 120 may be disposed. Between the upper semiconductor device 120 and the third redistribution pattern 192 exposed on the upper side of the third redistribution insulating layer 199, a connection bump 168 for electrically connecting the upper semiconductor device 120 to the third redistribution pattern 192 may be disposed. For example, a first pad 128 of the upper semiconductor device 120 may be electrically connected to a first through electrode 115 of the lower semiconductor device 110 via the connection bump 168 and the third redistribution pattern 192. A second pad 129 of the upper semiconductor device 120 may be electrically connected to a second through electrode 133 of the connecting substrate 130 via the connection bump 168 and the third redistribution pattern 192.

[0103] Figure 12 This is a cross-sectional view of a semiconductor package 10f according to various exemplary embodiments.

[0104] In addition to the packaging substrate 200, the second molding layer 169, and the heat dissipation component 180, it also includes... Figure 12 The semiconductor package 10f shown can be used with Figure 1 The semiconductor package 10 shown is the same as or similar to that described below. The following description will primarily focus on... Figure 12 The semiconductor package 10f shown in the figure and Figure 1 The differences between the semiconductor packages 10 shown in the figure.

[0105] Reference Figure 12The packaging substrate 200 can be a printed circuit board (PCB). The packaging substrate 200 may include a substrate base 210 formed of at least one of phenolic resin, epoxy resin, or polyimide or similar materials. Additionally, the packaging substrate 200 may include a first upper substrate pad 221 and a second upper substrate pad 223 disposed on the upper surface of the substrate base 210, and a lower substrate pad 230 disposed on the lower surface of the substrate base 210. The first upper substrate pad 221, the second upper substrate pad 223, and the lower substrate pad 230 may be formed of, for example, Cu, Ni, or Al. Internal wiring (not shown) may be formed in the substrate base 210 for electrically connecting the first upper substrate pad 221 to the lower substrate pad 230 and the second upper substrate pad 223 to the lower substrate pad 230.

[0106] A first lower connection bump 155 may be disposed between the package substrate 200 and the lower semiconductor device 110. More specifically, the first lower connection bump 155 may be disposed between the first upper substrate pad 221 and the first lower bump pad 145 of the package substrate 200, and the first upper substrate pad 221 may be electrically connected to the first lower bump pad 145. The first lower connection bump 155 may be used for signal transmission between the package substrate 200 and the lower semiconductor device 110 or between the package substrate 200 and the upper semiconductor device 120. In an exemplary embodiment, power supplied by an external device may be supplied to the lower semiconductor device 110 through the package substrate 200, the first lower connection bump 155, and the first through electrode 115.

[0107] The second lower connection bump 157 can be disposed between the package substrate 200 and the connection substrate 130. More specifically, the second lower connection bump 157 can be disposed between the second upper substrate pad 223 and the second lower bump pad 147 of the package substrate 200, and can electrically connect the second upper substrate pad 223 and the second lower bump pad 147. The second lower connection bump 157 can be used for signal transmission between the package substrate 200 and the upper semiconductor device 120. In an exemplary embodiment, power supplied by an external device can be supplied to the upper semiconductor device 120 through the package substrate 200, the second lower connection bump 157, and the second through electrode 133.

[0108] External connection terminals 300 can be attached to the lower surface of the package substrate 200. External connection terminals 300 can be attached to the pads 230 of the lower substrate. External connection terminals 300 can be, for example, solder balls or bumps. External connection terminals 300 can electrically connect the semiconductor package 10f to external devices.

[0109] The second molding layer 169 may fill the gap between the first redistribution structure 140 and the package substrate 200. Additionally, the second molding layer 169 may surround the side surface of the first molding layer 163 and the side surface of the upper semiconductor device 120. The second molding layer 169 may contact the side surface of the upper semiconductor device 120 and the side surface of the first molding layer 163. The second molding layer 169 may comprise an epoxy-based molding resin or a polyimide-based molding resin. For example, in some exemplary embodiments, the second molding layer 169 may include EMC. The second molding layer 169 may be formed, for example, by a molding underfill process.

[0110] A heat dissipation component 180 may be disposed on the upper surface of the upper semiconductor device 120. For example, the heat dissipation component 180 may comprise a material having high thermal conductivity. The heat dissipation component 180 may be, for example, a heat sink, a vapor chamber, or a heat pipe. Although in Figure 12 The space between the heat sink 180 and the upper semiconductor device 120 is not shown in detail, but a thermal interface material (TIM) can be disposed between them. The TIM can enhance the physical and thermal bonding between the heat sink 180 and the upper semiconductor device 120.

[0111] Figure 13 This is a cross-sectional view of a semiconductor package 10g according to various exemplary embodiments.

[0112] In addition to the shape of the second molding layer 169a Figure 13 The semiconductor package 10g shown can be used with Figure 12 The semiconductor package 10f shown is the same as or similar to that described below. The following will primarily describe... Figure 13 The semiconductor package 10g shown in the image is... Figure 12 The differences between the semiconductor packages 10f shown in the figure.

[0113] Reference Figure 13 The second molding layer 169a can expose at least a portion of the side surface of the upper semiconductor device 120. That is, the second molding layer 169a can completely or partially expose the side surface of the upper semiconductor device 120. For example, the second molding layer 169a can be formed by a capillary underfill process. Because at least a portion of the side surface of the upper semiconductor device 120 is exposed, the heat dissipation characteristics of the upper semiconductor device 120 can be improved.

[0114] Figures 14A to 14M This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to various exemplary embodiments. In the following, reference is made to... Figures 14A to 14M , will describe manufacturing Figure 12 The method of semiconductor package 10f is shown in the figure. For the sake of brevity, the previously given description will be omitted or simplified.

[0115] Reference Figure 14A A first semiconductor wafer W1 is provided. The first semiconductor wafer W1 may be formed from a plurality of semiconductor devices divided by a first scribe line SL1. Each semiconductor device includes a first semiconductor substrate 111, a first semiconductor device layer 113, and a first through electrode 115. The first semiconductor substrate 111 may include a first surface 111F and a second surface 111B' opposite to each other. The first semiconductor device layer 113 may be formed on the first surface 111F of the first semiconductor substrate 111. The first through electrode 115 may extend from the first surface 111F of the first semiconductor substrate 111 into the interior of the first semiconductor substrate 111 and may be columnar.

[0116] Reference Figure 14B On the first surface 111F of the first semiconductor substrate 111, a first upper bump pad 117 electrically connected to the first through electrode 115 can be formed, and a first upper connection bump 151 is formed on the first upper bump pad 117.

[0117] Reference Figure 14C A first semiconductor wafer W1, on which a first upper connection bump 151 is formed, is attached to a carrier substrate 510. The carrier substrate 510 may include a support substrate 511 and an adhesive material 513 located on the support substrate 511. The first semiconductor wafer W1 may be attached to the carrier substrate 510 such that the first upper connection bump 151 faces the carrier substrate 510. The adhesive material 513 may surround the first upper bump pad 117.

[0118] Reference Figure 14D A portion of the first through electrode 115 can be exposed by removing a portion of the first semiconductor substrate 111. Since a portion of the first semiconductor substrate 111 has been removed, the first through electrode 115 passes through the first semiconductor substrate 111. Selectively, as... Figure 14D As shown, the first through electrode 115 can protrude from the second surface 111B of the first semiconductor substrate 111.

[0119] To expose the first through electrode 115, a portion of the first semiconductor substrate 111 can be removed by using a chemical mechanical polishing (CMP) process, an etch-back process, or a combination of the above processes.

[0120] Reference Figure 14EA first back cover protective layer 119 is formed covering the second surface 111B of the first semiconductor wafer W1. The first back cover protective layer 119 can be formed by, for example, a spin coating process or a spray coating process. The first back cover protective layer 119 can be formed of, for example, an insulating polymer. In order to form the first back cover protective layer 119, an insulating polymer layer can be formed covering the second surface 111B of the first semiconductor substrate 111 and the first through electrode 115, and the first through electrode 115 can be exposed by partially removing the insulating polymer layer. For example, a portion of the insulating polymer layer can be removed by an etch-back process.

[0121] Reference Figure 14E and Figure 14F After forming the first back protective layer 119, a sawing process is performed to cut the first semiconductor wafer W1 along the first dicing track SL1. Through the sawing process, the first semiconductor wafer W1 can be divided into multiple lower semiconductor devices 110. Additionally, the support substrate 511 can be removed.

[0122] Reference Figure 14G A second semiconductor wafer W2 is provided. The second semiconductor wafer W2 may be formed from a plurality of second semiconductor devices divided by a second dicing track SL2. Each second semiconductor device includes a second semiconductor substrate 121, a second semiconductor device layer 123, a first bump pad 125, and a second bump pad 127. The second semiconductor substrate 121 may include a first surface 121F and a second surface 121B opposite to each other. The second semiconductor device layer 123 may be formed on the first surface 121F of the second semiconductor substrate 121.

[0123] Reference Figure 14H It can be stacked on the second semiconductor wafer W2 Figure 14F The diagram shows a lower semiconductor device 110 and a connection substrate 130. The lower semiconductor device 110 can be positioned on a first bump pad 125 of the second semiconductor wafer W2, and a first upper connection bump 151 can be disposed between the first bump pad 125 and the first upper bump pad 117 of the lower semiconductor device 110. The connection substrate 130 is positioned on a second bump pad 127 of the second semiconductor wafer W2, and a second upper connection bump 153 can be disposed between the second bump pad 127 and the second upper bump pad 135 of the connection substrate 130. An insulating adhesive layer 161 can be formed on one surface of the lower semiconductor device 110 and one surface of each connection substrate 130. The insulating adhesive layer 161 can be, for example, NCF.

[0124] After the lower semiconductor device 110 and the connection substrate 130 are disposed on the second semiconductor wafer W2, a reflow process or a thermal compression process can be performed. Through the reflow process or the thermal compression process, the first upper connection bump 151 can be attached to the first upper bump pad 117 and the first bump pad 125, and the second upper connection bump 153 can be attached to the second upper bump pad 135 and the second bump pad 127.

[0125] Reference Figure 14I A first molding layer 163 for molding the lower semiconductor device 110 and the interconnect substrate 130 is formed on the second semiconductor wafer W2. In order to form the first molding layer 163, molding material can be supplied to the second semiconductor wafer W2, and the molding material can be hardened by a hardening process.

[0126] The first molding layer 163 may cover the side surface of the lower semiconductor device 110 and the side surface of the connecting substrate 130, but may not cover one surface of the lower semiconductor device 110 facing the second semiconductor wafer W2 and one surface of each connecting substrate 130 facing the second semiconductor wafer W2. For example, to form the first molding layer 163, a molding material may be formed covering the lower semiconductor device 110 and the connecting substrate 130, and the molding material may be removed by a planarization process such as CMP until said one surface of the lower semiconductor device 110 and said one surface of each connecting substrate 130 are exposed. Alternatively, in some exemplary embodiments, to form the first molding layer 163, a molding film may be disposed on said one surface of the lower semiconductor device 110 and said one surface of each connecting substrate 130, and then the molding material injected between the molding film and the second semiconductor wafer W2 may be hardened.

[0127] Reference Figure 14J A first redistribution structure 140 may be formed on the upwardly exposed surface of the lower semiconductor device 110 and on the upwardly exposed surface of each connection substrate 130. After forming the first redistribution structure 140, a first lower connection bump 155 is formed on the first lower bump pad 145 and a second lower connection bump 157 is formed on the second lower bump pad 147.

[0128] Reference Figure 14K Perform dicing along the second dicing track SL2 of the second semiconductor wafer W2. Figure 14J The sawing process of the obtained material. Through the sawing process, the material can be... Figure 14J The obtained materials are divided into, for example Figure 1 The individualized semiconductor package 10 shown.

[0129] Reference Figure 14L Stacked on the packaging substrate 200 Figure 14KThe resulting material. A first lower connecting bump 155 can be positioned on a first upper substrate pad 221 of the packaging substrate 200, and a second lower connecting bump 157 can be positioned on a second upper substrate pad 223 of the packaging substrate 200. The first lower connecting bump 155 can be attached to the first upper substrate pad 221, and the second lower connecting bump 157 can be attached to the second upper substrate pad 223, through a reflow process or a thermocompression process.

[0130] Reference Figure 14M A second molding layer 169 can be formed on the packaging substrate 200. The second molding layer 169 can fill the space between the first redistribution structure 140 and the packaging substrate 200, and can cover the side surfaces of the first molding layer 163 and the side surfaces of the first redistribution structure 140. For example, the second molding layer 169 can be formed by a molding underfill process.

[0131] After the second molding layer 169 is formed, the heat dissipation member 180 can be attached to the upper semiconductor device 120. For example, the heat dissipation member 180 can be located between the heat dissipation member 180 and the upper semiconductor device 120, and the heat dissipation member 180 can be physically bonded to the upper semiconductor device 120 via the heat dissipation member 180.

[0132] In an exemplary embodiment, when the upper semiconductor device 120 is a logic chip and the lower semiconductor device 110 is a memory chip, the heat dissipation characteristics of the semiconductor package 10 can be improved because the heat dissipation member 180 is attached to the logic chip, which generates a relatively large amount of heat. Furthermore, since power supplied by an external device is supplied to the logic chip through the second through electrodes 133 of the connecting substrate 130, each having a large width, power can be stably supplied to the logic chip.

[0133] Figures 15A to 15C This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to various exemplary embodiments. In the following description, references to... Figures 14A to 14M The method and reference described for manufacturing semiconductor package 10f Figures 15A to 15C The differences between the methods described for manufacturing semiconductor packages.

[0134] Reference Figure 15A A lower semiconductor device 110 and a connecting substrate 130 can be stacked on the second semiconductor wafer W2. At this time, in the lower semiconductor device 110, with... Figure 14B Similarly, the first through electrode 115 is not exposed through the second surface 111B' of the first semiconductor substrate 111.

[0135] Reference Figure 15BA first molding layer 163 is formed on the second semiconductor wafer W2 for molding the lower semiconductor device 110 and the interconnect substrate 130. The first molding layer 163 can cover the lower semiconductor device 110 and the interconnect substrate 130.

[0136] Reference Figure 15C A polishing process can be performed on the first molding layer 163, the lower semiconductor device 110, and the interconnect substrate 130 to expose the first through electrode 115. For example, a CMP process can be performed on the first molding layer 163, the lower semiconductor device 110, and the interconnect substrate 130. Through the CMP process, the first through electrode 115 of the lower semiconductor device 110 can be exposed through the second surface 111B of the first semiconductor substrate 111. In addition, through the CMP process, a planarized surface can be obtained on the first molding layer 163, the lower semiconductor device 110, and the interconnect substrate 130.

[0137] After performing the grinding process, further processing with... Figures 14J to 14M The same or similar processes can be used to manufacture semiconductor packages.

[0138] Although various embodiments have been specifically shown and described above, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of this disclosure as defined in the appended claims.

Claims

1. A semiconductor package comprising: a package substrate; a lower semiconductor device disposed on the package substrate and including a plurality of first through electrodes; a plurality of first lower connection bumps disposed between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the plurality of first through electrodes; a connection substrate disposed on the package substrate and spaced apart from the lower semiconductor device in a horizontal direction, and including a plurality of second through electrodes; a plurality of second lower connection bumps disposed between the package substrate and the connection substrate and electrically connecting the package substrate to the plurality of second through electrodes; and an upper semiconductor device disposed on the lower semiconductor device and electrically connected to the plurality of first through electrodes and the plurality of second through electrodes, wherein the lower semiconductor device includes: a substrate including a first surface facing the upper semiconductor device and a second surface opposite the first surface; and a semiconductor device layer disposed on the first surface or the second surface of the substrate. The upper semiconductor device is configured to receive power through the plurality of second through electrodes.

2. The semiconductor package of claim 1, wherein, A second horizontal width of each of the plurality of second through electrodes is greater than a first horizontal width of each of the plurality of first through electrodes.

3. The semiconductor package of claim 1, wherein, The first horizontal width is 1 to 7 μm, and the second horizontal width is 10 to 20 μm.

4. The semiconductor package of claim 3, wherein, A second horizontal width of each of the plurality of second lower connection bumps is greater than a first horizontal width of each of the plurality of first lower connection bumps.

5. The semiconductor package of claim 1, wherein, 6.The semiconductor package of claim 1, further comprising: a plurality of first lower bump pads respectively electrically connected to the plurality of first through electrodes, the plurality of first lower connection bumps respectively attached to the plurality of first lower bump pads; and a plurality of second lower bump pads respectively electrically connected to the plurality of second through electrodes, the plurality of second lower connection bumps respectively attached to the plurality of second lower bump pads, wherein a second horizontal width of each of the plurality of second lower bump pads is greater than a first horizontal width of each of the plurality of first lower bump pads. 7.The semiconductor package of claim 1, further comprising: a plurality of first upper connection bumps electrically connecting the upper semiconductor device to the plurality of first through electrodes; and a plurality of second upper connection bumps electrically connecting the upper semiconductor device to the plurality of second through electrodes. 8.The semiconductor package of claim 1, further comprising: ​ ​ a first molding layer surrounding side surfaces of the lower semiconductor device and side surfaces of the connection substrate; and a second molding layer surrounding side surfaces of the first molding layer and covering at least a portion of side surfaces of the upper semiconductor device. 9.The semiconductor package of claim 1, further comprising: a first redistribution insulating layer covering a lower surface of the lower semiconductor device, the lower surface of the lower semiconductor device being opposite to an upper surface of the lower semiconductor device facing the upper semiconductor device, and covering a lower surface of the connection substrate, the lower surface of the connection substrate being opposite to an upper surface of the connection substrate facing the upper semiconductor device; and a first redistribution pattern having at least a portion disposed in the first redistribution insulating layer, the first redistribution pattern electrically connecting the plurality of first lower connection bumps to the plurality of first through electrodes and electrically connecting the plurality of second lower connection bumps to the plurality of second through electrodes. 10.The semiconductor package of claim 1, further comprising: a second redistribution insulating layer covering an upper surface of the upper semiconductor device facing a lower surface of the lower semiconductor device; and a second redistribution pattern having at least a portion disposed in the second redistribution insulating layer, the second redistribution pattern electrically connecting the upper semiconductor device to the plurality of first through electrodes and electrically connecting the upper semiconductor device to the plurality of second through electrodes. 11.A semiconductor package comprising: a lower semiconductor device including a plurality of first through electrodes; a connection substrate spaced apart from the lower semiconductor device in a horizontal direction, and including a plurality of second through electrodes; an upper semiconductor device stacked on an upper surface of the lower semiconductor device and an upper surface of the connection substrate, the upper semiconductor device electrically connected to the plurality of first through electrodes and electrically connected to the plurality of second through electrodes; and a redistribution structure disposed on a lower surface of the lower semiconductor device and a lower surface of the connection substrate, the redistribution structure electrically connected to the plurality of first through electrodes and electrically connected to the plurality of second through electrodes, wherein the redistribution structure includes: a redistribution insulating layer; a plurality of first lower bump pads respectively electrically connected to the plurality of first through electrodes, the plurality of first lower bump pads at least partially protruding from the redistribution insulating layer; and a plurality of second lower bump pads respectively electrically connected to the plurality of second through electrodes, the plurality of second lower bump pads at least partially protruding from the redistribution insulating layer, and wherein a horizontal width of each of the plurality of second lower bump pads is different from a horizontal width of each of the plurality of first lower bump pads.

12. The semiconductor package of claim 11, wherein, A planar area of the upper semiconductor device is greater than a sum of a planar area of the lower semiconductor device and a planar area of the connection substrate.

13. The semiconductor package of claim 11, further comprising: a plurality of first lower connection bumps respectively on the plurality of first lower bump pads; and a plurality of second lower connection bumps respectively on the plurality of second lower bump pads, wherein a horizontal width of each of the plurality of first lower connection bumps is different from a horizontal width of each of the plurality of second lower connection bumps.

14. The semiconductor package of claim 11, further comprising a heat dissipation member on the upper semiconductor device.

15. The semiconductor package of claim 11, wherein, The lower semiconductor device includes a memory chip, and the upper semiconductor device includes a logic chip.

16. The semiconductor package of claim 11, further comprising: a plurality of first upper connection bumps arranged between the upper semiconductor device and the lower semiconductor device, the plurality of first upper connection bumps respectively electrically connected to the plurality of first through electrodes; and a plurality of second upper connection bumps arranged between the upper semiconductor device and the connection substrate, the plurality of second upper connection bumps respectively electrically connected to the plurality of second through electrodes, wherein a first horizontal width of each of the plurality of first upper connection bumps is different from a second horizontal width of each of the plurality of second upper connection bumps.

17. A semiconductor package, comprising: a package substrate; a memory chip arranged on the package substrate and including a plurality of first through electrodes; a connection substrate arranged on the package substrate and including a plurality of second through electrodes, each of the plurality of second through electrodes having a second width greater than a first width of each of the plurality of first through electrodes; a logic chip arranged on an upper surface of the memory chip and an upper surface of the connection substrate, the logic chip electrically connected to the plurality of first through electrodes and the plurality of second through electrodes; a heat dissipation member on the logic chip; a redistribution structure arranged on a lower surface of the memory chip and a lower surface of the connection substrate, the redistribution structure including a plurality of first lower bump pads respectively electrically connected to the plurality of first through electrodes, and including a plurality of second lower bump pads respectively electrically connected to the plurality of second through electrodes; a plurality of first lower connection bumps between the plurality of first lower bump pads and the package substrate; and a plurality of second lower connection bumps between the plurality of second lower bump pads and the package substrate, wherein the memory chip includes: a first substrate including a first surface facing the logic chip and a second surface opposite the first surface; and a first semiconductor device layer on the first surface of the first substrate, wherein the logic chip includes: a second substrate including a third surface facing the memory chip and a fourth surface opposite the third surface; and a second semiconductor device layer on the third surface of the second substrate, and wherein a planar area of the logic chip is greater than a sum of a planar area of the memory chip and a planar area of the connection substrate.

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