Semiconductor Structure and Method for Preparing the Same

Abstract

The present invention relates to a method for fabricating a semiconductor structure, comprising the following steps: providing a dielectric layer; forming a low dielectric constant material layer within or on the surface of the dielectric layer, and forming a wire layer within the dielectric layer, with the low dielectric constant material layer located at least between adjacent wire layers. This reduces the parasitic capacitance between adjacent copper wires in the same layer of the semiconductor structure, and the process is easy to operate and control. Therefore, the process can be accurately controlled to effectively reduce the parasitic capacitance between adjacent copper wires in the same layer of the semiconductor structure, improving the reliability and service life of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In the process of semiconductor manufacturing, as the feature size of integrated circuits decreases, the pitch of copper metal lines formed by the single damascene process is very small, and the resistivity of copper metal lines will increase sharply, especially at the process nodes of 90 nm and below; this will result in a large parasitic capacitance between adjacent copper metal lines, which has a great impact on the reliability and service life of the device. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same in view of the above technical problems.

[0004] A method for manufacturing a semiconductor structure includes the following steps:

[0005] Provide a dielectric layer;

[0006] Form a low-k dielectric material layer in or on the surface of the dielectric layer, and form a wire layer in the dielectric layer, and the low-k dielectric material layer is at least located between adjacent wire layers.

[0007] By the above method for manufacturing a semiconductor structure, the parasitic capacitance between adjacent copper wires in the same layer of the semiconductor structure is reduced, and the process is easy to operate and control. Therefore, the process can be accurately controlled to effectively reduce the parasitic capacitance between adjacent copper wires in the same layer of the semiconductor structure, and improve the reliability and service life of the device.

[0008] In one embodiment, forming the low-k dielectric material layer and the wire layer in the dielectric layer includes:

[0009] Form trenches in the dielectric layer;

[0010] Form a metal barrier layer on the sidewalls and bottom of the trenches;

[0011] Form the wire layer on the surface of the metal barrier layer, and the wire layer fills the trenches;

[0012] Form grooves on the dielectric layer, and the grooves are located between adjacent wire layers;

[0013] Form a low-k dielectric material layer at least on the sidewalls and bottom of the grooves.

[0014] In one embodiment, the longitudinal cross-sectional shape of the groove includes an inverted trapezoid.

[0015] In one embodiment, the bottom of the groove is not higher than the bottom of the wire layer.

[0016] In one embodiment, forming the low dielectric constant material layer and the wire layer in the dielectric layer includes:

[0017] Forming a trench in the dielectric layer;

[0018] Forming a low dielectric constant material layer on the sidewall of the trench;

[0019] Forming a metal barrier layer on the surface of the low dielectric constant material layer and the bottom of the trench;

[0020] Forming the wire layer on the surface of the metal barrier layer, and the wire layer fills the trench.

[0021] In one embodiment, forming the low dielectric constant material layer on the upper surface of the dielectric layer and forming the wire layer in the dielectric layer includes:

[0022] Forming a low dielectric constant material layer on the upper surface of the dielectric layer;

[0023] Forming a trench in the dielectric layer and the low dielectric constant material layer;

[0024] Forming a metal barrier layer on the sidewall and the bottom of the trench;

[0025] Forming the wire layer on the surface of the metal barrier layer, and the wire layer fills the trench.

[0026] In one embodiment, after forming the low dielectric constant material layer and the wire layer in the dielectric layer, the following steps are further included: forming a protective layer on the surface of the dielectric layer, and the protective layer covers the surfaces of the dielectric layer, the low dielectric constant material layer and the wire layer.

[0027] In one embodiment, characterized in that a conductive structure is formed in the provided dielectric layer, the trench exposes the conductive structure, and the wire layer is electrically connected to the conductive structure.

[0028] The present invention also provides a semiconductor structure, including:

[0029] A dielectric layer;

[0030] A wire layer, located in the dielectric layer;

[0031] A low dielectric constant material layer, located in the dielectric layer or on the upper surface of the dielectric layer, and at least located between adjacent wire layers.

[0032] In one embodiment, the low dielectric constant material layer is located within the dielectric layer, and the low dielectric constant material layer located between adjacent wire layers includes a horizontally connected portion and an inclined portion integrally connected thereto. The inclined portions are located on both sides of the horizontally connected portion, and the bottom of the inclined portion is connected to the horizontally connected portion.

[0033] In one embodiment, the horizontally connected portion is not higher than the bottom of the wire layer.

[0034] In one embodiment, the low dielectric constant material layer is located within the dielectric layer, around the wire layer, and between the wire layer and the dielectric layer.

[0035] In one embodiment, the low dielectric constant material layer is located on the upper surface of the dielectric layer, and the wire layer passes through the low dielectric constant material layer in the thickness direction and extends into the dielectric layer.

[0036] In one embodiment, it further includes:

[0037] A conductive structure located within the dielectric layer and below the wire layer;

[0038] A metal barrier layer located between the wire layer and the conductive structure and the dielectric layer or between the wire layer and the conductive structure and the low dielectric constant material layer. Description of the Drawings

[0039] Figure 1 It is a flowchart showing the manufacturing method of a semiconductor structure according to an embodiment of the present invention;

[0040] Figure 2 It is a flowchart showing the manufacturing method of a semiconductor structure according to another embodiment of the present invention;

[0041] Figure 3 It is a schematic cross-sectional structure diagram after providing a dielectric layer in an embodiment of the present invention;

[0042] Figure 4 It is a schematic cross-sectional structure diagram after forming a trench in an embodiment of the present invention;

[0043] Figures 5 to 6 It is a schematic cross-sectional structure diagram after forming a wire layer and a metal barrier layer in an embodiment of the present invention;

[0044] Figure 7 It is a schematic cross-sectional structure diagram after forming a trench in an embodiment of the present invention;

[0045] Figure 8 It is a schematic cross-sectional structure diagram after forming a low dielectric constant material layer in an embodiment of the present invention;

[0046] Figures 9 to 10 Schematic cross-sectional structure diagram of forming a protective layer in an embodiment of the present invention; wherein, Figure 10 It is also a schematic cross-sectional structure diagram of a semiconductor structure provided in an embodiment of the present invention;

[0047] Figure 11 Schematic cross-sectional structure diagram after forming a trench in another embodiment of the present invention;

[0048] Figures 12 to 13 Schematic cross-sectional structure diagram of forming a low-k dielectric layer in another embodiment of the present invention;

[0049] Figures 14 to 16 Schematic cross-sectional structure diagram of forming a wire layer and a metal barrier layer in another embodiment of the present invention;

[0050] Figure 17 Schematic cross-sectional structure diagram after forming a protective layer in another embodiment of the present invention; wherein, Figure 17 It is also a schematic cross-sectional structure diagram of a semiconductor structure provided in another embodiment of the present invention;

[0051] Figure 18 Schematic cross-sectional structure diagram after forming a low-k dielectric layer in still another embodiment of the present invention;

[0052] Figure 19 Schematic cross-sectional structure diagram after forming a trench in still another embodiment of the present invention;

[0053] Figures 20 to 22 Schematic cross-sectional structure diagram of forming a wire layer and a metal barrier layer in still another embodiment of the present invention;

[0054] Figure 23 Schematic cross-sectional structure diagram after forming a protective layer in still another embodiment of the present invention; wherein, Figure 23 It is also a schematic cross-sectional structure diagram of a semiconductor structure provided in still another embodiment of the present invention.

[0055] Reference numerals: 10, dielectric layer; 11, low-k dielectric layer; 12, wire layer; 13, conductive structure; 14, conductive metal layer; 15, barrier layer; 16, trench; 17, metal barrier layer; 18, groove; 19, protective layer. Detailed embodiments

[0056] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0058] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0059] To reduce the parasitic capacitance generated between copper wires in a semiconductor, as Figure 1 shown, the present invention provides a method for preparing a semiconductor structure, including the following steps:

[0060] Step S10: Provide a dielectric layer 10;

[0061] Step S20: Form a low dielectric constant material layer 11 inside or on the surface of the dielectric layer 10, and form a wire layer 12 inside the dielectric layer 10. The low dielectric constant material layer 11 is at least located between adjacent wire layers 12.

[0062] For step S10, as Figure 3 shown, in an alternative embodiment, the provided dielectric layer 10 can be formed of an oxide, which can be silicon dioxide. The dielectric layer 10 can include a conductive structure 13, and the conductive structure 13 can include a conductive metal layer 14 and a barrier layer 15. The conductive metal layer 14 can be aluminum, and the barrier layer 15 can be titanium or titanium nitride. The barrier layer 15 is located between the conductive metal layer 14 and the dielectric layer 10.

[0063] For step S20, in an alternative embodiment, it specifically includes the following steps:

[0064] Step S201: Form a trench 16 inside the dielectric layer 10, as Figure 4 shown.

[0065] Specifically, form a mask layer on the surface of the dielectric layer 10. The mask layer can be a photoresist layer. Pattern the mask layer by lithography and etching; etch the dielectric layer 10 according to the patterned mask layer to form the trench 16, and remove the mask layer; clean the residues inside the trench 16. The trench 16 exposes the conductive structure 13; specifically, the dielectric layer 10 can be etched by a dry etching process.

[0066] Step S202: Form a metal barrier layer 17 on the sidewalls and bottom of the trench 16, as Figure 5 shown.

[0067] Specifically, the metal barrier layer 17 is formed on the sidewalls and bottom wall of the trench 16 through a deposition process. The metal barrier layer 17 can be made of tantalum or tantalum nitride material, and the metal barrier layer 17 can alleviate the diffusion of metals such as copper into the dielectric layer 10.

[0068] Step S203: Form a wire layer 12 on the surface of the metal barrier layer 17. The wire layer 12 fills the trench 16, as Figure 5 and Figure 6 shown.

[0069] Specifically, the wire layer 12 can be made of metal copper. Electrochemical plating is used to grow metal copper on the surface of the metal barrier layer 17, and chemical mechanical polishing is used to polish the upper surface of the semiconductor structure until the upper surface of the dielectric layer 10 is exposed, retaining the metal copper and metal barrier material layer in the trench 16 to form the wire layer 12 and the metal barrier layer 17.

[0070] Step S204: Form a groove 18 on the dielectric layer 10. The groove 18 is located between adjacent wire layers 12, as Figure 7 shown.

[0071] Specifically, the dielectric layer 10 between adjacent wire layers 12 is etched away through a dry etching process or other etching processes with high selectivity to form the groove 18. The longitudinal cross-sectional shape of the groove 18 includes an inverted trapezoid, and the bottom of the groove 18 is not higher than the bottom of the wire layer 12.

[0072] Step S205: Form a low dielectric constant material layer 11 at least on the sidewalls and bottom of the groove 18, as Figure 8 shown.

[0073] Specifically, a deposition process is used to form the low dielectric constant material layer 11 on the upper surface of the dielectric layer 10, the bottom, and the sidewalls of the groove 18. The low dielectric constant material can be silicon carbonitride. In other alternative embodiments, the low dielectric constant material layer 11 can also be deposited on the top of the wire layer 12.

[0074] In other alternative embodiments, step S20 specifically includes the following steps:

[0075] Step S201: Form a trench 16 in the dielectric layer 10, as Figure 11 shown.

[0076] Specifically, a mask layer is formed on the surface of the dielectric layer 10. The mask layer can be a photoresist layer. The mask layer is lithographically etched to pattern the mask layer; the dielectric layer 10 is etched according to the patterned mask layer to form a trench 16; and the mask layer is removed; the residues in the trench 16 are cleaned. The trench 16 exposes the conductive structure 13; specifically, the trench 16 can be formed by a dry etching process.

[0077] Step S202: A low dielectric constant material layer 11 is formed on the sidewalls of the trench 16, such as Figure 12 and Figure 13 shown.

[0078] Specifically, a low dielectric constant material layer 11 is deposited on the sidewalls, bottom wall of the trench 16, and the upper surface of the dielectric layer 10. The low dielectric constant material layer 11 can be a silicon carbonitride layer. After the deposition of the low dielectric constant material layer 11 is completed, the low dielectric constant material layer 11 on the upper surface of the dielectric layer 10 and the low dielectric constant material layer 11 at the bottom of the trench 16 are removed, exposing the bottom wall of the trench 16 and the upper surface of the dielectric layer 10, and only the low dielectric constant material on the sidewalls of the trench 16 is retained; specifically, the low dielectric constant material layer 11 on the upper surface of the dielectric layer 10 and the low dielectric constant material layer 11 at the bottom of the trench 16 can be removed by an etch-back process.

[0079] Step S203: A metal barrier layer 17 is formed on the surface of the low dielectric constant material layer 11 and the bottom of the trench 16, such as Figure 14 shown.

[0080] Specifically, a metal barrier material layer is deposited on the surface of the low dielectric constant material layer 11, the bottom of the trench 16, and the upper surface of the dielectric layer 10. The metal barrier material layer can be tantalum or tantalum nitride, and the metal barrier material layer on the surface of the low dielectric constant material layer 11 and the bottom of the trench 16 forms the metal barrier layer 17.

[0081] Step S204: A wire layer 12 is formed on the surface of the metal barrier layer 17, and the wire layer 12 fills the trench 16, such as Figure 15 and Figure 16 shown.

[0082] Specifically, the wire layer 12 can be made of metallic copper. Metallic copper is grown on the surface of the metal barrier layer 17 by an electroplating process, and the upper surface of the semiconductor structure is polished by a chemical mechanical polishing process to remove the metallic copper and the metal barrier material layer on the upper surface of the dielectric layer 10, and the metallic copper and the metal barrier material layer in the trench 16 are retained to form the wire layer 12 and the metal barrier layer 17.

[0083] In other optional embodiments, step S20 specifically includes the following steps:

[0084] Step S201: Form a low dielectric constant material layer 11 on the upper surface of the dielectric layer 10, such as Figure 18 shown.

[0085] Adopt a deposition process to deposit and form a low dielectric constant material layer 11 on the upper surface of the dielectric layer 10. The low dielectric constant material layer 11 can be formed of silicon carbonitride.

[0086] Step S202: Form trenches 16 in the dielectric layer 10 and the low dielectric constant material layer 11, such as Figure 19 shown.

[0087] Specifically, form a mask layer on the upper surface of the low dielectric constant material layer 11. The mask layer can be a photoresist layer. Photolithographically etch the mask layer to pattern the mask layer, and the patterned mask layer exposes the low dielectric constant material layer 11; etch the low dielectric constant material layer 11 and the dielectric layer 10 based on the patterned mask layer to form trenches 16;; Remove the mask layer and clean the residues between the trenches 16. The trenches 16 expose the conductive structure 13; specifically, the trenches 16 can be formed by a dry etching process.

[0088] Step S203: Form a metal barrier layer 17 on the sidewalls and bottom of the trenches 16, such as Figure 20 shown.

[0089] Specifically, deposit and form a metal barrier material layer on the sidewalls, bottom, and upper surface of the low dielectric constant material layer 11 of the trenches 16. The metal barrier material layer on the sidewalls and bottom of the trenches 16 forms the metal barrier layer 17.

[0090] Step S204: Form a wire layer 12 on the surface of the metal barrier layer 17. The wire layer 12 fills the trenches 16, such as Figure 21 and Figure 22 shown.

[0091] Specifically, the wire layer 12 can be made of copper metal. Electrochemically deposit copper metal on the surface of the metal barrier layer 17, and polish the upper surface of the semiconductor structure by a chemical mechanical polishing process until the upper surface of the dielectric constant layer is exposed, and retain the copper metal and the metal barrier material layer in the trenches 16 to form the wire layer 12 and the metal barrier layer 17.

[0092] After step S20, there is also included step S30: Form a protective layer 19 on the surface of the dielectric layer 10. The protective layer 19 covers the surfaces of the dielectric layer 10, the low dielectric constant material layer 11, and the wire layer 12, such as Figure 10 , Figure 17 or Figure 23 shown.

[0093] Specifically, the protective layer 19 can be silicon nitride, and the protective layer 19 is formed by a deposition process, such as Figures 9 to 10As shown, in other alternative embodiments, the protective layer 19 may be a silicon dioxide material layer deposited on the low dielectric constant material layer 11, and the silicon dioxide material layer is planarized by a chemical mechanical polishing process to obtain the protective layer 19.

[0094] The present invention also provides a semiconductor structure, such as Figure 10 shown, including: a dielectric layer 10; a wire layer 12 located within the dielectric layer 10; a low dielectric constant material layer 11 located within the dielectric layer 10 or on the upper surface of the dielectric layer 10, and at least between adjacent wire layers 12.

[0095] The dielectric layer 10 may be formed of an oxide, which may be silicon dioxide, and the wire layer 12 may be formed of metallic copper. In an alternative embodiment, the dielectric layer 10 includes a conductive structure 13, and the conductive structure 13 includes a conductive metal layer 14 and a barrier layer 15, and the wire layer 12 is electrically connected to the conductive metal layer 14. The conductive metal layer 14 may be metallic aluminum, and the barrier layer 15 may be titanium or titanium nitride, and the barrier layer 15 is located between the conductive metal layer 14 and the dielectric layer 10.

[0096] Specifically, the low dielectric constant material layer 11 is located within the dielectric layer 10. The dielectric layer 10 may be formed of silicon dioxide, and the low dielectric constant material layer 11 may be formed of silicon carbonitride. The low dielectric constant material layer 11 located between two adjacent wire layers 12 includes a horizontally connected portion and an inclined portion integrally connected. The inclined portions are located on both sides of the horizontally connected portion, and the bottom of the inclined portion is connected to the horizontally connected portion, and the horizontally connected portion is not higher than the bottom of the wire layer 12. In other alternative embodiments, the low dielectric constant material layer 11 further includes a horizontally connected portion on the upper surface of the wire layer 12, and the two sides of the horizontally connected portion on the upper surface of the wire layer 12 are respectively integrally connected to the tops of the inclined portions on both sides of the wire layer 12.

[0097] Specifically, the semiconductor structure further includes a metal barrier layer 17, and the metal barrier layer 17 is located between the wire layer 12 and the dielectric layer 10, or between the wire layer 12 and the conductive structure 13 and the low dielectric constant material layer 11. The metal barrier layer 17 may be a tantalum layer or a tantalum nitride layer, which can prevent the diffusion of metallic copper into the dielectric layer 10.

[0098] As Figure 17 shown, in an alternative embodiment, the present invention also provides a semiconductor structure. The semiconductor structure provided in this embodiment is substantially the same as the semiconductor structure described in Figure 10 , and the difference between the two is the position of the low dielectric constant material layer 11. Compared with Figure 10In the semiconductor structure, in this embodiment, the low-k dielectric layer 11 is located within the dielectric layer 10, around the wire layer 12, and between the wire layer 12 and the dielectric layer 10. The upper surface of the low-k dielectric layer 11 is flush with the upper surface of the wire layer 12, and the lower surface is flush with the lower surface of the wire layer 12. A protective layer 19 is formed on the upper surface of the dielectric layer 10. The protective layer 19 can be a silicon nitride layer, formed by a deposition process, covering the dielectric layer 10, the wire layer 12, and the low-k dielectric layer 11. Other structures in the semiconductor structure of this embodiment are the same as those in Figure 10 the semiconductor structure in

[0099] As Figure 23 shown, in an alternative embodiment, the present invention also provides a semiconductor structure. The semiconductor structure provided in this embodiment is substantially the same as the semiconductor structure described in Figure 10 . The difference between the two lies in the different position of the low-k dielectric layer 11. Compared with the semiconductor structure in Figure 10 , in the semiconductor structure of this embodiment, the low-k dielectric layer 11 is located on the upper surface of the dielectric layer 10. The wire layer 12 passes through the low-k dielectric layer 11 in the thickness direction and extends into the dielectric layer 10. A protective layer 19 is formed on the surface of the low-k dielectric layer 11. The protective layer 19 can be a silicon nitride layer, formed by a deposition process, covering the wire layer 12 and the low-k dielectric layer 11. Other structures in the semiconductor structure of this embodiment are the same as those in Figure 10 the semiconductor structure in

[0100] In summary, through the low-k dielectric layer 11, the parasitic capacitance between adjacent copper wires in the same layer of the semiconductor structure is reduced, and the process is easy to operate and control. Therefore, the process can be accurately controlled to effectively reduce the parasitic capacitance between adjacent copper wires in the same layer of the semiconductor structure, improving the reliability and service life of the device.

[0101] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0102] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Comprising the following steps: Providing a dielectric layer; Forming a wire layer within the dielectric layer; Forming a groove on the dielectric layer, the groove being located between adjacent wire layers; Forming a low dielectric constant material layer at least on the side walls and bottom of the groove, the low dielectric constant material layer being at least located between adjacent wire layers, the low dielectric constant material layer within the dielectric layer and between adjacent wire layers comprising an integrally connected horizontal portion and inclined portions, the inclined portions being located on both sides of the horizontal portion, and the bottom of the inclined portion being connected to the horizontal portion; Forming a protective layer on the surface of the dielectric layer, the protective layer covering the surfaces of the dielectric layer, the low dielectric constant material layer and the wire layer, the protective layer comprising an embedded portion filling the groove, the bottom of the embedded portion being lower than the top surface of the wire layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein, Forming the wire layer within the dielectric layer comprises: Forming a trench within the dielectric layer; Forming a metal barrier layer on the side walls and bottom of the trench; Forming the wire layer on the surface of the metal barrier layer, the wire layer filling the trench.

3. The method for preparing a semiconductor structure according to claim 2, wherein, The longitudinal cross-sectional shape of the groove comprises an inverted trapezoid.

4. The method for preparing a semiconductor structure according to claim 2, wherein, The bottom of the groove is not higher than the bottom of the wire layer.

5. The method for preparing a semiconductor structure according to any one of claims 2 to 4, characterized in that, A conductive structure is formed within the provided dielectric layer, the trench exposing the conductive structure, and the wire layer is electrically connected to the conductive structure.

6. A semiconductor structure, characterized in that, Comprising: A dielectric layer; A wire layer, located within the dielectric layer, the material of the wire layer being copper; A groove, the groove being located between adjacent wire layers; A low dielectric constant material layer, at least located on the side walls and bottom of the groove, and at least located between adjacent wire layers; the low dielectric constant material layer within the dielectric layer and between adjacent wire layers comprises an integrally connected horizontal portion and inclined portions, the inclined portions being located on both sides of the horizontal portion, and the bottom of the inclined portion being connected to the horizontal portion; A protective layer, located on the surface of the dielectric layer and covering the surfaces of the dielectric layer, the low dielectric constant material layer and the wire layer, the protective layer comprising an embedded portion filling the groove, the bottom of the embedded portion being lower than the top surface of the wire layer.

7. The semiconductor structure according to claim 6, wherein: The horizontal portion is not higher than the bottom of the wire layer.

8. The semiconductor structure according to any one of claims 6 to 7, characterized in that, Further comprising: A conductive structure, located within the dielectric layer and below the wire layer; A metal barrier layer, located between the wire layer and the conductive structure and the dielectric layer or between the wire layer and the conductive structure and the low dielectric constant material layer.

Images