Semiconductor device

Abstract

A semiconductor device includes a substrate having a first active region; a first active pattern and a second active pattern extending in a first direction and spaced apart from each other in a second direction, and each having a source pattern, a channel pattern, and a drain pattern sequentially stacked; a first gate electrode and a second gate electrode surrounding the channel patterns of the first active pattern and the second active pattern and extending in the first direction; an interlayer dielectric layer covering the first active pattern and the second active pattern and the first gate electrode and the second gate electrode; a first active contact penetrating the interlayer dielectric layer and coupled with the first active region between the first active pattern and the second active pattern; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first active pattern and the second active pattern including an overlap region vertically overlapping the first power rail.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2019-0174078, entitled "Semiconductor Device", filed with the Korean Intellectual Property Office on December 24, 2019, is incorporated herein by reference in its entirety. Technical Field

[0003] The examples involve semiconductor devices. Background Technology

[0004] Semiconductor devices are advantageous in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices can include semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data operations, and hybrid semiconductor devices that incorporate both storage and logic elements. With the advancement of the electronics industry, semiconductor devices increasingly require high levels of integration. For example, there is a growing demand for high reliability, high speed, and / or versatility. Semiconductor devices are becoming increasingly complex and integrated to meet these requirements. Summary of the Invention

[0005] The embodiment relates to a semiconductor device, comprising: a substrate including a first active region; a first active pattern and a second active pattern on the first active region, the first active pattern and the second active pattern extending along a first direction and spaced apart from each other in a second direction intersecting the first direction, and each of the first active pattern and the second active pattern having sequentially stacked source pattern, channel pattern and drain pattern; a first gate electrode and a second gate electrode surrounding the channel pattern of the first active pattern and the second active pattern and extending along the first direction; an interlayer dielectric layer covering the first active pattern and the second active pattern and the first gate electrode and the second gate electrode; a first active contact penetrating the interlayer dielectric layer and coupled to the first active region between the first active pattern and the second active pattern; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first active pattern and the second active pattern including an overlapping region vertically overlapping the first power rail.

[0006] Embodiments relate to a semiconductor device including a substrate including a first active region; a first active pattern and a second active pattern on the first active region, the first active pattern and the second active pattern extending along a first direction and spaced apart from each other in a second direction intersecting the first direction, and the first active pattern and the second active pattern protruding in a vertical direction from a top surface of the substrate; a first gate electrode and a second gate electrode surrounding the first active pattern and the second active pattern and extending along the first direction, an upper portion of the first active pattern and the second active pattern protruding in the vertical direction above a top surface of the first gate electrode and the second gate electrode; an interlayer dielectric layer covering the first active pattern and the second active pattern and the first gate electrode and the second gate electrode; a first active contact penetrating the interlayer dielectric layer and coupled with the first active region between the first active pattern and the second active pattern; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, wherein, in a plan view, the first power rail spans the first active pattern and the second active pattern and extends along the second direction.

[0007] Embodiments relate to a semiconductor device including a first power rail, a second power rail, and a third power rail arranged along a first direction on a substrate; and a logic cell between the first power rail and the third power rail, the logic cell including a first active region adjacent to the first power rail, a second active region spanned by the second power rail, and a third active region adjacent to the third power rail; a first active pattern to a third active pattern on the first active region to the third active region, respectively, each of the first active pattern to the third active pattern having a bar shape extending along the first direction when viewed in a plan angle; and a gate electrode on the first active pattern to the third active pattern. Each of the first active pattern to the third active pattern can extend vertically from the substrate and penetrate the gate electrode, the first active pattern can have a first length in the first direction, the second active pattern can have a second length in the first direction, and the second length can be 2 to 5 times the first length. BRIEF DESCRIPTION OF DRAWINGS

[0008] Example embodiments are described in detail below with reference to the attached drawing figures, wherein:

[0009] Figure 1 , Figure 2 and Figure 3 shows a conceptual plan view showing a logic cell of a semiconductor device according to an example embodiment.

[0010] Figure 4 shows a plan view showing a semiconductor device according to an example embodiment.

[0011] Figure 5A , 5B , 5C, and 5D show, respectively, a cross-sectional view taken alongFigure 4 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0012] Figure 6A A perspective view is shown of a vertical transistor displayed on a first PMOSFET region and on a third PMOSFET region adjacent to the first PMOSFET region in a first direction.

[0013] Figure 6B A perspective view showing a vertical transistor on an NMOSFET region is shown.

[0014] Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 and Figure 17 A plan view of each stage in a method for manufacturing a semiconductor device according to an example embodiment is shown.

[0015] Figure 8A , Figure 10A , Figure 12A , Figure 14A , Figure 16A and Figure 18A The following are shown respectively along Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 and Figure 17 The cross-sectional view taken by line AA′ in the diagram.

[0016] Figure 8B , Figure 10B , Figure 12B , Figure 14B , Figure 16B and Figure 18B They respectively show along Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 and Figure 17 The cross-sectional view taken by line B-B'.

[0017] Figure 19 A plan view showing the arrangement of logic cells in a semiconductor device according to an example embodiment is shown. Detailed Implementation

[0018] Figure 1 , Figure 2 and Figure 3 A conceptual plan view showing the logic cells of a semiconductor device according to an example embodiment is shown.

[0019] refer to Figure 1A single height cell SHC can be provided, where height refers to a length of the single height cell SHC in a first horizontal direction D1. For example, a first power rail POR1 and a second power rail POR2 can be disposed on a substrate SUB. The first power rail POR1 can be a path or conductor provided with a drain voltage VDD (e.g., a power supply voltage). The second power rail POR2 can be a path or conductor provided with a source voltage VSS (e.g., a ground voltage).

[0020] A single height cell SHC can be defined between the first power rail POR1 and the second power rail POR2. The single height cell SHC can include one PMOSFET region PR and one NMOSFET region NR. For example, the single height cell SHC can have a CMOS structure disposed between the first power rail POR1 and the second power rail POR2.

[0021] Each of the PMOSFET region PR and the NMOSFET region NR can have a first width W1 in a first direction D1, which can be a first horizontal direction. A first height HE1 can be defined to indicate a length of the single height cell SHC in the first direction D1. The first height HE1 can be substantially the same as a distance (e.g., a pitch) between the first power rail POR1 and the second power rail POR2.

[0022] The single height cell SHC can constitute one logic cell. The logic cell can be a logic device (e.g., an inverter or a flip-flop) that performs a specific function. For example, the logic cell can include transistors that constitute the logic device, and can also include wiring that connects the transistors to each other.

[0023] Reference Figure 2 A double height cell DHC can be provided. For example, a first power rail POR1, a second power rail POR2, and a third power rail POR3 can be disposed on a substrate SUB. The first power rail POR1 to the third power rail POR3 can be sequentially arranged in a first direction D1. The third power rail POR3 can be a path or conductor provided with a drain voltage VDD.

[0024] A double height cell DHC can be defined between the first power rail POR1 and the third power rail POR3. The double height cell DHC can include a first PMOSFET region PR1, an NMOSFET region NR, and a second PMOSFET region PR2. The first PMOSFET region PR1 can be adjacent to the first power rail POR1, and the second PMOSFET region PR2 can be adjacent to the third power rail POR3. The NMOSFET region NR can overlap the second power rail POR2.

[0025] Each of the first PMOSFET region PR1 and the second PMOSFET region PR2 can have a first width W1 in the first direction D1. The NMOSFET region NR can have a second width W2 in the first direction D1. The second width W2 can be twice or three times the first width W1. A second height HE2 can be defined to indicate a length of the double height cell DHC in the first direction D1. The second height HE2 can be about twice the first height HE1. Figure 1

[0026] The NMOSFET region NR of the double height cell DHC can be greater than the NMOSFET region NR of the single height cell SHC discussed above (e.g., W2 > W1). Thus, a channel size of a transistor disposed on the NMOSFET region NR of the double height cell DHC can be greater than a channel size of a transistor disposed on the NMOSFET region NR of the single height cell SHC. Accordingly, the double height cell DHC can improve electrical characteristics of the semiconductor device. Figure 1

[0027] In example embodiments, both the first PMOSFET region PR1 and the second PMOSFET region PR2 can include PMOS transistors that constitute a logic device or cell. In other example embodiments, one of the first PMOSFET region PR1 and the second PMOSFET region PR2 can be a dummy region that does not constitute a logic device.

[0028] Referring to Figure 3 A triple height cell THC can be provided. For example, a first power rail POR1, a second power rail POR2, a third power rail POR3, and a fourth power rail POR4 can be disposed on the substrate SUB. The first power rail POR1 to the fourth power rail POR4 can be sequentially disposed in the first direction D1. The fourth power rail POR4 can be a path through which a source voltage VSS is provided.

[0029] The triple height cell THC can be defined between the first power rail POR1 and the fourth power rail POR4. The triple height cell THC can include a first PMOSFET region PR1, a first NMOSFET region NR1, a second PMOSFET region PR2, and a second NMOSFET region NR2. The first PMOSFET region PR1 can be adjacent to the first power rail POR1, and the second NMOSFET region NR2 can be adjacent to the fourth power rail POR4. The first NMOSFET region NR1 can overlap the second power rail POR2, and the second PMOSFET region PR2 can overlap the third power rail POR3.

[0030] ​​Each of the first PMOSFET region PR1 and the second NMOSFET region NR2 can have a first width W1 in the first direction D1. Each of the first NMOSFET region NR1 and the second PMOSFET region PR2 can have a second width W2 in the first direction D1. A third height HE3 can be defined to indicate a length of the triple-height cell THC in the first direction D1. The third height HE3 can be about three times of the first height HE1. Figure 1

[0031] A multi-height cell can refer to Figure 2 a double-height cell DHC and / or Figure 3 a triple-height cell THC.

[0032] Figure 4 A plan view showing a semiconductor device according to an example embodiment is shown. Figure 5A 、 5B , 5C and 5D show cross-sectional views taken along lines A-A', B-B', C-C' and D-D' of Figure 4 , respectively.

[0033] The semiconductor device according to the present example embodiment is an illustrative example of the double-height cell DHC discussed above with reference to Figure 2 .

[0034] With reference to Figure 4 and Figure 5A to 5D , a double-height cell DHC can be provided on a substrate SUB. The double-height cell DHC according to an example embodiment can include vertical transistors constituting a logic circuit. The substrate SUB can be a compound semiconductor substrate or a semiconductor substrate including, for example, silicon, germanium, or silicon germanium.

[0035] The substrate SUB can include a first PMOSFET region PR1, a NMOSFET region NR, and a second PMOSFET region PR2. The NMOSFET region NR can be interposed between the first PMOSFET region PR1 and the second PMOSFET region PR2 in the first direction D1. The first PMOSFET region PR1 and the second PMOSFET region PR2 and the NMOSFET region NR can be defined by a second trench TR2 formed on an upper portion of the substrate SUB. The first PMOSFET region PR1 and the second PMOSFET region PR2 and the NMOSFET region NR can extend in a second direction D2, respectively, which can be a second horizontal direction.

[0036] ​A first source pattern SOP1 can be provided on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The length of the first source pattern SOP1 in the first direction D1, when viewed in a planar angle, can be greater than the width of each of the first PMOSFET region PR1 and the second PMOSFET region PR2 in the first direction D1 (e.g., W1). For example, the first source pattern SOP1 can cover the first PMOSFET region PR1 or the second PMOSFET region PR2. The second source pattern SOP2 can have the same size as the size of the NMOSFET region NR, when viewed in a planar angle. The second source pattern SOP2 and the NMOSFET region NR can overlap each other. Figure 2

[0037] The first source pattern SOP1 and the second source pattern SOP2 can each be a portion of the substrate SUB. The first source pattern SOP1 and the second source pattern SOP2 can be formed by doping an impurity into an upper portion of the substrate SUB. The first source pattern SOP1 can be a p-type impurity region of the substrate SUB. The second source pattern SOP2 can be an n-type impurity region of the substrate SUB.

[0038] A first active pattern AP1 can be provided on the first source pattern SOP1 of each of the first PMOSFET region PR1 and the second PMOSFET region PR2. A second active pattern AP2 can be provided on the second source pattern SOP2 of the NMOSFET region NR. The first active pattern AP1 can be a semiconductor pillar that protrudes in a vertical direction (e.g., a third direction D3) and is grown from the first source pattern SOP1 that serves as a seed. The second active pattern AP2 can be a semiconductor pillar that protrudes in the third direction D3 and is grown from the second source pattern SOP2 that serves as a seed. The first active pattern AP1 and the second active pattern AP2 can include the same or different semiconductor material as the semiconductor material of the substrate SUB. For example, the first active pattern AP1 and the second active pattern AP2 can include silicon.

[0039] A first trench TR1 can be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The substrate SUB can include a device isolation layer ST on which the first trench TR1 and the second trench TR2 are filled. The device isolation layer ST can include a silicon oxide layer.

[0040] ​Each of the first active patterns AP1 and the second active patterns AP2 can have a bar shape extending in the first direction D1 when viewed in a planar angle. The first active patterns AP1 on the first PMOSFET regions PR1 and the second PMOSFET regions PR2 can be arranged in the second direction D2 at a first pitch. The second active patterns AP2 on the NMOSFET regions NR can be arranged in the second direction D2 at a second pitch. The first pitch and the second pitch can be identical to each other.

[0041] The first active patterns AP1 can protrude from the first source patterns SOP1. The first active patterns AP1 can protrude vertically with respect to the device isolation layer ST. Each first active pattern AP1 can include a first channel pattern CHP1 extending from the first source pattern SOP1 along a third direction D3, and can further include a first drain pattern DOP1 on the first channel pattern CHP1. The first drain pattern DOP1 can be an epitaxial pattern selectively epitaxially grown from the first channel pattern CHP1. The first channel pattern CHP1 can include undoped silicon, and the first drain pattern DOP1 can include silicon doped with p-type impurities.

[0042] The second active patterns AP2 can protrude from the second source patterns SOP2. The second active patterns AP2 can protrude vertically in the third direction D3 with respect to the device isolation layer ST. Each second active pattern AP2 can include a second channel pattern CHP2 extending from the second source pattern SOP2 along the third direction D3, and can further include a second drain pattern DOP2 on the second channel pattern CHP2. The second drain pattern DOP2 can be an epitaxial pattern selectively epitaxially grown from the second channel pattern CHP2. The second channel pattern CHP2 can include undoped silicon, and the second drain pattern DOP2 can include silicon doped with n-type impurities.

[0043] Each of the first active patterns AP1 and the second active patterns AP2 can have a third width W3 in the second direction D2, as shown in Figure 5A For example, the first active patterns AP1 and the second active patterns AP2 can have substantially the same width.

[0044] Referring to Figure 5C , the first active patterns AP1 can have a first length LE1 in the first direction D1. The second active patterns AP2 can have a second length LE2 in the first direction D1. The second length LE2 can be two to five times the first length LE1. For example, the second length LE2 can be two to three times the first length LE1.

[0045] Referring to Figure 4 and Figure 5CThe second active pattern AP2 can include an overlap region OVR that vertically overlaps the second power rail POR2. The second active pattern AP2 can include a first extension region ER1 that extends from the overlap region OVR in the first direction D1, and can further include a second extension region ER2 that extends from the overlap region OVR in a direction opposite the first direction D1. The second power rail POR2 can straddle the second active pattern AP2 arranged along the second direction D2 when viewed at a planar angle.

[0046] Referring to, for example Figure 4 The first active pattern AP1 on the first PMOSFET region PR1 can not vertically overlap the first power rail POR1. The first active pattern AP1 on the first PMOSFET region PR1 can be offset from the first power rail POR1. The first active pattern AP1 on the second PMOSFET region PR2 can not vertically overlap the third power rail POR3. The first active pattern AP1 on the second PMOSFET region PR2 can be offset from the third power rail POR3.

[0047] A plurality of gate electrodes GE can be disposed on the device isolation layer ST extending parallel to each other in the first direction D1. The gate electrodes GE can straddle the first active pattern AP1 and the second active pattern AP2 linearly arranged in the first direction D1.

[0048] Each gate electrode GE can have a bar shape or a line shape extending in the first direction D1. At least one gate electrode GE can extend from the first PMOSFET region PR1 through the NMOSFET region NR to the second PMOSFET region PR2. The gate electrode GE can not extend beyond a boundary of the dual-height cell DHC. For example, one end of the gate electrode GE can be adjacent to the first power rail POR1 and the other end of the gate electrode GE can be adjacent to the third power rail POR3.

[0049] The gate electrode GE can surround the first active pattern AP1 and the second active pattern AP2 and the first channel pattern CHP1 and the second channel pattern CHP2. The gate electrode GE can surround a sidewall of each of the first channel pattern CHP1 and the second channel pattern CHP2. For example, the gate electrode GE can include one or more of, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0050] A gate dielectric pattern GI can be interposed between the gate electrode GE and each of the first and second channel patterns CHP1 and CHP2. The gate dielectric pattern GI can cover a bottom surface and inner walls of the gate electrode GE. The gate dielectric pattern GI can have an uppermost surface that is coplanar with a top surface of the gate electrode GE. The gate dielectric pattern GI can include one or more of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric material. For example, the high-k dielectric material can include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, titanium oxide barium, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0051] The first and second drain patterns DOP1 and DOP2 can vertically protrude above the gate electrode GE. A top surface of the gate electrode GE can be located at a level that is the same as or lower than a level of a bottom surface of each of the first and second drain patterns DOP1 and DOP2. For example, each of the first and second active patterns AP1 and AP2 can have a structure that vertically extends from the substrate SUB and penetrates the gate electrode GE.

[0052] A semiconductor device according to the present embodiment can include a vertical transistor in which a carrier migrates in a third direction D3. For example, when the transistor is turned on due to a voltage applied to the gate electrode GE, the carrier can migrate from the source pattern SOP1 or SOP2 to the drain pattern DOP1 or DOP2 through the channel pattern CHP1 or CHP2. The gate electrode GE according to the present embodiment can completely surround four side walls of the channel pattern CHP1 or CHP2. The vertical transistor according to the present embodiment can have a gate-all-around structure. Because the gate electrode GE completely surrounds the channel patterns CHP1 and CHP2, the semiconductor device according to the present example embodiment can have excellent electrical characteristics.

[0053] A first interlayer dielectric layer ILD1 can be provided to cover the gate electrode GE and the first and second active patterns AP1 and AP2. The first interlayer dielectric layer ILD1 can include, for example, a silicon oxide layer or a silicon oxynitride layer.

[0054] At least one first active contact AC1 can penetrate the first interlayer dielectric layer ILD1 and the device isolation layer ST and be coupled to the first source pattern SOP1. At least one second active contact AC2 can penetrate the first interlayer dielectric layer ILD1 and the device isolation layer ST and be coupled to the second source pattern SOP2. A third active contact AC3 can penetrate the first interlayer dielectric layer ILD1 and be coupled to the first and second drain patterns DOP1 and DOP2. A gate contact GC can penetrate the first interlayer dielectric layer ILD1 and be coupled to the gate electrode GE.

[0055] The first power rail POR1 can have a first active contact AC1 coupled with the first source pattern SOP1 on the first PMOSFET region PR1 underneath it. The first active contact AC1 can vertically overlap the first power rail POR1. The first active contact AC1 can have a bar shape extending in the second direction D2.

[0056] The third power rail POR3 can have a first active contact AC1 coupled with the first source pattern SOP1 on the second PMOSFET region PR2 underneath it. The first active contact AC1 can vertically overlap the third power rail POR3. The first active contact AC1 can have a bar shape extending in the second direction D2.

[0057] Figure 6A A perspective view showing vertical transistors on the first PMOSFET region PR1 and the third PMOSFET region PR3 is shown, where the third PMOSFET region PR3 is adjacent to the first PMOSFET region PR1 in the first direction D1.

[0058] Reference is made to Figure 6A , although not shown in Figure 4 , the third PMOSFET region PR3 can be disposed adjacent to the first PMOSFET region PR1 in the first direction D1. The third PMOSFET region PR3 can be a PMOSFET region of another logic cell adjacent to the double-height cell DHC of Figure 4 in the first direction D1.

[0059] The first active contact AC1 can be between a pair of first active patterns AP1 adjacent to each other in the first direction D1. The first active contact AC1 can extend in the second direction D2 between the pair of first active patterns AP1. The first active contact AC1 can extend in the second direction D2 parallel to and underneath the first power rail POR1.

[0060] Reference is made back to Figure 4 The second power rail POR2 can have a second active contact AC2 coupled with the second source pattern SOP2 on the NMOSFET region NR underneath it. The second active contact AC2 can vertically overlap the second power rail POR2. The second active contact AC2 can have a planar shape different from a planar shape of the first active contact AC1. The second active contact AC2 can have a bar shape extending in the first direction D1.

[0061] Figure 6B A perspective view showing vertical transistors on the NMOSFET region NR is shown.

[0062] Referring to Figure 6B , the second active contacts AC2 can be between a pair of second active patterns AP2 adjacent to each other in the second direction D2. The second active contacts AC2 can extend between the pair of second active patterns AP2 in the first direction D1. The second active contacts AC2 can be coupled with regions of the second active pattern SOP2 between the pair of second active patterns AP2.

[0063] As shown in Figure 6A , on the first source pattern SOP1, the first active patterns AP1 can be divided into two first active patterns AP1, which can be arranged in the first direction D1. Accordingly, the first active contacts AC1 can be disposed between the two first active patterns AP1.

[0064] In contrast, as shown in Figure 6B , on the second source pattern SOP2, the second active patterns AP2 can not be divided, but can extend continuously in the first direction D1. Accordingly, the shape of the second active contacts AC2 can not be the same as that of the first active contacts AC1. The second active contacts AC2 can be disposed in spaces between the second active patterns AP2 spaced apart from each other in the second direction.

[0065] Referring back to Figure 4 and Figure 5A to 5D , the third active contacts AC3 can have a bar shape extending in the second direction D2. The third active contacts AC3 can have a bottom surface in contact with a top surface of the first drain pattern DOP1 and the second drain pattern DOP2.

[0066] The third active contacts AC3 can be connected to each other with the first drain patterns DOP1 arranged in the second direction D2. The third active contacts AC3 can be connected to each other with the second drain patterns DOP2 arranged in the second direction D2.

[0067] The gate contact GC can be disposed on the device isolation layer ST. The gate contact GC can have a bottom surface in contact with a top surface of the gate electrode GE. For example, top surfaces of the first to third active contacts AC1, AC2, AC3 and the gate contact GC can be coplanar with a top surface of the first interlayer dielectric layer ILD1.

[0068] The bottom surfaces of the first and second active contacts AC1, AC2 can be at substantially the same level. The bottom surface of the gate contact GC can be higher than the bottom surfaces of the first and second active contacts AC1, AC2. The bottom surface of the third active contact AC3 can be higher than the bottom surface of the gate contact GC.

[0069] The first to third active contacts AC1 to AC3 and the gate contact GC can include one or more electrically conductive metal nitrides (e.g., titanium nitride or tantalum nitride) and metals (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0070] The second interlayer dielectric layer ILD2 can be provided on the first interlayer dielectric layer ILD1. The first wiring layer M1 can be provided in the second interlayer dielectric layer ILD2. The first wiring layer M1 can include connection lines IL and first, second, and third power rails POR1, POR2, and POR3. The conductive lines POR1, POR2, POR3, and IL of the first wiring layer M1 can have a linear shape extending parallel to each other in the second direction D2.

[0071] The first wiring layer M1 can have vias VI thereunder that electrically connect the first wiring layer M1 to the first, second, and third active contacts AC1, AC2, and AC3 and the gate contact GC thereunder. The first wiring layer M1 and the vias VI can include a metallic material, e.g., cobalt, tungsten, or copper.

[0072] Each of the first power rail POR1 and the third power rail POR3 can be electrically connected to the first active contact AC1 thereunder. The second power rail POR2 can be electrically connected to the second active contact AC2 thereunder. The connection lines IL can have first connection lines electrically connected to the respective third active contacts AC3. The connection lines IL can also have second connection lines electrically connected to the respective gate contacts GC.

[0073] Although not shown, a plurality of wiring layers can be further provided on the first wiring layer M1. The logic units of the semiconductor device can be connected to each other by the plurality of wiring layers.

[0074] Figure 7 、 Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 and Figure 17 show plan views of stages in a method of manufacturing a semiconductor device according to example embodiments. Figure 8A 、 Figure 10A 、 Figure 12A 、 Figure 14A 、 Figure 16A and Figure 18A show cross-sectional views taken along the line A-A’ in Figure 7 、 Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 and Figure 17 respectively. Figure 8B 、 Figure 10B ,Figure 12B , Figure 14B , Figure 16B and Figure 18B respectively show cross-sectional views taken along lines B-B’ of Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 and Figure 17 .

[0075] Referring to Figure 7 , Figure 8A and Figure 8B , a substrate SUB can be provided that has an area on which a dual height cell DHC is to be formed. The substrate SUB can include a first PMOSFET region PR1, a NMOSFET region NR, and a second PMOSFET region PR2.

[0076] The substrate SUB can be doped with impurities to form an impurity region on an upper portion of the substrate SUB. The impurity region of the first PMOSFET region PR1 and the second PMOSFET region PR2 can have a first conductivity type (e.g., p-type). The impurity region of the NMOSFET region NR can have a second conductivity type (e.g., n-type).

[0077] The upper portion of the substrate SUB can be patterned to form a second trench TR2 that defines a first source pattern SOP1 and a second source pattern SOP2. The first source pattern SOP1 can be formed on the first PMOSFET region PR1 and the second PMOSFET region PR2. The second source pattern SOP2 can be formed on the NMOSFET region NR.

[0078] A device isolation layer ST can be formed to fill the second trench TR2. The formation of the device isolation layer ST can include forming a dielectric layer on the substrate SUB that fills the second trench TR2, and then planarizing the dielectric layer until top surfaces of the first source pattern SOP1 and the second source pattern SOP2 are exposed. The device isolation layer ST can include, for example, a silicon oxide layer.

[0079] Referring to Figure 9 , Figure 10A and Figure 10B , an epitaxial growth process can be performed on an entire surface of the substrate SUB, thereby forming a semiconductor layer SL. The epitaxial growth process can be performed by using a same or different semiconductor material as the substrate SUB. For example, the epitaxial growth process can be performed using silicon, and thus the semiconductor layer SL can include a silicon layer.

[0080] The semiconductor layer SL can include crystalline regions CR on the first source pattern SOP1 and the second source pattern SOP2, and can also include amorphous regions AR on the device isolation layer ST. The crystalline regions CR of the semiconductor layer SL can grow from the first source pattern SOP1 and the second source pattern SOP2, which serve as seeds, and thus can have the same crystalline structure as the crystalline structure of the first source pattern SOP1 and the second source pattern SOP2. The amorphous regions AR of the semiconductor layer SL can grow from the device isolation layer ST, which serves as a seed, and thus can be amorphous.

[0081] Referring to Figure 11 , Figure 12A and Figure 12B The semiconductor layer SL can be patterned to form first active patterns AP1 and second active patterns AP2. The first active patterns AP1 and the second active patterns AP2 can be formed on the first source patterns SOP1 and the second source patterns SOP2, respectively. For example, the forming of the first active patterns AP1 and the second active patterns AP2 can include forming a mask pattern on the semiconductor layer SL, and anisotropically etching the semiconductor layer SL using the mask pattern as an etching mask.

[0082] When the semiconductor layer SL is etched, the first source patterns SOP1 and the second source patterns SOP2 can be partially etched to form first trenches TR1. The first trenches TR1 can be formed between adjacent first active patterns AP1 or between adjacent second active patterns AP2.

[0083] Each of the first active patterns AP1 and the second active patterns AP2 can be formed to have a semiconductor columnar shape that vertically protrudes from a top surface of the substrate SUB. The first active patterns AP1 can include first channel patterns CHP1 on the first source patterns SOP1. The second active patterns AP2 can include second channel patterns CHP2 on the second source patterns SOP2. The first channel patterns CHP1 and the second channel patterns CHP2 can include undoped crystalline silicon.

[0084] Each of the first active patterns AP1 and the second active patterns AP2 can be formed to have a third width W3 in the second direction D2. The first active patterns AP1 and the second active patterns AP2 can have substantially the same width. The first active patterns AP1 can be formed to have a first length LE1 in the first direction D1. The second active patterns AP2 can be formed to have a second length LE2 in the first direction D1. The second length LE2 can be twice or five times the first length LE1. For example, the second length LE2 can be twice or three times the first length LE1.

[0085] On the first source pattern SOP1, the first active pattern AP1 can be arranged in the second direction D2 with a first pitch. On the second source pattern SOP2, the second active pattern AP2 can be arranged in the second direction D2 with a second pitch. The first pitch and the second pitch can be identical to each other.

[0086] Referring to Figure 13 , Figure 14A and Figure 14B , a dielectric layer can additionally be deposited on the device isolation layer ST. In this way, the device isolation layer ST can be thickened. The device isolation layer ST can have a top surface that is higher than the top surfaces of the first source pattern SOP1 and the second source pattern SOP2. The first channel pattern CHP1 and the second channel pattern CHP2 can be exposed on the device isolation layer ST.

[0087] The gate dielectric layer GIL and the gate electrode layer GL can be sequentially formed on the entire surface of the substrate SUB. The gate dielectric layer GIL can conformally cover the exposed first channel pattern CHP1 and the second channel pattern CHP2. The gate electrode layer GL can fill the space between the first channel pattern CHP1 and the second channel pattern CHP2. The gate electrode layer GL can be formed to have a top surface that is higher than the top surfaces of the first channel pattern CHP1 and the second channel pattern CHP2.

[0088] The gate dielectric layer GIL can be formed by using, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD). The gate dielectric layer GIL can include silicon oxide, silicon oxynitride, or a high-k dielectric material. The gate electrode layer GL can include one or more of a conductive metal nitride material and a metal material.

[0089] Referring to Figure 15 , Figure 16A and Figure 16B , the gate electrode layer GL can be patterned to form gate electrodes GE. The gate electrodes GE can be formed to extend in parallel to each other in the first direction D1. For example, the gate electrodes GE can extend in the first direction D1 while surrounding the first active pattern AP1 and the second active pattern AP2 that are aligned to each other in the first direction D1.

[0090] A first interlayer dielectric layer ILD1 can be formed on the gate electrodes GE. The first interlayer dielectric layer ILD1 can fill the space between the gate electrodes GE. The first interlayer dielectric layer ILD1 can include, for example, a silicon oxide layer or a silicon oxynitride layer.

[0091] A planarization process can be performed until the top surfaces of the first channel pattern CHP1 and the second channel pattern CHP2 are exposed. Accordingly, the top surfaces of the gate electrodes GE and the first interlayer dielectric layer ILD1 can be coplanar with the top surfaces of the first channel pattern CHP1 and the second channel pattern CHP2.

[0092] A selective epitaxial growth process can be performed on the exposed top surfaces of the first and second channel patterns CHP1, CHP2, and as a result, first and second drain patterns DOP1, DOP2 can be formed on the first and second channel patterns CHP1, CHP2, respectively. The first and second drain patterns DOP1, DOP2 can vertically protrude relative to the top surface of the gate electrode GE. The first channel pattern CHP1 and the first drain pattern DOP1 can constitute a first active pattern AP1. The second channel pattern CHP2 and the second drain pattern DOP2 can constitute a second active pattern AP2.

[0093] Because the first and second drain patterns DOP1, DOP2 are grown from the first and second channel patterns CHP1, CHP2, which serve as seeds, the first and second drain patterns DOP1, DOP2 can have the same crystal structure as the crystal structure of the first and second channel patterns CHP1, CHP2. The first and second drain patterns DOP1, DOP2 can include silicon, germanium, or silicon germanium. The first drain pattern DOP1 can be doped to have a first conductivity type, and the second drain pattern DOP2 can be doped to have a second conductivity type.

[0094] Referring to Figure 17 , Figure 18A and Figure 18B , a dielectric layer can additionally be deposited on the first interlayer dielectric layer ILD1, and thus, the first interlayer dielectric layer ILD1 can cover the first and second drain patterns DOP1, DOP2.

[0095] First and second active contacts AC1, AC2 can be formed, which penetrate the first interlayer dielectric layer ILD1 and are coupled with the first and second source patterns SOP1, SOP2, respectively. The formation of the first and second active contacts AC1, AC2 can include forming first and second holes, which penetrate the first interlayer dielectric layer ILD1 and expose the first and second source patterns SOP1, SOP2, respectively, and then filling the first and second holes with a conductive material.

[0096] A third active contact AC3 can be formed, which penetrates the first interlayer dielectric layer ILD1 and is coupled with the first and second drain patterns DOP1, DOP2. A gate contact GC can be formed, which penetrates the first interlayer dielectric layer ILD1 and is coupled with the gate electrode GE.

[0097] Referring back to Figure 4 and Figure 5A to 5DA second interlayer dielectric layer ILD2 can be formed on the first interlayer dielectric layer ILD1. A first wiring layer M1 can be formed in the second interlayer dielectric layer ILD2. The first wiring layer M1 can include a first power rail POR1, a second power rail POR2, and a third power rail POR3, and a connection line IL extending parallel to each other in the second direction D2. A damascene process can be used to form the first power rail POR1, the second power rail POR2, and the third power rail POR3, and the connection line IL.

[0098] A via VI can be formed below the first wiring layer M1. The first wiring layer M1 can be electrically connected with the first active contact AC1, the second active contact AC2, and the third active contact AC3, and the gate contact GC through the via VI.

[0099] Figure 19 A plan view showing an arrangement of logic cells of a semiconductor device according to an example embodiment is shown.

[0100] Reference is made to Figure 19 A single height cell SHC, a double height cell DHC (lower left and upper left of Figure 1 , Figure 2 and Figure 3 respectively), and a triple height cell THC (right of Figure 19 ) can be provided on the substrate SUB, which are the same or similar to the height cells discussed above with reference to Figure 19 . The double height cell DHC can be adjacent to the single height cell SHC in the first direction D1. The triple height cell THC can be provided adjacent to the single height cell SHC and the double height cell DHC in the second direction D2.

[0101] Each of the single height cell SHC, the double height cell DHC, and the triple height cell THC can include at least one PMOSFET region and at least one NMOSFET region. Each of the single height cell SHC, the double height cell DHC, and the triple height cell THC can include the vertical transistors discussed above with reference to Figure 4 to 6B .

[0102] The double height cell DHC can be provided between the first power rail POR1 and the third power rail POR3. The second power rail POR2 can span the double height cell DHC. The single height cell SHC can be provided between the third power rail POR3 and the fourth power rail POR4.

[0103] The triple height cell THC can be defined between the first power rail POR1 and the fourth power rail POR4. The second power rail POR2 and the third power rail POR3 can span the triple height cell THC.

[0104] The third power rail POR3 can have a second PMOSFET region PR2 of double height cells DHC, a third PMOSFET region PR3 of single height cells SHC, and a fifth PMOSFET region PR5 of triple height cells THC thereunder when viewed in plan angle. In another implementation (not shown), the second PMOSFET region PR2 and the third PMOSFET region PR3 can be offset from the third power rail POR3 in the first direction D1 such that the second PMOSFET region PR2 and the third PMOSFET region PR3 do not vertically overlap the third power rail POR3.

[0105] The structure of vertical transistors between the third power rail POR3 and the second PMOSFET region PR2 and the third PMOSFET region PR3 can be substantially the same as the structure of the transistors discussed above with reference to Figure 6A

[0106] The fifth PMOSFET region PR5 can include a region vertically overlapping the third power rail POR3 when viewed in plan angle. The third power rail POR3 can span the center of the fifth PMOSFET region PR5. The structure of vertical transistors between the fifth PMOSFET region PR5 and the third power rail POR3 can be substantially the same as the structure of the transistors discussed above with reference to Figure 6B

[0107] As described above, embodiments relate to a semiconductor device including vertical field effect transistors. Embodiments can provide a semiconductor device having improved electrical characteristics and increased integration and a method of manufacturing the same.

[0108] According to an example embodiment, a semiconductor device can be configured such that a vertical transistor is disposed on a multi-height cell. The vertical transistor disposed on the multi-height cell can have an active region having an area greater than an area of an active region of a vertical transistor disposed on a single-height cell, and thus the transistor is improved in electrical performance.

[0109] Example embodiments have been disclosed herein and, although a particular terminology is employed, it is understood that the examples are intended in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, attributes and / or benefits from a particular example described can be used, incorporated into and / or combined with other examples described, unless expressly stated otherwise. Thus, it will be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the application and, as such, within the spirit and scope of the application as set forth in the appended claims.​​

Claims

1. A semiconductor device comprising: a substrate comprising a first active area; a first active pattern and a second active pattern on the first active area, the first active pattern and the second active pattern extending along a first direction and spaced apart from each other in a second direction that intersects the first direction, and each of the first active pattern and the second active pattern having a source pattern, a channel pattern, and a drain pattern sequentially stacked; a first gate electrode and a second gate electrode surrounding the channel patterns of the first active pattern and the second active pattern and extending along the first direction; an interlayer dielectric layer covering the first active pattern and the second active pattern and the first gate electrode and the second gate electrode; a first active contact penetrating the interlayer dielectric layer and coupled to the first active area between the first active pattern and the second active pattern; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first active pattern and the second active pattern comprising an overlap region vertically overlapping the first power rail. Each of the first active pattern and the second active pattern further comprises:

2. The semiconductor device of claim 1, wherein, a first extension region extending from the overlap region along the first direction; and a second extension region extending from the overlap region along a direction opposite to the first direction. The first active contact extends along the first direction between the first active pattern and the second active pattern.

3. The semiconductor device of claim 1, wherein, 4. The semiconductor device of claim 3, further comprising a second active contact penetrating the interlayer dielectric layer and coupled to the drain patterns of the first active pattern and the second active pattern, wherein: the second active contact extends along the second direction between the first active pattern and the second active pattern, and a bottom surface of the second active contact is higher than a bottom surface of the first active contact.

5. The semiconductor device of claim 1, further comprising a gate contact penetrating the interlayer dielectric layer and coupled to at least one of the first gate electrode and the second gate electrode, a bottom surface of the gate contact is higher than a bottom surface of the first active contact. wherein, The substrate further comprises a second active area, 6. The semiconductor device of claim 1, wherein, wherein the semiconductor device further comprises: a third active pattern and a fourth active pattern on the second active area, the third active pattern and the fourth active pattern extending along the first direction and spaced apart from each other in the second direction, and each of the third active pattern and the fourth active pattern having a source pattern, a channel pattern, and a drain pattern sequentially stacked; a second active contact penetrating the interlayer dielectric layer and coupled to the second active area; and a second power rail on the interlayer dielectric layer and electrically connected to the second active contact, wherein the third active pattern and the fourth active pattern are offset from the second power rail when viewed at a planar angle.

7. The semiconductor device of claim 6, wherein: ​ The first active contact extends in the first direction between the first active pattern and the second active pattern, and The second active contact extends in the second direction under the second power rail.

8. The semiconductor device of claim 6, wherein: The first gate electrode extends in the first direction from the first active pattern and around a channel pattern of the third active pattern, and The second gate electrode extends in the first direction from the second active pattern and around a channel pattern of the fourth active pattern.

9. The semiconductor device of claim 6, wherein: Each of the third and fourth active patterns has a first length in the first direction, Each of the first and second active patterns has a second length in the first direction, and The second length is 2 to 5 times the first length.

10. The semiconductor device of claim 9, wherein, A width of each of the first and second active patterns in the second direction is the same as a width of each of the third and fourth active patterns in the second direction.

11. A semiconductor device, comprising: a substrate including a first active region; first and second active patterns on the first active region, the first and second active patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and the first and second active patterns protruding in a vertical direction from a top surface of the substrate; first and second gate electrodes surrounding the first and second active patterns and extending in the first direction, upper portions of the first and second active patterns protruding in the vertical direction above a top surface of the first and second gate electrodes; an interlayer dielectric layer covering the first and second active patterns and the first and second gate electrodes; a first active contact penetrating the interlayer dielectric layer and coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, wherein, in a plan view, the first power rail spans the first and second active patterns and extends in the second direction.

12. The semiconductor device of claim 11, wherein, The first active contact extends in the first direction between the first active pattern and the second active pattern.

13. The semiconductor device of claim 11, wherein, The substrate further includes a second active region, wherein the semiconductor device further comprises: third and fourth active patterns on the second active region, the third and fourth active patterns extending in the first direction and spaced apart from each other in the second direction, and the third and fourth active patterns protruding vertically from a top surface of the substrate; a second active contact penetrating the interlayer dielectric layer and coupled to the second active region; and a second power rail on the interlayer dielectric layer and electrically connected to the second active contact, wherein, in plan view, the second power rail is offset from the third active pattern and the fourth active pattern and extends in the second direction.

14. The semiconductor device of claim 13, wherein: each of the third active pattern and the fourth active pattern has a first length in the first direction, each of the first active pattern and the second active pattern has a second length in the first direction, and the second length is 2 to 5 times the first length.

15. The semiconductor device of claim 13, wherein: the first active region is one of a PMOSFET region and an NMOSFET region, and the second active region is the other of the PMOSFET region and the NMOSFET region.

16. A semiconductor device, comprising: a substrate; a first power rail, a second power rail, and a third power rail arranged in a first direction on the substrate; and a logic cell between the first power rail and the third power rail, the logic cell comprising: a first active region adjacent to the first power rail, a second active region straddled by the second power rail, and a third active region adjacent to the third power rail; a first active pattern, a second active pattern, and a third active pattern on the first active region, the second active region, and the third active region, respectively, each of the first active pattern, the second active pattern, and the third active pattern having a bar shape extending in the first direction when viewed in plan; a gate electrode on the first active pattern, the second active pattern, and the third active pattern; and an interlayer dielectric layer covering the first active pattern, the second active pattern, the third active pattern, and the gate electrode, wherein: the first power rail, the second power rail, and the third power rail are on the interlayer dielectric layer, each of the first active pattern, the second active pattern, and the third active pattern extends vertically from the substrate and penetrates the gate electrode, the first active pattern has a first length in the first direction, the second active pattern has a second length in the first direction, the second length is 2 to 5 times the first length.

17. The semiconductor device of claim 16, wherein: each of the first active region and the third active region is one of a PMOSFET region and an NMOSFET region, and the second active region is the other of the PMOSFET region and the NMOSFET region.

18. The semiconductor device of claim 16, wherein: the first power rail and the third power rail are connected to one of a source voltage and a drain voltage, and the second power rail is connected to the other of the source voltage and the drain voltage.

19. The semiconductor device of claim 16, wherein, The first active pattern and the second active pattern have the same width in a second direction, the second direction intersecting the first direction.

20. The semiconductor device of claim 16, wherein: The third active pattern has a third length in the first direction, and The third length is the same as the first length.

Images