Electrostatic protection circuit and semiconductor device

Abstract

The electrostatic protection circuit and the semiconductor device are characterized by including: a first diode having a positive electrode connected to a signal terminal; a second diode having a negative electrode connected to the negative electrode of the first diode and a positive electrode connected to a GND terminal; and a depletion-type MOS transistor connected in parallel with the first diode.

Description

Technical Field

[0001] The present invention relates to an electrostatic protection circuit for a semiconductor device. Background Art

[0002] An existing electrostatic protection circuit for a semiconductor device is composed of a PNP transistor in which an emitter terminal is connected to a signal terminal and a collector terminal is connected to a GND terminal. In a semiconductor device having such an electrostatic protection circuit, even if the signal terminal drops below the potential of the GND terminal, no operational problems occur (for example, refer to Patent Document 1).

[0003]

Prior Art Documents

[0004]

Patent Documents

[0005]

Patent Document 1

[0006]

Problems to be Solved by the Invention

[0007] As Figure 6 shown, in the case of manufacturing an electrostatic protection PNP transistor (shown by a solid line) of an electrostatic protection circuit 60 using a CMOS process, the base is generally composed of an N well (Nwell). The PNP transistor configured in this way can be regarded as a series connection of a diode D1 with a P-type region 61 as the positive electrode and an Nwell as the negative electrode, and a diode D2 with a P-type region 62 as the positive electrode and an Nwell as the negative electrode. In addition, the positive electrode of the diode D1, the Nwell, and the P substrate (Psub) can be regarded as the emitter, base, and collector of a parasitic PNP transistor (shown by a dashed line).

[0008] However, when it becomes high temperature, the leakage current of the diode D2 flows through the diode D1. The parasitic PNP transistor allows a collector current to flow after amplifying the leakage current according to its current amplification factor. Therefore, in the existing electrostatic protection circuit, when it becomes high temperature, the collector current of the parasitic PNP transistor flows from the signal terminal into the GND terminal, so the input current of the signal terminal increases.

[0009] An object of the present invention is to provide an electrostatic protection circuit and a semiconductor device in which the increase amount of the input current of a signal terminal is small at high temperature.

[0010]

Means for Solving the Problems

[0011] The electrostatic protection circuit according to an embodiment of the present invention is characterized by including: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to the cathode of the first diode and whose anode is connected to a GND terminal; and a depletion-type MOS transistor connected in parallel with the first diode.

[0012] In addition, the semiconductor device according to an embodiment of the present invention is characterized in that: the above-mentioned electrostatic protection circuit is provided between the signal terminal and the internal circuit.

[0013]

Effect of the Invention

[0014] According to the electrostatic protection circuit of the present invention, a depletion-type MOS transistor is provided in parallel with the first diode, so that an electrostatic protection circuit and a semiconductor device with a small increase in the input current of the signal terminal at high temperature can be provided. Description of the Drawings

[0015] Figure 1 It is a circuit diagram showing a semiconductor device including the electrostatic protection circuit according to the first embodiment.

[0016] Figure 2 It is a circuit diagram showing another example of the electrostatic protection circuit according to the first embodiment.

[0017] Figure 3 It is a circuit diagram showing a semiconductor device including the electrostatic protection circuit according to the second embodiment.

[0018] Figure 4 It is a circuit diagram showing another example of the electrostatic protection circuit according to the second embodiment.

[0019] Figure 5 It is a circuit diagram showing another example of the electrostatic protection circuit according to the first embodiment.

[0020] Figure 6 It is a cross-sectional view of a conventional semiconductor device including an electrostatic protection circuit. Detailed Embodiment

[0021] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The semiconductor device according to an embodiment of the present invention has: a signal terminal for inputting and outputting signals; an internal circuit connected to the signal terminal; and an electrostatic protection circuit provided between the signal terminal and the internal circuit. Regarding the internal circuit of the semiconductor device, its detailed description will be omitted.

[0022] <First Embodiment>

[0023] Figure 1This is a circuit diagram showing a semiconductor device equipped with the electrostatic protection circuit according to the first embodiment.

[0024] The semiconductor device 100 includes an electrostatic protection circuit 10 and an internal circuit 40. The electrostatic protection circuit 10 includes diodes 11, 12, a depletion-type p-channel MOS transistor (hereinafter referred to as a pMOS transistor) 13, and a resistor 14. The resistor 14 is a gate protection resistor for the transistors of the internal circuit 40.

[0025] In the diode 11, the positive electrode is connected to the signal terminal, and the negative electrode is connected to the negative electrode of the diode 12. The positive electrode of the diode 12 is connected to the GND terminal. In the pMOS transistor 13, the drain is connected to the internal circuit 40, and the gate, source, and body are connected to the negative electrode of the diode 11. The resistor 14 is connected between the positive electrode of the diode 11 and the drain of the pMOS transistor 13.

[0026] Next, the operation of the electrostatic protection circuit 10 of the first embodiment will be described. In addition, in the electrostatic protection circuit 10, it is the same as the prior art that a parasitic PNP transistor is formed by the positive and negative electrodes of the diode 11 and Psub.

[0027] <Steady state where the voltage of the signal terminal is higher than the voltage of the GND terminal>

[0028] In the pMOS transistor 13, the gate is connected to the source, but since it is a depletion type, a channel exists between the drain and the source. Since the current supply capacity of the pMOS transistor 13 is sufficiently larger than the leakage current flowing through the diode 12, the voltage drop due to the on-resistance of the pMOS transistor 13 approaches 0V. Therefore, most of the leakage current of the diode 12 flows through the pMOS transistor 13, and no current flows through the diode 11. Thus, no current flows through the parasitic PNP transistor, so the current flowing through the signal terminal can be suppressed to a small value.

[0029] <Reverse connection state where the voltage of the signal terminal is lower than the voltage of the GND terminal>

[0030] The pMOS transistor 13 operates as a constant current source with an overdrive voltage of |VTPD| (threshold voltage). The reverse current flows from the GND terminal through the diode 12 and the pMOS transistor 13 into the signal terminal, but it can be suppressed to an allowable current by the pMOS transistor 13. Thus, even though the pMOS transistor 13 is connected in parallel with the diode 11, there is no problem in the operation of the semiconductor device in the reverse connection state.

[0031] As described above, the electrostatic protection circuit 10 according to this embodiment includes a pMOS transistor 13 in parallel with a diode 11, so that no current flows through the parasitic transistor at high temperatures, and thus the increase in the input current of the signal terminal can be reduced.

[0032] In addition, even if the pMOS transistor 13 is replaced with Figure 2 a depletion-type n-channel MOS transistor 23 connected as shown, the same effect can be obtained.

[0033] <Second Embodiment>

[0034] Figure 3 FIG. is a circuit diagram of a semiconductor device including the electrostatic protection circuit according to the second embodiment.

[0035] Relative to Figure 1 the electrostatic protection circuit 10, Figure 3 the electrostatic protection circuit 20 further includes a resistor 15. In addition, the same reference numerals are given to the same structural elements as those of the electrostatic protection circuit 10 shown in Figure 1 and repeated descriptions are appropriately omitted.

[0036] <Steady State where the Voltage of the Signal Terminal is Higher than the Voltage of the GND Terminal>

[0037] A resistor 15 is connected between the source of the pMOS transistor 13 and the negative electrode of the diode 12. Since the resistance value of the resistor 15 is sufficiently small, the same operation as that of the electrostatic protection circuit 10 of Figure 1 can be performed.

[0038] <Reverse Connection State where the Voltage of the Signal Terminal is Lower than the Voltage of the GND Terminal>

[0039] In the reverse connection state, the current flowing through the pMOS transistor 13 is generally determined by |VTPD| / R. Here, R is the resistance value of the resistor 15. That is, this current can be set to a current value that can be allowed as a reverse current. Therefore, compared with the electrostatic protection circuit 10 of the first embodiment, the size of the pMOS transistor 13 can be reduced.

[0040] As described above, the electrostatic protection circuit 20 of this embodiment includes a pMOS transistor 13 and a resistor 15 in parallel with a diode 11, so that no current flows through the parasitic transistor at high temperatures, and thus the increase in the input current of the signal terminal can be reduced.

[0041] In addition, even if the pMOS transistor 13 and the resistor 15 are replaced with Figure 4 a depletion-type n-channel MOS transistor 23 and a resistor 25 connected as shown, the same effect can be obtained.

[0042] As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0043] For example, the diodes 11 and 12 can also be replaced with electrostatic protection elements of MOS transistors. As an example, in Figure 5 it shows the replacement of the diode in the electrostatic protection circuit 10 of Figure 1 with an electrostatic protection circuit 30 of enhancement-mode n-channel MOS transistors 31 and 32.

[0044] In addition, for example, the resistor 14 can also be connected between the drain of the pMOS transistor 13 (the source of the nMOS transistor 23) and the internal circuit 40. In this case, for protection, a resistor can also be provided in series with the path of the drain of the pMOS transistor 13 (the source of the nMOS transistor 23) and the body. For example, a resistor is provided between the connection point of the gate, source, and body of the pMOS transistor 13 and the negative electrode of the diode 11.

[0045] Reference Numeral Explanation

[0046] 10, 20, 30 Electrostatic protection circuits; 11, 12 Diodes; 13 Depletion-mode p-channel MOS transistor; 23 Depletion-mode n-channel MOS transistor; 31, 32 Enhancement-mode n-channel MOS transistors; 40 Internal circuit; 100 Semiconductor device.

Claims

1. An electrostatic protection circuit, which is an electrostatic protection circuit for a signal terminal of a semiconductor device, characterized in that it comprises: a first diode, whose anode is connected to the signal terminal; a second diode, whose cathode is connected to the cathode of the first diode and whose anode is connected to the GND terminal; and a depletion-mode MOS transistor, which is connected in parallel with the first diode, the depletion-mode MOS transistor is a pMOS transistor whose drain is connected to the internal circuit and whose gate, source, and body are connected to the cathode of the first diode.

2. The electrostatic protection circuit according to claim 1, characterized in that: a resistor is connected between the source of the pMOS transistor and the cathode of the first diode.

3. An electrostatic protection circuit, which is an electrostatic protection circuit for a signal terminal of a semiconductor device, characterized in that it comprises: a first diode, whose anode is connected to the signal terminal; a second diode, whose cathode is connected to the cathode of the first diode and whose anode is connected to the GND terminal; and a depletion-mode MOS transistor, which is connected in parallel with the first diode, the depletion-mode MOS transistor is an nMOS transistor whose gate, source, and body are connected to the internal circuit and whose drain is connected to the cathode of the first diode.

4. The electrostatic protection circuit according to claim 3, characterized in that: a resistor is connected between the source of the nMOS transistor and the internal circuit.

5. A semiconductor device, characterized in that: an electrostatic protection circuit according to any one of claims 1 to 4 is provided between the signal terminal and the internal circuit.

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