Memory device and semiconductor device

Abstract

The present invention relates to a memory device and a semiconductor device. The memory device can include a source region, a channel, a gate insulating layer pattern, a select gate pattern, a first gate pattern, a second gate pattern, and a drain region. The source region can include a first impurity having a first conductivity type at an upper portion of a substrate. The channel can contact the source region. Each channel can extend in a vertical direction perpendicular to an upper surface of the substrate. The select gate pattern can be on a sidewall of the channel. The first gate pattern can be on the sidewall of the channel. The first gate pattern can be a common electrode of all of the plurality of channels. The second gate pattern can be on the sidewall of the channel. The drain region can include a second impurity having a second conductivity type different from the first conductivity type at an upper portion of each channel.

Description

Technical Field

[0001] The example implementations generally relate to storage devices and methods of manufacturing them. More specifically, the example implementations relate to vertical channel storage devices and methods of manufacturing them. Background Technology

[0002] In DRAM (Dynamic Random Access Memory) devices, a single cell may include a transistor and a capacitor. Due to the high integration of DRAM devices, limitations in capacitor storage capacity and increased leakage current within the single cell can become problems. Therefore, memory devices without capacitors can be advantageous. Furthermore, for high integration of memory devices, vertical-channel memory devices, including vertical-channel memory, can be beneficial. Summary of the Invention

[0003] The example implementation provides a highly integrated storage device.

[0004] According to an example embodiment, a memory device is provided that may include a source region, a channel, a gate insulating layer pattern, a select gate pattern, a first gate pattern, a second gate pattern, and a drain region. The source region may include a first impurity having a first conductivity type at an upper portion of a substrate. A channel may contact the source region. Each channel may extend in a vertical direction perpendicular to the upper surface of the substrate. The plurality of channels may include a first channel and a second channel. The gate insulating layer pattern may surround or may cover a portion of the first channel. The select gate pattern may be on the gate insulating layer pattern. The select gate pattern may extend in a first direction parallel to the upper surface of the substrate. The first gate pattern may be on the gate insulating layer pattern. The second gate pattern may be on the gate insulating layer pattern. The second gate pattern may extend parallel to the upper surface of the select gate pattern. The drain region may include a second impurity having a second conductivity type different from the first conductivity type at an upper portion of the first channel. The select gate pattern, the first gate pattern, and the second gate pattern may be spaced apart from each other in a vertical direction. At least one of the source region and the first gate pattern may have a plate shape and may be a common electrode of the first and second channels.

[0005] According to an example embodiment, a memory device is provided that may include a source region, a channel, a gate insulating layer pattern, a select gate pattern, a first gate pattern, a second gate pattern, a drain region, and a bit line. The source region may include a first impurity having a first conductivity type at an upper portion of a substrate. A channel may contact the source region. Each channel may extend in a direction perpendicular to the upper surface of the substrate. The channels may be arranged in a first direction and a second direction parallel to the upper surface of the substrate and perpendicular to each other. The gate insulating layer pattern may surround the channel. The select gate pattern may be on the gate insulating layer pattern. The select gate pattern may surround the channel arranged in the first direction and may extend in the first direction. The channel may include a first channel, a second channel spaced apart from the first channel in the first direction, and a third channel spaced apart from the first channel in the second direction. The first gate pattern may be on the gate insulating layer pattern. The second gate pattern may be on the gate insulating layer pattern. The second gate pattern may surround the first and second channels, or may cover a portion of each of the first and second channels, and may extend in the first direction. The drain region may include a second impurity having a second conductivity type different from the first conductivity type at an upper portion of the first channel. The bit line can be electrically connected to the drain region. The bit line can extend in a second direction. The selected gate pattern, the first gate pattern, and the second gate pattern can be spaced apart from each other in a vertical direction. The first gate pattern can surround the first channel, the second channel, and the third channel, or can cover the portions of the first channel, the second channel, and the third channel, and the first gate pattern can be used as a common gate for the first channel, the second channel, and the third channel.

[0006] According to an example embodiment, a memory device is provided that may include a source region, a channel, a gate insulating layer pattern, a select gate pattern, a first gate pattern, a second gate pattern, and a drain region. The source region may include a first impurity having a first conductivity type at an upper portion of the substrate. A channel may contact the source region. Each channel may extend in a vertical direction perpendicular to the upper surface of the substrate. Select gate patterns may be respectively located on the sidewalls of the channel. The first gate pattern may be on the sidewalls of the channel. The first gate pattern may be a common electrode. Second gate patterns may be respectively located on the sidewalls of the channel. The drain regions may include a second impurity having a second conductivity type different from the first conductivity type at their respective upper portions of the channels.

[0007] In an example embodiment, the unit cell of the memory device can be formed on a channel projecting vertically from the upper surface of the substrate. This improves the integration density of the memory device. Furthermore, at least one of the gate patterns of the first and second transistors included in the unit cell can have a wide pattern shape, allowing the gate pattern with a wide pattern shape to be shared with other unit cells. This simplifies the process for manufacturing the memory device. Additionally, since the channel of the transistor included in the unit cell can be undoped, variations or problems associated with the doping process can be reduced. Attached Figure Description

[0008] The exemplary implementation will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 45 These are non-limiting exemplary embodiments that embody the inventive concept described herein.

[0009] Figure 1 It is a cross-sectional view. Figure 2 It's a floor plan. Figure 3 and Figure 4 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention;

[0010] Figure 5 This is a circuit diagram of a unit cell of a storage device according to an exemplary embodiment of the present invention;

[0011] Figure 6 It is the IV curve of the bit line in a unit cell according to an exemplary embodiment of the present invention;

[0012] Figure 7 The energy band of the channel is shown in an example embodiment of the present invention when data 0 is written into a unit cell;

[0013] Figure 8 The energy band of the channel is shown in an example embodiment of the present invention when data 1 is written into a unit cell;

[0014] Figure 9 This is a timing diagram of the applied voltage to a selected unit cell based on the operation of a storage device, according to an exemplary embodiment of the present invention.

[0015] Figures 10 to 29 These are cross-sectional and plan views illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention;

[0016] Figure 30A This is a cross-sectional view illustrating an exemplary embodiment of a stacked storage device according to a concept of the present invention;

[0017] Figure 30BThis is a cross-sectional view illustrating an exemplary embodiment of a stacked storage device according to a concept of the present invention;

[0018] Figures 31 to 35 These are cross-sectional and plan views illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention;

[0019] Figure 36 and Figure 37 This is a cross-sectional view illustrating an exemplary embodiment of a storage device according to a concept of the present invention;

[0020] Figure 38 This is a circuit diagram of a unit storage cell in a storage device according to an exemplary embodiment of the present invention;

[0021] Figure 39 and Figure 40 This is a cross-sectional view illustrating an exemplary embodiment of a storage device according to the present invention; and

[0022] Figures 41 to 45 These are circuit diagrams illustrating exemplary embodiments of the storage device according to the present invention. Detailed Implementation

[0023] In the following text, a direction substantially perpendicular to the upper surface of the substrate may be referred to as the vertical direction. Two directions substantially parallel to the upper surface of the substrate and traversing each other may be referred to as the first direction and the second direction, respectively. In some embodiments, the first direction and the second direction may be substantially perpendicular to each other.

[0024] Figure 1 It is a cross-sectional view. Figure 2 It's a floor plan. Figure 3 and Figure 4 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention. Figure 5 This is a circuit diagram of a unit cell of a storage device according to an exemplary embodiment of the present invention.

[0025] Figure 4 Some components of the storage device are shown.

[0026] Reference Figures 1 to 5 In a storage device, unit cells can be arranged in an array on the cell region of substrate 100.

[0027] Each unit cell may include a common source region 102, a selection transistor 20, a first transistor 22, a second transistor 24, and a drain region 136. The components included in each unit cell may be arranged in the vertical direction.

[0028] The first transistor 22 and the second transistor 24 may be connected in series adjacent to each other and may have an energy barrier in the channel region. One of the gate patterns of the first transistor 22 and the second transistor 24 may have an unpatterned shape, such that the gate pattern with the unpatterned shape can be used as a common gate pattern shared with other unit cells. The common gate pattern may be shared with multiple unit cells.

[0029] In the memory device, a common source region 102 may be formed on the upper portion of the substrate 100. A channel structure 138 may be formed on the common source region 102 of the substrate 100. A select gate pattern 108a, a first gate pattern 114, and a second gate pattern 118 may be formed on the sidewalls of the channel structure 138, and the select gate pattern 108a, the first gate pattern 114, and the second gate pattern 118 may be spaced apart from each other in the vertical direction. A bit line structure 154 may be electrically connected to the upper surface of the channel structure 138.

[0030] Substrate 100 may include semiconductor materials such as silicon, germanium, or silicon-germanium, or III-V compounds such as GaP, GaAs, GaSb, etc. In some example embodiments, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0031] The common source region 102 may be a region including impurities having a first conductivity type. In some embodiments, the common source region 102 may be the upper portion of the substrate 100 doped with impurities having a first conductivity type. For example, the first conductivity type may be N-type. The upper surface of the substrate 100 may correspond to the common source region 102.

[0032] In the example embodiment, the common source region 102 can be formed over the entire upper portion of the substrate 100 of the cell region. That is, the common source region 102 can have a single-plate shape. Therefore, device isolation patterns do not need to be formed on the substrate 100 of the cell region. The common source region 102 can serve as the common source for all unit cells formed on the substrate 100 of the cell region.

[0033] In some example implementations, each common source region 102 may have a linear shape extending in a first direction or a second direction. In this case, a device isolation pattern may be formed between the common source regions 102 on the substrate 100. When used here, "element A extends in direction X" (or similar language) may mean that element A extends longitudinally in direction X.

[0034] The lower sacrificial layer 104 may be formed on the substrate 100. The first insulating intermediate layer 106 may be formed on the lower sacrificial layer 104.

[0035] The lower sacrificial layer 104 may include an insulating material that is etch-selective relative to silicon oxide. In an example embodiment, the lower sacrificial layer 104 may include silicon nitride or aluminum oxide. The first insulating intermediate layer 106 may include silicon oxide. Each of the insulating intermediate layers described below may also include silicon oxide.

[0036] The select gate pattern 108a can be formed on the first insulating intermediate layer 106. Therefore, the select gate pattern 108a can be spaced apart from the upper surface of the substrate 100 in the vertical direction. The select gate pattern 108a can have a linear shape extending in the first direction. Furthermore, the select gate patterns 108a can be spaced apart from each other in a second direction.

[0037] Each select gate pattern 108a can be used as the gate electrode of the select transistor 20.

[0038] To accelerate the operation of the memory device, the select gate pattern 108a may have low resistance. In an example embodiment, the select gate pattern 108a may comprise doped polysilicon. In some example embodiments, the select gate pattern 108a may comprise a metallic material having a lower resistance than polysilicon.

[0039] The second insulating intermediate layer 112 can be formed on the first insulating intermediate layer 106 and the select gate pattern 108a to fill the space between the select gate pattern 108a. The upper surface of the second insulating intermediate layer 112 can be flat.

[0040] A first gate pattern 114 may be formed on a second insulating interlayer 112. The first gate pattern 114 may be spaced apart from the selected gate pattern 108a in the vertical direction. In an example embodiment, the first gate pattern 114 may have a wide pattern shape. That is, the first gate pattern 114 may have a single-plate shape. Therefore, the first gate pattern 114 can be used as the common gate electrode of the first transistor 22. In some embodiments, a single first gate pattern 114 may be the gate electrode of all the plurality of first transistors 22 and may be referred to as the common gate electrode of the plurality of first transistors 22. In some embodiments, a single first gate pattern 114 may be the gate electrode corresponding to the plurality of channels 134 of the first transistor 22 and may be referred to as the common electrode of all the plurality of channels 134.

[0041] In an example embodiment, the first transistor 22 can be used as a transistor for modulating the electronic energy barrier. In this case, the first transistor 22 can have a high energy barrier, and therefore the first gate pattern 114 can have a high work function. In an example embodiment, the first gate pattern 114 can include a material having a first work function of 4.5 eV or greater.

[0042] In an example implementation, the first gate pattern 114 may include polysilicon doped with P-type impurities. In some example implementations, the first gate pattern 114 may include a metal having a first work function.

[0043] The third insulating intermediate layer 116 may be formed on the first gate pattern 114. The lower surface of the third insulating intermediate layer 116 may be flat.

[0044] A second gate pattern 118 may be formed on a third insulating intermediate layer 116. The second gate pattern 118 may be spaced apart from the first gate pattern 114 in a vertical direction. In an example embodiment, each second gate pattern 118 may have a linear shape extending in a first direction. Furthermore, the second gate patterns 118 may be spaced apart from each other in a second direction. Therefore, the second gate patterns 118 may be configured to face the selected gate pattern 108a respectively. Each second gate pattern 118 may serve as the gate electrode of the second transistor 24.

[0045] In an example embodiment, the second transistor 24 can be used as a transistor for modulating the hole barrier. In this case, the second transistor 24 can have a low barrier, and the second gate pattern 118 can have a second work function lower than the first work function. In an example embodiment, the second gate pattern 118 can include a conductive material having a work function lower than 4.5 eV.

[0046] In an example implementation, the second gate pattern 118 may include polysilicon doped with N-type impurities. In some example implementations, the second gate pattern 118 may include a metal having a second work function.

[0047] A fourth insulating intermediate layer 122 may be formed on the third insulating intermediate layer 116 and the second gate pattern 118 to fill the space between the second gate patterns 118. The upper surface of the fourth insulating intermediate layer 122 may be flat.

[0048] As described above, a stacked structure including a lower sacrificial layer 104, a first insulating intermediate layer 106, a select gate pattern 108a, a second insulating intermediate layer 112, a first gate pattern 114, a third insulating intermediate layer 116, a second gate pattern 118, and a fourth insulating intermediate layer 122 can be formed on the substrate 100 of the cell region.

[0049] Multiple channel structures 138 can pass through the stacked structure. Each channel structure 138 can be formed in a channel hole that passes through the stacked structure and exposes a common source region 102.

[0050] The channel structure 138 may pass through the second gate pattern 118, the first gate pattern 114, the select gate pattern 108a, the lower sacrificial layer 104, and the first to fourth insulating intermediate layers 106, 112, 116, and 122, and the channel structure 138 may extend to the common source region 102 of the substrate 100. The channel structure 138 may have a columnar shape. When used herein, "an element having a columnar shape" (or similar language) means an element comprising a bottom surface and a vertical portion extending vertically from the bottom surface. The vertical portion may or may not be perpendicular to the bottom surface.

[0051] The channel structure 138 may pass together through the second gate pattern 118 and the select gate pattern 108a. The channel structure 138 may be regularly arranged in a first direction and a second direction. Each of the select gate pattern 108a, the first gate pattern 114, and the second gate pattern 118 may cover at least a portion of the channel structure 138, or may extend around the channel structure 138. In some embodiments, each of the select gate pattern 108a, the first gate pattern 114, and the second gate pattern 118 may surround the channel structure 138, such as... Figure 3 and Figure 4 As shown. When used here, “component A covers or extends around component B” (or similar language) means that component A extends over component B, but does not necessarily mean that component A completely covers or completely surrounds component B.

[0052] The channel structure 138 may include a channel 134, a gate insulating layer pattern 132 on the outer wall of the channel 134, and a drain region 136 at the upper part of the channel 134.

[0053] In some embodiments, the drain region 136 can be formed by doping the upper portion of the channel 134 with impurities, and the channel 134 and the drain region 136 can comprise the same semiconductor material. In an example embodiment, the channel 134 and the drain region 136 can comprise polycrystalline silicon or monocrystalline silicon.

[0054] In an example embodiment, channel 134 may have a cylindrical shape. In some embodiments, channel 134 may have a hollow cylindrical shape. In this case, a buried insulating pattern may be further formed to fill the interior space of channel 134. The bottom of channel 134 may contact common source region 102, such that channel 134 and common source region 102 can be electrically connected to each other.

[0055] The first surface of the gate insulating layer pattern 132 may contact the channel 134. In addition, the second surface of the gate insulating layer pattern 132 may contact the second gate pattern 118, the first gate pattern 114 and the select gate pattern 108a.

[0056] Therefore, the stacked structure including channel 134, gate insulating layer pattern 132, and select gate pattern 108a can be used as select transistor 20. The stacked structure including channel 134, gate insulating layer pattern 132, and first gate pattern 114 can be used as first transistor 22. The stacked structure including channel 134, gate insulating layer pattern 132, and second gate pattern 118 can be used as second transistor 24.

[0057] In an example implementation, channel 134 may include an intrinsic semiconductor material that is not doped with impurities.

[0058] The drain region 136 may be doped with an impurity having a second conductivity type different from the first conductivity type. For example, the second conductivity type may be P-type.

[0059] The fifth insulating intermediate layer 140 can be formed on the fourth insulating intermediate layer 122 and the channel structure 138.

[0060] Bit line contact 150 can pass through the fifth insulating interlayer 140. Bit line contact 150 can be electrically connected to the drain region 136 of channel structure 138. Furthermore, a bit line 152 extending in a second direction can be formed on bit line contact 150. That is, bit line 152 can extend in a direction perpendicular to the extension direction of selected gate pattern 108a and second gate pattern 118. Bit line structure 154 may include bit line contact 150 and bit line 152.

[0061] A sixth insulating intermediate layer 156 may be formed on the fifth insulating intermediate layer 140 to fill the space between the multiple bit lines 152.

[0062] As described above, each unit cell of the memory device may include a first transistor 22 and a second transistor 24 having an energy barrier. One of the first transistor 22 and the second transistor 24 may include a gate pattern having an unpatterned shape. That is, the first transistor 22 and the second transistor 24 may have a common gate pattern shared with other unit cells in the cell region. Therefore, the process for forming the gate pattern can be simplified, and defects in the memory device can be reduced.

[0063] Furthermore, in memory devices, each element included in a unit cell can be stacked in the vertical direction. Therefore, the horizontal area of ​​the substrate used to form the unit cell can be reduced, allowing for high integration of the memory device.

[0064] In the following, a method for operating a unit cell of a storage device according to an example embodiment may be described.

[0065] Figure 6 It is the IV curve of the bit line in the unit cell of the exemplary embodiment of the present invention. Figure 7 The energy band of the channel is shown in an example embodiment of the invention when data 0 is written into the unit cell. Figure 8 The energy band of the channel is shown in an example embodiment of the present invention when data 1 is written into a unit cell.

[0066] exist Figure 7 and Figure 8 middle, Figure 1 Part A is shown in the horizontal direction. For example... Figure 7 and Figure 8 As shown, the drain region 136, the second transistor 24, the first transistor 22, the select transistor 20, and the source region 102 can be arranged sequentially from the bit line structure.

[0067] Due to the difference in work function between the first gate pattern 114 and the second gate pattern 118, the channel of a single cell can have a high energy barrier. Furthermore, the energy barrier of the channel can be adjusted by applying voltage to the first gate pattern 114 and the second gate pattern 118.

[0068] Reference Figure 6 Bit line current (I) BL It can exhibit hysteresis characteristics. Therefore, in a unit cell, the bit line current (I0) BL - Line voltage (V) BL The curve of ) can be used as a thyristor operation.

[0069] Reference Figure 6 and Figure 7 The unit cell can adjust the applied voltage of the first gate pattern 114 and the applied voltage of the second gate pattern 118 to have a high energy barrier at the channel, so that data 0 can be written into the unit cell. In this case, almost no current can flow through the unit cell, and data 0 can be read by sensing the current.

[0070] Reference Figure 6 and Figure 8 The unit cell can adjust the applied voltage of the first gate pattern 114 and the applied voltage of the second gate pattern 118 to have a low energy barrier at the channel. A positive feedback loop can then be generated, causing the channel energy barrier to collapse. Therefore, data 1 can be written into the unit cell. In this case, current can flow through the unit cell, and data 1 can be read by sensing the current.

[0071] When the unit cell is in operation, the voltage between the common source region 102 and the drain region 136 can be controlled by adjusting the applied voltage of the selected gate pattern 108a.

[0072] The methods for performing data write, read, and hold operations in a storage device will be described in detail below. The storage device can operate as a DRAM device.

[0073] Figure 9 This is a timing diagram of the applied voltage to a selected unit cell based on the operation of a storage device according to an exemplary embodiment of the present invention.

[0074] Table 1 shows a specific example of the applied voltage for the selected unit cell. However, the applied voltage is not limited to this.

[0075] Table 1

[0076]

[0077] Write data 1

[0078] When data 1 is written into the unit cell, the selection transistor 20 of the selected unit cell can be fully turned on. Therefore, a turn-on voltage can be applied to the selection gate.

[0079] In each operation, the same first voltage can be applied to the first gate pattern 114. The first voltage can be a negative voltage. Therefore, in the initial state, the energy barrier facing the channel of the first gate pattern 114 can be maintained at a high level.

[0080] A second voltage can be applied to the second gate pattern 118, and a first line voltage can be applied to the bit line.

[0081] In this configuration, the energy barrier between the channels facing the first gate pattern 114 and the second gate pattern 118 can be reduced, allowing holes to be injected into the channel facing the second gate pattern 118. Conversely, electrons can be injected into the channel facing the first gate pattern 114. When a positive feedback loop is generated, the energy barrier may collapse. Therefore, the energy barrier between the channels facing the first gate pattern 114 and the second gate pattern 118 is lowered, allowing drain current to flow through the channels.

[0082] Write data 0

[0083] When the data 0 is written into the unit cell, the selection transistor 20 of the selected unit cell can be completely turned off. Therefore, a turn-off voltage can be applied to the selection gate.

[0084] A second voltage can be applied to the second gate pattern 118, and a second bit line voltage can be applied to the bit line. The second bit line voltage can be lower than the first bit line voltage.

[0085] A first voltage can be applied to the first gate pattern 114 such that the energy barrier of the channel facing the first gate pattern 114 can be maintained at a high level. A constant DC voltage can be applied to the first gate pattern 114.

[0086] In this configuration, the channel facing the second gate pattern 118 can have a lower energy barrier than the drain region 136. Therefore, the high energy barrier between the channels facing the first gate pattern 114 and the second gate pattern 118 allows the drain current to flow almost entirely through the channel.

[0087] Keep data 1 or data 0

[0088] After data is written to the selected cell, the written data can be retained. The applied voltage for retaining the data can be similar to the applied voltage for writing data 0. However, a turn-on voltage can be applied to the selected gate pattern. Furthermore, a third voltage can be applied to the second gate pattern 118, and the third voltage can be higher than the second voltage. Therefore, data can be retained in the cell without writing data to it.

[0089] Read data

[0090] The voltage applied for reading data can be similar to the voltage applied for holding data. However, the first line voltage can be applied to the bit line. Therefore, data may not be written into the unit cell. The data written into the selected unit cell can be distinguished by measuring the current flowing through the selected unit cell.

[0091] Figures 10 to 29 These are cross-sectional and plan views illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention.

[0092] Reference Figure 10 and Figure 11 A substrate 100 having an impurity-doped cell region of a first conductivity type can be used to form a common source region 102 at the upper part of the substrate 100.

[0093] A lower sacrificial layer 104 may be formed on the common source region 102 of the substrate 100. The lower sacrificial layer 104 may serve as an etch stop layer and an impurity diffusion barrier layer. In some example embodiments, the lower sacrificial layer 104 may not be formed.

[0094] Reference Figure 12 and Figure 13 A first insulating intermediate layer 106 may be formed on the lower sacrificial layer 104. A select gate layer 108 may be formed on the first insulating intermediate layer 106.

[0095] In an example implementation, the gate layer 108 may comprise polysilicon doped with impurities. The impurities may be N-type or P-type impurities.

[0096] Reference Figure 14 and Figure 15 The select gate layer 108 can be patterned to form select gate patterns 108a. Each select gate pattern 108a can have a line extending in a first direction. A first trench 110 extending in the first direction can be formed between the select gate patterns 108a.

[0097] Reference Figure 16 and Figure 17 A second insulating intermediate layer 112 can be formed on the selected gate pattern 108a to fill the first trench 110 between the selected gate patterns 108a.

[0098] In an example implementation, an insulating layer may be formed to fill the first trench 110 between the select gate patterns 108a. The insulating layer may be planarized until the upper surface of the select gate pattern 108a can be exposed. Thereafter, an insulating layer may be further formed on the select gate pattern 108a and the insulating layer to form a second insulating intermediate layer 112. Thus, the upper surface of the second insulating intermediate layer 112 may be planar.

[0099] A first gate layer 114 can be formed on the second insulating intermediate layer 112.

[0100] The first gate layer 114 may include a conductive material having a first work function. In an example embodiment, the first gate layer 114 may be a polysilicon layer doped with p-type impurities.

[0101] The patterning process for the first gate layer 114 can be omitted. Therefore, the first gate layer 114 can be formed on the substrate 100 of the cell region and can be used as a common first gate pattern for the first transistors. A single first gate layer 114 can be the gate for all of the plurality of first transistors. Hereinafter, the first gate layer 114 is referred to as the first gate pattern and is given the same reference numerals as the first gate pattern. Because the patterning process for the first gate layer 114 is omitted, the process can be simplified and process defects can be reduced.

[0102] Reference Figure 18 and Figure 19 A third insulating intermediate layer 116 may be formed on the first gate pattern 114. A second gate layer may be formed on the third insulating intermediate layer 116.

[0103] The second gate layer may include a conductive material having a second work function lower than the first work function. In an example embodiment, the second gate layer may be a polysilicon layer doped with N-type impurities.

[0104] Subsequently, the second gate layer can be patterned to form a second gate pattern 118. Each second gate pattern 118 may have a line extending in the first direction. A second trench 120 extending in the first direction may be formed between the second gate patterns 118. Thus, the second gate patterns 118 can be configured to face the selected gate pattern 108a.

[0105] Reference Figure 20 and Figure 21 A fourth insulating intermediate layer 122 can be formed on the second gate pattern 118 to fill the second trench 120.

[0106] In an example implementation, an insulating layer may be formed to fill the second trench 120, and then the insulating layer may be planarized until the upper surface of the second gate pattern 118 can be exposed. Thereafter, an insulating layer may be further formed on the second gate pattern 118 and the insulating layer to form a fourth insulating intermediate layer 122. Therefore, the upper surface of the fourth insulating intermediate layer 122 can be planar.

[0107] A stop layer 124 may be formed on the fourth insulating intermediate layer 122. The stop layer 124 may comprise an insulating material that is etch-selective relative to silicon oxide. In an example embodiment, the stop layer 124 may comprise a silicon nitride. In some example embodiments, a stop layer may not be formed.

[0108] A hard mask layer can be formed on the stop layer 124, and the hard mask layer can be patterned to form a hard mask 126. In the patterning process used to form the hard mask, the stop layer 124 can be used as an etch stop layer. The hard mask 126 may include a hole 127 that exposes the stop layer 124 disposed on the second gate pattern 118 and the select gate pattern 108a.

[0109] Reference Figure 22 Hard mask 126 can be used as an etching mask to sequentially etch stop layer 124, fourth insulating intermediate layer 122, second gate pattern 118, third insulating intermediate layer 116, first gate pattern 114, second insulating intermediate layer 112, selected gate pattern 108a, and first insulating intermediate layer 106 to form initial channel via 128. In the etching process, lower sacrificial layer 104 can be used as an etch stop layer. Therefore, lower sacrificial layer 104 can be exposed at the bottom of initial channel via 128.

[0110] Reference Figure 23A gate insulating layer can be conformally formed on the sidewalls and bottom of the initial channel via 128 and on the surface of the hard mask 126. The gate insulating layer can be etched anisotropically, and then the sacrificial layer 104 can be etched off to form a channel via 130 that exposes the common source region 102. A gate insulating layer pattern 132 can be formed on the sidewalls of the channel via 130.

[0111] The channel hole 130 can be formed through the second gate pattern 118, the first gate pattern 114 and the select gate pattern 108a.

[0112] Reference Figure 24 and Figure 25 A channel layer can be formed on the gate insulating layer pattern 132, the hard mask 126, and the common source region 102 to fully fill the channel via 130. The channel layer may include, for example, a single-crystal semiconductor material or polycrystalline silicon.

[0113] In an example embodiment, the process for forming the channel layer may include a selective epitaxial growth process using a substrate 100 as a seed crystal. In this case, the channel layer may include, for example, a single-crystal semiconductor material. For example, the channel layer may include single-crystal silicon and silicon-germanium. In some example embodiments, the channel layer may include MoS, graphene, etc.

[0114] In some example implementations, the channel layer may include polycrystalline silicon formed by a chemical vapor deposition process.

[0115] Subsequently, the channel layer and hard mask 126 can be planarized until the upper surface of the stop layer 124 can be exposed. During the planarization process, the hard mask 126 can be removed. Therefore, the channel 134 can be formed in the channel hole 130.

[0116] Reference Figure 26 and Figure 27 The upper part of the channel 134 can be doped with impurities of a second conductivity type to form a drain region 136.

[0117] The bottom of the drain region 136 may be higher than the top surface of the second gate pattern 118.

[0118] In an example implementation, the stop layer 124 may be removed after the drain region 136 is formed. In some example implementations, the stop layer 124 may not be removed.

[0119] Therefore, a channel structure 138 can be formed in the channel via 130. The channel structure 138 may include a channel 134, a gate insulating layer pattern 132, and a drain region 136.

[0120] Reference Figure 28 and Figure 29A fifth insulating intermediate layer 140 and a sixth insulating intermediate layer 156 can be formed on the fourth insulating intermediate layer 122 and the channel structure 138 (see reference). Figure 3 ).

[0121] The sixth insulating intermediate layer 156 can be etched to form a trench 144 extending in the second direction. In addition, the fifth insulating intermediate layer 140 exposed at the bottom of the trench 144 can be etched to form a first contact hole 142 exposing the upper surface of the channel structure 138.

[0122] Refer again Figures 1 to 3 A conductive layer can be formed to fill the trench 144 and the first contact hole 142. The conductive layer can be planarized until the upper surface of the sixth insulating intermediate layer 156 can be exposed to form bit lines 152 filling the trench 144 and bit line contacts 150 filling the first contact hole 142.

[0123] Bit line 152 can extend in the second direction. Therefore, bit line 152 can intersect with the selected gate pattern 108a and the second gate pattern 118.

[0124] As described above, memory devices can be manufactured. In the process for manufacturing memory devices, the first gate pattern does not need to be patterned, thereby simplifying the process.

[0125] In example implementations, each unit cell in the memory device may include a source region, a select transistor, a first transistor, a second transistor, and a drain region. However, in some example implementations, the elements included in the unit cell may be arranged in various ways in the vertical direction, and the first transistor and the second transistor may be arranged adjacent to each other.

[0126] Various examples of the arrangement of elements included in a unit cell can be described with reference to Table 2. Each element can be arranged at one of the first to fifth layers from the substrate. That is, refer to... Figure 1 The memory devices shown can correspond to Example 1 in Table 2. In Table 2, the selection transistor, common gate, and gate with a linear shape are referred to as the selection TR, the first gate, and the second gate, respectively.

[0127] [Table 2]

[0128] Level 1 Second level Third level Fourth level Fifth level Example 1 Source region Select TR First gate Second gate Drain region Example 2 Source region First gate Second gate Select TR Drain region Example 3 Source region Select TR Second gate First gate Drain region Example 4 Source region Second gate First gate Select TR Drain region Example 5 Drain region Select TR First gate Second gate Source region Example 6 Drain region First gate Second gate Select TR Source region Example 7 Drain region Select TR Second gate First gate Source region Example 8 Drain region Second gate First gate Select TR Source region

[0129] In Examples 1 to 4, the source regions may be formed on the substrate. In Examples 1 to 4, the source regions may be formed over the entire upper portion of the substrate, or each source region may have a linear shape extending in a second direction.

[0130] In Examples 5 to 8, the drain region may be formed on the substrate. In Examples 5 to 8, the drain region may be formed over the entire upper portion of the substrate, or each drain region may have a linear shape extending in a second direction.

[0131] In some example implementations, each unit cell may include two selection transistors. That is, each unit cell may include a source region, a lower selection transistor, a first transistor, a second transistor, an upper selection transistor, and a drain region. In each example in Table 2, the upper selection transistor may be further formed between the fourth and fifth layers.

[0132] Figure 30A This is a cross-sectional view illustrating an exemplary embodiment of a stacked storage device according to a concept of the present invention. Figure 30B This is a cross-sectional view illustrating an exemplary embodiment of a stacked storage device according to a concept of the present invention.

[0133] like Figure 30A and Figure 30B As shown, the storage device may further include storage cells stacked in the vertical direction.

[0134] Reference Figure 30A In a memory device, bit line 152 can be formed between a lower cell LC and an upper cell UC above it, and bit line 152 can be shared by both the lower cell LC and the upper cell UC. In this case, the lower cell LC and the upper cell UC can be symmetrical about bit line 152.

[0135] Reference Figure 30B In a memory cell, a common source region 102 can be formed between the lower cell LC and the upper cell UC above it. In this case, the lower cell LC and the upper cell UC can be symmetrical about the common source region 102.

[0136] Figures 31 to 35 These are cross-sectional and plan views illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention.

[0137] In addition to the option that the gate pattern can be formed of metal, the memory cells of this memory device can be compared with a reference. Figure 1 The storage cells of the storage devices shown are basically the same.

[0138] Reference Figure 31 and Figure 32 First, it can be executed and referenced. Figure 10 and Figure 11 The process shown is the same as the process described. Thereafter, a first insulating intermediate layer 106 can be formed on the lower sacrificial layer 104. A first sacrificial layer can be formed on the first insulating intermediate layer 106.

[0139] The first sacrificial layer may include a material that is etch-selective relative to the lower sacrificial layer 104 and the subsequently formed first and second gate layers.

[0140] For example, when the lower sacrificial layer 104 comprises aluminum oxide, the first sacrificial layer may comprise silicon nitride. For example, the lower sacrificial layer 104 may not be formed.

[0141] The first sacrificial layer can be patterned to form a first sacrificial pattern 160. Each first sacrificial pattern 160 can have a line extending in a first direction. First grooves 110 extending in the first direction can be formed between the first sacrificial patterns 160.

[0142] Then, it can be executed and referenced. Figures 12 to 27 The same process is shown. Subsequently, a fifth insulating intermediate layer 140 can be formed on the fourth insulating intermediate layer 122 and the channel structure 138.

[0143] Reference Figure 33 and Figure 34 An etching process can be performed to replace the first sacrificial pattern with a metallic material through a replacement process.

[0144] Specifically, the fifth insulating intermediate layer 140, the fourth insulating intermediate layer 122, the second gate pattern 118, the third insulating intermediate layer 116, the first gate pattern 114, the second insulating intermediate layer 112, the first sacrificial pattern 160, and the first insulating intermediate layer 106 can be etched sequentially to form a trench 162 extending in the second direction. For example, the trench 162 can be formed at the boundary of the cell block.

[0145] The first sacrificial pattern 160 exposed by the sidewalls of the trench 162 can be removed to form the gap 164. Since the trench 162 extends in the second direction, all of the first sacrificial pattern 160 can be removed along the second direction.

[0146] Reference Figure 35 A metallic material can be formed to fully fill the gap 164. In an example embodiment, a barrier metal layer can be conformally formed on the surface of the gap 164, and a metal layer can be formed on the barrier metal layer to fill the gap 164. The barrier metal layer may include, for example, titanium, titanium nitride, tantalum, and tantalum nitride. The metal layer may include, for example, tungsten.

[0147] Subsequently, the filling groove (162, such as) can be selectively removed. Figure 34 The metal material (as referenced) is used to form the selected gate pattern 168 that fills the gap 164. Additionally, an insulating material (not shown) may be formed to fill the trench 162.

[0148] As described above, the memory device may include a select gate pattern comprising a metallic material having a lower resistance than that of polysilicon.

[0149] Figure 36 and Figure 37 This is a cross-sectional view illustrating an exemplary embodiment of a storage device according to a concept of the present invention. Figure 38 This is a circuit diagram of a unit storage cell in a storage device according to an exemplary embodiment of the present invention.

[0150] Figure 36 This is a cross-sectional view of the storage device cut in the second direction. Figure 37 It is a cross-sectional view of the storage device cut in the first direction.

[0151] In the following text, Figures 36 to 38 Each element included in the storage device shown can be individually connected to... Figures 1 to 3 Each element in the illustrated memory device is substantially the same. That is, a unit cell of the memory device may include a source region, a selection transistor, a first transistor, a second transistor, and a drain region.

[0152] However, in this memory device, the first gate pattern 114 can be electrically connected to the common source region 102. In an example embodiment, the second gate pattern 118 and the select gate pattern 108a can extend perpendicularly to each other, and the bit line 152 can extend in the same direction as the extension direction of the second gate pattern 118. That is, the select gate pattern 108a can extend in a first direction, and the second gate pattern 118 and the bit line 152 can extend in a second direction. Overlay wiring can be electrically connected to each unit cell.

[0153] Reference Figures 36 to 38 Each unit cell in the memory device may include a channel structure 138 formed on a substrate 100 and a first gate pattern 114, a second gate pattern 118, and a select gate pattern 108a formed on the sidewalls of the channel structure 138. The first gate pattern 114, the second gate pattern 118, and the select gate pattern 108a may be spaced apart from each other in the vertical direction. Furthermore, a common source region 102 may be formed at the top of the substrate 100. A bit line structure 154 may be formed on the channel structure 138, and the bit line structure 154 may be electrically connected to the channel structure 138. Furthermore, similar to... Figure 1 The storage device shown may include first to sixth insulating intermediate layers 106, 112, 116, 122, 140 and 156.

[0154] The upper insulating intermediate layer 170 can cover the bit line structure 154 and the structure formed below the bit line structure 154.

[0155] In an example implementation, in a unit cell of the memory device, a first gate pattern 114 may be formed at the lowest level, and a selected gate pattern 108a may be formed at the highest level.

[0156] The cell region of the substrate 100 may include a cell block region with a square shape.

[0157] In the cell block region, the selected gate pattern 108a may extend in a first direction. The first gate pattern 114 may be unpatterned, allowing it to have a wide pattern shape. The second gate pattern 118 may extend in a second direction. Furthermore, the bit line 152 included in the bit line structure 154 may extend in the second direction.

[0158] In an example embodiment, the edge portions of the select gate pattern 108a in the first direction may each include a metal pattern 108b. A polysilicon pattern may be formed between the metal patterns 108b. That is, since the metal patterns 108b with low resistance can be included at the edge portions of the select gate pattern 108a, the resistance of the select gate pattern 108a can be reduced.

[0159] The first contact plug 180 may be electrically connected to each select gate pattern 108a. The first contact plug 180 may contact the upper surface of the select gate pattern 108a located at the edge portion of the cell block region in a first direction. The first contact plug 180 may extend through the upper insulating interlayer 170 to the upper surface of the select gate pattern 108a. In an example embodiment, the first contact plug 180 may contact the upper surface of the metal pattern 108b in the select gate pattern 108a. The first contact plug 180 may be electrically insulated from the bit line 152 and the first gate pattern 114 and the second gate pattern 118.

[0160] In an example implementation, the edge portions of the first gate pattern 114 and the second gate pattern 118 in the second direction may have a stepped shape.

[0161] The second contact plug 182 may be electrically connected to the first gate pattern 114 and the common source region 102. The second contact plug 182 may contact the edge portion of the first gate pattern 114 in the second direction and may extend to the common source region 102.

[0162] In an example implementation, the second contact plug 182 may penetrate the upper insulating intermediate layer 170 and may contact the surface of the first gate pattern 114 and the upper surface of the common source region 102. For example, the second contact plug 182 may contact the sidewalls and upper surface of the first gate pattern 114 and may extend into the common source region 102. For example, the second contact plug 182 may penetrate the first gate pattern 114 and may contact the first gate pattern 114 and the common source region 102. In this case, the second contact plug 182 may be electrically insulated from the bit line 152, the second gate pattern 118, and the select gate pattern 108a.

[0163] The third contact plug 184 may be electrically connected to the second gate pattern 118. The third contact plug 184 may contact the upper surface of the second gate pattern 118 located at the edge portion of the cell block region in the second direction. The third contact plug 184 may pass through the upper insulating intermediate layer 170 and may extend to the upper surface of the second gate pattern 118. The third contact plug 184 may be electrically insulated from the bit line 152, the first gate pattern 114, and the select gate pattern 108a.

[0164] As described above, the first gate pattern 114 and the common source region 102 can be electrically connected to each other. Therefore, wiring can be simplified.

[0165] In this configuration, the electronic barrier of the first transistor 22 can be controlled to be high. Therefore, the memory cell can be operated even when the same voltage is applied to the first gate pattern 114 and the common source region 102.

[0166] For example, the work function of the first gate pattern 114 can be controlled to be high. That is, the work function of the first gate pattern 114 can be controlled by the doping of materials, impurities, etc. For example, the electronic barrier of the first transistor can be controlled by the work function of the channel 134 of the first transistor 22 or by the fixed charge located at the gate insulating layer pattern 132 or the channel of the first transistor 22.

[0167] Figure 39 and Figure 40 This is a cross-sectional view illustrating an exemplary embodiment of a storage device according to a concept of the present invention.

[0168] Figure 39 This is a cross-sectional view of the storage device cut in the second direction. Figure 40 It is a cross-sectional view of the storage device cut in the first direction.

[0169] In addition to the contact plugs connected to each unit cell, Figure 39 and Figure 40 The storage device shown can be used with Figure 36 and Figure 37The vertical semiconductor devices shown are basically the same.

[0170] Reference Figure 38 , Figure 39 and Figure 40 Each unit in the storage device may include a first transistor 22, a second transistor 24 and a selection transistor 20 stacked sequentially on a substrate.

[0171] In an example implementation, the edge portions of the first gate pattern 114 and the second gate pattern 118 in the first direction may have a stepped shape.

[0172] The second contact plug 182 can be electrically connected to the first gate pattern 114 and the common source region 102. The second contact plug 182 can be formed on the edge portion of the first gate pattern 114 in a first direction.

[0173] The third contact plug 184 can be electrically connected to the second gate pattern 118. The third contact plug 184 can contact the upper surface of the second gate pattern 118 at the edge portion in the second direction.

[0174] The first contact plug 180 may be electrically connected to each select gate pattern 108a. The first contact plug 180 may contact the upper surface of the select gate pattern 108a located at the edge portion of the cell block region in a first direction.

[0175] As described above, each unit cell of the memory device may include a source region, a select transistor, a first transistor, a second transistor, and a drain region. In some example embodiments, in each element included in the unit cell, at least two of the electrodes other than the select gate pattern of the select transistor may be electrically connected to each other and may be shared.

[0176] Various examples of connections between electrodes included in a unit cell can be described with reference to a circuit diagram.

[0177] Figures 41 to 45 These are circuit diagrams illustrating exemplary embodiments of the storage device according to the present invention.

[0178] Figures 41 to 43 Each unit cell in the memory device shown may have a selection transistor 20, a first transistor 22 and a second transistor 24 stacked sequentially from the substrate.

[0179] Reference Figure 41The first gate pattern and the second gate pattern can be electrically connected to each other and can be used as a common electrode. In this case, the difference in work function between the first gate pattern and the second gate pattern can be controlled to be increased. Therefore, even when the same voltage is applied to the first gate pattern and the second gate pattern, a sufficiently high energy barrier can be generated.

[0180] Reference Figure 42 The second gate pattern can be electrically connected to the drain region. That is, the second gate pattern and the bit line can be electrically connected to each other and can be used as a common electrode.

[0181] Reference Figure 43 The first gate pattern, the second gate pattern, and the drain region can be electrically connected to each other and can be used as a common electrode.

[0182] Figure 44 and Figure 45 Each unit cell in the memory device shown may have a first transistor 22, a second transistor 24 and a selection transistor 20 stacked sequentially from the substrate.

[0183] Reference Figure 44 The first gate pattern and the second gate pattern can be electrically connected to each other and can be used as a common electrode.

[0184] Reference Figure 45 The first gate pattern, the second gate pattern, and the source region can be electrically connected to each other and can be used as a common electrode.

[0185] As described above, in each element included in the unit cell, at least two of the electrodes, excluding the select gate pattern of the select transistor, can be electrically connected to each other and can be shared. Therefore, wiring can be simplified.

[0186] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting the inventive concept. Although some exemplary embodiments have been described, those skilled in the art will readily recognize that many modifications are possible in the exemplary embodiments without substantially departing from the scope of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. It will therefore be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

[0187] This application claims priority to Korean Patent Application No. 10-2019-0173982, filed on December 24, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device comprising: a source region including a first impurity having a first conductivity type at an upper portion of a substrate; a plurality of channels contacting the source region, each of the plurality of channels extending in a vertical direction perpendicular to an upper surface of the substrate, and the plurality of channels including a first channel and a second channel; a gate insulating layer pattern covering a portion of the first channel; a select gate pattern on the gate insulating layer pattern, the select gate pattern extending in a first direction parallel to the upper surface of the substrate; a first gate pattern on the gate insulating layer pattern; a second gate pattern on the gate insulating layer pattern, the second gate pattern extending parallel to the select gate pattern; and a drain region including a second impurity having a second conductivity type different from the first conductivity type at an upper portion of the first channel, wherein the select gate pattern, the first gate pattern, and the second gate pattern are spaced apart from each other in the vertical direction, wherein at least one of the source region and the first gate pattern has a plate shape and is a common electrode of the first channel and the second channel, and wherein the first gate pattern includes a first conductive material having a first work function, and the second gate pattern includes a second conductive material having a second work function different from the first work function.

2. The memory device of claim 1, wherein the plurality of channels are arranged in the first direction and a second direction parallel to the upper surface of the substrate and transverse to the first direction, the first gate pattern having a single plate shape covering a portion of each of the plurality of channels.

3. The memory device of claim 1, wherein the second gate pattern extends in the first direction.

4. The memory device of claim 3, wherein the first channel and the second channel are spaced apart in the first direction, and wherein each of the select gate pattern and the second gate pattern covers the portion of the first channel and a portion of the second channel.

5. The memory device of claim 1, wherein a bit line is electrically connected to the drain region, and the bit line extends in a second direction perpendicular to the first direction.

6. The memory device of claim 1, wherein each of the plurality of channels includes a semiconductor material.

7. The memory device of claim 1, wherein the second work function is lower than the first work function.

8. The memory device of claim 1, wherein the second channel is spaced apart from the first channel in a second direction parallel to the upper surface of the substrate and transverse to the first direction, and the select gate pattern includes a first select gate pattern covering the portion of the first channel and a second select gate pattern covering a portion of the second channel and spaced apart from the first select gate pattern in the second direction.

9. The memory device of claim 1, wherein the select gate pattern, the first gate pattern, and the second gate pattern are between the source region and the drain region, and wherein the select gate pattern is not between the first gate pattern and the second gate pattern.

10. The memory device of claim 1, wherein at least two of the first gate pattern, the second gate pattern, the source region, and the drain region are electrically connected to each other.

11. The memory device of claim 1, wherein the first gate pattern and the source region are electrically connected to each other.

12. A memory device, comprising: a source region including a first impurity having a first conductivity type at an upper portion of a substrate; a plurality of channels contacting the source region, each of the plurality of channels extending in a vertical direction perpendicular to an upper surface of the substrate, the plurality of channels being arranged in a first direction and a second direction parallel to the upper surface of the substrate and perpendicular to each other, and the plurality of channels including a first channel, a second channel spaced apart from the first channel in the first direction, and a third channel spaced apart from the first channel in the second direction; a gate insulating layer pattern covering a portion of the first channel; a select gate pattern on the gate insulating layer pattern, the select gate pattern covering the portion of the first channel and a portion of the second channel and extending in the first direction; a first gate pattern on the gate insulating layer pattern; a second gate pattern on the gate insulating layer pattern, the second gate pattern covering the portion of the first channel and the portion of the second channel and extending in the first direction; a drain region including a second impurity having a second conductivity type different from the first conductivity type at an upper portion of the first channel; and a bit line electrically connected to the drain region, the bit line extending in the second direction, wherein the select gate pattern, the first gate pattern, and the second gate pattern are spaced apart from each other in the vertical direction, wherein the first gate pattern covers the portion of the first channel and the portion of the second channel and a portion of the third channel, and is a common gate for the first channel, the second channel, and the third channel, and wherein the first gate pattern includes a first conductive material having a first work function, and the second gate pattern includes a second conductive material having a second work function different from the first work function.

13. The memory device of claim 12, wherein the first gate pattern is a single pattern covering the portion of the first channel, the portion of the second channel, and the portion of the third channel.

14. The memory device of claim 12, wherein the second work function is lower than the first work function. ​ 15. The memory device of claim 12, wherein the select gate pattern includes a first select gate pattern covering the portion of the first channel and a second select gate pattern covering the portion of the third channel and spaced apart from the first select gate pattern in the second direction.

16. A semiconductor device comprising: a source region including a first impurity having a first conductivity type at an upper portion of a substrate; a plurality of channels contacting the source region, each of the plurality of channels extending in a vertical direction perpendicular to an upper surface of the substrate; a plurality of select gate patterns on sidewalls of the plurality of channels, respectively; a first gate pattern on the sidewalls of the plurality of channels; a plurality of second gate patterns on the sidewalls of the plurality of channels, respectively; and a plurality of drain regions including a second impurity having a second conductivity type different from the first conductivity type at respective upper portions of the plurality of channels, wherein the first gate pattern includes a first conductive material having a first work function and the plurality of second gate patterns include a second conductive material having a second work function different from the first work function.

17. The semiconductor device of claim 16, wherein the second work function is lower than the first work function.

18. The semiconductor device of claim 16, wherein the plurality of drain regions are spaced apart from the source region in the vertical direction, and the plurality of select gate patterns, the first gate pattern, the plurality of second gate patterns are between the plurality of drain regions and the source region.

19. The semiconductor device of claim 16, further comprising a bit line electrically connected to one of the plurality of drain regions. ​

Images