Built-in self-test circuit and temperature measurement circuit including built-in self-test circuit

Abstract

A temperature measurement circuit comprises: a bandgap reference circuit configured to generate a fixed bandgap reference voltage that is independent of an operating temperature; a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the bandgap reference voltage; a sensing circuit configured to generate a temperature-varying voltage based on a bias current, wherein the temperature-varying voltage varies according to the operating temperature; an analog-to-digital converter circuit configured to generate a first digital code indicating the operating temperature based on the measurement reference voltage and the temperature-varying voltage; and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the bandgap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0175903 filed on December 27, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate generally to semiconductor integrated circuits, and more particularly to a built-in self-test (BIST) circuit and a temperature measurement circuit including the BIST circuit. Background Art

[0004] The operating temperature can be monitored and measured to improve the performance of semiconductor integrated circuits. For example, based on the measured operating temperature, the power level of the electronic device can be controlled, the refresh cycle of the storage device can be controlled, the circuit damage can be prevented, and so on. As the operating speed and performance level increase, thermal management becomes more important. An on-chip temperature sensor integrated in the same semiconductor die as the integrated circuit can be used to detect the temperature of each junction of the integrated circuit. If the on-chip temperature sensor fails, the performance of the semiconductor integrated circuit may be degraded or the semiconductor integrated circuit may be damaged due to erroneous information about the operating temperature. Specifically, erroneous temperature information of a semiconductor integrated circuit used in a vehicle may directly affect the life of the vehicle driver. Summary of the invention

[0005] According to an exemplary embodiment of the present invention, a temperature measurement circuit includes: a bandgap reference circuit, configured to generate a fixed bandgap reference voltage that is independent of an operating temperature; a reference voltage generator circuit, configured to generate a measurement reference voltage by adjusting the bandgap reference voltage; a sensing circuit, configured to generate a temperature-varying voltage based on a bias current, wherein the temperature-varying voltage varies according to the operating temperature; an analog-to-digital converter circuit, configured to generate a first digital code indicating the operating temperature based on the measurement reference voltage and the temperature-varying voltage; and an analog built-in self-test (BIST) circuit, configured to generate a plurality of flag signals indicating whether each of the bandgap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

[0006] According to an exemplary embodiment of the inventive concept, a temperature measurement circuit includes: a temperature detection circuit and an analog built-in self-test (BIST) circuit. The temperature detection circuit includes: an analog circuit configured to generate a fixed measurement reference voltage independent of an operating temperature and a temperature-varying voltage that varies according to the operating temperature; and an analog-to-digital converter circuit configured to generate a digital code indicating the operating temperature based on the measurement reference voltage and the temperature-varying voltage. The analog BIST circuit generates a plurality of flag signals indicating whether each of a plurality of voltages of the analog circuit is included in a predetermined range.

[0007] According to an exemplary embodiment of the present invention, a built-in self-test (BIST) circuit configured to monitor a temperature detection circuit including an analog circuit and an analog-to-digital converter circuit includes: an analog BIST circuit configured to generate a plurality of flag signals indicating whether each of a plurality of monitoring voltages of the analog circuit is included in a predetermined range; and a digital BIST circuit configured to apply a test signal to the analog-to-digital converter circuit in a test mode to generate a plurality of alarm signals indicating whether the analog-to-digital converter circuit operates normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0009] Figure 1 is a diagram illustrating a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0010] Figure 2 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A block diagram of the analog circuit included in the temperature measurement circuit.

[0011] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 A circuit diagram of a bandgap reference circuit included in the analog circuit.

[0012] Figure 4 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 A circuit diagram of a reference voltage generator included in an analog circuit.

[0013] Figure 5 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 A circuit diagram of a sensing circuit included in an analog circuit.

[0014] Figure 6 is a circuit diagram illustrating a bandgap reference voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0015] Figure 7 is used to describe an exemplary embodiment according to the inventive concept Figure 6 Diagram of the operation of the bandgap reference voltage monitor.

[0016] Figure 8 is a circuit diagram illustrating a measurement reference voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0017] Fig. 9 is used to describe an exemplary embodiment according to the inventive concept Figure 8 A diagram of the measurement reference voltage monitor's operation.

[0018] Fig.10 is a circuit diagram illustrating a bias voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0019] Fig.11 is used to describe an exemplary embodiment according to the inventive concept Fig.10 Diagram of the operation of the bias voltage monitor.

[0020] Fig.12 is a block diagram illustrating an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0021] Fig.13 is a circuit diagram for describing a bias current and a bias voltage of an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0022] Fig.14 is a block diagram illustrating a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0023] Fig.15 and Fig.16 is used to describe exemplary embodiments according to the inventive concept Fig.14 FIG. 5 is a diagram of an example operation of a digital BIST circuit.

[0024] Fig.17 and Fig.18 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0025] Fig.19 is used to describe exemplary embodiments according to the inventive concept Fig.14 FIG. 5 is a diagram of an example operation of a digital BIST circuit.

[0026] Fig. 20 and Fig.21is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0027] Fig. 22 is used to describe exemplary embodiments according to the inventive concept Fig.14 FIG. 5 is a diagram of an example operation of a digital BIST circuit.

[0028] Fig.23 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0029] Fig.24 is a block diagram illustrating an analog-to-digital converter included in a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0030] Fig.25 and Fig.26 is used to describe an exemplary embodiment according to the inventive concept Fig.24 FIG. 1 is a diagram of an example operation of an analog-to-digital converter.

[0031] Fig. 27 is a graph for describing a transition time of a ramp voltage according to an exemplary embodiment of the inventive concept.

[0032] Fig.28 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0033] Fig.29 is a diagram illustrating an example layout of a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0034] Fig.30 is a diagram showing an exemplary embodiment according to the inventive concept Fig.29 A circuit diagram of an example configuration of a temperature measurement circuit.

[0035] Fig.31 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0036] Fig.32 is a diagram illustrating a semiconductor integrated circuit including a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0037] Fig.33 is a diagram illustrating an operation of a system including a temperature measurement circuit according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0038] Exemplary embodiments of the inventive concept provide a built-in self-test (BIST) circuit capable of effectively monitoring a temperature detection circuit and a temperature measurement circuit including the BIST circuit.

[0039] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings.Throughout the application, like reference numerals may refer to like elements.

[0040] Figure 1 is a diagram illustrating a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0041] refer to Figure 1 , the temperature measurement circuit 1000 may include a temperature detection circuit 10 and a built-in self-test (BIST) circuit 20. As will be described below with reference to Fig.32 As described, the temperature detection circuit 10 and the BIST circuit 20 may be integrated in the same semiconductor die, in which case the temperature measurement circuit 1000 may be referred to as an on-chip temperature sensor.

[0042] The temperature detection circuit 10 may include an analog circuit 100 and an analog-to-digital converter ADC 200 .

[0043] The analog circuit 100 can generate a fixed measurement reference voltage VREF independent of the operating temperature and a temperature-varying voltage VTEM that varies according to the operating temperature. The analog-to-digital converter 200 can generate a digital code DCD indicating the operating temperature based on the measurement reference voltage VREF and the temperature-varying voltage VTEM. The analog-to-digital converter 200 can be a circuit.

[0044] The BIST circuit 20 may include at least one of the analog BIST circuit ABIST 300 and the digital BIST circuit DBIST 400. In an exemplary embodiment of the inventive concept, the BIST circuit 20 may include only the analog BIST circuit 300, and the digital BIST circuit 400 may be omitted. In an exemplary embodiment of the inventive concept, the BIST circuit 20 may include only the digital BIST circuit 400, and the analog BIST circuit 300 may be omitted. In an exemplary embodiment of the inventive concept, the BIST circuit 20 may include both the analog BIST circuit 300 and the digital BIST circuit 400.

[0045] The analog BIST circuit 300 may generate a plurality of flag signals FG1-FGk indicating whether each of the plurality of monitoring voltages VM1-VMk of the analog circuit 100 is included in a normal range. The normal range may be a predetermined range indicating normal operation of a particular component. The monitoring voltage may indicate a voltage used in the analog circuit 100 and / or provided to other components (e.g., the analog-to-digital converter 200) outside the analog circuit 100. For example, the monitoring voltages VM1-VMk may include a voltage as will be described below with reference to Figures 6 to 13 The described measurement comprises at least one of a reference voltage VREF, a temperature-dependent voltage VTEM and a bias voltage VBS.

[0046] The digital BIST circuit 400 may apply the test signal TS to the analog-to-digital converter 200 in the test mode to generate a plurality of alarm signals ALM1-ALMs indicating whether the analog-to-digital converter 200 is operating normally. The digital BIST circuit 400 may apply the test signal TS instead of the temperature-dependent voltage VTEM in the test mode to receive the digital code DCD for generating the plurality of alarm signals ALM1-ALMs. Figures 14 to 31 A plurality of alarm signals ALM1 -ALMs will be described.

[0047] In this way, the BIST circuit and the temperature measurement circuit according to the exemplary embodiment of the inventive concept can effectively diagnose the failure of the temperature measurement circuit by monitoring whether the multiple voltages are within the normal range using the BIST circuit. In addition, the BIST circuit and the temperature measurement circuit according to the exemplary embodiment of the inventive concept can effectively diagnose the analog-to-digital converter included in the temperature measurement circuit by performing various tests using the digital BIST circuit.

[0048] Figure 2 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A block diagram of the analog circuit included in the temperature measurement circuit.

[0049] refer to Figure 2 , the analog circuit 100 may include a bandgap reference circuit GBGR 110, a reference voltage generator GREF 120, and a sensing circuit GTEM 130. The reference voltage generator 120 may be a circuit.

[0050] The bandgap reference circuit 110 can generate a fixed bandgap reference voltage VBGR that is independent of the operating temperature. The reference voltage generator 120 can generate a measurement reference voltage VREF by adjusting the bandgap reference voltage VBGR. Similar to the bandgap reference voltage VBGR, the measurement reference voltage VREF can be fixed and independent of the operating temperature. The sensing circuit 130 can generate a temperature-dependent voltage VTEM based on the bias current IBS, so that the temperature-dependent voltage VTEM can change according to the operating temperature.

[0051] Figure 2 It is illustrated that the bias current IBS is provided from the bandgap reference circuit 110 , but the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, the bias current IBS may be generated in the sensing circuit 130 .

[0052] In the following, reference will be made to Figures 3 to 5 1. The exemplary embodiment of the bandgap reference circuit 110, the reference voltage generator 120, and the sensing circuit 130 is described. However, the inventive concept is not limited to Figures 3 to 5 The configuration of the analog circuit 100 can be implemented differently.

[0053] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 A circuit diagram of a bandgap reference circuit included in the analog circuit.

[0054] refer to Figure 3 The bandgap reference circuit 110 may include a first p-channel metal oxide semiconductor (PMOS) transistor PM11, a second PMOS transistor PM12, a first resistor R1, a second resistor R2, a third resistor R3, a feedback amplifier AMP, a first sensing unit 111 and a second sensing unit 112, which are as shown in FIG. Figure 3 The ground is shown connected between the power supply voltage VDD and the ground voltage VSS.

[0055] The first sensing unit 111 may be implemented using a single signal bipolar junction transistor (BJT), and the second sensing unit 112 may be implemented using a plurality of BJTs. Using such a bandgap reference circuit, a fixed bandgap reference voltage VBGR and / or bandgap reference current independent of operating temperature may be provided.

[0056] The emitter voltage of the second sensing unit 112 is inversely proportional to the operating temperature. The voltage across the third resistor R3 and the current flowing through the third resistor R3 are proportional to the operating temperature. As a result, the bandgap reference voltage VBGR can be fixed regardless of the operating temperature through the positive and negative proportional characteristics of the circuit. For example, the bandgap reference voltage VBGR can be provided at the connection node of the second PMOS transistor PM12 and the second resistor R2.

[0057] Figure 4 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 A circuit diagram of a reference voltage generator included in an analog circuit.

[0058] refer to Figure 4 The reference voltage generator 120 may include an amplifier AMP, a PMOS transistor PM21, and a plurality of voltage dividing resistors R0-RN. Figure 4 As shown, the ground is connected between the power supply voltage VDD and the ground voltage VSS. The measurement reference voltage VREF and the multiple divided voltages VREF1 to VREFN can be determined according to the ratio of the divided voltage resistors R0 to RN. The amplifier AMP, the PMOS transistor PM21 and the resistor R0 form a feedback loop, so the divided voltage VREF1 can converge to the bandgap reference voltage VBGR. The bandgap reference voltage VBGR can be fixed, so the measurement reference voltage VREF proportional to the bandgap reference voltage VBGR can be fixed regardless of the operating temperature.

[0059] Figure 5 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 A circuit diagram of a sensing circuit included in an analog circuit.

[0060] refer to Figure 5 , the sensing circuit 130 may include a current-voltage converter 135 , a first amplifier AMP1 , a second amplifier AMP2 , a first resistor R1 , and a second resistor R2 .

[0061] The current-voltage converter 135 may include a current source CST and a sensing unit SU connected between a power supply voltage VDD and a ground voltage VSS. The sensing unit SU may be implemented using a BJT. The sensing voltage VBE corresponding to the emitter voltage of the BJT may be inversely proportional to the operating temperature. The positive terminal of the first amplifier AMP1 may receive the sensing voltage VBE, and the negative terminal may be connected to the output terminal, so that the first amplifier AMP1 may form a unit gain amplifier. The output terminal of the first amplifier AMP1 may be connected to the negative terminal of the second amplifier AMP2 through a first resistor R1. The second amplifier AMP2 may receive a reference voltage VREFi through a positive terminal. The output terminal of the second amplifier AMP2 may be connected to the negative terminal of the second amplifier AMP2 through a second resistor R2.

[0062] Through such a configuration, the sensing voltage VBE which is inversely proportional to the operating temperature can be inverted and amplified to generate a temperature-varying voltage VTEM which increases as the operating temperature increases.

[0063] As reference Figures 3 to 5 As described above, a fixed measurement reference voltage VREF that is independent of the operating temperature and a temperature-varying voltage VTEM that varies according to the operating temperature can be provided to the Figure 1 The analog-to-digital converter 200 in FIG. The analog-to-digital converter 200 may generate a digital code DCD indicating an operating temperature based on a measurement reference voltage VREF and a temperature-varying voltage VTEM.

[0064] Figure 62 is a circuit diagram illustrating a bandgap reference voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept, and Figure 7 is used to describe an exemplary embodiment according to the inventive concept Figure 6 Diagram of the operation of the bandgap reference voltage monitor.

[0065] refer to Figure 6 , the bandgap reference voltage monitor 310 may include a power supply voltage divider 311 and a comparator COM1. The power supply voltage divider 311 and the comparator COM1 may be circuits.

[0066] The power supply voltage divider 311 may generate a power supply divided voltage VD11 corresponding to the lowest limit level of the bandgap reference voltage VBGR by dividing the power supply voltage VDD.

[0067] In an exemplary embodiment of the present inventive concept, Figure 6 As shown, the power supply voltage divider 311 may include: a first voltage dividing resistor R11 connected between the power supply voltage VDD and the voltage dividing node N11; and a second voltage dividing resistor R12 connected between the voltage dividing node N11 and the ground voltage VSS. The power supply divided voltage VD11 may be provided at the voltage dividing node N11, and the power supply divided voltage VD11 corresponds to the lowest limit level of the normal range for setting the bandgap reference voltage VBGR. In other words, if the bandgap reference voltage VBGR is excessively reduced, it is determined that the bandgap reference voltage VBGR deviates from the normal range. The lowest limit level of the bandgap reference voltage VBGR or the power supply divided voltage VD11 may be appropriately controlled by adjusting the resistance ratio of the first voltage dividing resistor R11 and the second voltage dividing resistor R12.

[0068] refer to Figure 6 and Figure 7 The comparator COM1 can generate the bandgap flag signal FG1 by comparing the bandgap reference voltage VBGR with the power supply divided voltage VD11, so that the bandgap flag signal FG1 can be activated when the bandgap reference voltage VBGR is lower than the lowest limit level of the bandgap reference voltage VBGR.

[0069] For example, when the bandgap reference voltage VBGR is higher than the lowest limit level, the bandgap flag signal FG1 can be deactivated to a first logic level (e.g., a logic low level L); when the bandgap reference voltage VBGR is lower than the lowest limit level, the bandgap flag signal FG1 can be activated to a second logic level (e.g., a logic high level H).

[0070] Figure 8 is a circuit diagram illustrating a measurement reference voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept, and Fig. 9is used to describe an exemplary embodiment according to the inventive concept Figure 8 A diagram of the measurement reference voltage monitor's operation.

[0071] refer to Figure 8 , the measurement reference voltage monitor 320 may include a bandgap reference voltage divider 321, a measurement reference voltage divider 322, and a comparator COM2. The bandgap reference voltage divider 321, the measurement reference voltage divider 322, and the comparator COM2 may be circuits.

[0072] The bandgap reference voltage divider 321 can generate a first bandgap divided voltage VD21 corresponding to the highest limit level of the measurement reference voltage VREF and a second bandgap divided voltage VD22 corresponding to the lowest limit level of the measurement reference voltage VREF by dividing the bandgap reference voltage VBGR.

[0073] In an exemplary embodiment of the present inventive concept, Figure 8 As shown, the bandgap reference voltage divider 321 may include: a first voltage dividing resistor R21, connected between the power supply voltage VDD and the first voltage dividing node N21; a second voltage dividing resistor R22, connected between the first voltage dividing node N21 and the second voltage dividing node N22; and a third voltage dividing resistor R23, connected between the second voltage dividing node N22 and the ground voltage VSS.

[0074] A first bandgap voltage division VD21 may be provided at a first voltage division node N21, and the first bandgap voltage division V21 may correspond to the highest limit level of a normal range for setting a measurement reference voltage VREF. A second bandgap voltage division VD22 may be provided at a second voltage division node N22, and the second bandgap voltage division V22 may correspond to the lowest limit level of a normal range for setting a measurement reference voltage VREF. In other words, if the bandgap reference voltage VBGR excessively increases or decreases, it is determined that the measurement reference voltage VREF deviates from the normal range. The highest and lowest limit levels of the measurement reference voltage VREF, or the first bandgap voltage division VD21 and the second bandgap voltage division VD22 may be appropriately controlled by adjusting the resistance ratio of the first voltage division resistor R21, the second voltage division resistor R22, and the third voltage division resistor R23.

[0075] The measurement reference voltage divider 322 may generate a measurement divided voltage VD23 by dividing the measurement reference voltage VREF.

[0076] In an exemplary embodiment of the present inventive concept, Figure 8As shown, the measurement reference voltage divider 322 may include: a fourth voltage-dividing resistor R24 ​​connected between the measurement reference voltage VREF and the third voltage-dividing node N23; and a fifth voltage-dividing resistor R25 connected between the third voltage-dividing node N23 and the ground voltage VSS. The measurement voltage division VD23 may be provided at the third voltage-dividing node N23. The measurement voltage division VD23 may be appropriately controlled by adjusting the resistance ratio of the fourth voltage-dividing resistor R24 ​​and the fifth voltage-dividing resistor R25.

[0077] refer to Figure 8 and Fig. 9 The comparator COM2 can generate a reference voltage flag signal FG2 by comparing the measurement voltage divider VD23 with the first bandgap voltage divider VD21 and the second bandgap voltage divider VD22, thereby activating the reference voltage flag signal FG2 when the measurement reference voltage VREF is higher than the highest limit level of the measurement reference voltage VREF or lower than the lowest limit level of the measurement reference voltage VREF.

[0078] For example, when the measurement reference voltage VREF is lower than the highest limit level and higher than the lowest limit level, the reference voltage flag signal FG2 can be deactivated to a first logic level (e.g., a logic low level L), and when the measurement reference voltage VREF is higher than the highest limit level or lower than the lowest limit level, the reference voltage flag signal FG2 can be activated to a second logic level (e.g., a logic high level H).

[0079] Fig.10 is a circuit diagram illustrating a bias voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept, Fig.11 is used to describe an exemplary embodiment according to the inventive concept Fig.10 Diagram of the operation of the bias voltage monitor.

[0080] refer to Fig.10 , the bias voltage monitor 330 may include a measurement reference voltage divider 331, a current-voltage converter 332, and a comparator COM3. The measurement reference voltage divider 331, the current-voltage converter 332, and the comparator COM3 may be a circuit.

[0081] The measurement reference voltage divider 331 can generate a first measurement reference divided voltage VD31 corresponding to the highest limit level of the bias voltage VBS and a second measurement reference divided voltage VD32 corresponding to the lowest limit level of the bias voltage VBS by dividing the measurement reference voltage VREF.

[0082] In an exemplary embodiment of the present inventive concept, Fig.10As shown, the bias voltage divider 331 may include: a first voltage dividing resistor R31, connected between the measurement reference voltage VREF and the first voltage dividing node N31; a second voltage dividing resistor R32, connected between the first voltage dividing node N31 and the second voltage dividing node N32; and a third voltage dividing resistor R33, connected between the second voltage dividing node N32 and the ground voltage VSS.

[0083] A first measurement reference voltage division VD31 may be provided at a first voltage division node N31, and the measurement reference voltage division VD31 may correspond to the highest limit level of a normal range for setting the bias voltage VBS. A second measurement reference voltage division VD32 may be provided at a second voltage division node N32, and the second measurement reference voltage division VD32 may correspond to the lowest limit level of a normal range for setting the bias voltage VBS. In other words, if the bias voltage VBS is excessively increased or decreased, it is determined that the bias voltage VBS deviates from the normal range. The highest and lowest limit levels of the bias voltage VBS, or the first measurement reference voltage division VD31 and the second measurement reference voltage division VD32 may be appropriately controlled by adjusting the resistance ratio of the first voltage division resistor R31, the second voltage division resistor R32, and the third voltage division resistor R33.

[0084] The current-to-voltage converter 332 may generate a bias voltage VBS based on the bias current IBS. Fig.10 As shown, the current-voltage converter 332 may include a current source CSM and a resistor R34 connected between the power supply voltage VDD and the ground voltage VSS. In an exemplary embodiment of the inventive concept, the current source CSM may be omitted, and in this case, the current source CSM may be provided. Figure 2 The bandgap reference circuit 110 in provides a bias current IBS.

[0085] refer to Fig.10 and Fig.11 The comparator COM3 can generate a bias voltage flag signal FG3 by comparing the bias voltage VBS with the first measurement reference divided voltage VD31 and the second measurement reference divided voltage VD32, thereby activating the bias voltage flag signal FG3 when the bias voltage VBS is higher than the highest limit level of the bias voltage VBS or lower than the lowest limit level of the bias voltage VBS.

[0086] For example, when the bias voltage VBS is lower than the highest limit level and higher than the lowest limit level, the bias voltage flag signal FG3 can be deactivated to a first logic level (e.g., a logic low level L); when the bias voltage VBS is higher than the highest limit level or lower than the lowest limit level, the bias voltage flag signal FG3 can be activated to a second logic level (e.g., a logic high level H).

[0087] Fig.12is a block diagram illustrating an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0088] refer to Fig.12 , the analog BIST circuit 350 may include a bandgap reference voltage monitor VMON1 310, a measurement reference voltage monitor VMON2 320, and a bias voltage monitor VMON3 330. Each of the bandgap reference voltage monitor 310, the measurement reference voltage monitor 320, and the bias voltage monitor 330 may be a circuit. The analog BIST circuit 350 may receive a bandgap reference voltage VBGR and a measurement reference voltage VREF from the analog circuit 100. In addition, the analog BIST circuit 350 may generate a bias voltage VBS internally based on a bias current IBS. According to an exemplary embodiment of the inventive concept, the analog BIST circuit 350 may receive a bias current IBS from the analog circuit 100 or generate a bias current IBS internally.

[0089] As reference Figure 6 and Figure 7 As described, the bandgap reference voltage monitor 310 may generate the bandgap flag signal FG1 based on the bandgap reference voltage VBGR and the power supply voltage VDD, such that the bandgap flag signal FG1 may be activated when the bandgap reference voltage VBGR deviates from its normal range.

[0090] As reference Figure 8 and Fig. 9 As described, the measurement reference voltage monitor 320 may generate the reference voltage flag signal FG2 based on the measurement reference voltage VREF and the bandgap reference voltage VBGR, and thus may activate the reference voltage flag signal FG2 when the measurement reference voltage VREF deviates from its normal range.

[0091] As reference Fig.10 and Fig.11 As described, the bias voltage monitor 330 may generate the bias voltage flag signal FG3 based on the bias voltage VBS corresponding to the bias current IBS and the measurement reference voltage VREF, and thus may activate the bias voltage flag signal FG3 when the bias voltage VBS deviates from its normal range.

[0092] In other words, each of the monitors 310 , 320 , and 330 may generate one of the flag signals FG1 , FG2 , and FG3 by comparing one monitoring voltage with one comparison reference voltage.

[0093] As reference Figure 6 and Figure 7 As described, in the case of the bandgap reference voltage monitor 310, the power supply voltage VDD corresponds to the comparison reference voltage, and the bandgap reference voltage VBGR corresponds to the monitoring voltage. Figure 8 and Fig. 9 As described, in the case of the measurement reference voltage monitor 320, the bandgap reference voltage VBGR corresponds to the comparison reference voltage, and the measurement reference voltage VREF corresponds to the monitoring voltage. Fig.10 and Fig.11 As described, in the case of the bias voltage monitor 330 , the measurement reference voltage VREF corresponds to the comparison reference voltage, and the bias voltage VBS corresponds to the monitoring voltage.

[0094] In this way, the monitoring voltage of one voltage monitor can be used as a comparison reference voltage of another voltage monitor. As described above, the bandgap reference voltage VBGR corresponding to the monitoring voltage of the bandgap reference voltage monitor 310 can be used as a comparison reference voltage of the measurement reference voltage monitor 320, and the measurement reference voltage VREF corresponding to the monitoring voltage of the measurement reference voltage monitor 320 can be used as a comparison reference voltage of the bias voltage monitor 330. In this way, the deviation of the monitoring voltage of the previous voltage monitor can be propagated to the next voltage monitor, so that the last voltage monitor can determine the comprehensive deviation of multiple voltage monitors.

[0095] According to an exemplary embodiment of the inventive concept, the analog BIST circuit may include one or two of the bandgap reference voltage monitor 310, the measurement reference voltage monitor 320, and the bias voltage monitor 330. In addition, the analog BIST circuit according to an exemplary embodiment of the inventive concept may include four or more voltage monitors for monitoring whether four or more voltages are included in their respective normal ranges.

[0096] Fig.13 is a circuit diagram for describing a bias current and a bias voltage of an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0097] Fig.13 shows a reference in which Figure 5 The current-to-voltage converter 135 included in the sensing circuit 130 described above and the Fig.10 The current-voltage converter 332 included in the bias voltage monitor 330 described above is implemented as an integral exemplary embodiment. Figure 5 and Fig.10 Provide a description.

[0098] refer to Fig.13 , the current-voltage converter 135 of the sensing circuit 130 may include a first current source CST for generating the bias current IBS, and the current-voltage converter 332 of the bias voltage monitor 330 may include a second current source CSM for generating the bias current IBS.

[0099] The first current source CST and the second current source CSM may include PMOS transistors PM1 and PM2 forming a current mirror. In this case, a standard for normal operation of the analog circuit 100 may be appropriately set by generating a temperature-fixed bias voltage VBS and a temperature-varying sense voltage VBE using the same bias current IBS.

[0100] Fig.14 is a block diagram illustrating a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0101] refer to Fig.14 , the digital BIST circuit 400 may include a counter 410, a memory MEM 420, a test signal generator GTS 430, and a digital logic block DLB 440. The elements of the digital BIST circuit 400 may be circuits.

[0102] The counter 410 can monitor the operation timing of the analog-to-digital converter 200. The counter 410 can generate a count signal CNT corresponding to the operation timing based on the timing signal TIM and the clock signal CLK. For example, as will be described below with reference to Figure 24 to Figure 25 As described above, the timing signal TIM may include a scanning start signal SOS, a conversion start signal SOC, a conversion end signal EOC, and the like.

[0103] The memory 420 may store information for operation of the digital BIST circuit 400 and information on test results obtained by the digital BIST circuit 400 .

[0104] The test signal generator 430 may generate a test signal TS for respective tests. In the test mode, the test signal TS may be applied to the analog-to-digital converter 200 instead of the temperature-varying voltage VTEM.

[0105] The digital logic block 440 may receive the digital code DCD, control the overall operation of the digital BIST circuit 400 , and generate a plurality of alarm signals MONO, LNT, OFF, STC, FLT, FCT, STT, CNV, and PRV according to test results.

[0106] Fig.15 and Fig.16 It is used to describe the exemplary embodiments according to the inventive concept Fig.14 FIG. 5 is a diagram of an example operation of a digital BIST circuit.

[0107] refer to Fig.14 and Fig.15, the test signal generator 430 may generate a ramp voltage VRMP having a voltage level that sequentially increases or sequentially decreases in the test mode, and apply the ramp voltage VRMP to the analog-to-digital converter 200 as the test signal TS. Fig.15 A non-limiting example is shown in which the ramp voltage VRMP increases sequentially.

[0108] The digital logic block 440 can test whether the analog-to-digital converter 200 operates normally based on a plurality of values ​​DL1-DLp obtained by applying the ramp voltage VRMP instead of the temperature-varying voltage VTEM to the analog-to-digital converter 200 in the test mode. Fig.15 As shown, the analog-to-digital converter 200 can be implemented so that the values ​​DL1-DLp can increase as the temperature-dependent voltage VTEM or the ramp voltage VRMP increases. According to an exemplary embodiment of the inventive concept, the analog-to-digital converter 200 can be implemented so that the values ​​DL1-DLp can decrease as the temperature-dependent voltage VTEM or the ramp voltage VRMP increases.

[0109] Fig.16 The monotonicity and linearity of example values ​​DL1-DLp of the digital code DCD are shown. The analog-to-digital converter 200 is required to generate a digital code DCD having a value that is monotonically linearly proportional to the operating temperature. By testing such monotonicity and linearity, it is determined whether the analog-to-digital converter 200 is operating properly.

[0110] Hereinafter, it is assumed that the alarm signal is activated at a logic high level H and is deactivated at a logic low level L, but the inventive concept is not limited thereto.

[0111] Fig.17 and Fig.18 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0112] refer to Fig.14 , Fig.15 and Fig.17 When the temperature measurement circuit enters the test mode ( S11 ), the test signal generator 430 may generate a ramp voltage VRMP and apply the ramp voltage VRMP as a test signal TS to the analog-to-digital converter 200 ( S12 ).

[0113] The digital logic block 440 may receive a plurality of values ​​DL1-DLp of the digital code DCD generated when the ramp voltage VRMP is applied to the analog-to-digital converter 200 (S13). The digital logic block 440 may determine whether the difference DLi+1-DLi between two adjacent values ​​DLi+1 and DLi among the plurality of values ​​DL1-DLp is less than zero (S14). When the difference DLi+1-DLi is less than zero (S14: Yes), the digital logic block 440 may activate the monotonic alarm signal MONO to a logic high level H (S15). On the contrary, when the difference DLi+1-DLi is not less than zero (S14: No), the digital logic block 440 may deactivate the monotonic alarm signal MONO to a logic low level L (S16).

[0114] In this manner, the digital BIST circuit 400 may generate the monotonic alarm signal MONO based on the plurality of values ​​DL1 ˜DLp of the digital code DCD, such that the monotonic alarm signal MONO may indicate whether the digital code DCD increases or decreases monotonically.

[0115] refer to Fig.14 , Fig.15 and Fig.18 When the temperature measurement circuit enters the test mode ( S21 ), the test signal generator 430 may generate a ramp voltage VRMP and apply the ramp voltage VRMP as a test signal TS to the analog-to-digital converter 200 ( S22 ).

[0116] The digital logic block 440 may receive a plurality of values ​​DL1-DLp of the digital code DCD generated when the ramp voltage VRMP is applied to the analog-to-digital converter 200 (S23). The digital logic block 440 may determine whether a difference DLi+1-DLi between two adjacent values ​​DLi+1 and DLi among the plurality of values ​​DL1-DLp is greater than a reference value RF1 (S24). When the difference DLi+1-DLi is greater than the reference value RF1 (S24: Yes), the digital logic block 440 may activate the linear alarm signal LNT to a logic high level H (S25). On the contrary, when the difference DLi+1-DLi is not greater than the reference value RF1 (S24: No), the digital logic block 440 may deactivate the linear alarm signal LNT to a logic low level L (S26).

[0117] In this way, the digital BIST circuit 400 can generate the linear alarm signal INT based on the plurality of values ​​DL1 ˜DLp of the digital code DCD, so that the linear alarm signal INT can indicate whether the digital code DCD is uniformly increasing or decreasing.

[0118] Fig.19 It is used to describe the exemplary embodiments according to the inventive concept Fig.14 FIG. 5 is a diagram of an example operation of a digital BIST circuit.

[0119] Fig.19 A voltage level VMAX corresponding to the maximum value DLMAX of the digital code DCD and a voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD are shown.

[0120] Fig.14 The test signal generator 430 in can generate a test signal TS, which has a voltage level VH higher than the voltage level VMAX corresponding to the maximum value DLMAX of the digital code DCD, a voltage level VL lower than the voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD, or a voltage level VI corresponding to the center value DLI of the digital code DCD.

[0121] The test signal TS can be used to perform the Fig. 20 and Fig.21 Describes the test operation.

[0122] Fig. 20 and Fig.21 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0123] refer to Fig.14 , Fig.19 and Fig. 20 When the temperature measurement circuit enters the test mode (S31), the test signal generator 430 may generate a test signal TS having a voltage level VI corresponding to a center value DLI of the digital code DCD to be applied to the analog-to-digital converter 200 (S32).

[0124] The digital logic block 440 may receive a measurement value DLI' of a digital code DCD generated when the voltage level VI is applied to the analog-to-digital converter 200 (S33). The digital logic block 440 may determine whether an absolute difference value |DLI-DLI'| between the measurement value DLI' and the center value DLI is greater than a reference value RF2 (S34). When the absolute difference value |DLI-DLI'| is greater than the reference value RF2 (S34: Yes), the digital logic block 440 may activate the offset alarm signal OFF to a logic high level H (S35). On the contrary, when the absolute difference value |DLI-DLI'| is not greater than the reference value RF2 (S34: No), the digital logic block 440 may deactivate the offset alarm signal OFF to a logic low level L (S35).

[0125] In this way, the digital BIST circuit 400 can generate the offset alarm signal OFF based on the measurement value DLI′ and the center value DLI, so that the offset alarm signal OFF can indicate whether the offset of the digital code DCD deviates from its normal range represented by the reference value RF2.

[0126] refer to Fig.14 , Fig.19 and Fig.21 When the temperature measurement circuit enters the test mode (S41), the test signal generator 430 may generate a test signal TS having a voltage level VH higher than a voltage level VMAX corresponding to a maximum value DLMAX of the digital code DCD to be applied to the analog-to-digital converter 200 (S42).

[0127] The digital logic block 440 may receive a first measurement value DLH of the digital code DCD generated when the voltage level VH is applied to the analog-to-digital converter 200 (S43). The digital logic block 440 may determine whether the first measurement value DLH is equal to the maximum value DLMAX (S44). When the first measurement value DLH is not equal to the maximum value DLMAX (S44: No), the digital logic block 440 may activate the clipping alarm signal STC to a logic high level H (S45).

[0128] When the first measurement value DLH is equal to the maximum value DLMAX ( S44 : YES), the test signal generator 430 may generate a test signal TS having a voltage level VL lower than a voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD to be applied to the analog-to-digital converter 200 ( S46 ).

[0129] The digital logic block 440 may receive a second measurement value DLL of the digital code DCD generated when the voltage level VL is applied to the analog-to-digital converter 200 (S47). The digital logic block 440 may determine whether the second measurement value DLL is equal to the minimum value DLMIN (S48). When the second measurement value DLL is not equal to the minimum value DLMIN (S48: No), the digital logic block 440 may activate the clipping alarm signal STC to a logic high level H (S45). When the second measurement value DLL is equal to the minimum value DLMIN (S48: Yes), the digital logic block 440 may deactivate the clipping alarm signal STC to a logic low level L (S49).

[0130] In this way, the digital BIST circuit 400 can generate the clipping alarm signal STC based on the first measurement value DLH and the second measurement value DLL, so that the clipping alarm signal STC can indicate whether each bit of the digital code DCD is fixed regardless of the operating temperature.

[0131] Fig. 22 It is used to describe the exemplary embodiments according to the inventive concept Fig.14 FIG. 5 is a diagram of an example operation of a digital BIST circuit.

[0132] refer to Fig. 22The digital BIST circuit 400 may further include a pull-up control circuit 450 connected to an output node NO that generates a digital code DCD of the analog-to-digital converter ADC 200. According to an exemplary embodiment of the inventive concept, the pull-up control circuit 450 may be included in the analog-to-digital converter 200.

[0133] The pull-up control circuit 450 of the digital BIST circuit may include: a pull-up resistor RU connected to a power supply voltage VDD; and a pull-up switch SWU configured to control the electrical connection between the pull-up resistor RU and an output node NO of the digital code DCD. In addition, the pull-up control circuit 450 may include: a pull-down resistor RD connected to a ground voltage VSS; and a pull-down switch SWD configured to control the electrical connection between the pull-down resistor RD and the output node NO of the digital code DCD. The pull-up control circuit 450 may be based on the output node NO of the digital code DCD. Fig.14 The digital logic block 440 in FIG. 4A provides switch control signals SCU and SCD to turn on the pull-up switch SWU and the pull-down switch SWD.

[0134] In other words, in the test mode, the digital BIST circuit applies a test signal TS having a voltage level (VH) higher than a voltage level VMAX corresponding to a maximum value DLMAX of the digital code DCD to the analog-to-digital converter 200 when the pull-down switch SWD is turned on, and applies a test signal TS having a voltage level (VL) lower than a voltage level VMIN corresponding to a minimum value DLMIN of the digital code DCD to the analog-to-digital converter 200 when the pull-up switch SWU is turned on, to generate a floating alarm signal FLT. Fig.23 This is further described.

[0135] For ease of explanation, Fig. 22 A configuration corresponding to one output node NO is shown. When a plurality of output nodes are implemented to output a plurality of bits of the digital code DCD in parallel, a plurality of pull-up control circuits may be respectively allocated to the plurality of output nodes.

[0136] Such a pull-up path and / or a pull-down path may be used to perform the Fig.23 The test operation described.

[0137] Fig.23 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0138] refer to Fig.14 , Fig. 22 and Fig.23, when the temperature measurement circuit enters the test mode (S51), the test signal generator 430 may activate the switch control signal SCD and pull down the output node NO by electrically connecting the output node NO to the ground voltage VSS (S52). In addition, the test signal generator 430 may generate a test signal TS having a voltage level VH higher than a voltage level VMAX corresponding to a maximum value DLMAX of the digital code DCD to be applied to the analog-to-digital converter 200 (S53).

[0139] The digital logic block 440 may receive a first measurement value DLH of the digital code DCD generated when the output node NO is pulled down and the voltage level VH is applied to the analog-to-digital converter 200 (S54). The digital logic block 440 may determine whether the first measurement value DLH is equal to the maximum value DLMAX (S55). When the first measurement value DLH is not equal to the maximum value DLMAX (S55: No), the digital logic block 440 may activate the floating alarm signal FLT to a logic high level H (S56).

[0140] When the first measurement value DLH is equal to the maximum value DLMAX (S55: Yes), the test signal generator 430 may activate the switch control signal SCH and pull up the output node NO by electrically connecting the output node NO to the power supply voltage VDD (S57). In addition, the test signal generator 430 may generate a test signal TS having a voltage level VL lower than a voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD to be applied to the analog-to-digital converter 200 (S58).

[0141] The digital logic block 440 may receive a second measurement value DLL of the digital code DCD generated when the output node NO is pulled up and the voltage level VL is applied to the analog-to-digital converter 200 (S59). The digital logic block 440 may determine whether the second measurement value DLL is equal to the minimum value DLMIN (S60). When the second measurement value DLL is not equal to the minimum value DLMIN (S60: No), the digital logic block 440 may activate the floating alarm signal FLT to a logic high level H (S56). When the second measurement value DLL is equal to the minimum value DLMIN (S60: Yes), the digital logic block 440 may deactivate the floating alarm signal FLT to a logic low level L (S61).

[0142] In this way, the digital BIST circuit 400 may generate the floating alarm signal FLT based on the first measurement value DLH and the second measurement value DLL, so that the floating alarm signal FLT may indicate whether the output node NO of the digital code DCD is disconnected.

[0143] Fig.24is a block diagram illustrating an analog-to-digital converter included in a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0144] refer to Fig.24 , the analog-to-digital converter 200 may include a scan voltage generator 210, a comparator COM 220, a converter 230, and a controller CTRL 240. The scan voltage generator 210, the comparator 220, the converter 230, and the controller 240 may be circuits. In addition, the analog-to-digital converter 200 may further include an input selector MUX 250 configured to select one of the temperature-varying voltage VTEM and the test signal TS based on the mode signal MD to apply the selected one to the comparator 220. Using the input selector 250, the test signal TS may be applied to the analog-to-digital converter 200 instead of the temperature-varying voltage VTEM in the test mode.

[0145] As will be referred to below Fig.25 and Fig.26 As described, the scan voltage generator 210 can generate a plurality of scan voltages VS0-VSq having different voltage levels based on the measurement reference voltage VREF, and output the plurality of scan voltages VS0-VSq one by one according to the unit scan time tS. The scan voltage generator 210 may include: a voltage divider 211 configured to generate a plurality of scan voltages VS0-VSq based on the measurement reference voltage VREF; and a selector MUX212 configured to select and output one of the plurality of scan voltages VSC based on a selection signal SEL.

[0146] The comparator 220 may generate a plurality of comparison result values ​​CMP by comparing the temperature-varying voltage VTEM or the test signal TS with the plurality of scan voltages VS0 ˜VSq. The converter 230 may generate a digital code DCD based on the plurality of comparison result values ​​CMP.

[0147] The controller 240 may control the scan voltage generator 210, the comparator 220, and the converter 230. The controller 240 may generate a selection signal SEL for controlling the selector 212. The controller 240 may generate a scan start signal SOS and a conversion start signal SOC for controlling the converter 230. The controller may receive a conversion end signal EOC from the converter 230.

[0148] Fig.25 and Fig.26 is used to describe an exemplary embodiment according to the inventive concept Fig.24 FIG. 1 is a diagram of an example operation of an analog-to-digital converter. Fig.25 An example is shown in which the temperature-dependent voltage VTEM corresponds to the value "010" of the digital code DCD. Fig.26Another example in which the temperature-varying voltage VTEM corresponds to a value of “110” of the digital code DCD is shown.

[0149] refer to Fig.25 and Fig.26 During the plurality of unit scan times tS, the plurality of scan voltages VS0-VSq may be selected by a binary scan scheme, thereby determining the scan voltage of the next unit scan time based on the comparison result of the comparator 220 during the previous unit scan time. However, the inventive concept is not limited to such a binary scan scheme.

[0150] Fig.14 The counter 410 in the embodiment may generate a stable alarm signal STT based on the scan start signal SOS and the conversion start signal SOC, so that the stable alarm signal STT may indicate whether the total scan time for outputting a plurality of scan voltages VS0 to VSq from the scan voltage generator 210 is shorter than the first reference time. Here, the total scan time corresponds to N*tS, where N is the number of bits of the digital code DCD, and tS is the unit scan time. In addition, the counter 410 may generate a conversion alarm signal CNV based on the conversion start signal SOC and the conversion end signal EOC, so that the conversion alarm signal CNV may indicate whether the conversion time tC of the digital code DCD generated by the converter 230 is shorter than the second reference time.

[0151] Fig. 27 is a graph for describing a transition time of a ramp voltage according to an exemplary embodiment of the inventive concept.

[0152] Fig. 27 A first case CASE1 and a second case CASE2 in which the scan voltage changes from a first scan voltage VSa to a second scan voltage VSb are shown. The first case CASE1 indicates that the transition time of the change is relatively short, and the second case CASE2 indicates that the transition time of the change is relatively long. If a binary scan scheme is performed based on a relatively short first unit scan time tSa, the transition time of the scan voltage may not be ensured. For example, the measurement value DLa under the first case CASE1 may indicate an accurate value of the digital code DCD, while the measurement value DLa under the second case CASE2 may include an error. In contrast, if a binary scan scheme is performed based on a relatively long second unit scan time tSb, the transition time of the scan voltage may be ensured. For example, the measurement value DLb may indicate an accurate value of the digital code DCD under the first case CASE1 and the second case CASE2.

[0153] This control of the unit scan time can be used to perform the following Fig.28 The test operation described.

[0154] Fig.28is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0155] refer to Fig.14 as well as Figure 24 to Figure 28 , when the temperature measurement circuit enters the test mode (S71), the digital BIST circuit 400 can control the analog-to-digital converter 200 so that the analog-to-digital converter 200 can perform a binary scan operation based on the first unit scan time tSa (S72), and the digital logic block 440 can receive a first measurement value DLa of the digital code DCD corresponding to the first unit scan time tSa (S73). In addition, the digital BIST circuit 400 can control the analog-to-digital converter 200 so that the analog-to-digital converter 200 can perform a binary scan operation based on the second unit scan time tSb (S74), and the digital logic block 440 can receive a second measurement value DLb of the digital code DCD corresponding to the second unit scan time tSb (S75).

[0156] The digital logic block 440 may determine whether the first measurement value DLa is equal to the second measurement value DLb (S76). When the first measurement value DLa is not equal to the second measurement value DLb (S76: No), the digital logic block 440 may activate the fluctuation alarm signal FCT to a logic high level H (S77). On the contrary, when the first measurement value DLa is equal to the second measurement value DLb (S76: Yes), the digital logic block 440 may deactivate the fluctuation alarm signal FCT to a logic low level L (S78).

[0157] In this way, the digital BIST circuit 400 can generate a fluctuation alarm signal FCT based on the first measurement value DLa corresponding to the first unit scan time tSa and the second measurement value DLb corresponding to the second unit scan time tSb, so that the fluctuation alarm signal FCT can indicate whether the unit scan time is included in the normal range.

[0158] Fig.29 is a diagram illustrating an example layout of a temperature measurement circuit according to an exemplary embodiment of the inventive concept, Fig.30 is a diagram showing an exemplary embodiment according to the inventive concept Fig.29 A circuit diagram of an example configuration of a temperature measurement circuit.

[0159] refer to Fig.29 and Fig.30 The temperature measurement circuit may include a main circuit 1001 and a plurality of local sensing units SUL1-SUL3, which are integrated in a semiconductor die SDIE. The main circuit 1001 may include a main sensing unit SUM. The main circuit 1001 may also include a temperature detection circuit and a BIST circuit as described above.

[0160] The main sensing unit SUM may be disposed at the main position POSM and generate a main sensing voltage VBEM that varies according to a main operating temperature at the main position POSM.

[0161] The plurality of local sensing units SUL1 ˜ SUL3 may be disposed at the plurality of local positions POSL1 ˜ POSL3 and generate a plurality of local sensing voltages VBEL1 ˜ VBEL3 that vary according to local operating temperatures at the plurality of local positions POSL1 ˜ POSL3 .

[0162] like Fig.30 As shown, the main sensing unit SUM and the plurality of local sensing units SUL1-SUL3 can be selectively connected to a current source generating a bias current IBS using switches SWM and SWL1-SWL3. Control signals SSM and SSL1-SSL3 for respectively controlling the switches SWM and SWL1-SWL3 can be provided from a digital logic block 440 in the digital BIST circuit 400, respectively.

[0163] Such a sensing unit can be used to perform the Fig.31 The test operation described.

[0164] Fig.31 is a flowchart illustrating a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0165] refer to Fig.14 as well as Figure 29 to Figure 31 , when the temperature measurement circuit enters the test mode (S81), the digital BIST circuit 400 may select the main sensing voltage VBEM generated by the main sensing unit SUM (S82), and receive the first measurement value DLM of the digital code DCD corresponding to the main sensing voltage VBEM (S83). In addition, the digital BIST circuit 400 may select the local sensing voltage VBEL1 generated by the local sensing unit SUL1 closest to the main sensing unit SUM (S84), and receive the second measurement value DLL1 of the digital code DCD corresponding to the local sensing voltage VBEL1 (S85).

[0166] The digital logic block 440 may determine whether the absolute difference value |DLM-DLL1| between the first measurement value DLM and the second measurement value DLL1 is greater than the reference value RF3 (S86). When the absolute difference value |DLM-DLL1| is greater than the reference value RF3 (S86: Yes), the digital logic block 440 may activate the probe check alarm signal PRV to a logic high level H (S87). On the contrary, when the absolute difference value |DLM-DLL1| is not greater than the reference value RF3 (S86: No), the digital logic block 440 may deactivate the probe check alarm signal PRV to a logic low level L (S88).

[0167] In this manner, the digital BIST circuit 400 may generate the probe check alarm signal PRV based on the first measurement value DLM corresponding to the main sensing voltage VBEM and the second measurement value DLL1 corresponding to the local sensing voltage VBEL1 .

[0168] Fig.32 is a diagram illustrating a semiconductor integrated circuit including a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0169] refer to Fig.32 , the semiconductor integrated circuit 2000 may include an internal circuit 30, a temperature detection circuit 10, a BIST circuit 20, and a control circuit 40, which are integrated in the same semiconductor die SDIE. In an exemplary embodiment of the present invention, the control circuit 40 may be arranged in another semiconductor die. The semiconductor die SDIE may include a semiconductor substrate SUP and a dielectric layer DLY above the semiconductor substrate SUB. The temperature detection circuit 10 may detect the operating temperature of the internal circuit 30, and the BIST circuit 20 may monitor whether the temperature detection circuit 10 operates normally. As described, the BIST circuit 20 may provide a flag signal and / or an alarm signal to the control circuit 40 as a monitoring result. The control circuit 40 may control the semiconductor integrated circuit 2000 based on the flag signal and / or the alarm signal.

[0170] Fig.33 is a diagram illustrating an operation of a system including a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0171] refer to Fig.33, when the system is powered on (S100), the temperature measurement circuit may perform a test operation (S200) in response to a power-on signal PWO. When the temperature measurement circuit operates normally (no fault), the temperature measurement circuit may detect the operating temperature of the system (S300). When the temperature measurement circuit operates abnormally (faulty), the system may enter a safe mode (S400), and the above-mentioned flag signal FG and / or alarm signal ALM may be provided by a BIST circuit included in the temperature measurement circuit. The system may set the temperature measurement circuit to a shutdown mode (S500) based on the flag signal FG and / or the alarm signal ALM. The system may power off the temperature measurement circuit (S600) in response to a power-off signal PWD to prevent the output of the temperature measurement circuit or save power consumption.

[0172] As described above, the BIST circuit and the temperature measurement circuit according to exemplary embodiments of the inventive concept may effectively diagnose a failure of the temperature measurement circuit by monitoring whether a plurality of voltages are within a normal range using the BIST circuit.

[0173] In addition, the BIST circuit and the temperature measurement circuit according to the exemplary embodiments of the inventive concept may effectively diagnose an analog-to-digital converter included in the temperature measurement circuit by performing various tests using a digital BIST circuit.

[0174] The inventive concept can be applied to any electronic device and system that needs information about operating temperature. For example, the inventive concept can be applied to various systems, such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video recorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0175] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A temperature measurement circuit, comprising: a bandgap reference circuit configured to generate a fixed bandgap reference voltage that is independent of operating temperature; a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the bandgap reference voltage; a sensing circuit configured to generate a temperature-varying voltage based on a bias current, wherein the temperature-varying voltage varies according to the operating temperature; an analog-to-digital converter circuit configured to generate a first digital code indicative of the operating temperature based on the measurement reference voltage and the temperature-varying voltage; and Simulates the built-in self-test (BIST) circuit, configured to generate: a first flag signal indicating whether the bandgap reference voltage is within a first predetermined range, a second flag signal indicating whether the measurement reference voltage is included in a second predetermined range, and A third flag signal indicates whether the bias voltage corresponding to the bias current is included in a third predetermined range.

2. The temperature measurement circuit according to claim 1, wherein the analog built-in self-test (BIST) circuit comprises: a power supply voltage divider circuit configured to generate a power supply divided voltage corresponding to the lowest limit level of the bandgap reference voltage by dividing the power supply voltage; as well as A comparator circuit is configured to generate a bandgap flag signal by comparing the bandgap reference voltage with the power supply divided voltage, wherein the bandgap flag signal is activated when the bandgap reference voltage is lower than a lowest limit level of the bandgap reference voltage.

3. The temperature measurement circuit according to claim 1, wherein the analog built-in self-test (BIST) circuit comprises: a bandgap reference voltage divider circuit configured to generate a first bandgap divided voltage corresponding to a highest limit level of the measurement reference voltage and a second bandgap divided voltage corresponding to a lowest limit level of the measurement reference voltage by dividing the bandgap reference voltage; a measurement reference voltage divider circuit configured to generate a measurement divided voltage by dividing the measurement reference voltage; as well as a comparator circuit configured to generate a reference voltage flag signal by comparing the measured divided voltage with the first bandgap divided voltage and the second bandgap divided voltage, wherein the reference voltage flag signal is activated when the measured reference voltage is higher than a highest limit level of the measured reference voltage or lower than a lowest limit level of the measured reference voltage.

4. The temperature measurement circuit according to claim 1, wherein the analog built-in self-test (BIST) circuit comprises: a measurement reference voltage divider circuit configured to generate a first measurement reference divided voltage corresponding to a highest limit level of the bias voltage and a second measurement reference divided voltage corresponding to a lowest limit level of the bias voltage by dividing the measurement reference voltage; a current-to-voltage converter circuit configured to generate the bias voltage based on the bias current; as well as A comparator circuit is configured to generate a bias voltage flag signal by comparing the bias voltage with the first measurement reference divided voltage and the second measurement reference divided voltage, wherein the bias voltage flag signal is activated when the bias voltage is higher than a highest limit level of the bias voltage or lower than a lowest limit level of the bias voltage.

5. The temperature measurement circuit according to claim 4, wherein: The sensing circuit includes a first current source configured to generate the bias current, and the current-to-voltage converter circuit includes a second current source configured to generate the bias current, such that the first current source and the second current source form a current mirror.

6. The temperature measurement circuit according to claim 1, wherein the analog built-in self-test (BIST) circuit comprises: a bandgap reference voltage monitoring circuit configured to generate a bandgap flag signal based on the bandgap reference voltage and a power supply voltage, wherein the bandgap flag signal is activated when the bandgap reference voltage deviates from a predetermined range of the bandgap reference voltage; a measurement reference voltage monitoring circuit configured to generate a reference voltage flag signal based on the measurement reference voltage and the bandgap reference voltage, wherein the reference voltage flag signal is activated when the measurement reference voltage deviates from a predetermined range of the measurement reference voltage; and The bias voltage monitoring circuit is configured to generate a bias voltage flag signal based on the bias voltage and the measurement reference voltage, wherein the bias voltage flag signal is activated when the bias voltage deviates from a predetermined range of the bias voltage.

7. The temperature measurement circuit according to claim 1, further comprising: A digital BIST circuit is configured to apply a test signal instead of the temperature-dependent voltage to the analog-to-digital converter circuit in a test mode to receive a second digital code from the analog-to-digital converter circuit, thereby generating a plurality of alarm signals based on the second digital code, wherein the plurality of alarm signals indicate whether the analog-to-digital converter circuit operates normally.

8. The temperature measurement circuit according to claim 7, wherein the digital BIST circuit comprises: The test signal generator circuit is configured to generate a ramp voltage having a sequentially increasing or sequentially decreasing voltage level in a test mode, and apply the ramp voltage as a test signal to the analog-to-digital converter circuit.

9. The temperature measurement circuit according to claim 8, wherein: the digital BIST circuit generating at least one of a monotonic alarm signal and a linear alarm signal based on a plurality of values ​​of the second digital code, The monotonic alarm signal indicates whether the second digital code is monotonically increasing or decreasing, and The linear alarm signal indicates whether the second digital code changes evenly.

10. The temperature measurement circuit according to claim 7, wherein: In a test mode, the digital BIST circuit applies a test signal having a voltage level corresponding to a center value of the second digital code to the analog-to-digital converter circuit to generate an offset alarm signal indicating whether a difference between a measured value of the second digital code and the center value of the second digital code is greater than a reference value.

11. The temperature measurement circuit according to claim 7, wherein: In a test mode, the digital BIST circuit applies a test signal having a higher voltage level than a voltage level corresponding to a maximum value of the second digital code to the analog-to-digital converter circuit, and applies a test signal having a lower voltage level than a voltage level corresponding to a minimum value of the second digital code to the analog-to-digital converter circuit to generate a clipping alarm signal indicating whether a first measured value of the second digital code is equal to the maximum value of the second digital code and whether a second measured value of the second digital code is equal to the minimum value of the second digital code.

12. The temperature measurement circuit according to claim 7, wherein the digital BIST circuit comprises: Pull-up resistor, connected to the supply voltage; a pull-up switch configured to control an electrical connection between the pull-up resistor and an output node of the second digital code; Pull-down resistor, connected to ground voltage; as well as A pull-down switch is configured to control an electrical connection between the pull-down resistor and the output node of the second digital code.

13. The temperature measurement circuit according to claim 12, wherein: In a test mode, the digital BIST circuit applies a test signal having a voltage level higher than a voltage level corresponding to a maximum value of the second digital code to the analog-to-digital converter circuit when the pull-down switch is turned on, and applies a test signal having a voltage level lower than a voltage level corresponding to a minimum value of the second digital code to the analog-to-digital converter circuit when the pull-up switch is turned on, so as to generate a floating alarm signal indicating whether a first measured value of the second digital code is equal to a maximum value of the second digital code and whether a second measured value of the second digital code is equal to a minimum value of the second digital code.

14. The temperature measurement circuit according to claim 7, wherein: The analog-to-digital converter circuit comprises: a scanning voltage generator circuit configured to generate a plurality of scanning voltages having different voltage levels based on the measurement reference voltage, and output the plurality of scanning voltages one by one according to a unit scanning time; a comparator circuit configured to generate a plurality of comparison result values ​​by comparing the temperature-dependent voltage with the plurality of scanning voltages; a converter circuit configured to generate the second digital code based on the plurality of comparison result values; and A controller circuit is configured to control the scan voltage generator circuit, the comparator circuit, and the converter circuit.

15. The temperature measurement circuit according to claim 14, wherein: The digital BIST circuit changes the unit scan time between a first unit scan time and a second unit scan time that is longer than the first unit scan time to generate a fluctuation alarm signal, wherein the fluctuation alarm signal indicates whether a first measurement value of the second digital code corresponding to the first unit scan time is equal to a second measurement value of the second digital code corresponding to the second unit scan time.

16. The temperature measurement circuit according to claim 14, wherein: The digital BIST circuit includes a counter configured to monitor an operation timing of the analog-to-digital converter circuit, and the digital BIST circuit generates at least one of a stable alarm signal and a conversion alarm signal using the counter, The stability alarm signal indicates whether a total scan time during which the plurality of scan voltages are output from the scan voltage generator circuit is shorter than a first reference time, and The conversion alarm signal indicates whether a conversion time for generating the second digital code by the converter circuit is shorter than a second reference time.

17. The temperature measurement circuit according to claim 7, further comprising: a main sensing unit disposed at a main position and configured to generate a main sensing voltage that varies according to a main operating temperature at the main position; as well as A plurality of local sensing units are arranged at a plurality of local positions and configured to generate a plurality of local sensing voltages varying according to local operating temperatures at the plurality of local positions.

18. The temperature measurement circuit according to claim 17, wherein: The digital BIST circuit receives a first measurement value of the second digital code corresponding to the main sensing voltage and a second measurement value of the second digital code corresponding to a local sensing voltage provided by a local sensing unit among the multiple local sensing units closest to the main sensing unit to generate a probe check alarm signal, which indicates whether a difference between the first measurement value and the second measurement value is less than a reference value.

19. A temperature measurement circuit, comprising: Temperature detection circuit, including: an analog circuit configured to generate a fixed measurement reference voltage independent of an operating temperature and a temperature-dependent voltage that varies according to the operating temperature; and an analog-to-digital converter circuit configured to generate a digital code indicative of the operating temperature based on the measurement reference voltage and the temperature-dependent voltage; and The analog built-in self-test (BIST) circuit is configured to generate a plurality of flag signals, wherein a corresponding flag signal of the plurality of flag signals indicates whether each of a plurality of voltages of the analog circuit is included in a corresponding predetermined range.

20. A built-in self-test (BIST) circuit configured to monitor a temperature detection circuit including an analog circuit and an analog-to-digital converter circuit, the BIST circuit comprising: an analog BIST circuit configured to generate a plurality of flag signals, a corresponding flag signal of the plurality of flag signals indicating whether each of a plurality of monitoring voltages of the analog circuit is within a corresponding predetermined range; as well as The digital BIST circuit is configured to apply a test signal to the analog-to-digital converter circuit in a test mode to generate a plurality of alarm signals indicating whether the analog-to-digital converter circuit operates normally.

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