Method for manufacturing semiconductor element

Abstract

A method for manufacturing a semiconductor device includes providing a first substrate and forming a resist layer on the first substrate. In some embodiments, the method further includes performing an exposure process on the resist layer. The exposure process includes exposing the resist layer to a radiation source through an intervening mask. In some instances, the intervening mask includes a second substrate, a multilayer structure formed on the second substrate, a cover layer formed on the multilayer structure, and an absorber layer disposed on the cover layer. In some embodiments, the absorber layer includes a first main pattern area and an opening area spaced a certain distance from the first main pattern area. In various instances, the method further includes developing the exposed resist layer to form a patterned resist layer after performing the exposure process.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. Background Art

[0002] The electronics industry continues to have a growing demand for smaller and faster electronic devices that are simultaneously capable of supporting an increasing number of increasingly complex and sophisticated functions. Thus, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking the size (e.g., minimum feature size) of semiconductor ICs and thereby increasing production efficiency and reducing associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] As just one example, a semiconductor photolithography process may use a photolithography template (e.g., a photomask or reticle) to optically transfer a pattern onto a substrate. This process may be accomplished, for example, by projecting a radiation source through an intervening photomask or reticle onto a substrate having a coating of a photosensitive material (e.g., a photoresist). The minimum feature size that can be patterned by such a photolithography process is limited by the wavelength of the projected radiation source. In view of this, extreme ultraviolet (EUV) radiation sources and photolithography processes including EUV photomasks ("masks") have been introduced. However, EUV masks may degrade with use, resulting in poor pattern transfer, which may cause device and / or circuit degradation or failure.

[0004] Therefore, the prior art has not proven to be completely satisfactory in all respects. Summary of the invention

[0005] A method for manufacturing a semiconductor device comprises: providing a first substrate; forming a resist layer on the first substrate; performing an exposure process on the resist layer, wherein the exposure process comprises exposing the resist layer to a radiation source through an intervening mask, and wherein the intervening mask comprises: a second substrate, a multilayer structure, a cover layer, and an absorber layer. The multilayer structure is formed on the second substrate, the cover layer is formed on the multilayer structure, and the absorber layer is disposed on the cover layer, wherein the absorber layer comprises a first main pattern area and an opening area spaced apart from the first main pattern area; and after performing the exposure process, developing the exposed resist layer to form a patterned resist layer.

[0006] A method for manufacturing a semiconductor element comprises: depositing a first material layer on a semiconductor substrate, wherein the first material layer comprises a hard mask; forming a second material layer on the first material layer, wherein the second material layer comprises a photoresist layer; and exposing the photoresist layer using an extreme ultraviolet (EUV) photolithography system comprising an EUV mask, wherein the EUV mask comprises a multi-layer structure, a covering layer formed on the multi-layer structure, and an absorber layer formed on the covering layer, and wherein the absorber layer comprises a main pattern area and an opening area separated from the main pattern area by a certain distance.

[0007] A method for manufacturing a semiconductor element comprises: manufacturing an extreme ultraviolet (EUV) mask, wherein manufacturing the EUV mask comprises forming a covering layer on a multilayer structure disposed on a substrate, forming an absorber layer on the covering layer, and patterning the absorber layer to form a main pattern area and an opening area separated from the main pattern area by a certain distance, wherein the main pattern area and the opening area are patterned simultaneously; and performing a photolithography process using the EUV mask, wherein the photolithography process transfers the pattern from the EUV mask to the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 The various aspects of the present disclosure can be best understood from the following detailed description when read together. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a schematic diagram of a photolithography system according to some embodiments;

[0010] Figure 2 is a cross section of an EUV mask according to some embodiments;

[0011] Figure 3A is a top view of a mask including unpatterned areas between main pattern areas, and Figure 3B is a cross-sectional view thereof;

[0012] Figure 4A is a top view of a mask including an open area between main pattern areas according to some embodiments, and Figure 4B is a cross-sectional view thereof;

[0013] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 providing a top view of a mask having various openings formed in an opening region according to some embodiments;

[0014] Fig.12 is a flow chart of a simplified method for making and using an EUV mask according to one or more aspects of the present disclosure;

[0015] Fig.13 is a flow chart of a method for manufacturing a semiconductor device according to one or more aspects of the present disclosure; and

[0016] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D and Fig.14E Provide the basis Fig.13 Some embodiments of the method of constructing a semiconductor component at various stages of manufacture.

[0017]

Explanation of symbols

[0018] 100: Photolithography system

[0019] 102: Radiation Source

[0020] 104:Illuminator

[0021] 106:Masking station

[0022] 108,302,402,502,602,702,802,902,1002,1102: Mask

[0023] 110: Projection optics

[0024] 112: Pupil Phase Modulator

[0025] 114: Projection pupil plane

[0026] 116:Semiconductor substrate

[0027] 118:Substrate table

[0028] 202,310,410:Substrate

[0029] 203: Back coating

[0030] 204,312,412:Multi-layer structure

[0031] 206,314,414: Covering layer

[0032] 208: Absorber

[0033] 210: Anti-reflective coating

[0034] 304: first main pattern area

[0035] 306: Second main pattern area

[0036] 308: Unpatterned area

[0037] 316,416: Absorber layer

[0038] 320,420: Hydrogen

[0039] 322,422:EUV light

[0040] 324,424: Hydrogen ions

[0041] 326,426: Interface

[0042] 328: Bubbles

[0043] 404: first main pattern area

[0044] 406: Second main pattern area

[0045] 408: Opening area

[0046] 411,604: Open

[0047] 504: Round opening

[0048] 704,804,1004: Rectangular opening

[0049] 904: first rectangular opening

[0050] 906: Second rectangular opening

[0051] 1104: First type of opening

[0052] 1106: Second type of opening

[0053] 1108: The third type of opening

[0054] 1200,1300:Method

[0055] 1202,1204,1302,1304,1306,1308,1310: Blocks

[0056] 1400: Device

[0057] 1402:Substrate

[0058] 1404: Bottom layer

[0059] 1404': Patterned hard mask layer

[0060] 1406: resist layer

[0061] 1406': Patterned resist layer

[0062] 1406a: Unexposed part

[0063] 1406b: Exposure part

[0064] D1,D2,D3: distance

[0065] L1, L2, L3, L4, L5, L6, Lx: Length

[0066] S,S1: interval

[0067] W: Width

[0068] X,Y: Direction DETAILED DESCRIPTION

[0069] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the description below, the formation of a first feature on or above a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0070] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "on," "upper," etc., may be used herein to facilitate describing the relationship of one element or feature to another element or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. Additionally, throughout this disclosure, the terms "mask," "photomask," and "reticle" may be used interchangeably to refer to a photolithography template, such as an EUV mask.

[0071] Figure 1 A schematic diagram illustrating a photolithography system 100 according to some embodiments. The photolithography system 100, which may also be generally referred to as a scanner, is operable to perform a photolithography process, including exposing with a particular exposure mode using a respective radiation source. In at least some of the disclosed embodiments, the photolithography system 100 comprises an extreme ultraviolet (EUV) photolithography system designed to expose a resist layer with EUV light. Thus, in various embodiments, the resist layer comprises a material that is sensitive to EUV light (e.g., an EUV resist). Figure 1The photolithography system 100 includes: a plurality of subsystems, such as a radiation source 102, an illuminator 104, a mask stage 106 for receiving a mask 108, a projection optic 110, and a substrate stage 118 for receiving a semiconductor substrate 116. A general description of the operation of the photolithography system 100 can be given as follows: EUV light from the radiation source 102 is directed toward the illuminator 104 (which includes a set of mirrors) and projected onto the reflective mask 108. The reflected mask image is directed toward the projection optic 110, which focuses the EUV light and projects the EUV light onto the semiconductor substrate 116 to expose the EUV resist layer deposited thereon. In addition, in various examples, each subsystem of the photolithography system 100 can be housed in a high vacuum environment and thus operate in a high vacuum environment, for example to reduce atmospheric absorption of the EUV light.

[0072] In the embodiments described herein, the radiation source 102 may be used to generate EUV light. In some embodiments, the radiation source 102 includes a plasma source, such as a discharge produced plasma (DPP) or a laser produced plasma (LPP). In some instances, the EUV light may include light having a wavelength ranging from about 1 nm to about 100 nm. In a particular instance, the radiation source 102 generates EUV light having a wavelength centered at about 13.5 nm. Therefore, the radiation source 102 may also be referred to as an EUV radiation source 102. In some embodiments, the radiation source 102 also includes a collector, which may be used to collect the EUV light generated from the plasma source and direct the EUV light toward imaging optics, such as an illuminator 104.

[0073] As described above, light from the radiation source 102 is directed toward the illuminator 104. In some embodiments, the illuminator 104 may include reflective optics (e.g., for EUV light lithography system 100), such as a single mirror or a mirror system having multiple mirrors, to direct light from the radiation source 102 onto the mask stage 106, and in particular onto the mask 108 secured to the mask stage 106. In some examples, the illuminator 104 may include a zone plate, for example, to improve the focusing of the EUV light. In some embodiments, the illuminator 104 may be used to shape the EUV light passing therethrough according to a particular pupil shape, and include, for example, a dipole shape, a quadrupole shape, a toroidal shape, a single beam shape, a multiple beam shape, and / or combinations thereof. In some embodiments, the illuminator 104 may be operable to configure the mirrors (i.e., of the illuminator 104) to provide desired illumination to the mask 108. In one example, the mirrors of the illuminator 104 may be used to reflect the EUV light to different illumination locations. In some embodiments, the stage prior to the illuminator 104 may additionally include other configurable mirrors that can be used to direct EUV light to different illumination positions within the mirror of the illuminator 104. In some embodiments, the illuminator 104 is used to provide on-axis illumination (ONI) to the mask 108. In some embodiments, the illuminator 104 is used to provide off-axis illumination (OAI) to the mask 108. It should be noted that the optics used in the EUV light lithography system 100, especially the optics for the illuminator 104 and the projection optics 110, may include mirrors with multi-layer thin film coatings, which are called Bragg reflectors. As an example, such multi-layer thin film coatings may include alternating layers of Mo and Si, which provide high reflectivity at EUV wavelengths (e.g., about 13 nm).

[0074] As discussed above, the photolithography system 100 also includes a mask stage 106 for holding a mask 108. Since the photolithography system 100 may be housed in and therefore operated in a high vacuum environment, the mask stage 106 may include an electrostatic chuck (e-chuck) to hold the mask 108. Like the optical components of the EUV photolithography system 100, the mask 108 is also reflective. Details of the mask 108 are described below. Figure 2 The examples are discussed in more detail. Figure 1As illustrated, light reflects from the mask 108 and is directed toward the projection optics 110, which collects the EUV light reflected from the mask 108. As an example, the EUV light (reflected from the mask 108) collected by the projection optics 110 carries an image of the pattern defined by the mask 108. In various embodiments, the projection optics 110 provide for imaging the pattern of the mask 108 onto these semiconductor substrates 116 fixed on the substrate stage 118 of the photolithography system 100. In detail, in various embodiments, the projection optics 110 focuses the collected EUV light and projects the EUV light onto the semiconductor substrate 116 to expose the EUV resist layer deposited on the semiconductor substrate 116. As described above, the projection optics 110 may include reflective optics, as used in an EUV photolithography system such as the photolithography system 100. In some embodiments, the illuminator 104 and the projection optics 110 are collectively referred to as an optical module of the photolithography system 100.

[0075] In some embodiments, the photolithography system 100 further includes a pupil phase modulator 112 to modulate the optical phase of the EUV light directed from the mask 108 so that the light has a phase distribution along a projection pupil plane 114. In some embodiments, the pupil phase modulator 112 includes a mechanism for tuning a mirror of the projection optics 110 to perform phase modulation. For example, in some embodiments, a mirror of the projection optics 110 can be used to reflect the EUV light passing through the pupil phase modulator 112, thereby modulating the phase of the light passing through the projection optics 110. In some embodiments, the pupil phase modulator 112 utilizes a pupil filter disposed on the projection pupil plane 114. As an example, a pupil filter can be used to filter out specific spatial frequency components of the EUV light reflected from the mask 108. In some embodiments, the pupil filter can be used as a phase pupil filter that modulates the phase distribution of the light directed through the projection optics 110.

[0076] As discussed above, the photolithography system 100 also includes a substrate stage 118 to hold a semiconductor substrate 116 to be patterned. In various embodiments, the semiconductor substrate 116 includes a semiconductor wafer, such as a silicon wafer, a germanium wafer, a silicon germanium wafer, a III-V wafer, or other types of wafers known in the art. The semiconductor substrate 116 may be coated with a resist layer that is sensitive to EUV light (e.g., an EUV resist layer). EUV resists may have strict performance standards. For illustrative purposes, the EUV resist may be designed to provide a resolution of at least about 22 nm, a line-width roughness (LWR) of at least about 2 nm, and have a resistance of at least about 15 mJ / cm 2In the embodiments described herein, various subsystems of the photolithography system 100 (including those described above) are integrated and operable to perform photolithography exposure processes including EUV photolithography processes. It is believed that the photolithography system 100 may further include other modules or subsystems that may be integrated with (or coupled to) one or more of the subsystems or components described herein.

[0077] Return to mask 108 and refer to Figure 2 An example of Figure 1 An example cross section of an EUV mask 108 is shown. Figure 2 As shown, the EUV mask 108 may include a substrate 202 having a backside coating 203, a multilayer structure 204, a capping layer 206, and one or more absorbers 208 having an anti-reflective coating (ARC) 210. In some embodiments, the substrate 202 includes a low thermal expansion material (LTEM) substrate (e.g., such as SiO2 doped with TiO2), and the backside coating 203 includes chromium nitride (Cr x N y ) layer. In some examples, the substrate 202 has a thickness of about 6.3 mm to 6.5 mm. In some examples, the backside coating 203 has a thickness of about 70 to 100 nm. As an example, the multilayer structure 204 may include a molybdenum-silicon (Mo-Si) multilayer deposited on top of the substrate 202, for example using an ion deposition technique. In some embodiments, the multilayer structure 204 has a thickness of about 250 to 350 nm, and in some examples, each Mo-Si layer pair has a thickness of about 3 nm (for the Mo layer) and about 4 nm (for the Si layer). In various embodiments, the capping layer 206 includes a ruthenium (Ru) capping layer, which in some examples may have a thickness of about 2.5 nm. In some embodiments, the capping layer 206 may include a Si capping layer having a thickness of about 4 nm. The capping layer 206 may help protect the multilayer structure 204 (e.g., during the manufacture of the mask 108), and may also serve as an etch stop layer for a subsequent absorber layer etch process. In some embodiments, the absorber 208 may include, for example, a TaBO layer, a TaBN layer, a TaBO / TaBN layer, a Ta x N y layer, Ta x B y O z N uThe absorber 208 may include a layer or a combination thereof, which may have a thickness of about 50 to 75 nm and is used to absorb EUV light (e.g., having a wavelength of about 13.5 nm). In some examples, the absorber 208 may use other materials such as Al, Cr, Ta, and W, etc. In some examples, the ARC layer 210 includes Ta. x B y O z N u Layer, Hf x O y Layer or Si x O y N z Although some examples of materials that can be used for each of substrate 202, backside coating 203, multilayer structure 204, capping layer 206, absorber 208, and ARC layer 210 have been given, it should be understood that other suitable materials known in the art may equally be used without departing from the scope of the present disclosure.

[0078] For purposes of illustration, an exemplary method of manufacturing the mask 108 is described herein. In some embodiments, the manufacturing process includes two processing stages: (1) a mask blank manufacturing process, and (2) a mask patterning process. During the mask blank manufacturing process, a mask blank is formed by depositing a suitable layer (e.g., a reflective multilayer, such as a Mo-Si multilayer) on a suitable substrate (e.g., an LTEM substrate having a flat, defect-free surface). In various embodiments, the surface roughness of the mask blank is less than about 50 nm. As an example, a capping layer (e.g., ruthenium) is formed on a multilayer-coated substrate, followed by deposition of an absorber layer. The mask blank can then be patterned (e.g., patterning the absorber layer) to form a desired pattern on the mask 108. In some embodiments, an ARC layer can be deposited on the absorber layer before patterning the mask blank. The patterned mask 108 can then be used to transfer circuit and / or device patterns onto a semiconductor wafer. In various embodiments, the pattern defined by mask 108 may be repeatedly transferred to multiple wafers through various photolithography processes. In addition, a set of masks (such as mask 108) may be used to construct a complete integrated circuit (IC) device and / or circuit.

[0079] In various embodiments, the mask 108 (described above) can be manufactured to include different structural types, such as a binary intensity mask (BIM) or a phase-shifting mask (PSM). An illustrative BIM includes an opaque absorption region and a reflective region, wherein the BIM includes a pattern to be transferred to the semiconductor substrate 116 (e.g., an IC pattern). The opaque absorption region includes an absorber, as described above, which is used to absorb incident light (e.g., incident EUV light). In the reflective region, the absorber has been removed (e.g., during the mask patterning process described above), and the incident light is reflected by the multiple layers. In addition, in some embodiments, the mask 108 may include a PSM, which utilizes interference generated by the phase difference of light passing therethrough. Examples of PSMs include alternating PSMs (AltPSMs), attenuated PSMs (AttPSMs), and chromeless PSMs (cPSMs). As an example, an AltPSM may include phase shifters (of opposite phase) disposed on either side of each patterned mask feature. In some examples, an AttPSM may include an absorber layer having a transmittance greater than zero (e.g., Mo-Si with an intensity transmittance of about 6%). In some cases, for example, since the cPSM does not contain phase shifter material or chrome on the mask, the cPSM may be described as a 100% transmittance AltPSM.

[0080] As described above, the mask 108 includes a patterned image that can be used to transfer circuit and / or device patterns onto a semiconductor wafer (e.g., semiconductor substrate 116) via the photolithography system 100. In order to achieve high fidelity pattern transfer from the patterned mask 108 to the semiconductor substrate 116, the photolithography process should be defect-free. In some cases, mask defects may appear in the form of particles that may be unintentionally deposited on the surface of the overlying layer and, if not removed, may cause degradation of the photolithographically transferred pattern. Particles may be introduced by any of a variety of methods, such as during a chemical mechanical polishing (CMP) process, a cleaning process, and / or during the handling of the EUV mask 108. At least some existing methods for avoiding and / or removing particle contamination from reflective EUV masks (e.g., mask 108) include wet chemical processes to clean the mask. Alternatively or in addition to the mask cleaning technique, a pellicle may be used on the EUV mask to act as a protective shield that protects the mask from damage and / or contaminating particles. As an example, the pellicle is suspended (e.g., by being attached to a frame of the EUV mask) a distance (e.g., a few millimeters) from the patterned surface of the mask while remaining within the optical path between the patterned surface and the wafer to be patterned, so that any particles that land on the pellicle (e.g., but not on the patterned surface of the mask) are away from the focal plane of the projection optics 110 and are therefore not imaged onto the target semiconductor wafer.

[0081] In other cases, mask defects may occur during the photolithography process. For example, in at least some EUV photolithography processes, surface blistering and layer splitting of the EUV mask caused by hydrogen ion and / or helium implantation may occur during the EUV exposure process. In various instances, the surface blistering causes film expansion of the EUV mask absorber layer and peeling of the absorber layer from the underlying cover layer, resulting in a defective EUV mask. The pattern transferred to the substrate using the defective EUV mask may have low fidelity compared to the target pattern, resulting in device and / or circuit degradation or failure. Therefore, such defective EUV masks may be scrapped instead. Therefore, the prior art has not proven to be completely satisfactory in all respects.

[0082] To further illustrate the process by which mask defects may be formed during EUV photolithography, refer to Figure 3A / Figure 3B , which illustrates an exemplary mask 302. In detail, Figure 3A A top view of the mask 302 is provided, and Figure 3B Provide a mask 302 along a direction substantially parallel to Figure 3A In some aspects, the mask 302 may be similar to the above reference Figure 2108 as described. For example, mask 302 can include substrate 310, multilayer structure 312, cover layer 314, and absorber layer 316, which can be substantially the same as substrate 202, multilayer structure 204, cover layer 206, and absorber 208, respectively, as described above. In some examples, mask 302 includes first main pattern area 304 and second main pattern area 306. As an example, first main pattern area 304, second main pattern area 306 include areas where absorber layer 316 has been patterned, for example, to define various features (e.g., as part of a semiconductor device and / or circuit) to be transferred to a semiconductor wafer using mask 302 as part of a photolithography process.

[0083] As shown, the mask 302 also includes an unpatterned area 308 between the first main pattern area 304 and the second main pattern area 306, where the absorber layer 316 has not yet been patterned. In at least some techniques, surface blistering and layer splitting of the mask may occur within these unpatterned areas 308 of the mask 302. For example and with reference to Figure 3B , EUV photolithography exposure can be performed in a vacuum environment including ambient hydrogen (H2) 320. In some cases, EUV light 322 from the exposure process can interact with hydrogen 320 to produce hydrogen ions 324 (e.g., H - or H + ). The generated hydrogen ions 324 may then penetrate into the absorber layer 316 and diffuse therethrough. When the diffused hydrogen ions 324 reach the interface 326 between the absorber layer 316 and the cover layer 314, the hydrogen ions 324 may react with a metal layer (e.g., such as Ru) within the cover layer 314 to form hydrogen (H2) 320. As a result, the hydrogen 320 formed at the interface 326 may accumulate between the cover layer 314 and the absorber layer 316 and cause the surface of the absorber layer 316 to protrude and form bubbles 328. The bubbles 328 may in turn cause the cover layer 314 and the absorber layer 316 to peel off from each other. As a result, the mask 302 may be scrapped.

[0084] Although the above examples have been described with reference to hydrogen (H2) 320 interacting with EUV light 322, such surface blistering and layer splitting may also occur due to helium ion implantation. For example, in some cases, helium ions introduced during a helium ion beam photolithography process may similarly penetrate into the absorber layer 316 and accumulate at the interface 326, thereby forming bubbles 328. Although Figure 3A / Figure 3BThe examples are shown and described as having surface blisters formed in the unpatterned area 308 between the first main pattern area 304 and the second main pattern area 306, but it should be understood that such examples are not intended to be limiting, and surface blisters may also occur in other unpatterned areas 308 on other sides of the first main pattern area 304 and the second main pattern area 306.

[0085] Embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all of which need be discussed herein, and all embodiments do not require a particular advantage. For example, embodiments of the present disclosure provide an EUV mask and related methods that are designed to address at least some of the shortcomings of the prior art as described above. For example, in various embodiments, the EUV mask includes one or more openings in the absorber layer, wherein the one or more openings are separated from the main pattern area. As an example, the openings may expose an underlying capping layer, and the openings may be disposed a sufficient distance from the main pattern area so that the main pattern area is not affected by the one or more openings. As described above, the main pattern area may include several areas where the absorber layer has been patterned to define various features (e.g., as part of a device and / or circuit) for transfer to a semiconductor wafer as part of a photolithography process. Thus, in some embodiments, one or more openings disclosed herein may be positioned a sufficient distance from a main pattern area so that features defined by the main pattern area can be transferred to a semiconductor wafer (e.g., by an EUV photolithography process) with high fidelity without being substantially affected by the one or more openings.

[0086] In various embodiments, adding one or more openings in the absorber layer and away from the main pattern area provides reduced thermal film expansion (e.g., which causes surface blistering and layer splitting). Therefore, the mask structure disclosed herein can reduce and / or eliminate the blistering and peeling problems faced in at least some processes. In some examples, the EUV mask includes a main pattern area and an opening area, wherein the opening area includes one or more openings. In various embodiments, the opening area includes at least one opening, and each opening in the opening area penetrates the EUV mask absorber layer and exposes the underlying capping layer, wherein the capping layer may include Ru. In some embodiments, the thermal expansion of the EUV mask can be further reduced by increasing the size and number of openings in the opening area. As an example, the openings in the opening area provide for the release of hydrogen to the atmosphere without the accumulation of hydrogen between the absorber layer and the capping layer. In addition, and in some embodiments, one or more openings in the opening area can be formed simultaneously with the features formed in the main pattern area. Those skilled in the art will recognize other benefits and advantages of the methods and structures as described herein, and the described embodiments are not intended to be limited beyond what is specifically recited in the appended claims.

[0087] Reference now Figure 4A / Figure 4B , which illustrates an exemplary mask 402 according to various embodiments, which includes one or more openings formed in an opening region. In particular, Figure 4A A top view of mask 402 is provided, and Figure 4B Provide a mask 402 along a direction substantially parallel to Figure 4A In some aspects, the mask 402 may be similar to the above reference Figure 2 The mask 108 and mask 402 described above can be used in a photolithography system, such as the one described above with reference to Figure 1 1. The photolithography system 100 discussed above. In some examples, the mask 402 can include a substrate 410, a multilayer structure 412, a capping layer 414, and an absorber layer 416, which can be substantially the same as the substrate 202, the multilayer structure 204, the capping layer 206, and the absorber 208, respectively, described above. In some embodiments, the mask 402 can also include a backside coating (e.g., such as the backside coating 203) and an ARC layer (e.g., such as the ARC layer 210). In some examples, the mask 402 includes a first main pattern area 404 and a second main pattern area 406, which can be similar to the main pattern areas 304, 306 discussed above. Thus, the main pattern areas 404, 406 can include areas where the absorber layer 416 has been patterned, for example, to define various features (e.g., as part of a device and / or circuit) to be transferred to a semiconductor wafer using the mask 402 as part of a photolithography process.

[0088] Compared to at least some masks that include unpatterned areas (e.g., such as unpatterned areas 308) between main pattern areas, and in some embodiments, mask 402 includes an opening area 408 between and away from first main pattern area 404, second main pattern area 406. Compared to first main pattern area 404, second main pattern area 406, and in some embodiments, opening area 408 may not necessarily define a feature that forms a portion of a semiconductor device and / or circuit. It will be understood that an opening area need not necessarily be disposed between two main pattern areas. For example, in some cases, an opening area may have a main pattern area disposed on one side of the opening area and not disposed on the other side of the opening area. In addition, in some examples, multiple opening areas (each having at least one opening) may be disposed in different portions of the mask, as long as each opening area is separated by a sufficient distance from an adjacent main pattern area, as further described herein. The open area 408 and any other open areas on the mask 402 include at least one opening in the absorber layer 416 of the mask 402 that exposes the underlying cover layer 414. As shown, and in some examples, the open area 408 is a distance D1 from the first main pattern area 404 and a distance D2 from the second main pattern area 406. In some embodiments, the distance D1 is the same as the distance D2. However, in some cases, the distance D1 may be different from the distance D2. In some examples, each of the distances D1 and D2 may be less than or equal to about 5 microns. By providing the distances D1 and D2 between the open area 408 and the respective first main pattern area 404 and second main pattern area 406, the first main pattern area 404 and the second main pattern area 406 will not be affected by the opening formed in the open area 408. In other words, the distances D1 and D2 between the opening area 408 and the respective first main pattern areas 404 and second main pattern areas 406 ensure that the features defined by the first main pattern areas 404 and second main pattern areas 406 can be transferred to the semiconductor wafer with high fidelity using the mask 402 (for example, through an EUV photolithography process) without being substantially affected by the openings formed in the opening area 408.

[0089] According to various embodiments, the openings formed within the opening region 408 provide for hydrogen release to the atmosphere without accumulation of hydrogen between the absorber layer and the cover layer. Thus, the openings formed provide for reduced thermal film expansion and reduce and / or eliminate surface blistering and layer splitting. For purposes of illustration, reference is made to Figure 4B, which shows an EUV photolithography exposure process using a mask 402 including an opening region 408 and having openings 411. It should be noted that the number of openings 411 and the shapes and sizes of openings 411 are merely exemplary, and the openings formed within the opening region 408 may include any number of openings in a plurality of openings having various shapes and sizes, as discussed in more detail below. In some embodiments, the EUV exposure process is performed in a vacuum environment including ambient hydrogen (H2) 420. In some cases, EUV light 422 from the exposure process may interact with hydrogen 420 to produce hydrogen ions 424 (e.g., H - or H + ). At least some of the generated hydrogen ions 424 may penetrate to the portion of the patterned absorber layer 416 within the opening region 408 and diffuse therein to reach the interface 426 between the absorber layer 416 and the capping layer 414. Alternatively, some of the generated hydrogen ions 424 may travel through the opening 411 to directly reach the exposed surface of the capping layer 414 without passing through the patterned absorber layer 416. Regardless of how the hydrogen ions 424 reach the capping layer 414 (e.g., by diffusing through the portion of the patterned absorber layer 416 or directly through the opening 411), the hydrogen ions 424 may react with the metal layer (e.g., Ru) within the capping layer 414 to form hydrogen gas (H2) 420. In some embodiments, the hydrogen gas 420 formed on the exposed surface of the capping layer 414 may be released directly into the atmosphere through the opening 411. In some cases, hydrogen 420 formed at interface 426 between absorber layer 416 and cover layer 414 may diffuse to adjacent openings 411 rather than accumulating at interface 426 and then being released into the atmosphere through adjacent openings 411. Thus, by using mask 402 including open regions 408 in which surface area coverage of absorber layer 416 has been reduced due to the formation of openings within open regions 408, accumulation of hydrogen (and / or helium) between the cover and absorber layers is reduced and / or eliminated, thereby reducing and / or eliminating surface blistering and layer splitting.

[0090] As described above, the EUV exposure process performed in the photolithography system 100 (within which the mask 402 is secured to the mask stage 106) is performed in a vacuum environment that includes ambient hydrogen 420. In various embodiments, the hydrogen 420 within the photolithography system 100 may be periodically, and in some cases continuously, purged or flushed from the photolithography system 100 to remove particles and maintain the purity of the system. Thus, in various embodiments, the hydrogen 420 (regardless of whether it is released directly into the atmosphere via the opening 411 or diffused into an adjacent opening 411 to be released into the atmosphere via the adjacent opening 411) may be flushed as part of a known photolithography system 100 purge or flush. However, the EUV exposure process may continue to be performed regardless of the presence or absence of the hydrogen 420 because the EUV exposure process is typically performed in such a hydrogen 420 environment. Most notably, and in accordance with embodiments of the present disclosure, the openings within the open region 408 will prevent or significantly reduce the accumulation of hydrogen gas 420 between the cover layer and the absorber layer, as discussed herein.

[0091] As described above, there may be any number of multiple openings within an opening region (e.g., such as opening region 408), wherein each opening has any of a plurality of various shapes and sizes. In some embodiments, the larger the area of ​​the opening, the better the hydrogen release (e.g., the release of hydrogen formed by the reaction of hydrogen ions with the capping metal). In addition, the geometric design and size of the openings are not limited to any particular geometric design and / or size, as long as the openings remain within the opening region, and as long as the main pattern area is not affected by the openings within the opening region. In some embodiments, from a top view (e.g., similar to Figure 4A The openings in the opening region may include any of a variety of shapes, such as circles, ellipses, rectangles, squares, triangles, quadrilaterals, parallelograms, rhombuses, trapezoids, pentagons, hexagons, or other desired shapes, from a perspective of the view shown in FIG. 1 . In some examples, the distance between the main pattern region and the opening region, or the distance between the main pattern region and the nearest opening in the opening region, may be less than or equal to about 5 microns. Moreover, in some embodiments, the width of individual openings in the opening region may be less than or equal to about 20 nm. Additional details and examples of openings that may be formed in the opening region are provided below with reference to FIG. Figures 5 to 11 Describe in more detail.

[0092] In detail, Figures 5 to 11Exemplary embodiments illustrating various shapes, mask layouts, and sizes of openings that may be formed within an opening area (e.g., such as opening area 408). It will be understood that the examples shown and discussed are merely illustrative and are not intended to be limiting, and that other shapes, layouts, and sizes of openings may equally be used without departing from the scope of the present disclosure. For example, in at least one example, the openings may be substantially equal to the size of opening area 408, such that the absorber layer may be removed from the entire opening area 408. The selection of the shape, layout, and size of the openings formed by opening area 408 may be determined based on the features defined within the adjacent first main pattern area 404. For example, more critical features formed by the first main pattern area 404 may benefit from or be better protected by a greater number and / or greater size of openings within opening area 408 (e.g., by correspondingly reducing / eliminating nearby surface blistering and layer splitting), while less critical features formed within the first main pattern area 404 may be adequately protected by a smaller number and / or smaller size of openings within opening area 408.

[0093] Reference now Figure 5 , which illustrates a top view of a mask 502 according to some embodiments. The mask 502 can be substantially similar to the mask 402, but the openings in the opening area 408 have a different layout design and a different spacing between the main pattern area 404 and the opening area 408. As described above, the opening area 408 is disposed between the first main pattern area 404 and the second main pattern area 406 and is spaced apart from the first main pattern area 404 and the second main pattern area 406. In this example, the mask 502 includes a single circular opening 504 disposed in the opening area 408. In some embodiments, the circular opening 504 can have a width W less than or equal to about 20 nm. The width W can be substantially equal to the diameter of the circular opening 504. Figure 5 Distances D1 and D2 are further shown, where each of distances D1 and D2 may be less than or equal to about 5 microns, as previously described, and distance D3 is less than both D1 and D2. In some cases, distance D3 may be equal to about 0 nm, meaning that the main pattern area 404 and the open area 408 are adjacent to each other. Figure 5 The example of shows that the distance D3 between the main pattern area 404 and the opening area 408 is, but the distance D1 between the main pattern area 404 and the nearest opening (eg, circular opening 504 in this example) within the opening area 408 is maintained less than or equal to about 5 microns.

[0094] refer to Figure 6, which illustrates a top view of a mask 602 according to some embodiments. Mask 602 may be similar to mask 402, wherein the openings in the opening area 408 have different layout designs. The opening area 408 is disposed between the first main pattern area 404 and the second main pattern area 406 and is spaced apart from the first main pattern area 404 and the second main pattern area 406 by distances D1 and D2, respectively, wherein each of the distances D1 and D2 may be less than or equal to about 5 microns. In this example, mask 602 includes a plurality of elliptical / circular openings 604 disposed in the opening area 408. In some embodiments, the plurality of elliptical / circular openings 604 may be configured in an array pattern. In some examples, each of the plurality of elliptical / circular openings 604 may have a width W less than or equal to about 20 nm, and the spacing S between adjacent openings may be less than or equal to about 1 micron. In some cases, if the plurality of elliptical / circular openings 604 are circular, the width W may be substantially equal to the diameter of the opening 604. In some embodiments, if the plurality of elliptical / circular openings 604 are elliptical, the width W may be substantially equal to the minor axis diameter of the openings 604. For purposes of discussion, the minor axis diameter is the shorter of the two perpendicular diameters (minor axis diameter and major axis diameter) defining the ellipse.

[0095] Figure 7 A top view of a mask 702 according to some embodiments is illustrated. The mask 702 may be similar to the mask 402, wherein the openings in the opening area 408 have different layout designs. The opening area 408 is disposed between the first main pattern area 404 and the second main pattern area 406, and is spaced apart from the first main pattern area 404 and the second main pattern area 406 by distances D1 and D2, respectively, wherein each of the distances D1 and D2 may be less than or equal to about 5 microns. In this example, the mask 702 includes a plurality of rectangular openings 704 disposed in the opening area 408. In some embodiments, each rectangular opening 704 may have a width W less than or equal to about 20 nm. In some cases, each rectangular opening 704 may also have a length L1 less than or equal to about 3 microns. In some embodiments, the spacing S between adjacent rectangular openings 704 may be less than or equal to about 1 micron. In some embodiments, the plurality of rectangular openings 704 may be configured in an array pattern and may be oriented in a direction Y, as shown.

[0096] Figure 8A top view of a mask 802 according to some embodiments is illustrated. The mask 802 may be similar to the mask 402, wherein the openings in the opening area 408 have different layout designs. The opening area 408 is disposed between the first main pattern area 404 and the second main pattern area 406, and is spaced apart from the first main pattern area 404 and the second main pattern area 406 by distances D1 and D2, respectively, wherein each of the distances D1 and D2 may be less than or equal to about 5 microns. In this example, the mask 802 includes a plurality of rectangular openings 804 disposed in the opening area 408. In some embodiments, each rectangular opening 804 may have a width W less than or equal to about 20 nm. In some cases, the rectangular openings 804 may have different lengths Lx. For example, the length Lx may be equal to about 100 nm, 150 nm, 160 nm, 1 micron, 3 microns, or other appropriate values. In some embodiments, the spacing S between adjacent rectangular openings 804 (in direction X) may be less than or equal to about 1 micron, and the spacing S1 between adjacent rectangular openings 804 (in direction Y) may be less than or equal to about 500 nm. In some cases, the spacing S1 may be referred to as an end-to-end spacing. As an example, the total number of rectangular openings 804 (e.g., in direction X or direction Y) may be calculated by design rules based on the total length of the opening area 408 (e.g., in direction X or direction Y), the size of the individual openings, and the spacing therebetween. As an example, consider that the length of the opening area 408 in direction Y is about 16 microns, where there are five rectangular openings spanning the direction Y of the opening area 408, where the length of four of these openings is equal to 3 microns, the length of one opening is equal to 2 microns, and the end-to-end spacing between adjacent openings is 500 nm. Therefore, the total length of the openings and the spacing therebetween are equal to the length of the opening area 408. In another example, consider that the length of the open area 408 in the direction Y is about 16 microns, where there are five rectangular openings spanning the direction Y of the open area 408, where the lengths of all five openings are equal to 2.8 microns, and the end-to-end spacing between adjacent openings is 500 nm. Therefore, the total length of the openings and the spacing therebetween are equal to the length of the open area 408. Many other examples of opening sizes and spacings may be equally used without departing from the scope of the present disclosure. In some examples, the plurality of rectangular openings 804 may be oriented in the direction Y, as shown.

[0097] Fig. 9A top view of a mask 902 according to some embodiments is illustrated. The mask 902 may be similar to the mask 402, wherein the openings in the opening region 408 have different layout designs. The opening region 408 is disposed between the first main pattern region 404 and the second main pattern region 406, and is spaced apart from the first main pattern region 404 and the second main pattern region 406 by distances D1 and D2, respectively, wherein each of the distances D1 and D2 may be less than or equal to about 5 microns. In the present example, the mask 902 includes a first rectangular opening 904 having a first length L2 disposed in the opening region 408 and a second rectangular opening 906 having a second length L3. In the illustrated embodiment, the second length L3 is greater than the first length L2. However, in some examples, the first length L2 may be greater than the second length L3. In various embodiments, the lengths L2 and L3 may have various lengths similar to the length Lx described above. In some embodiments, each rectangular opening 904, 906 may have a width W less than or equal to about 20 nm. In some examples, the interval S (in direction X) between adjacent first rectangular openings 904 and second rectangular openings 906 may be less than or equal to about 1 micron, and the interval S1 (in direction Y) between adjacent first rectangular openings 904 may be less than or equal to about 500 nm. In some embodiments, a plurality of first rectangular openings 904 and second rectangular openings 906 may be arranged in an array pattern and may be oriented in direction Y, as shown.

[0098] Fig.10 A top view of a mask 1002 according to some embodiments is illustrated. The mask 1002 may be similar to the mask 402, wherein the openings in the opening region 408 have different layout designs. The opening region 408 is disposed between the first main pattern region 404 and the second main pattern region 406, and is spaced apart from the first main pattern region 404 and the second main pattern region 406 by distances D1 and D2, respectively, wherein each of the distances D1 and D2 may be less than or equal to about 5 microns. In this example, the mask 1002 includes a plurality of rectangular openings 1004 disposed in the opening region 408. In some embodiments, each rectangular opening 1004 may have a width W less than or equal to about 20 nm. In some cases, each rectangular opening 1004 may also have a length L4 less than or equal to about 5 microns. In some examples, the spacing S between adjacent rectangular openings 1004 may be less than or equal to about 1 micron. In some embodiments, the plurality of rectangular openings 1004 may be configured in an array pattern and may be oriented in a direction X, as shown.

[0099] Fig.11A top view of a mask 1102 according to some embodiments is illustrated. The mask 1102 may be similar to the mask 402, wherein the openings within the opening region 408 have a different layout design. The opening region 408 is disposed between the first main pattern region 404 and the second main pattern region 406, and is spaced apart from the first main pattern region 404 and the second main pattern region 406 by distances D1 and D2, respectively, wherein each of the distances D1 and D2 may be less than or equal to about 5 microns. In the present example, the mask 1102 includes a plurality of first type openings 1104, a plurality of second type openings 1106, and a plurality of third type openings 1108 disposed within the opening region 408. Although three types of openings are illustrated, it will be understood that more or fewer types of openings may also be formed within the opening region 408 without departing from the scope of the present disclosure. In some examples, the first type of opening 1104 may be similar to the circular opening 504 or the plurality of elliptical / circular openings 604 discussed above, and thus the first type of opening 1104 may also have a width W (or diameter) less than or equal to about 20 nm. In some embodiments, each of the second type of opening 1106 and the third type of opening 1108 may have a width W less than or equal to about 20 nm. In some cases, the second type of opening 1106 may have a length L5, and the third type of opening 1108 may have a length L6. In various embodiments, the lengths L5 and L6 may have various lengths similar to the length Lx discussed above. In some embodiments, the second type of opening 1106 may be oriented in direction Y, and the third type of opening 1108 may be oriented in direction X, as shown.

[0100] Reference now Fig.12, which illustrates a flow chart of a simplified method 1200 for making and using an EUV mask according to one or more aspects of the present disclosure. The method 1200 begins at block 1202 where an EUV mask is made. In an embodiment of block 1202, the EUV mask made may include any of the masks 108, 402, 502, 602, 702, 802, 902, 1002, or 1102 discussed above. In addition, as previously described, the EUV mask manufacturing process may include two processing stages: (1) a mask blank manufacturing process, and (2) a mask patterning process. In some embodiments, the mask blank manufacturing process includes depositing a suitable layer (e.g., such as a multi-layer structure) on a substrate. As an example, a capping layer (e.g., ruthenium) is formed on a multi-layer coated substrate, followed by deposition of an absorber layer. The mask blank may then be patterned (e.g., patterning the absorber layer) to form a desired pattern on the EUV mask. In some embodiments, an ARC layer may be deposited on the absorber layer prior to patterning the mask blank. In various examples, as described above, the pattern formed in the absorber layer may include a main pattern region and an opening region spaced a distance from the main pattern region. In some embodiments, the main pattern region defines features corresponding to semiconductor elements or circuits, and the opening region includes at least one opening that exposes an underlying capping layer (e.g., a Ru layer). In at least some embodiments, and in the embodiments of block 1202, the main pattern region (including corresponding features defining at least a portion of a semiconductor element or circuit) and the opening region (including corresponding openings exposing the capping layer)) may be formed simultaneously. That is, in some examples, the absorber layer in each of the main pattern region and the opening region may be patterned simultaneously to provide a patterned EUV mask.

[0101] Next, method 1200 proceeds to block 1204, where a photolithography process is performed using the patterned EUV mask. For example, the patterned EUV mask can be used to transfer circuit and / or device patterns onto a semiconductor wafer using an EUV photolithography system (e.g., such as system 100). In some embodiments, the EUV mask is loaded / fixed onto a substrate stage of the EUV photolithography system. In operation, EUV light from a radiation source of the EUV photolithography system is directed toward an illuminator of the EUV photolithography system and projected onto the EUV mask including a main pattern area and an opening area. The reflected mask image is then directed toward the projection optics of the EUV photolithography system, which focuses the EUV light and projects the EUV light onto the semiconductor wafer loaded on the substrate stage to expose the EUV resist layer deposited thereon, thereby transferring the pattern from the EUV mask to the semiconductor wafer. In some embodiments, and during operation of the EUV photolithography system, hydrogen can be released from the EUV mask from at least one opening formed in the opening area, thereby reducing and / or eliminating blistering and delamination issues faced in at least some processes. In various embodiments, the pattern defined by the EUV mask can be repeatedly transferred to multiple wafers via various photolithography processes. In addition, a set of EUV masks can be used to construct a complete IC device and / or circuit, each EUV mask may include a main pattern area and an opening area spaced a certain distance from the main pattern area. According to various embodiments of method 1200, additional processing methods may be implemented before, during, and after method 1200, and some of the above-mentioned processing steps may be replaced or eliminated.

[0102] refer to Fig.13 , which illustrates a flow chart of a more detailed method 1300 for manufacturing semiconductor devices and / or ICs using an EUV mask as described above according to various embodiments. Method 1300 may be implemented in whole or in part by a photolithography system such as EUV system 100. However, in some embodiments, portions of method 1300 may be implemented by other types of photolithography systems such as a deep ultraviolet (DUV) photolithography system, an electron beam (e-beam) photolithography system, an X-ray photolithography system, and / or other photolithography systems. It will be understood that additional operations may be provided before, during, and after method 1300, and that some of the operations described may be replaced, eliminated, or moved for additional embodiments of the method. It should also be noted that method 1300 is illustrative and is not intended to limit the present disclosure to that expressly recited in the appended claims. The following description will be made in conjunction with Fig.14A , Fig. 14B , Fig. 14C , Fig.14D and Fig.14E The method 1300 is further described.

[0103] In detail, Fig.14A , Fig. 14B , Fig. 14C , Fig.14D and Fig.14E A cross-sectional view of a semiconductor device 1400 at various stages of fabrication is provided, constructed according to some embodiments of the method 1300. The semiconductor device 1400 may be an intermediate device or a portion thereof fabricated during processing of an IC, which may include logic circuits, memory structures, passive components (such as resistors, capacitors, and inductors), and active components such as diodes, field-effect transistors (FETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, fin-like FETs (FinFETs), other three-dimensional (3D) FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.

[0104] The method 1300 begins at block 1302 where a substrate is provided. Fig.14A 1402 , a cross-sectional view of a semiconductor device 1400 including a substrate 1402 is illustrated. In some embodiments, the substrate 1402 may include a semiconductor substrate such as silicon. However, in some embodiments, the substrate may alternatively or additionally include other materials such as germanium, silicon carbide (SiC), silicon germanium (SiGe), diamond, compound semiconductors, alloy semiconductors, and the substrate 1402 may optionally include one or more epitaxial layers (epi-layers), may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features. In some embodiments, the substrate 1402 may also include a conductive or insulating layer formed on the substrate 1402, and the substrate 1402 may include various doping configurations according to design requirements known in the art.

[0105] In some embodiments, substrate 1402 includes a bottom layer (or material layer) 1404 to be processed, such as patterned or implanted. For example, bottom layer 1404 may include a hard mask layer to be patterned. In some cases, bottom layer 1404 may include an epitaxial semiconductor layer to be ion implanted. However, in some embodiments, substrate 1402 may not include a bottom layer, but instead a bottom layer (e.g., 1404) is formed on substrate 1402 as appropriate. In one embodiment, bottom layer 1404 may include a hard mask layer including a material such as silicon oxide, silicon nitride (SiN), silicon oxynitride, titanium nitride, or other suitable material or combination. In some embodiments, bottom layer 1404 may include an anti-reflection coating (ARC), such as a nitrogen-free anti-reflection coating (NFARC), which includes silicon oxide, silicon carbide, or plasma enhanced chemical vapor deposited silicon oxide. In various embodiments, the bottom layer 1404 may include a high-k dielectric layer, a gate layer, a hard mask layer, an interface layer, a capping layer, a diffusion / barrier layer, a dielectric layer, a conductive layer, other suitable layers, and / or combinations thereof.

[0106] The method 1300 proceeds to block 1304 where a resist layer (in some examples, an EUV resist layer) 1406 is formed on the substrate 1402 or on the optional bottom layer 1404 ( Fig.14A ). In various examples, the resist layer 1406 is sensitive to radiation used in the photolithography exposure process and is resistant to the etching process (or ion implantation process). In some embodiments, the resist layer 1406 may be formed by a spin coating process. In some examples, an adhesion layer (such as a HMDS layer) is formed on the substrate 1402 or on the optional bottom layer 1404 before the resist layer 1406 is formed. In some embodiments, after the resist layer 1406 is formed and before the exposure process is performed, a pre-bake process may be performed, for example, to evaporate the solvent and densify the resist layer 1406. In various embodiments, the resist layer 1406 may be sensitive to various types of radiation, such as DUV radiation (e.g., 248 nm radiation from a KrF laser or 193 nm radiation from an ArF laser), EUV radiation (e.g., 13.5 nm radiation), an electron beam (e-beam), or an ion beam. In at least some examples, and according to various embodiments, the resist layer 1406 is sensitive to EUV radiation. In some examples, the resist layer 1406 is soluble in a positive developer or a negative developer after being exposed to EUV radiation.

[0107] The method 1300 proceeds to block 1306 where a pattern is exposed onto the resist coated substrate. Fig. 14B In an example of block 1306, a cross-sectional view of a device 1400 is illustrated, wherein a resist layer 1406 ( Fig.14A ) has been exposed (e.g., by a photolithography imaging system) by an intervening mask. In at least some embodiments, the resist layer 1406 is exposed by EUV radiation (e.g., 13.5 nm) using an EUV system (e.g., such as photolithography system 100) and an EUV mask (e.g., any of masks 108, 402, 502, 602, 702, 802, 902, 1002, or 1102 discussed above). Alternatively, in some embodiments, the resist layer 1406 may be exposed by DUV radiation (e.g., from a 248 nm KrF excimer laser or a 193 nm ArF excimer laser), X-ray radiation, electron beam, ion beam, and / or other suitable radiation sources. In some embodiments, and when an EUV system is used, the exposure of block 1306 may be performed in a vacuum and in a hydrogen environment, as described above. Furthermore, in various embodiments and during operation of the EUV photolithography system, hydrogen gas may be released from the EUV mask from one or more openings formed in the opening region of the EUV mask, rather than accumulating between the capping layer and the absorber layer of the EUV mask. As a result, and in accordance with various embodiments, blistering and / or peeling of the absorber layer of the EUV mask may be eliminated and / or significantly reduced. Furthermore, a pattern formed using an EUV mask having one or more openings may have high fidelity compared to a target pattern, thereby providing improved device and / or circuit performance.

[0108] In some embodiments, after the exposure of block 1306, a baking process may be performed. For example, in some embodiments, after the exposure of the resist layer 1406, and before performing a resist development process, a post-bake process may be performed to stabilize and harden the developed resist layer. In some examples, and as a result of the exposure process of block 1306, a latent pattern is formed in the resist layer 1406. As an example, the latent pattern refers to an exposed pattern on the resist layer 1406, which will subsequently become a physical resist pattern after the development process. In various embodiments, the latent pattern of the resist layer 1406 may include unexposed portions 1406a and exposed portions 1406b. In various embodiments, the exposed portions 1406b of the resist layer 1406 may be physically or chemically changed due to the exposure process of block 1306. In some embodiments, if a positive resist has been used, the exposed portions 1406b will be dissolved in a subsequent development process. In some cases, if a negative resist has been used, the exposed portions 1406b will become insoluble, and a subsequent development process may instead dissolve the unexposed portions 1406a.

[0109] The method 1300 proceeds to block 1308 where a development process is performed to form a patterned resist layer. Fig. 14B and Fig. 14C In an embodiment of block 1308, after forming a latent image including unexposed and exposed portions 1406a / 1406b, a resist development process is performed to form a patterned resist layer 1406'. In some embodiments, the resist development process includes a wet chemical development process known in the art. As described above, if a negative resist has been used, the exposed portion 1406b will become insoluble. Therefore, reference Fig. 14C , which shows the device 1400 after a development process, illustrating the use of a negative resist.

[0110] The method 1300 proceeds to block 1310 where a fabrication process is performed on the substrate through the openings of the patterned resist layer. For example, the fabrication process may be performed on the semiconductor device 1400 using the patterned resist layer 1406' as a mask so that the fabrication process is applied to portions of the semiconductor device 1400 within the openings of the patterned resist layer 1406' (e.g., exposed areas of the bottom layer 1404) while protecting other portions covered by the patterned resist layer 1406' from the fabrication process. In some embodiments, the fabrication process of block 1310 may include an etching process applied to the bottom layer 1404 using the patterned resist layer 1406' as an etching mask so that a pattern is transferred from the patterned resist layer 1406' to the bottom layer 1404. Alternatively, in some embodiments, the fabrication process of block 1310 may include an ion implantation process applied to the semiconductor device 1400 using the patterned resist layer 1406 ′ as an ion implantation mask to form various doped features in the semiconductor device 1400 (eg, within the bottom layer 1404 ).

[0111] As described above, and in this example, the bottom layer 1404 may include a hard mask layer. In a further implementation of this example, the pattern of the patterned resist layer 1406' may first be transferred to the bottom layer 1404 (e.g., the hard mask layer), thereby forming the patterned hard mask layer 1404' ( Fig.14D), and then transferred to other layers of the substrate 1402. For example, a dry (plasma) etching process, a wet etching process, a combination thereof, and / or other etching methods can be used to etch the bottom layer 1404 through the opening of the patterned resist layer 1406'. For example, the dry etching process may include an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, other suitable gases and / or plasma and / or a combination thereof. In some embodiments, the patterned resist layer 1406' may be partially or completely consumed during the etching of the bottom layer 1404 and the formation of the patterned hard mask layer 1404'. In one embodiment, any portion of the patterned resist layer 1406' remaining after the etching process may be stripped away, thereby leaving the patterned hard mask layer 1404' on the substrate 1402, such as Fig.14E shown.

[0112] Method 1300 may include other steps before, during, or after the above steps. In one embodiment, substrate 1402 is a semiconductor substrate, and method 1300 proceeds to form a fin field effect transistor (FinFET) device. In such an example, method 1300 may further include forming a plurality of active fins in semiconductor substrate 1402. In addition, and in a further implementation of this example, block 1310 may further include: etching substrate 1402 through openings of patterned hard mask 1404' to form trenches in substrate 1402; filling these trenches with dielectric material; performing a chemical mechanical polishing (CMP) process to form shallow trench isolation (STI) features; epitaxial growth and / or recessing of STI features to form fin-shaped active regions. In some embodiments, method 1300 includes other steps to form a plurality of gate electrodes, gate spacers, doped source / drain regions, contacts for gate / source / drain features, etc. In some embodiments, subsequent processing may form various contacts / vias / lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, which are used to connect the various features to form a functional circuit that may include one or more devices (e.g., one or more FinFET devices). In a further implementation of this example, the multi-layer interconnect may include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. The various interconnect features may use various conductive materials, including copper, tungsten and / or silicide. In one example, a metal damascene and / or dual metal damascene process is used to form a copper-related multi-layer interconnect structure. In addition, additional processing steps may be performed before, during, and after method 1300, and some of the processing steps described above may be replaced or eliminated according to various embodiments of method 1300.

[0113] With respect to the description provided herein, the present disclosure provides embodiments of EUV masks and related methods. In various embodiments, the EUV mask includes one or more openings (in an absorber layer) formed in an opening region of the EUV mask, wherein the opening region is spaced apart from a main pattern region. These openings may expose an underlying capping layer (e.g., such as a Ru capping layer), and these openings may be disposed a sufficient distance from the main pattern region such that the main pattern region is not affected by the one or more openings. In various embodiments, the addition of one or more openings in the absorber layer and away from the main pattern region provides reduced thermal film expansion (e.g., which results in surface blistering and layer splitting). Thus, the EUV mask structures disclosed herein are capable of reducing and / or eliminating blistering and delamination issues faced in at least some processes. In some embodiments, thermal expansion of the EUV mask may be further reduced by increasing the size and number of openings in the opening region. As an example, the openings in the opening region provide for the release of hydrogen to the atmosphere without accumulation of hydrogen between the absorber layer and the capping layer. Furthermore, and in some embodiments, the one or more openings in the opening region may be formed simultaneously with the features formed in the main pattern region. Those skilled in the art will readily appreciate that the methods and structures described herein may be applied to a variety of other mask and photolithography processes to advantageously achieve similar benefits from such other mask and photolithography processes without departing from the scope of the present disclosure.

[0114] Thus, some embodiments of the present disclosure describe a method of manufacturing a semiconductor device, the method comprising providing a first substrate and forming a resist layer on the first substrate. In some embodiments, the method further comprises performing an exposure process on the resist layer. The exposure process comprises exposing the resist layer to a radiation source through an intervening mask. In some instances, the intervening mask comprises a second substrate, a multilayer structure formed on the second substrate, a capping layer formed on the multilayer structure, and an absorber layer disposed on the capping layer. In some embodiments, the absorber layer comprises a first main pattern region and an opening region spaced a certain distance from the first main pattern region. In various instances, the method further comprises, after performing the exposure process, developing the exposed resist layer to form a patterned resist layer. In some embodiments, the intervening mask comprises an extreme ultraviolet (EUV) mask. In some embodiments, the capping layer comprises ruthenium (Ru). In some embodiments, the opening region comprises at least one opening exposing the capping layer. In some embodiments, during the exposure process, hydrogen is released from the at least one opening. In some embodiments, the distance between the first main pattern region and the opening region is less than or equal to about 5 microns. In some embodiments, the width of the at least one opening is less than or equal to about 20 nm. In some embodiments, the absorber layer includes a TaBO layer, a TaBN layer, a TaBO / TaBN layer, a Ta x N y Layer or Ta x By O z N u In some embodiments, the absorber layer includes a second main pattern area separated from the opening area by a distance, wherein the first main pattern area is disposed on a first side of the opening area, and wherein the second main pattern area is disposed on a second side of the main pattern area opposite the first side. In some embodiments, the first main pattern area defines a feature corresponding to a semiconductor element or circuit. In some embodiments, the absorber layer includes another opening area having at least one opening, and wherein the another opening area is separated from the first main pattern area by a distance.

[0115] In a further embodiment, a method is discussed, the method comprising depositing a first material layer on a semiconductor substrate, the first material layer comprising a hard mask. In some embodiments, the method further comprises forming a second material layer on the first material layer, the second material layer comprising a resist layer. In various examples, the method further comprises exposing a photoresist layer using an EUV photolithography system comprising an EUV mask. The EUV mask comprises a multilayer structure, a cover layer formed on the multilayer structure, and an absorber layer formed on the cover layer, and the absorber layer comprises a main pattern area and an opening area spaced a certain distance from the main pattern area. In some embodiments, the cover layer comprises ruthenium (Ru). In some embodiments, the opening area comprises at least one opening for exposing the cover layer. In some embodiments, during the exposure of the photoresist layer, hydrogen is released from at least one opening. In some embodiments, the method of manufacturing a semiconductor device further comprises: after exposing the photoresist layer, developing the exposed photoresist layer to transfer a pattern from the EUV mask to the photoresist layer, wherein the pattern comprises features corresponding to a semiconductor device or circuit defined by the main pattern area.

[0116] In addition, some embodiments discuss a method including manufacturing an EUV mask. The manufacturing of the EUV mask includes: forming a capping layer on a multilayer structure disposed on a substrate; forming an absorber layer on the capping layer; and patterning the absorber layer to form a main pattern area and an opening area spaced a certain distance from the main pattern area. In some embodiments, the main pattern area and the opening area are patterned simultaneously. In some instances, the method further includes performing a photolithography process using the EUV mask, wherein the photolithography process transfers the pattern from the EUV mask to the semiconductor substrate. In some embodiments, the method of manufacturing a semiconductor element further includes: while performing the photolithography process, releasing hydrogen from at least one opening formed in the opening area. In some embodiments, the method of manufacturing a semiconductor element further includes: performing multiple subsequent photolithography processes using the EUV mask without causing blistering of the absorber layer and without causing the capping layer and the absorber layer to peel off from each other. In some embodiments, the capping layer includes ruthenium (Ru).

[0117] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a first substrate; forming a resist layer on the first substrate; An exposure process is performed on the resist layer, wherein the exposure process includes exposing the resist layer to a radiation source through an intervening mask, and wherein the intervening mask includes: a second substrate; a multi-layer structure formed on the second substrate; a cover layer formed on the multi-layer structure; and an absorbent layer disposed on the cover layer; The absorber layer includes a first main pattern area and an opening area separated from the first main pattern area, the opening area includes at least one opening exposing the covering layer, wherein the first main pattern area is configured to define a feature corresponding to a semiconductor element or a circuit, and the opening area is configured to release hydrogen from the at least one opening during the exposure process; and after performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The intervening mask includes an extreme ultraviolet mask.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The capping layer includes ruthenium.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The at least one opening is oval or circular.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: A distance between the first main pattern region and the opening region enables the features defined by the first main pattern region to be transferred to the exposed resist layer without being affected by the at least one opening formed in the opening region.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The distance between the first main pattern area and the opening area is less than or equal to about 5 micrometers.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The at least one opening has a width less than or equal to approximately 20 nanometers.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The absorber layer includes a tantalum boron oxide layer, a tantalum boron nitride layer, a tantalum boron oxide / tantalum boron nitride layer, a tantalum nitride layer or a tantalum boron oxynitride layer.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The absorber layer includes a second main pattern area separated from the opening area by the distance, wherein the first main pattern area is disposed on a first side of the opening area, and wherein the second main pattern area is disposed on a second side of the main pattern area opposite to the first side.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that: The second main pattern region defines another feature corresponding to the semiconductor device or the circuit.

11. The method for manufacturing a semiconductor device according to claim 1, wherein: The absorber layer includes another opening region having at least one opening, and wherein the another opening region is spaced apart a distance from the first main pattern region.

12. A method for manufacturing a semiconductor element, characterized in that: Include: Depositing a first material layer on a semiconductor substrate, wherein the first material layer includes a hard mask; forming a second material layer on the first material layer, wherein the second material layer comprises a photoresist layer; and An exposure process is performed on the photoresist layer using an EUV lithography system including an EUV mask, wherein the EUV mask includes a multi-layer structure, a cover layer formed on the multi-layer structure, and an absorber layer formed on the cover layer, and wherein the absorber layer includes a main pattern area and an opening area separated from the main pattern area by a certain distance, the opening area includes at least one opening exposing the cover layer, wherein the main pattern area is configured to define a feature corresponding to a semiconductor device or a circuit, and the opening area is configured to release hydrogen from the at least one opening during the exposure process.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: The capping layer includes ruthenium.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The at least one opening is oval or circular.

15. The method for manufacturing a semiconductor device according to claim 12, wherein: The certain distance enables the feature defined by the main pattern area to be transferred to the photoresist layer without being affected by the at least one opening formed in the opening area.

16. The method for manufacturing a semiconductor device according to claim 12, wherein: The method further comprises: after exposing the photoresist layer, developing the exposed photoresist layer to transfer a pattern from the EUV mask to the photoresist layer, wherein the pattern includes the feature corresponding to the semiconductor device or the circuit defined by the main pattern area.

17. A method for manufacturing a semiconductor element, characterized in that: Include: Manufacturing an EUV mask, wherein the manufacturing of the EUV mask includes forming a capping layer on a multi-layer structure disposed on a substrate, forming an absorber layer on the capping layer, and patterning the absorber layer to form a main pattern region and an opening region spaced a certain distance from the main pattern region, wherein the main pattern region and the opening region are patterned simultaneously, the opening region includes at least one opening exposing the capping layer, wherein the main pattern region is configured to define a feature corresponding to a semiconductor device or a circuit; and A photolithography process is performed using the EUV mask, wherein the photolithography process transfers a pattern from the EUV mask to a semiconductor substrate, and the opening region is configured to release hydrogen from the at least one opening during the photolithography process.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that: Further including: The hydrogen gas is used to flush or purge a system including the EUV shield.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: Further including: A plurality of subsequent photolithography processes are performed using the EUV mask without causing blistering of the absorber layer and without causing the cap layer and the absorber layer to delaminate from each other.

20. The method for manufacturing a semiconductor device according to claim 17, wherein: The capping layer includes ruthenium.

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