Wind power converter digitized temperature and humidity detection control system

Abstract

The present application relates to wind power converter digitized temperature and humidity detection control system, including analog acquisition device, signal control board and converter controller connected in turn, analog acquisition device is connected with wind power converter, is used for collecting wind power converter's temperature and humidity data;Signal control board is used for signal expansion, it is provided with FPGA chip and DSP chip that are mutually signal connected on it, FPGA chip obtains temperature and humidity data on analog acquisition device and writes in internal register, and the temperature and humidity data in internal register are periodically read by DSP chip, and the converter controller is started or stops heating, dehumidification operation.The present application can effectively reduce the device cost of converter, and reduce the unreliable problem of cable connection between devices.Full digital sampling can also improve the temperature and humidity detection accuracy, make the temperature and humidity control in converter cabinet more accurate, improve the heating efficiency of converter and the utilization rate of whole machine.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital control of wind power converters, and particularly relates to a digital temperature and humidity detection control system for a wind power converter. BACKGROUND

[0002] With the vigorous development of clean energy such as wind energy, the installed capacity of wind power generation in China has been increasing, and the influence on the operation of the power grid cannot be ignored. As the core equipment in a wind turbine generator set, the wind power converter is responsible for the conversion of mechanical energy to electrical energy of the wind turbine generator set, and its reliability directly affects the utilization rate of the whole machine, and even threatens the safe and stable operation of the power grid. Due to the complex and changeable application environment of the wind power converter, including severe cold, humidity and other harsh environments, the converter needs to be heated, dehumidified and other necessary preparations before starting, which on the one hand solves the problem that the device cannot work reliably due to too low ambient temperature, and on the other hand avoids too high humidity to reduce the insulation of the system and cause electrical short circuit fault. By increasing the temperature and humidity detection device, the heating and dehumidification of the wind power converter are controlled, so as to ensure the safe operation of the wind power converter equipment.

[0003] The commonly used temperature and humidity detection method in the wind power converter is to use a mechanical temperature controller and a humidity controller (as shown in Figure 1 When the set temperature value or humidity value is reached, a dry contact point signal is given, and the main controller controls the heating and dehumidification of the system by judging the state of the dry contact point. The main disadvantage of this method is that the specific values of the temperature and humidity in the cabinet cannot be obtained in real time, and the sampling deviation is large, and the control precision is not high. SUMMARY

[0004] In order to solve the problems existing in the prior art, the present application provides a digital temperature and humidity detection control system for a wind power converter, which comprises an analog acquisition device, a signal control board and a converter controller connected in sequence, wherein,

[0005] The analog acquisition device is connected with the wind power converter and is used for acquiring temperature and humidity data of the wind power converter;

[0006] The signal control board is connected with the analog acquisition device through a 50-pin flat cable and is used for signal expansion, and an FPGA chip and a DSP chip connected with each other in signal are arranged on the signal control board, the FPGA chip acquires the temperature and humidity data on the analog acquisition device through an IIC single data bus and writes the data into an internal register, and the DSP chip is used for periodically reading the temperature and humidity data in the internal register, so as to start or stop the heating and dehumidification operation of the converter controller.

[0007] The analog acquisition device comprises an analog acquisition board and a temperature and humidity sensing chip, the temperature and humidity sensing chip is welded on the analog acquisition board, the temperature and humidity sensing chip is selected from an AM2302 temperature and humidity sensing chip, and the DSP chip and the FPGA chip communicate through a 16-bit data bus.

[0008] The register in the FPGA chip comprises a resource allocator and a plurality of memory units, the resource allocator is connected with a data transition interface module in the FPGA chip through a read operation interface and a write operation interface, and is used for realizing resource scheduling of the plurality of memory units according to the data type of reading and writing, wherein each memory unit further comprises a plurality of sub-memory units, and when data is written into the corresponding memory unit, only a plurality of sub-memory units of a corresponding size are enabled according to the size of the written data.

[0009] The memory unit comprises an enable timing judgment module, and the enable timing judgment module judges the sub-memory unit in the memory unit to be enabled currently according to the address position of the written data.

[0010] The FPGA chip comprises a preprocessing module, the preprocessing module is used for converting serial sampling data into low-frequency digital-analog sampling data, the preprocessing module comprises a shunt module, a digital oscillation circuit, a plurality of mixing circuit modules and a filter circuit, the plurality of mixing circuit modules are connected with the shunt module, the digital oscillation circuit and the filter circuit, the shunt module is used for converting the serial sampling data into a plurality of parallel data, the digital oscillation circuit is used for generating a local oscillator signal of the plurality of parallel data, each mixing circuit module mixes the data of each parallel circuit and the local oscillator signal, respectively, the filter circuit is used for filtering the mixed data of the mixing circuit module, and finally, the low-frequency digital-analog sampling data is output.

[0011] The wind power converter digital temperature and humidity detection control system provided by the application can effectively reduce the device cost of the converter, and reduce the problem of unreliable cable connection between devices. The fully digital sampling can also improve the temperature and humidity detection accuracy, make the temperature and humidity control in the converter cabinet more accurate, and improve the heating efficiency and overall utilization rate of the converter. The accurate temperature and humidity detection control method ensures the long-time safe and stable operation of the converter in a harsh environment. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A schematic diagram of a mechanical temperature and humidity detection and heating control method of the prior art.

[0013] Figure 2 A whole logic architecture diagram of the wind power converter digital temperature and humidity detection control system of the application.

[0014] Figure 3 An IIC single-bus communication protocol adopted by the application.

[0015] Figure 4 The DSP chip of the present application accesses the memory interface of the FPGA chip.

[0016] Figure 5 The logic working framework diagram of the FPGA chip used in the first embodiment of the present application.

[0017] Figure 6 The logic working framework diagram of the FPGA chip used in the second embodiment of the present application.

[0018] Figure 7 The logic working framework diagram of the FPGA chip used in the third embodiment of the present application.

[0019] Figure 8 The logic working framework diagram of the pre-processing module used in the third embodiment of the present application.

[0020] Figure 9 The single bus communication timing diagram of the IIC of the present application.

[0021] Figure 10 The start signal diagram of the single bus communication of the IIC of the present application.

[0022] Figure 11 The data bit timing diagram of the single bus communication of the IIC of the present application.

[0023] Figure 12 The single bus communication flow chart of the FPGA of the present application. DETAILED DESCRIPTION

[0024] In order to have a further understanding of the technical solutions and beneficial effects of the present application, the technical solutions of the present application and the beneficial effects generated thereby will be described in detail below with reference to the accompanying drawings.

[0025] In order to realize the detection and control of the temperature and humidity in the converter cabinet and solve the problems that the traditional mechanical temperature and humidity controller cannot accurately obtain the temperature and humidity values, the control precision is poor, and the control effect is not ideal, the present application provides a wind power converter digital temperature and humidity detection and control system. Through the overall architecture design, the logic function module design of the chip, and the working timing design, accurate temperature and humidity detection and control are realized, and the long-time safe and stable operation of the converter in a harsh environment is ensured.

[0026] Figure 2 The overall logic architecture diagram of the wind power converter digital temperature and humidity detection and control system of the present application is shown in FIG. 1. Figure 2As shown, the wind power converter digitized temperature and humidity detection control system of the present application, the complete hardware circuit board includes analog acquisition device, signal control board and converter controller connected in turn, the analog acquisition device is the analog acquisition board welded with AM2302 temperature and humidity sensing chip, which is used for responsible for front-end analog data acquisition, the signal control board is connected with the analog acquisition board, which is used for responsible for IO signal expansion, the control core board of the signal control board is welded with FPGA chip and DSP chip connected with each other, which is used for responsible for centralized control of the system, the control core board can be buckled on the signal control board through the plug-in; 50-pin flat cable is used to connect the analog acquisition board and the signal control board. When working specifically: the AM2302 temperature and humidity sensor starts to sample the temperature and humidity analog data of the wind power converter in real time, then the measured temperature and humidity data are sent to the FPGA chip through IIC bus communication, the FPGA chip analyzes the received data and stores them in the internal register through IIC single data bus; finally, the DSP chip reads the values in the FPGA internal register periodically through the EMIF bus communication mode, preferably through 16-bit data bus communication, so as to obtain the real-time temperature and humidity in the cabinet, and further judge whether the entire converter system needs to perform heating and dehumidifying operation. Figure 3 and Figure 4 IIC single bus communication protocol and the memory interface diagram of the DSP chip accessing the FPGA chip used in the present application.

[0027] In the present application, the power supply unit (not shown in the figure) outputs stable DC voltage (15VDC and 24VDC each one way) to the entire hardware circuit board for power supply; for example, one way of 24VDC power supply is connected to the signal control board X1 terminal, and one way of 15VDC power supply is connected to the signal control board X4 terminal.

[0028] Figure 5 The logic working framework diagram of the FPGA chip used in the first embodiment of the present application, in order to ensure the precise synchronism and real-time performance of wind power data in the reading and writing process, the present application designs the circuit working principle of the FPGA chip, which can ensure high-precision synchronous reading and writing operation.

[0029] As shown in Figure 5 The FPGA chip designed in the first embodiment of the present application includes a central control coordination module, a timing synchronization module, a data transition interface module and a register, the central control coordination module is connected with the analog acquisition device and the DSP chip, and is connected with the register information through the timing synchronization module and the data transition interface module, so as to realize data writing and reading.

[0030] It should be noted that the data transition interface module and the timing synchronization module in the application can be set to two or more, but the number of data transition interface modules and timing synchronization modules is the same, that is, each timing synchronization module corresponds to control a data transition interface module, through the setting of multiple groups of data transition interface modules and timing synchronization modules, multiple read-write operation channels are formed, during operation, one channel can perform write data operation, another channel can perform read data operation, or one channel can perform the previous cycle write data (or read data) operation, and another channel can perform the next cycle write data (or read data) operation, so as to ensure that the read and write are performed without interval, and the wind power converter temperature and humidity data are synchronized to be acquired and analyzed, so that the wind power converter is ensured to be in the best working state as soon as possible, and the fault of the wind power converter is found in time.

[0031] Correspondingly, the register includes a resource allocator and a plurality of memory units, the plurality of memory units correspond to different operation periods or different data types in the same operation period, and the resource allocator is used for writing the data in different operation periods and the data of different types in the same operation period into different memory units. Moreover, each memory unit of the application includes a plurality of sub-memory units, the granularity of each memory unit is increased through the setting of the plurality of sub-memory units, and the power consumption of the register is optimized. Specifically, the memory unit is provided with an enable timing judgment module connected with the sub-memory units and the resource allocator, the enable timing judgment module enables the corresponding sub-memory unit according to the position of the written data, so as to further ensure that the write data operation is smoothly performed with the minimum memory power consumption in the corresponding operation period; for example, when the data size that can be stored in each sub-memory unit is 1kb, the first sub-memory unit is enabled by the enable timing judgment module when the first kb of data is written, and the first sub-memory unit is reset after writing; the second sub-memory unit is enabled by the enable timing judgment module when the second kb of data is written, and the second sub-memory unit is reset after writing, and the like, until all the data to be written in the current operation period are written into the corresponding sub-memory unit. Correspondingly, in the operation period of reading data, the enable timing judgment module also reads the effective data in the sub-memory unit by the corresponding method. Thus, through the setting of the register and the plurality of memory units, the FPGA chip can store the data in different operation periods and different types of data; through the setting of the plurality of sub-memory units, the minimum power consumption of the register in the data writing stage is ensured, the loss of the FPGA chip is reduced, and the service life of the equipment is prolonged; at the same time, through the setting of the enable timing judgment module, on the one hand, the read-write data operation is smoothly performed, and the failure rate of the read-write operation is reduced, and on the other hand, the working power consumption of the register is further reduced.

[0032] Figure 6The logic working framework of the FPGA chip used in the second embodiment of the application shows a set of data transition interface modules and timing synchronization modules. In the second embodiment, the working logic of the central control coordination module, the data transition interface module and the timing synchronization module is expanded in detail to ensure the precise synchronization and real-time performance of the wind power data in the reading and writing process.

[0033] As shown in Figure 6 The central control coordination module is a terminal working module connected with the analog acquisition device and the DSP chip, used to receive corresponding read and write commands and command address information, and to sort, split and recombine the read and write commands and command address information according to the protocol with the memory to obtain command data matching the format of the internal memory. Meanwhile, the central control coordination module is connected with the register information through the timing synchronization module and the data transition interface module, serving as the terminal for sending and receiving read and write data to realize the writing and reading of data. Specifically, the central control coordination module includes a connection interface, a command feedback module, a read operation module and a write operation module. The connection interface is directly connected with the analog acquisition device and the DSP chip. In the writing operation cycle, the connection interface obtains the original data information to be written from the analog acquisition device, including the write command, the write command address information, the write data information and the write enable information. The connection interface sends the above information to the command feedback module and the write operation module. In the reading operation cycle, the connection interface sends the read data command and the read command address information obtained from the DSP chip to the command feedback module, and simultaneously transmits the valid data obtained from the read operation module to the DSP chip. The command feedback module sorts, splits and recombines the read and write commands and the command address information according to the protocol with the memory to obtain command data matching the format of the register, and transmits the command data to the data transition interface module. Meanwhile, the command feedback module recombines and buffers the read command and the read command address information, or the write command, the write command address information, the write data information and the write enable information to obtain the original timing signal for subsequent synchronization work. The write operation module and the read operation module are connected with the connection interface. The write operation module is used to obtain the write enable information and the write data information from the written data when there is data writing in the analog acquisition device, and transmits the write enable information and the write data information to the data transition interface module. The read operation module is used to receive the valid data feedback by the data transition interface when outputting the read data to the DSP chip, and outputs the valid data to the DSP chip through the connection interface.

[0034] The data transition interface module is connected with the timing synchronization module, and is used for completing the transition of read and write data between the central control coordination module and the register under the action of the timing synchronization module, so as to provide data meeting the timing and sequence requirements to the register or the DSP chip. The data transition interface module comprises a first information path, a second information path and an information transmission path. The first information path is connected with the read operation module, the write operation module and the information transmission path. In the write operation cycle, the first information path obtains the write enable information and the write data information from the write operation module, and transmits the information to the register through the information transmission path. In the read operation cycle, the first information path obtains the valid data in the register from the information transmission path, and transmits the data to the read operation module. The second information path is connected with the command feedback module and the information transmission path. The second information path obtains the read and write commands and the command address information from the command feedback module, and transmits the information to the information transmission path. The information transmission path is connected with the register. In the write operation cycle, the information transmission path transmits the write command, the write command address information, the write enable information and the write data information to the register. In the read operation cycle, the information transmission path transmits the read command and the read command address information to the register, and then receives the valid data feedback from the register and transmits the data to the read operation module.

[0035] The timing synchronization module is used for providing the synchronized timing to each logical working module in the data transition interface module, and ensuring the normal transmission of information and data. The timing synchronization module comprises a phase-locked loop, a frequency division circuit, a timing switch logic module and a timing synchronization module connected in sequence. The phase-locked loop is connected with the command feedback module in the central control coordination module. In one read and write operation cycle, the phase-locked loop obtains the original timing signal of the command feedback module, and generates a first command timing signal according to the original timing signal. The frequency division circuit generates a second command timing signal according to the first command timing signal. The timing switch logic module generates a timing control signal for controlling the output time of the second command timing signal. The timing synchronization module simultaneously obtains the second command timing signal and the timing control signal from the timing switch logic module, and simultaneously transmits the signals to the first information path, the second information path and the information transmission path in the data transition interface module, so as to ensure the synchronous work of each module in the data transition interface. In the present application, the first command timing signal is a high-speed timing signal, and the second command timing signal is a low-speed timing signal.

[0036] In the second embodiment of the present application, one complete write data operation cycle is as follows:

[0037] (1) The connection interface obtains the write command, the write command address information, the write data information and the write enable information from the analog acquisition device, and transmits the information to the command feedback module and the write operation module.

[0038] (2) The command feedback module sorts, splits and recombines the write command and the write command address information according to the protocol with the memory, obtains the command data matched with the register format, and transmits the command data to the second information channel; meanwhile, the command feedback module recombines and caches the write command, the write command address information, the write data information and the write enable information, obtains the original timing signal for the subsequent synchronous work, and transmits the original timing signal to the phase-locked loop;

[0039] (3) The phase-locked loop generates the first command timing signal according to the original timing signal, the frequency division circuit generates the second command timing signal according to the first command timing signal, the timing switch logic module generates the timing control signal for controlling the output time of the second command timing signal, and the timing synchronization module simultaneously obtains the second command timing signal and the timing control signal from the timing switch logic module, and simultaneously transmits the second command timing signal and the timing control signal to the first information channel, the second information channel and the information transmission channel in the data transition interface module, so as to ensure the synchronous work of the modules in the data transition interface module;

[0040] (4) The write operation module transmits the write data information and the write enable information to the first information channel; the first information channel transmits the write data information and the write enable information to the information transmission channel; and the second information channel transmits the write command and the write command address information to the information transmission channel.

[0041] (5) The information transmission channel writes the write command, the write command address information, the write data information and the write enable information into the register.

[0042] In the second embodiment of the application, a complete read data operation cycle is as follows:

[0043] (1) The connection interface obtains the read data command and the read command address information from the DSP chip;

[0044] (2) The command feedback module sorts, splits and recombines the read command and the read command address information according to the protocol with the memory, obtains the command data matched with the register format, and transmits the command data to the second information channel; meanwhile, the command feedback module recombines and caches the read command and the read command address information, obtains the original timing signal for the subsequent synchronous work, and transmits the original timing signal to the phase-locked loop;

[0045] (3) The phase-locked loop generates the first command timing signal according to the original timing signal, the frequency division circuit generates the second command timing signal according to the first command timing signal, the timing switch logic module generates the timing control signal for controlling the output time of the second command timing signal, and the timing synchronization module simultaneously obtains the second command timing signal and the timing control signal from the timing switch logic module, and simultaneously transmits the second command timing signal and the timing control signal to the first information channel, the second information channel and the information transmission channel in the data transition interface module, so as to ensure the synchronous work of the modules in the data transition interface module;

[0046] (4) the second information channel transmits the read command and the read command address information to the information transmission channel; the information transmission channel acquires the valid data in the register and transmits the valid data to the first information channel; the first information channel transmits the valid data to the read operation module, which transmits the valid data to the DSP chip through the connection interface.

[0047] In the second embodiment of the application, the working logic of the read-write data operation cycle alternately performed is as follows:

[0048] (1) the connection interface acquires the write command, the write command address information, the write data information and the write enable information from the analog acquisition device and transmits the information to the command feedback module and the write operation module;

[0049] (2) the command feedback module sorts, splits and recombines the write command and the write command address information according to the protocol with the memory, obtains the command data matched with the register format, and transmits the command data to the second information channel; at the same time, the command feedback module recombines and buffers the write command, the write command address information, the write data information and the write enable information, obtains the original timing signal for the subsequent synchronous work, and transmits the original timing signal to the phase-locked loop of one of the timing synchronization modules (hereinafter referred to as the first timing synchronization module, and the corresponding is the first data transition interface module);

[0050] (3) the connection interface acquires the read data command and the read command address information from the DSP chip;

[0051] (4) the command feedback module sorts, splits and recombines the read command and the read command address information according to the protocol with the memory, obtains the command data matched with the register format, and transmits the command data to the second information channel of the other second data transition interface module (hereinafter referred to as the second data transition interface module, and the corresponding is the second timing synchronization module); at the same time, the command feedback module recombines and buffers the read command and the read command address information, obtains the original timing signal for the subsequent synchronous work, and transmits the original timing signal to the phase-locked loop of the second timing synchronization module;

[0052] (5) the first timing synchronization module and the first data transition interface module perform steps (3) to (5) of the above-mentioned write data operation cycle to complete the writing of data.

[0053] (6) the second timing synchronization module and the second data transition interface module perform steps (3) to (4) of the above-mentioned read data operation cycle to complete the reading of data.

[0054] Therefore, in the process of alternately performing the read and write operations, the FPGA chip of the application only needs to wait for the connection interface and the command feedback module in the previous operation period to complete the corresponding work, and then immediately performs the operation in the next period, without waiting for the entire central control coordination module, the data transition interface module and the timing synchronization module to complete the corresponding work, thereby greatly improving the efficiency of data reading and writing, reducing the interval time of the data reading and writing period, and ensuring the real-time performance of the wind power converter parameter acquisition and control.

[0055] Figure 7 The logic working framework diagram of the FPGA chip used in the third embodiment of the application is similar to the logic structure of the second embodiment, and the difference lies in that the central control coordination module of the third embodiment further comprises a preprocessing module, please refer to the logic working framework diagram of the preprocessing module of the application shown in Figure 8 The preprocessing module is connected with the connection interface and the write operation module, and is used for converting the serial sampling data into low-frequency digital-analog sampling data; the preprocessing module comprises a shunt module, a digital oscillation circuit, a plurality of mixing circuit modules and a filter circuit, wherein each mixing circuit module is connected with the shunt module, the digital oscillation circuit and the filter circuit, the shunt module is used for converting the serial sampling data into a plurality of parallel data, the digital oscillation circuit is used for generating the local oscillator signal of the plurality of parallel data, each mixing circuit module respectively mixes the data of each parallel circuit and the local oscillator signal, and the filter circuit is used for filtering the mixed data of the mixing circuit module, and finally outputs the low-frequency digital-analog sampling data to the write operation module through the integration output interface. The preprocessing module is set to decompose one-way data into parallel multi-way data, thereby reducing the sampling clock size of the FPGA chip under the condition of the same data amount, increasing the data processing bandwidth of the FPGA, increasing the data acquisition rate of the FPGA chip, and minimizing the gap between the read and write operations, and further ensuring the synchronization and real-time performance of the data.

[0056] Figures 9-11 respectively are the IIC single bus communication timing diagram, the start signal diagram and the data bit timing diagram of the application, Figure 12 is the single bus communication flowchart of the FPGA of the application, please refer to Figure 2As shown, after the switch power supply is powered on, the hardware circuit board supplies power normally, the AM2302 temperature and humidity sensor starts to work, and the temperature and humidity values in the cabinet are periodically collected. After waiting for 2s, the FPGA pulls down the IIC data communication bus SDA for at least 1ms, then pulls up the bus, waits for the temperature and humidity sensor to pull down the data bus SDA for 80us and then pull up the data bus SDA for 80us, and then the temperature and humidity sensor serially outputs 40bit of data and check information from the data bus according to the communication protocol and timing once, and the FPGA receives all 40bit of data first, and then verifies, discards the data packet if the verification fails, and waits for the next communication period, and stores the temperature value in the address 0x4105 in the register and the humidity value in the address 0x4104 in the register if the verification is passed, and sets the data ready signal in the control word, and the register address is 0x4103 bit 2. The DSP periodically reads the content of the FPGA control word address through the EMIF bus, detects the temperature and humidity data ready signal, reads the temperature and humidity register address value, and the FPGA end automatically resets the control word. After the DSP obtains the temperature and humidity value, it is first judged whether the temperature is less than 0 DEG C and whether the humidity is greater than 85%, and if any condition is met, the heating control relay 2k283.1 is closed, and the heater in the cabinet is controlled to heat and dehumidify. Then the inverter controller always judges whether the temperature is greater than 5 DEG C and the humidity is less than 80%, at which time the controller exits the heating process, closes the heater, enters the standby process, and notifies the fan main control inverter that it is ready to run.

[0057] The method provided by the application can effectively reduce the device cost of the inverter and reduce the problem of unreliable cable connection between devices. The fully digital sampling can also improve the temperature and humidity detection accuracy, make the temperature and humidity control in the inverter cabinet more accurate, solve the problems of the traditional mechanical temperature and humidity controller, such as unable to accurately obtain temperature and humidity values, poor control accuracy and unsatisfactory control effect, and improve the heating efficiency and overall utilization rate of the inverter. The accurate temperature and humidity detection control method ensures the long-term safe and stable operation of the inverter in harsh environments, and can effectively reduce the device cost and save installation space.

[0058] Although the application has been described by the above preferred embodiments, it is not intended to limit the protection scope of the application, and any person skilled in the art can make various changes and modifications to the above embodiments without departing from the spirit and scope of the application, which are still within the protection scope of the application, therefore, the protection scope of the application is defined by the claims.

Claims

1. A wind power converter digitized temperature and humidity detection control system, characterized in that, The wind power converter comprises an analog acquisition device, a signal control board and a converter controller connected in sequence. The analog acquisition device is connected with the wind power converter and is used for acquiring temperature and humidity data of the wind power converter. The signal control board is connected with the analog acquisition device through a 50-pin flat cable and is used for signal expansion. The FPGA chip obtains the temperature and humidity data on the analog acquisition device through an IIC single data bus and writes the data into an internal register. The DSP chip is used for periodically reading the temperature and humidity data in the internal register to start or stop heating and dehumidifying operations of the converter controller.

2. The wind power converter digitized temperature and humidity detection control system of claim 1, wherein, The FPGA chip comprises a central control coordination module, a timing synchronization module, a data transition interface module and a register. The central control coordination module is connected with the analog acquisition device and the DSP chip and is connected with the register information through the timing synchronization module and the data transition interface module to realize data writing and reading. The central control coordination module comprises a connection interface, a command feedback module, a read operation module and a write operation module. The data transition interface module comprises a first information path, a second information path and an information transmission path. The first information path is connected with the read operation module, the write operation module and the information transmission path. The second information path is connected with the command feedback module and the information transmission path. The information transmission path is connected with the register. The data transition interface module and the timing synchronization module are provided as two or more than two. Each timing synchronization module controls one data transition interface module. Through the setting of multiple data transition interface modules and timing synchronization modules, multiple read-write operation channels are formed. The timing synchronization module comprises a phase-locked loop, a frequency divider circuit, a timing switch logic module and a timing synchronization module connected in sequence. The phase-locked loop is connected with the command feedback module in the central control coordination module. In one read-write operation cycle, the phase-locked loop obtains an original timing signal of the command feedback module and generates a first command timing signal according to the original timing signal. The frequency divider circuit generates a second command timing signal according to the first command timing signal. The timing switch logic module generates a timing control signal for controlling the output time of the second command timing signal. The timing synchronization module obtains the second command timing signal and the timing control signal from the timing switch logic module and simultaneously transmits them to the first information path, the second information path and the information transmission path in the data transition interface module to ensure the synchronous work of the modules in the data transition interface. The analog acquisition device comprises an analog acquisition board and a temperature and humidity sensor chip. The temperature and humidity sensor chip is selected from an AM2302 temperature and humidity sensor chip. The DSP chip and the FPGA chip communicate through a 16-bit data bus.

3. The wind power converter digitized temperature and humidity detection control system of claim 1, wherein, The register in the FPGA chip includes a resource allocator and a plurality of memory units, the resource allocator is connected with a data transition interface module in the FPGA chip through a read operation interface and a write operation interface, and is used for realizing resource scheduling of the plurality of memory units according to a read-write data type, wherein each memory unit further includes a plurality of sub-memory units, and when data is written into a corresponding memory unit, only a plurality of sub-memory units corresponding to a size of the written data are enabled according to the size of the written data.

4. The wind power converter digitized temperature and humidity detection control system of claim 3, wherein, Each memory unit includes an enable timing judgment module, and the enable timing judgment module judges a sub-memory unit in a memory unit that needs to be enabled currently according to an address position of the written data.

5. The wind power converter digitized temperature and humidity detection control system of claim 1, wherein, The FPGA chip includes a preprocessing module, and the preprocessing module is used for converting serial sampling data into low-frequency digital-analog sampling data. The preprocessing module includes a shunt module, a digital oscillation circuit, a plurality of mixing circuit modules and a filter circuit, wherein each mixing circuit module is connected with the shunt module, the digital oscillation circuit and the filter circuit, the shunt module is used for converting the serial sampling data into a plurality of parallel data, the digital oscillation circuit is used for generating a local oscillator signal of the plurality of parallel data, each mixing circuit module respectively mixes data of each parallel circuit and the local oscillator signal, the filter circuit is used for filtering mixed data of the mixing circuit module, and finally low-frequency digital-analog sampling data is output.

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