Method of using machine learning to control operation of a non-volatile memory device and storage system

Abstract

According to a method of controlling operation of a non-volatile memory device using machine learning, an operation condition of the non-volatile memory device is determined by performing an inference operation using a machine learning model. Training data generated based on feature information and error information indicating a result of error correction code (ECC) decoding of the non-volatile memory device is collected. The machine learning model is updated by performing a learning operation based on the training data. Optimal operation conditions for respective user environments are provided by collecting the training data in a storage system and performing the learning operation and the inference operation based on the training data.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0175273, filed on December 26, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to methods for using machine learning to control the operation of non-volatile memory devices and memory systems including non-volatile memory devices. Background Technology

[0004] Non-volatile memory devices, such as flash memory and resistive memory devices, can store data associated with multiple threshold voltage distributions, multiple resistance distributions, etc. Each corresponding "distribution" represents the logical state corresponding to the stored data. Once written to (or programmed) into a non-volatile memory cell, the stored data can be read by applying a predetermined read voltage. During or after programming a memory cell, its expected distribution may change or become distorted due to many events or conditions, including, for example, charge leakage, programming interference, read interference, word line and / or bit line connections, temperature variations, voltage variations, memory cell degradation, etc. In extreme cases, the expected distribution may become so offset and / or widened that a "read failure" occurs.

[0005] When a read failure occurs, some non-volatile memory devices can perform a read operation of a different type than the one that caused the failure (i.e., a read operation with a different read sequence). However, setting up a read sequence that correctly interprets the many events and conditions that may alter the distribution being read is not straightforward. Therefore, "read latency" (i.e., the time period required to read the stored data) can increase as changes in current operating conditions are assessed or identified according to an acceptable read sequence, and the performance of a non-volatile memory device can degrade with its increased read latency. Summary of the Invention

[0006] Some example embodiments may provide a method for controlling the operation of a non-volatile memory device and a storage system for performing the method, which can efficiently control the operating conditions of the non-volatile memory device.

[0007] According to an example embodiment, a method of controlling an operation of a non-volatile memory device using machine learning includes determining an operation condition of the non-volatile memory device by performing an inference operation using a machine learning model, collecting training data generated based on feature information and error information indicating a result of error correction code (ECC) decoding of the non-volatile memory device, and updating the machine learning model by performing a learning operation based on the training data.

[0008] According to an example embodiment, a method of controlling an operation of a non-volatile memory device using machine learning includes providing a plurality of read level sets each corresponding to a combination of levels of a read voltage for a read operation of the non-volatile memory device, determining an optimal read level set corresponding to current feature information among the plurality of read level sets by performing an inference operation based on the current feature information as an input of a machine learning model, collecting training data generated based on feature information and error information, the feature information including a physical address of the non-volatile memory device and cell count data indicating a threshold voltage distribution of a memory cell corresponding to the physical address, the error information indicating a result of error correction code (ECC) decoding of the non-volatile memory device, updating the machine learning model by performing a learning operation based on the training data, and determining a timing of performing the learning operation based on a probability of failure of the inference operation and a probability of failure of the ECC decoding.

[0009] According to an example embodiment, a storage system includes a non-volatile memory device and a storage controller configured to control the non-volatile memory device. The storage controller includes a data collector configured to collect training data generated based on feature information and error information indicating a result of error correction code (ECC) decoding of the non-volatile memory device, a buffer memory configured to store the training data, and a machine learning engine configured to determine an operation condition of the non-volatile memory device by performing an inference operation using a machine learning model, and to update the machine learning model by performing a learning operation based on the training data.

[0010] The method and the storage system of controlling an operation of a non-volatile memory device according to an example embodiment can provide optimized or improved operation conditions for various user environments by collecting training data in the storage system and performing a learning operation and an inference operation based on the training data. BRIEF DESCRIPTION OF DRAWINGS

[0011] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and

[0012] Figure 1 is a block diagram illustrating a machine learning device included in a non-volatile memory device according to an example embodiment.

[0013] Figure 2 is a flowchart showing a method of controlling operation of a non-volatile memory device according to an example embodiment.

[0014] Figure 3 is a block diagram showing a storage system according to an example embodiment.

[0015] Figure 4 is a block diagram showing a non-volatile memory device according to an example embodiment.

[0016] Figure 5 is a block diagram showing a memory cell array included in a non-volatile memory device according to an example embodiment. Figure 4

[0017] Figure 6 is a circuit diagram showing an equivalent circuit of a memory block described with reference to Figure 5

[0018] Figure 7 is a graph showing states of a multi-layer cell included in a non-volatile memory device according to an example embodiment.

[0019] Figure 8 is a graph showing an example read sequence according to an example embodiment.

[0020] Figure 9 is a flowchart showing a method of reading data according to a read sequence according to an example embodiment. Figure 8

[0021] Figure 10 is a flowchart showing an example embodiment of determining an operation condition in a method of controlling operation of a non-volatile memory device according to an example embodiment.

[0022] Figure 11 is a graph showing an example read sequence set for determining an operation condition according to an example embodiment. Figure 10

[0023] Figure 12 is a flowchart showing an example embodiment of determining an operation condition in a method of controlling operation of a non-volatile memory device according to an example embodiment.

[0024] Figure 13 is a graph showing a reliability level for determining an operation condition according to an example embodiment. Figure 12

[0025] Figure 14 is a flowchart showing an example embodiment of determining an operation condition in a method of controlling operation of a non-volatile memory device according to an example embodiment.

[0026] Figure 15 is a graph for describing a predetermined read voltage and an optimal read voltage.​​​​​

[0027] Figure 16 、 Figure 17 and Figure 18 is a diagram illustrating a read sequence according to an example embodiment.

[0028] Figure 19 is a diagram illustrating an example of a 2-bit soft decision read operation, Figure 20 is a diagram illustrating an example of a 3-bit soft decision read operation.

[0029] Figure 21 is a flowchart of a method of controlling an operation of a non-volatile memory device according to an example embodiment.

[0030] Figure 22 is a machine learning engine according to an example embodiment.

[0031] Figure 23 and Figure 24 are block diagrams illustrating a machine learning device included in a storage system according to an example embodiment.

[0032] Figure 25 and Figure 26 are diagrams for describing an example of a deep learning neural network structure driven by a machine learning device according to an example embodiment.

[0033] Figure 27 is a diagram illustrating an example of a node included in a neural network.

[0034] Figure 28 is a diagram illustrating a storage system according to an example embodiment. DETAILED DESCRIPTION

[0035] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. Like reference numerals can refer to like elements throughout. Repeated description can be omitted.

[0036] Figure 1 is a block diagram illustrating a machine learning device included in a non-volatile memory device according to an example embodiment, Figure 2 is a flowchart of a method of controlling an operation of a non-volatile memory device according to an example embodiment.

[0037] Referring to Figure 1 , the machine learning device 10 can include a machine learning engine 20, a data collector DCLL 30, and a buffer memory BUFF 40.

[0038] The machine learning engine 20 can include a controller CTRL and a machine learning module MLMDL. The controller CTRL can drive the machine learning module MLMDL to update the plurality of machine learning models MD1~MD3.

[0039] In some example embodiments, updating the machine learning model can include updating a weight value corresponding to the machine learning model. The weight value will be described below with reference to Figures 25 to 27

[0040] As will be described below, each of the plurality of machine learning models MD1~MD3 can correspond to one of operation conditions such as a read level set, a reliability level, a read sequence, and the like.

[0041] The buffer memory 40 can store data and / or information such as the training data TRD, the setting table STTBL, and the like.

[0042] For the sake of illustration, Figure 1 Three machine learning models MD1~MD3 are shown, but example embodiments are not limited thereto. The number of machine learning models can be variously implemented.

[0043] With reference to Figure 1 and Figure 2 , the machine learning engine 20 can determine an operation condition of the non-volatile memory device by performing an inference operation using the machine learning model MDi (i = 1, 2, 3) (S100). The machine learning engine 20 can perform the inference operation based on current feature information FTRINF_C as an input of the machine learning engine 20.

[0044] The data collector 30 can collect training data TRD generated based on the feature information FTRINF and error information ERRINF indicating a result of error correction code (ECC) decoding of the non-volatile memory device (S200). The machine learning engine 20 can update the machine learning model MDi by performing a learning operation based on the training data TRD (S300).

[0045] The feature information FTRINF can include a physical address of the non-volatile memory device and cell count data indicating a threshold voltage distribution of a memory cell corresponding to the physical address. The error information ERRINF can include at least one of a probability of ECC decoding failure and a number of errors determined by the ECC decoding.

[0046] The training data TRD can include the feature information FTRINF and a result of the inference operation successfully completed. In addition, the training data TRD can include an operation temperature, an operation voltage, a program and erase (P / E) cycle, a number of read operations, a delay of read, write (i.e., program), and erase operations, and the like.​

[0047] The controller CTRL can extract data corresponding to the machine learning model MDi from the feature information FTRINF and provide the extracted data as an input of a neural network implemented by the machine learning module MLMDL. In addition, the controller CTRL can optimize a weight value of the neural network corresponding to the machine learning model MDi. The neural network and the weight value will be described with reference to Figures 25 to 27 .

[0048] In a storage system including a non-volatile memory device such as a flash memory device, performance and reliability of the non-volatile memory device can be improved through a prediction algorithm for determining various operating conditions, but the prediction algorithm can not reflect various user environments and changes in characteristics of the non-volatile memory device. According to an example embodiment, machine learning can be used to prevent a decrease in accuracy of the prediction algorithm due to changes in user environments and workloads of the non-volatile memory device.

[0049] As such, the method of controlling operations of a non-volatile memory device and the storage system according to an example embodiment can provide optimized operating conditions for various user environments by collecting training data in the storage system and performing a learning operation and an inference operation based on the training data.

[0050] Figure 3 is a block diagram illustrating a storage system according to an example embodiment.

[0051] Referring to Figure 3 , the storage system 1000 includes a plurality of non-volatile memory devices 1100 and a storage controller 1200. The storage system 1000 can be a memory card, a solid state drive (SSD), a universal flash storage (UFS), etc.

[0052] The non-volatile memory device 1100 includes a memory cell array including a plurality of memory cells storing data. The non-volatile memory device 1100 can be optionally configured to receive a high voltage VPP. An example of the non-volatile memory device 1100 will be described with some additional details with reference to Figures 4 to 6 .

[0053] The storage controller 1200 can control overall operations of the non-volatile memory device 1100. The storage controller 1200 can control data transfer between an external host and the non-volatile memory device 1100. The storage controller 1200 can include a processor 1210 such as a central processing unit (CPU), a buffer memory 1220, a host interface 1250, a memory (e.g., NVM) interface 1260, an ECC block 1230, a machine learning engine MLD 20, and a data collector DCLL 30. The processor 1210 can perform operations for data transfer.

[0054] In some example embodiments, the buffer memory 1220 can be implemented by a static random access memory (SRAM). In other example embodiments, the buffer memory 1220 can be implemented by a dynamic random access memory (DRAM), a phase random access memory (PRAM), a ferroelectric random access memory (FRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), or the like. According to an example embodiment, the buffer memory 1220 can be located inside or outside of the storage controller 1200.

[0055] The host interface 1250 can be coupled to a host, and the memory interface 1260 can be coupled to the non-volatile memory device 1100 through a plurality of channels CH1, CH2, CH3, …, CHi. The processor 1210 can communicate with the host via the host interface 1250. For example, the host interface 1250 can be configured to communicate with the host using at least one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-E), a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), an enhanced small disk interface (ESDI), an electronic integrated drive (IDE), or the like. Also, the processor 1210 can communicate with the non-volatile memory device 1100 via the memory interface 1260.

[0056] In some example embodiments, the ECC block 1230 can perform ECC encoding and ECC decoding by using a Bose-Chaudhuri-Hocquenghem (BCH) code. In other example embodiments, the ECC block 1015 can perform ECC encoding and ECC decoding by using a low-density parity-check (LDPC) code. In yet other example embodiments, the ECC block 1230 can perform ECC encoding and ECC decoding by using a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a coded modulation such as a trellis coded modulation (TCM), a block coded modulation (BCM), or the like, or other error correction codes.

[0057] According to an example embodiment, the memory controller 1200 may be housed within the non-volatile memory device 1100, or the memory controller 1200 and the non-volatile memory device 1100 may be implemented as separate chips. According to an example embodiment, the ECC block 1230 may be included within the non-volatile memory device 1100 to reduce the amount of data transfer between the memory controller 1200 and the non-volatile memory device 1100. In this case, the non-volatile memory device 1100 may only transmit information about the read failure and error bits to the memory controller 1200 in the event of a read failure. The non-volatile memory device 1100 may provide valid read data, obtainable through ECC decoding, to the memory controller 1200 in the event of a successful read.

[0058] The machine learning engine 20 and data collector 30 can be implemented to perform as referenced. Figure 1 and Figure 2 The method for controlling the operation of a non-volatile memory device. Figure 1 The buffer memory 40 in the middle can correspond to Figure 3 The buffer memory 1220 is used in the machine learning engine 20. At least a portion of the machine learning engine 20 can be implemented as program code executed by the processor 1210.

[0059] Figure 4 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0060] Reference Figure 4 The non-volatile memory device (NVM) includes a memory cell array 100, a page buffer circuit 410, a data input / output circuit 420, an address decoder 430, a control circuit 450, and a voltage generator 460.

[0061] The memory cell array 100 can be connected to the address decoder 430 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). Furthermore, the memory cell array 100 can be connected to the page buffer circuit 410 via multiple bit lines (BL).

[0062] The memory cell array 100 may include multiple memory cells connected to multiple word lines (WL) and multiple bit lines (BL). In some example embodiments, the memory cell array 100 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional (or vertical) structure. In this case, the memory cell array 100 may include multiple NAND strings vertically oriented such that at least one memory cell is located above another memory cell.

[0063] The control circuit 450 can receive a command (signal) CMD and an address (signal) ADDR from the memory controller 20, and control erase, program, and read operations of the non-volatile memory device NVM based on the command signal CMD and the address signal ADDR. The erase operation can include performing a series of erase cycles, and the program operation can include performing a series of program cycles. Each program cycle can include a program period and a program verify period. Each erase cycle can include an erase period and an erase verify period. The read operation can include a normal read operation and a data recovery read operation.

[0064] For example, the control circuit 450 can generate a control signal CTL for controlling the voltage generator 460, and can generate a page buffer control signal PBC for controlling the page buffer circuit 410 based on the command signal CMD, and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 can provide the row address R_ADDR to the address decoder 430, and provide the column address C_ADDR to the data input / output circuit 420.

[0065] The address decoder 430 can be coupled to the memory cell array 100 through a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. During a program operation or a read operation, the address decoder 430 can determine one of the plurality of word lines WL as a selected word line and the remaining word lines of the plurality of word lines WL other than the selected word line as unselected word lines based on the row address R_ADDR.

[0066] Further, during the program operation or the read operation, the address decoder 430 can determine one of the plurality of string select lines SSL as a selected string select line and the remaining string select lines of the plurality of string select lines SSL other than the selected string select line as unselected string select lines based on the row address R_ADDR.

[0067] The voltage generator 460 can generate a word line voltage VWL required for an operation of the memory cell array 100 of the non-volatile memory device NVM based on the control signal CTL. The voltage generator 460 can receive power PWR from the memory controller 20. The word line voltage VWL can be applied to the plurality of word lines WL through the address decoder 430.

[0068] For example, during a program operation, the voltage generator 460 can apply a program voltage to the selected word line, and can apply a program pass voltage to the unselected word line. Further, during a program verify operation, the voltage generator 460 can apply a program verify voltage to the selected word line, and can apply a verify pass voltage to the unselected word line.

[0069] Further, during a normal read operation, the voltage generator 460 can apply a read voltage to a selected word line, and can apply a pass voltage to unselected word lines. During a data recovery read operation, the voltage generator 460 can apply a read voltage to a word line adjacent to a selected word line, and can apply a recovery read voltage to the selected word line.

[0070] The page buffer circuit 410 can be coupled to the memory cell array 100 by a plurality of bit lines BL. The page buffer circuit 410 can include a plurality of buffers. In some example embodiments, each buffer can be connected to only one bit line. In other example embodiments, each buffer can be connected to two or more bit lines.

[0071] The page buffer circuit 410 can temporarily store data to be programmed in a selected page of the memory cell array 100 or data read out from the selected page of the memory cell array 100.

[0072] The data input / output circuit 420 can be coupled to the page buffer circuit 410 by a data line DL. During a program operation, the data input / output circuit 410 can receive program data DATA received from the memory controller 20, and provide the program data DATA to the page buffer circuit 410 based on a column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 can provide read data DATA that has been read from the memory cell array 100 and stored in the page buffer circuit 410 to the memory controller 20 based on a column address C_ADDR received from the control circuit 450.

[0073] Further, the page buffer circuit 410 and the data input / output circuit 420 can read data from a first region of the memory cell array 100, and write the read data to a second region of the memory cell array 100 (e.g., without sending the data to a source external to the non-volatile memory device NVM, such as to the memory controller 20). That is, the page buffer circuit 410 and the data input / output circuit 420 can perform a copyback operation.

[0074] Hereinafter, a first direction D1 indicates a direction perpendicular to an upper surface of the semiconductor substrate, and second and third directions D2 and D3 indicate two directions parallel to the upper surface of the semiconductor substrate. For example, the second and third directions D2 and D3 can be perpendicular to each other. The first direction D1 can be referred to as a vertical direction, the second direction D2 can be referred to as a row direction, and the third direction D3 can be referred to as a column direction. Directions indicated by arrows and opposite directions in the drawings can be considered as the same direction.

[0075] Figure 5is a block diagram illustrating a memory cell array included in a non-volatile memory device of Figure 4 Figure 6 is a circuit diagram illustrating an equivalent circuit of a memory block described with reference to Figure 5

[0076] Referring to Figure 5 , the memory cell array 100 can include a plurality of memory blocks BLK1 to BLKz. In an example embodiment, the memory blocks BLK1 to BLKz are selected by an address decoder 430 in Figure 4 For example, the address decoder 430 can select a particular memory block BLK corresponding to a block address among the memory blocks BLK1 to BLKz.

[0077] Figure 6 The memory block BLKi included in the non-volatile memory device of

[0078] Referring to Figure 6 , the memory block BLKi can include NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 can include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. In Figure 6 , each of the NAND strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, example embodiments are not limited thereto. In some example embodiments, each of the NAND strings NS11 to NS33 can include any number of memory cells.

[0079] Each string selection transistor SST can be connected to a corresponding string selection line (one of SSL1 to SSL3). The plurality of memory cells MC1 to MC8 can be connected to corresponding gate lines GTL1 to GTL8, respectively. The gate lines GTL1 to GTL8 can be word lines, and some of the gate lines GTL1 to GTL8 can be dummy word lines. Each ground selection transistor GST can be connected to a corresponding ground selection line (one of GSL1 to GSL3). Each string selection transistor SST can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground selection transistor GST can be connected to the common source line CSL.

[0080] ​​Word lines having the same height (e.g., WL1) can be commonly connected, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated. Although not shown, gate lines corresponding to the middle switch lines can be separated as described below. In Figure 6 , a memory block BLKi is shown as being coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto. Each memory block in the memory cell array 100 can be coupled to any number of word lines and any number of bit lines.

[0081] A three-dimensional NAND flash memory device or a vertical NAND flash memory has been described as a non-volatile memory device to which example embodiments are applied, but example embodiments are limited to a specific memory type. For example, example embodiments can be applied to various non-volatile memory devices such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc. Figure 6

[0082] Figure 7 is a graph showing states of a multi-layer cell included in a non-volatile memory device according to an example embodiment.

[0083] Figure 7 First to eighth states S1 to S8 of a three-layer cell (TLC) are shown, in which each TLC can store three data bits. In Figure 7 , a horizontal axis represents a threshold voltage VTH of a memory cell, and a vertical axis represents a number of memory cells corresponding to the threshold voltage VTH. During a program operation, program success of the first to eighth states S1 to S8 can be distinguished by sequentially applying first to seventh verify read voltages VVR1 to VVR7 to a selected word line. In addition, during a normal read operation, the first to eighth states S1 to S8 can be distinguished by applying at least a part of first to seventh normal read voltages VR1 to VR7 to a selected word line, as will be described below with reference to Figure 12 and Figure 13 .

[0084] A threshold voltage distribution of a memory cell can shift due to degradation of a retention characteristic associated with a data retention capability of the memory cell and / or degradation of a read disturbance characteristic associated with a read operation. Errors can be caused in reading data due to distortion of the threshold voltage distribution, and thus a predetermined read voltage will be adjusted according to a change in an operating condition. According to example embodiments, an optimal operating condition for each user environment can be provided by performing a learning operation and an inference operation based on training data.

[0085] ​Figure 8 is a diagram illustrating an example read sequence according to example embodiments.

[0086] Referring to Figure 8 each read sequence RSEQ can comprise a plurality of read operations ROP1- ROPk having respective read times tRD1-tRDk that are different from each other.

[0087] There is a trade-off between the length of the read time and the accuracy of the corresponding read operation. In other words, a read operation having a shorter read time also has a higher likelihood of a read failure result, while a read operation having a longer read time has a higher likelihood of a successful read operation result. Therefore, each read sequence RSEQ can be set such that read operations having shorter read times will be performed before read operations having longer read times, e.g., as shown in Figure 8 Here, a first read operation ROP1 having a shortest read time tRD1 is performed first, then a second read operation ROP2 having a second read time tRD2 that is longer than the first read time tRD1 is performed after the first read operation ROP1, then a third read operation ROP3 having a third read time tRD3 that is longer than the second read time tRD2 is performed after the second read operation ROP2, and so on until a kth read operation ROPk having a longest read time tRDk.

[0088] Each of the read operations ROP1-ROPk can be performed using error checking and correction (ECC) decoding. The read operations ROP1-ROPk in the selected read sequence RSEQ can be performed sequentially until valid data is obtained, as correctly indicated by the ECC decoding. Once valid data is obtained, later read operations will not be performed, and the read sequence RSEQ is ended.

[0089] As a result, the read latency associated with the selected read sequence corresponds to the sum of the read times of the read operations that are performed until valid data is obtained. In Figure 8In the illustrated example of FIG. 1, if valid data is obtained through the first read operation ROP1, the read latency tLAT1 corresponds to the first read time tRD1, if valid data is obtained through the second read operation ROP2, the read latency tLAT2 corresponds to the sum tRD1 + tRD2 of the first read time tRD1 and the second read time tRD2, if valid data is obtained through the third read operation ROP3, the read latency tLAT3 corresponds to the sum tRD1 + tRD2 + tRD3 of the first read time tRD1, the second read time tRD2 and the third read time tRD3, and if valid data is obtained through the last read operation ROPk, the read latency tLATk corresponds to the sum tRD1 + tRD2 +... + tRDk of all read times tRD1 ~ tRDk.

[0090] Figure 9 is a flowchart illustrating a method of reading data according to the read sequence RSEQ. Figure 8

[0091] Referring to Figure 9 , according to the read sequence RSEQ, a first read operation ROP1 of highest priority is performed (S11). Here, as in the example of FIG. 1, it is assumed that each read operation is performed in conjunction with ECC decoding. Thus, when it is determined through ECC decoding that the error(s) in the read data is / are correctable (S12: YES), the first read time tRD1 of the first read operation ROP1 is determined as the read latency tLAT1 (S13). Thus, since the error(s), if any, is / are correctable, valid data is obtained and the read sequence RSEQ is ended. Figure 8

[0092] However, when the error(s) is / are not correctable (S12: NO), a second read operation ROP2 of next priority is performed (S21). Again, if it is determined through ECC decoding that the resulting error(s), if any, in the read data is / are correctable (S22: YES), the sum tRD1 + tRD2 of the read times of the first read operation ROP1 and the second read operation ROP2 is determined as the read latency tLAT2 (S23).

[0093] However, if the error(s) is / are not correctable (S22: NO), a third read operation ROP3 of next priority is performed (S31). Again, if it is determined through ECC decoding that the error(s), if any, in the read data is / are correctable (S32: YES), the sum tRD1 + tRD2 + tRD3 of the read times of the first read operation ROP1, the second read operation ROP2 and the third read operation ROP3 is determined as the read latency tLAT3 (S33).

[0094] ​​In this way, as long as no valid data is obtained by performing a read operation with a higher priority, the read operations set variously are executed in turn until the last read operation ROPk is performed (S41). Thus, finally, if the error(s) in the read data, if any, is / are determined to be correctable by ECC decoding (S42: YES), the sum of the read times tRD1 + tRD2 +... + tRDk of all read operations ROP1 ~ ROPk is determined as the read latency tLATk (S43).

[0095] However, if no valid data is obtained by the last read operation ROPk, it is determined that the current read operation is not possible (S50) (i.e., a read failure occurs), and the read sequence RSEQ is ended.

[0096] If the operating conditions are not too unfavorable, in many cases, valid data will be obtained by the first read operation ROP1. Thus, by using the illustrated read sequence, the read latency can be minimized so that the entire read operation can be performed with a minimum actual read latency. However, if the operating conditions worsen, it can not be possible to obtain valid data by using only the first read operation. Thus, a second read operation with a respective priority and possibly subsequent read operations can be performed. This necessity will obviously prolong the read latency of the entire read operation. Thus, by setting a plurality of read sequences respectively corresponding to different operating conditions, the performance of the non-volatile memory device can be improved, wherein the use of a particular read sequence among the plurality of read sequences can be adaptively selected.

[0097] As will be described below with reference to Figures 10 to 20 , according to example embodiments, operating conditions such as read level sets, reliability levels, read sequences, etc. can be optimized for changes in operating conditions.

[0098] Figure 10 is a flowchart illustrating an example embodiment of determining operating conditions in a method of controlling operations of a non-volatile memory device according to example embodiments, Figure 11 is a diagram illustrating an example read sequence set for Figure 10 determining operating conditions.

[0099] Referring to Figure 1 , Figure 10 and Figure 11 , a plurality of read level sets RLS1 ~ RLS3 is provided so that each read level set RLSi (i = 1, 2, 3) can correspond to a combination of levels VLij (j = 1 ~ m) of read voltages VR1 ~ VRm for read operations of the non-volatile memory device (S111), the plurality of read level sets RLS1 ~ RLS3 can be stored as a form of a setting table STTBL inFigure 1 in the buffer memory 40.

[0100] The optimal read level set corresponding to the current feature information FTRINF_C among the plurality of read level sets RLS1-RLS3 can be determined by performing an inference operation based on the current feature information FTRINF_C as an input to a machine learning model (S112).

[0101] In some example embodiments, the optimal read level set can be determined with respect to each of a plurality of memory planes included in the non-volatile memory device or with respect to each of a plurality of memory blocks included in the non-volatile memory device, respectively.

[0102] Figure 12 is a flowchart illustrating an example embodiment of determining an operation condition in a method of controlling an operation of a non-volatile memory device according to an example embodiment, Figure 13 is a graph illustrating a reliability level of determining an operation condition according to Figure 12

[0103] Referring to Figure 12 and Figure 13 The current cell count data indicative of a threshold voltage distribution of memory cells in the memory block can be monitored with respect to each of a plurality of memory blocks included in the non-volatile memory device (S121).

[0104] A plurality of reliability levels corresponding to the plurality of memory blocks can be determined by performing an inference operation based on the current cell count as an input to a machine learning model, such that each reliability level can indicate a lifetime of data stored in each memory block (S122).

[0105] In some example embodiments, the operation of monitoring the current cell count data and the operation of determining the plurality of reliability levels can be performed periodically. Figure 13 An example is illustrated in which reliability levels RL1-RL4 for respective memory blocks BLK1-BLK4 are determined at time points T1-T4. In Figure 13 RLi indicates a higher reliability level than RLi+1, i.e., R1 is the highest reliability level and R4 is the lowest reliability level. As a result, Figure 13 An example is illustrated in which the reliability levels of the memory blocks BLK1 to BLK4 in which data is analyzed can gradually decrease over time.

[0106] ​A rewrite operation can be performed relative to data stored in multiple memory blocks based on multiple reliability levels. For example, if the reliability level RL4 of memory block BLK3 is lower than a predetermined reference level, a rewrite operation can be performed relative to memory block BLK3, and memory block BLK3 can be initialized with the highest reliability level RL1.

[0107] Figure 14 This is a flowchart illustrating an example embodiment of determining operating conditions in a method for controlling the operation of a non-volatile memory device according to an example embodiment.

[0108] Reference Figure 14 Multiple read sequences can be configured for the non-volatile memory device (S131). (Refer to...) Figures 16 to 18 The described multiple read sequences can be stored as a setup table (STTBL). Figure 1 In the buffer memory 40.

[0109] The optimal read sequence corresponding to the current feature information among multiple read sequences can be determined by performing an inference operation based on the current feature information as input to the machine learning model (S132).

[0110] Figure 15 It is a graph used to describe the predetermined read voltage and the optimal read voltage.

[0111] Assuming a flash memory device is used in one embodiment of this disclosure, in Figure 15 The diagram illustrates the threshold voltage distribution for two adjacent states Si and Si+1. However, those skilled in the art will recognize that, assuming a resistive memory device, the following description can be applied to adjacent resistance distributions.

[0112] The optimal read voltage, Vop, is the minimum number of read voltages that result in erroneous bits among the data bits read simultaneously. The optimal read voltage, Vop, corresponds to a valley, i.e., the intersection of the threshold voltage distributions of the two states, Si and Si+1. The difference between the predetermined read voltage and the optimal read voltage increases as the distribution shifts and / or widens due to changes in operating conditions. As this difference increases, the probability of BER (bit error rate) or read failure also increases.

[0113] When the predetermined voltage is included in the first voltage range R1, errors in the read data can be corrected using ECC decoding with hard decision (HD). When the predetermined voltage is included in the second voltage range R2, errors in the read data can be corrected using ECC decoding with soft decision (SD). Some examples of HD and SD will be provided. Figure 19 and Figure 20 Described in some additional details.

[0114] When the bit error in the read data is too many and the predetermined read voltage is out of the second range R2, valid data cannot be obtained using the applicable ECC decoding. When valid data is not obtained by the previous read operation performed based on the predetermined read voltage, a valley search operation can be performed to determine the optimal read voltage Vop. Thereafter, the read operation can be performed using the optimal read voltage. Such a valley search operation and a read operation based on the optimal read voltage can be referred to as a "voltage-compensated read operation". In some embodiments, each read sequence can include a read operation based on a predetermined read voltage having a higher priority, and at least one voltage-compensated read operation having a lower priority, as shown in Figure 16 、 Figure 17 and Figure 18 . The valley search operation takes too much time and degrades the performance of the non-volatile memory device and the storage system including the non-volatile memory device. According to example embodiments, the read level set and the read sequence can be optimized for a user environment by performing a learning operation and an inference operation using machine learning.

[0115] Figure 16 、 Figure 17 and Figure 18 are graphs showing read sequences according to example embodiments.

[0116] Figure 16 、 Figure 17 and Figure 18 . The read sequences in

[0117] Referring to Figure 16 , the first read sequence RSEQ1 can include first to sixth read operations ROP11-ROP16 arranged according to respective priorities. The first read operation ROP11, the second read operation ROP12, and the third read operation ROP13 can be based on predetermined read voltages, and the fourth read operation ROP14, the fifth read operation ROP15, and the sixth read operation ROP16 can be voltage-compensated read operations.

[0118] As described above, the read operation with a shorter read time can be performed before the read operation with a longer read time. In other words, as the read time is shorter, the priority of the read operation can be higher. The first read operation ROP11 with the shortest read time, i.e., the first read time tRD11, can be performed first, the second read operation ROP12 with the second read time tRD12 longer than the first read time tRD11 can be performed after the first read operation ROP11, and the sixth read operation ROP16 with the longest read time tRD16 can be performed last.

[0119] Each of the first read operation ROP 11 and the second read operation ROP 12 can be a hard decision (HD) read operation that reads out hard decision data using a predetermined read voltage and performs ECC decoding based on the hard decision data. The first read operation ROP 11 can be a fast read operation DEF (F) based on the predetermined read voltage, and the second read operation ROP 12 can be a normal read operation DEF (N) based on the predetermined read voltage.

[0120] The third read operation ROP 13 can be a soft decision (SD) read operation that reads out hard decision data using a normal read operation DEF (N) based on a predetermined read voltage, provides reliability information around the predetermined read voltage using a plurality of read voltages for the hard decision data, and performs ECC decoding based on the hard decision data and the reliability information.

[0121] The fourth read operation ROP 14, the fifth read operation ROP 15, and the sixth read operation ROP 16 can combine a soft decision (SD) with a voltage-compensated read operation including a valley search operation VS1, VS2, and VS3, respectively, and a read operation based on a detected optimal read voltage. The valley search operations VS1, VS2, and VS3 can be variously implemented to have different search times and different read accuracies.

[0122] Referring to Figure 17 , the second read sequence RSEQ2 can include the first to fourth read operations ROP21 to ROP24 arranged according to respective priorities. The first read operation ROP21 and the second read operation ROP22 can be based on a predetermined read voltage, and the third read operation ROP23 and the fourth read operation ROP24 can be voltage-compensated read operations.

[0123] As described above, a read operation with a shorter read time can be performed before a read operation with a longer read time. The first read operation ROP21 with the shortest read time, i.e., the first read time tRD21, can be performed first, the second read operation ROP22 with the second read time tRD22 longer than the first read time tRD21 can be performed after the first read operation ROP21, and the fourth read operation ROP24 with the longest read time tRD24 can be performed last. The notations DEF (N), HD, SD, VS2, and VS3 are the same as described with reference to Figure 16 .

[0124] Referring to Figure 18The third read sequence RSEQ3 may include a first read operation ROP31, a second read operation ROP32, and a third read operation ROP33 arranged according to their respective priorities. The first read operation ROP31 may be based on a predetermined read voltage, and the second read operation ROP32 and the third read operation ROP33 may be voltage-compensated read operations.

[0125] As described above, a read operation with a shorter read time can be executed before a read operation with a longer read time. The first read operation ROP31, with the shortest read time (first read time tRD31), can be executed first. Then, the second read operation ROP32, with a longer read time tRD32 than the first read time tRD31, can be executed after ROP31. Finally, the last read operation ROP33, with the longest read time tRD33, can be executed. (Note: DEF(N), SD, VS2, and VS3 are labeled with reference.) Figure 16 The same as described above.

[0126] For example, the first read sequence RSEQ1 can be set for operating conditions in a relatively low BER range, and the operating conditions can be set for an intermediate BER range. Figure 17 The second read sequence RSEQ2 can be set for operating conditions in a relatively high BER range. Figure 18 The third read sequence is RSEQ3. Thus, the performance of non-volatile memory devices can be improved by setting multiple read sequences corresponding to different operating conditions and adaptively controlling the read sequences.

[0127] Figure 19 This is a diagram illustrating an example of a 2-bit soft-decision read operation. Figure 20 This is a diagram illustrating an example of a 3-bit soft decision read operation.

[0128] like Figure 19As shown, the non-volatile memory device can perform a 2-bit soft decision read operation. The 2-bit soft decision read operation can include three read operations using three voltages VI, V2, and V3 with regular intervals. For example, the three voltages VI, V2, and V3 can include a first voltage VI with a predetermined reference level for distinguishing between a first state Si corresponding to data "1" and a second state Si+1 corresponding to data "0", a second voltage V2 lower than the first voltage VI by a predetermined level, and a third voltage V3 higher than the first voltage VI by a predetermined level. In some embodiments, data 710 read by using the first voltage VI with the reference level can be hard decision data 710 read by a hard decision read operation, and the 2-bit soft decision read operation can use the hard decision data 710 read by the hard decision read operation without applying the first voltage VI with the reference level. The 2-bit soft decision read operation can generate soft decision data 720 with reliability information for the hard decision data 710 by performing a predetermined logical operation (e.g., XNOR operation 730) (or encoding) on data read via using the second voltage V2 and data read via using the third voltage V3. Each bit of the soft decision data 720 can represent a degree of reliability of a corresponding bit of the hard decision data 710. For example, a bit of the soft decision data 720 with a value of "1" can represent that a corresponding bit of the hard decision data 710 has strong (S) reliability, and a bit of the soft decision data 720 with a value of "0" can represent that a corresponding bit of the hard decision data 710 has weak (W) reliability.

[0129] As Figure 20As shown, the non-volatile memory device can perform a 3-bit soft decision read operation. The 3-bit soft decision read operation can include seven read operations using seven voltages V1, V2, V3, V4, V5, V6, and V7 with regular intervals. For example, the seven voltages V1, V2, V3, V4, V5, V6, and V7 can include the three voltages V1, V2, and V3 used in the 2-bit soft decision read operation, and can further include a fourth voltage V4 lower than the second voltage V2, a fifth voltage V5 between the second voltage V2 and the first voltage V1, a sixth voltage V6 between the first voltage V1 and the third voltage V3, and a seventh voltage V7 higher than the third voltage V3. In some embodiments, the data 710 read by using the first voltage V1 can be hard decision data 710 read by a hard decision read operation. The data 720 read by using the second voltage V2 and the third voltage V3 can be most significant bit (MSB) soft decision data 720 corresponding to the soft decision data 720 read by a 2-bit soft decision read operation. The 3-bit soft decision read operation can generate least significant bit (LSB) soft decision data 740 by performing a predetermined logical operation (e.g., XNOR operation 750) (or encoding) on data read via using the fourth voltage V4, the fifth voltage V5, the sixth voltage V6, and the seventh voltage V7. Each soft decision data 720 and 740 having two bits can represent a degree of reliability of a corresponding bit of the hard decision data 710. For example, each soft decision data 720 and 740 having a value of "11" can represent that a corresponding bit of the hard decision data 710 has very strong (VS) reliability, each soft decision data 720 and 740 having a value of "10" can represent that a corresponding bit of the hard decision data 710 has strong (S) reliability, each soft decision data 720 and 740 having a value of "00" can represent that a corresponding bit of the hard decision data 710 has weak (W) reliability, and each soft decision data 720 and 740 having a value of "01" can represent that a corresponding bit of the hard decision data 710 has very weak (VW) reliability.

[0130] Although Figure 19 and 20 Two adjacent states Si and Si+1 are shown, but a 3-bit soft decision read operation can be performed between any two adjacent states in a plurality of states. Figure 19 and Figure 20 The 2-bit soft decision read operation and the 3-bit soft decision read operation shown distinguish between any two adjacent states in a plurality of states. The memory cells of the non-volatile memory device can be multi-layer cells (MLCs) programmed to one 2 N state to store N bits of data. Although Figure 19 and Figure 20 MLCs storing two or three bits are shown, example embodiments can be applied to MLCs storing four or more bits.

[0131] Figure 21 This is a flowchart illustrating a method for controlling the operation of a non-volatile memory device according to an example embodiment.

[0132] Reference Figure 21 It can be executed as shown in the reference. Figures 14 to 20 The determined read sequence RSEQ (S10) can be used. Training data TRD can be collected based on the read sequence RSEQ and the result of ECC decoding (S20). Error information ERRINF, indicating the result of ECC decoding, can be accumulated (S30), and the probability of ECC decoding failure can be calculated based on the accumulated error information ERRINF (S40). When the probability PRFL is higher than the reference value TH (S50: Yes), the machine learning model MD can be updated by performing a learning operation (S60). When the probability PRFL is not higher than the reference value TH (S50: No), the machine learning model MD can be maintained.

[0133] In this way, the timing of performing the learning operation can be determined based on the probability of ECC decoding failure (PRFL). In some example embodiments, the failure probability (PRFL) can be the failure probability of a hard decision read operation. In some example embodiments, it can be as described in reference... Figure 8 and Figure 9 The monitored read latency can be used to determine a probability PRFL, which is then used to determine when to perform a learning operation. In some example embodiments, the timing of the learning operation can be determined based on the probability of inference operation failure.

[0134] Figure 22 It is a machine learning engine based on the example embodiment.

[0135] Reference Figure 22 The machine learning engine 21 may include a controller CTRL, a first machine learning module MLMDL1, and a second machine learning module MLMDL2. The controller can drive the machine learning modules MLMDL to update the machine learning model MD.

[0136] The first machine learning module, MLMDL1, can have a first-performance PFM1 and perform learning operations based on the training data TRD. The second machine learning module, MLMDL2, can have a second-performance PFM2, which is higher than the first-performance PFM1, and perform inference operations based on the current feature information FTRINF_C. This dual structure ensures that even if a delay occurs during the learning operation, the high-speed inference operation can proceed without delay.

[0137] In some example embodiments, a first number of nodes that concurrently perform node operations in the first machine learning model MLMDL1 can be less than a second number of nodes that concurrently perform node operations in the second machine learning model MLMDL2. In some example embodiments, a first hardware performance (e.g., a frequency of an operation clock signal) of the first machine learning model MLMDL1 can be lower than a second hardware performance of the second machine learning model MLMDL2.

[0138] Figure 23 and Figure 24 is a block diagram illustrating a machine learning device included in a storage system according to an example embodiment.

[0139] Referring to Figure 23 and Figure 24 , a size of the training data TRD can be reduced, and the size-reduced training data can be stored in the buffer memory. Hereinafter, a description of Figure 1 repeated can be omitted.

[0140] In some example embodiments, the training data TRD can be compressed, and the size-reduced training data TRD' can be stored in the buffer memory BUFF. The compression scheme can be a lossless compression scheme or a lossy compression scheme. In some example embodiments, the training data TRD can be normalized, and the size-reduced training data TRD' can be stored in the buffer memory BUFF. Here, "normalization" indicates that values of data are proportionally reduced, so that a range of the values can be narrowed. As such, a memory capacity of the buffer memory BUFF can be reduced or efficiently used by reducing the training data TRD and storing the size-reduced training data TRD'.

[0141] Referring to Figure 23 , the machine learning device 11 can include a machine learning engine MLD, a data collector DCLL, a buffer memory BUFF, a downsizing unit DNSZ, and an upsizing unit UPZ. The downsizing unit DNSZ can compress or normalize the training data TRD to store the size-reduced training data TRD' in the buffer memory BUFF. The upsizing unit UPZ can restore the training data TRD based on the size-reduced training data TRD' stored in the buffer memory BUFF, and provide the training data TRD to the machine learning engine MLD. The machine learning engine MLD can perform a learning operation based on the training data TRD, and perform an inference operation based on the current feature information FTRINF_C.

[0142] Compared to the machine learning device 11 of Figure 23 , in Figure 24The upsizing unit UPSZ is omitted in the machine learning device 12. In this case, the machine learning engine MLD can perform the learning operation based on the size-reduced training data TRD'. The downsizing unit DNSZ can provide the size-reduced current feature information FTRINF_C' during the inference operation, and the machine learning engine MLD can perform the inference operation based on the size-reduced current feature information FTRINF_C'.

[0143] Figure 25 and Figure 26 are diagrams for describing an example of a deep learning neural network structure driven by a machine learning device according to an example embodiment.

[0144] Referring to Figure 25 , a general neural network can include an input layer IL, a plurality of hidden layers HL1, HL2,..., HLn, and an output layer OL.

[0145] The input layer IL can include i input nodes x1, x2,..., xi, where i is a natural number. Feature information FTRINF of length i (e.g., a vector input data) can be input to the input nodes x1, x2,..., xi, such that each element of the feature information FTRINF is input to a corresponding node among the input nodes x1, x2,..., xi.

[0146] The plurality of hidden layers HL1, HL2,..., HLn can include n hidden layers, where n is a natural number, and can include a plurality of hidden nodes h 1 1, h 1 2, h 1 3,..., h 1 m , h 2 1, h 2 2, h 2 3,..., h 2 m , h n 1, h n 2, h n 3,..., h n m For example, the hidden layer HL1 can include m hidden nodes h 1 1, h 1 2, h 1 3,..., h 1 m , the hidden layer HL2 can include m hidden nodes h 2 1, h 2 2, h 2 3,..., h 2 m , and the hidden layer HLn can include m hidden nodes hn 1, h n 2, h n 3,..., h n m where m is a natural number.

[0147] The output layer OL can include j output nodes y1, y2,..., y j where j is a natural number. Each of the output nodes y1, y2,..., y j may correspond to a respective one of the classes to be classified. The output layer OL can output, for each class, an output value (e.g., a class score, or simply score) ODAT associated with the feature information FTRINF. The output layer OL can be referred to as a fully connected layer, and can indicate, for example, a probability that the feature information FTRINF corresponds to each operating condition.

[0148] Figure 25 The structure of the illustrated neural network can be represented by information about branches (or connections) between nodes, which are illustrated as lines, and weighted values assigned to each branch. Nodes within one layer can not be connected to each other, but nodes of different layers can be fully or partially connected to each other.

[0149] Each node (e.g., node h 1 1) can receive an output of a previous node (e.g., node x1), can perform a computation operation, calculation, or operation on the received output, and can output a result of the computation operation, calculation, or operation as an output to a next node (e.g., node h21). Each node can calculate a value to be output by applying an input to a specific function (e.g., a non-linear function).

[0150] In general, the structure of a neural network can be set in advance, and weighted values for connections between nodes can be appropriately set using data having known answers of which category data belongs to. Data having known answers is referred to as “training data”, and a process of determining weighted values is referred to as “training”. A neural network “learns” during a training process. A group of structures and weighted values that can be trained independently is referred to as a “model”, and a process of predicting which category input data belongs to by a model having determined weighted values, and then outputting a predicted value is referred to as a “test” process.

[0151] Referring to Figure 26 , the convolutional neural network can include a plurality of layers CONV1, RELU1, CONV2, RELU2, POOL1, CONV3, RELU3, CONV4, RELU4, POOL2, CONV5, RELU5, CONV6, RELU6, POOL3, and FC.

[0152] Unlike a general neural network, each layer of a convolutional neural network can have three dimensions of width, height, and depth, and thus data input to each layer can be volume data having three dimensions of width, height, and depth.

[0153] Each of the convolution layers CONV1, CONV2, CONV3, CONV4, CONV5, and CONV6 can perform a convolution operation on the current feature information FTRINF_C. The convolution operation represents an operation in which data is processed based on a mask having weighted values and an output value is obtained by multiplying input values by the weighted values and adding the total multiplied values. The mask can be referred to as a filter, a window, or a kernel.

[0154] Each of the RELU layers RELU1, RELU2, RELU3, RELU4, RELU5, and RELU6 can perform a rectified linear unit operation on input. Each of the pooling layers POOL1, POOL2, and POOL3 can perform a down-sampling operation on volume data of input along spatial dimensions of width and height. In general, one convolution layer (e.g., CONV1) and one RELU layer (e.g., RELU1) can form a pair of CONV / RELU layers in a convolutional neural network, the paired CONV / RELU layers can be repeatedly arranged in the convolutional neural network, and the pooling layers can be periodically inserted in the convolutional neural network, thereby reducing data size and extracting data features.

[0155] The output layer or the fully connected layer FC can output a result (e.g., a class score) of the current feature information FTRINF_C for each class. For example, when the convolution operation and the down-sampling operation are repeated, volume data of input corresponding to the current feature information FTRINF_C can be converted into a one-dimensional matrix or a vector. For example, the fully connected layer FC can represent probabilities that the current feature information FTRINF_C corresponds to the plurality of read level sets RLS1-RLS5, respectively. In this way, a read level set corresponding to the highest probability can be determined as an optimal read level set among the plurality of read level sets RLS1-RLS5.

[0156] Figure 27 is a diagram illustrating an example of a node included in a neural network and an example node operation performed by the node ND in the neural network.

[0157] When N inputs a1-a n The node ND can multiply the n inputs a1-a n and the corresponding n weights w1-w nMultiplication, summation of n values obtained by multiplication, addition of an offset "b" to the summation value, and generation of an output value by applying the value added with the offset "b" to a specific function "σ" can be performed. A learning operation can be performed to update all nodes in the neural network based on the training data TRD.

[0158] Figure 28 FIG. 1 is a diagram illustrating a storage system according to an example embodiment.

[0159] Referring to Figure 28 The computing system 2600 includes a processor 2610, a memory device 2620, a user interface 2630, a bus 2650, and a storage system 2660. In some embodiments, the computing system 2600 can further include a modem 2640, such as a baseband chipset.

[0160] The processor 2610 can perform a specific computation or task. For example, the processor 2610 can be a microprocessor, a central processing unit (CPU), a digital signal processor, etc. The processor 2610 can be coupled to the memory device 2620 via the bus 2650, such as an address bus, a control bus, and / or a data bus. In addition, the processor 2610 can be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus, and can control the user interface 2630 including at least one input device, such as a keyboard, a mouse, a touch screen, etc., and at least one output device, such as a printer, a display device, etc. The modem 2640 can perform wired or wireless communication with an external device.

[0161] The storage system 2660 can include a storage controller SCON 2670 and a non-volatile memory device NVM 2680. The storage controller 2670 can include a machine learning device ML as described above to perform a method of controlling an operation of a non-volatile memory device according to an example embodiment.

[0162] As described above, the method of controlling an operation of a non-volatile memory device and the storage system according to an example embodiment can provide optimized operating conditions for individual user environments by collecting training data in the storage system and performing a learning operation and an inference operation based on the training data.

[0163] The present disclosure can be applied to any electronic device and system including a nonvolatile memory device. For example, the present disclosure can be applied to a system such as a memory card, a solid state drive (SSD), an embedded Multi Media Card (eMMC), a Universal Flash Storage (UFS), a mobile phone, a smart phone, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a digital camera, a camcorder, a Personal Computer (PC), a server computer, a workstation, a laptop computer, a digital television, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an electronic book, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or the like.

[0164] It is conventional in the art to describe and depict embodiments in terms of blocks that carry out various functions described herein. These blocks can be physically implemented as analog and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, and the like. Such circuits can be embodied in one or more semiconductor chips, or on a substrate such as a printed circuit board. The circuits constituting the blocks can be implemented by dedicated hardware, or by a processor, such as one or more programmed microprocessors and associated circuitry, or by a combination of dedicated hardware to perform some functions of the blocks and a processor to perform other functions of the blocks. Each block of the embodiments can be physically separated from another block or blocks or can be physically combined with another block or blocks, as desired in the art. Similarly, aspects of the embodiments can be implemented by instructions stored in non-transitory storage media and executed by a processor.

[0165] The foregoing is a summary of example embodiments, and will not be interpreted as a limitation thereof. While certain example embodiments have been described, those skilled in the art will readily understand that many modifications can be made thereto without departing from the scope of the present disclosure.

Claims

1. A method of controlling operation of a non-volatile memory device using machine learning, the method comprising: determining an operation condition of the non-volatile memory device by performing an inference operation using a machine learning model; collecting training data generated based on feature information and error information, the error information indicating a result of error correction code (ECC) decoding of the non-volatile memory device; and updating the machine learning model by performing a learning operation based on the training data, wherein the feature information includes a physical address of the non-volatile memory device and cell count data indicating a threshold voltage distribution of memory cells corresponding to the physical address.

2. The method of claim 1, wherein, The error information includes at least one of a probability of ECC decoding failure and a number of errors determined by the ECC decoding.

3. The method of claim 1, wherein, The determining of the operation condition includes: providing a plurality of read level sets, each read level set corresponding to a combination of levels of read voltages for a read operation of the non-volatile memory device; and determining, by performing the inference operation based on current feature information as an input of the machine learning model, an optimal read level set corresponding to the current feature information among the plurality of read level sets, wherein the optimal read level is a read level resulting in a least number of error bits among data bits read out simultaneously.

4. The method of claim 3, wherein, The optimal read level set is determined with respect to each of a plurality of memory planes included in the non-volatile memory device or with respect to each of a plurality of memory blocks included in the non-volatile memory device, respectively.

5. The method of claim 1, wherein, The determining of the operation condition includes: monitoring, with respect to each of a plurality of memory blocks included in the non-volatile memory device, current cell count data indicating a threshold voltage distribution of memory cells in the memory block; and determining, by performing the inference operation based on the current cell count data as an input of the machine learning model, a plurality of reliability levels corresponding to the plurality of memory blocks, each reliability level indicating a lifetime of data stored in each memory block.

6. The method of claim 5, further comprising performing a rewrite operation with respect to data stored in the plurality of memory blocks based on the plurality of reliability levels.

7. The method of claim 5, wherein, The monitoring of the current cell count data and the determining of the plurality of reliability levels are performed periodically.

8. The method of claim 1, wherein, The determining of the operation condition includes: setting a plurality of read sequences of the non-volatile memory device; and determining, by performing the inference operation based on current feature information as an input of the machine learning model, an optimal read sequence corresponding to the current feature information among the plurality of read sequences.

9. The method of claim 1, wherein, The learning operation is performed by a first machine learning module having a first performance, and the inference operation is performed by a second machine learning module having a second performance higher than the first performance.

10. The method of claim 9, wherein, A first number of nodes performing node operations simultaneously in the first machine learning model is less than a second number of nodes performing node operations simultaneously in the second machine learning model.

11. The method of claim 1, wherein, The collecting of the training data includes reducing a size of the training data to store the size-reduced training data in a buffer memory.

12. The method of claim 11, wherein, The reducing of the size of the training data includes compressing the training data.

13. The method of claim 11, wherein, The reducing of the size of the training data includes normalizing the training data. 14.The method of claim 1, further comprising determining a timing of performing the learning operation based on a probability of the inference operation failing and a probability of the ECC decoding failing. 15.A method of controlling an operation of a non-volatile memory device using machine learning, the method comprising: providing a plurality of sets of read levels, each set of read levels corresponding to a combination of levels of read voltages for a read operation of the non-volatile memory device; determining, by performing an inference operation based on current feature information as an input of a machine learning model, an optimal set of read levels corresponding to the current feature information among the plurality of sets of read levels; collecting training data generated based on feature information and error information, the feature information including a physical address of the non-volatile memory device and cell count data indicating a threshold voltage distribution of a memory cell corresponding to the physical address, the error information indicating a result of error correction code (ECC) decoding of the non-volatile memory device; updating the machine learning model by performing a learning operation based on the training data; and determining a timing of performing the learning operation based on a probability of the inference operation failing and a probability of the ECC decoding failing. 16.A storage system comprising: a non-volatile memory device; and a storage controller configured to control the non-volatile memory device, the storage controller comprising: a data collector configured to collect training data generated based on feature information and error information, the error information indicating a result of error correction code (ECC) decoding of the non-volatile memory device; a buffer memory configured to store the training data; and a machine learning engine configured to determine an operation condition of the non-volatile memory device by performing an inference operation using a machine learning model, and to update the machine learning model by performing a learning operation based on the training data, wherein the feature information includes a physical address of the non-volatile memory device and cell count data indicating a threshold voltage distribution of a memory cell corresponding to the physical address. 17.The storage system of claim 16, wherein: the error information includes at least one of a probability of the ECC decoding failing and a number of errors determined by the ECC decoding. the machine learning engine determines an optimal set of read levels corresponding to the current feature information among a plurality of sets of read levels by performing an inference operation based on current feature information as an input of the machine learning model. the machine learning engine comprises:

18. The storage system of claim 16, wherein, a first machine learning module configured to perform the learning operation at a first performance; and 19. The storage system of claim 16, wherein, a second machine learning module configured to perform the inference operation at a second performance higher than the first performance. ​ ​

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