Method for inspecting pattern defects

Abstract

The present disclosure relates to a method for inspecting pattern defects. In a method for inspecting pattern defects, a plurality of patterns are formed over a substrate. The plurality of patterns are electrically isolated from each other. A portion of the plurality of patterns is scanned with an electron beam to charge the plurality of patterns. The intensity of secondary electrons emitted from the scanned portion of the plurality of patterns is obtained. One or more patterns among the plurality of patterns that exhibit an intensity of secondary electrons different from that of other patterns among the plurality of patterns are searched for.

Description

Technical Field

[0001] The present disclosure relates to a method for inspecting pattern defects. Background Art

[0002] Defect inspection is an important aspect of semiconductor manufacturing operations. As the semiconductor industry enters nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, defect inspection becomes more difficult. Specifically, in nanotechnology process nodes using extreme ultraviolet (EUV) defect inspection tools, the defect capture rate decreases as the size shrinks. Therefore, improvements in defect inspection, including film stacks, inspection tools, processes, and layout designs, have been studied to increase the defect capture rate. Summary of the Invention

[0003] According to one aspect of the present disclosure, there is provided a method for inspecting pattern defects, the method comprising: forming a plurality of patterns on a bottom layer, the plurality of patterns being electrically isolated from each other; scanning a portion of the plurality of patterns with an electron beam to charge the plurality of patterns; obtaining intensities of secondary electrons emitted from the scanned portion of the plurality of patterns; and searching for one or more patterns among the plurality of patterns that exhibit intensities of secondary electrons different from those of other patterns among the plurality of patterns.

[0004] According to another aspect of the present disclosure, there is provided a method for inspecting pattern defects, the method comprising: forming multiple sets of a plurality of patterns on a bottom layer, the plurality of patterns being electrically isolated from each other; scanning a portion of a first set of the plurality of patterns with an electron beam to find a defect; obtaining intensities of secondary electrons emitted from the scanned portion of the first set of the plurality of patterns; searching for one or more patterns among the plurality of patterns in the first set that exhibit intensities of secondary electrons different from those of other patterns among the plurality of patterns in the first set; when finding one pattern among the plurality of patterns that exhibits an intensity of secondary electrons different from those of other patterns among the plurality of patterns, obtaining a position of the one pattern among the plurality of patterns; and scanning a portion of a second set of the plurality of patterns with the electron beam to find a defect.

[0005] According to still another aspect of the present disclosure, there is provided a test device for detecting a defect, comprising: a bottom layer disposed on a substrate; a plurality of line patterns disposed on the bottom layer and electrically isolated from each other, wherein the plurality of line patterns are more conductive than the bottom layer, and the plurality of line patterns include at least one of a defect as a broken line pattern or a defect as a bridge between adjacent line patterns. Brief Description of the Drawings

[0006] As described in the following detailed description in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A A process control module (PCM) according to an embodiment of the present disclosure is shown, and Figure 1B a layout of a defect inspection pattern in the PCM according to an embodiment of the present disclosure is shown. Figure 1C and Figure 1D a cross-sectional view of a defect inspection pattern according to an embodiment of the present disclosure is shown.

[0008] Figure 2 An operation of detecting a defect using an electron beam according to an embodiment of the present disclosure is shown.

[0009] Figure 3A and Figure 3B An operation of detecting a defect using an electron beam according to an embodiment of the present disclosure is shown.

[0010] Figure 4A and Figure 4B An operation of detecting a defect using an electron beam according to an embodiment of the present disclosure is shown.

[0011] Figure 5A and Figure 5B A defect inspection pattern for electron beam defect inspection according to an embodiment of the present disclosure is shown.

[0012] Figure 6A and Figure 6B A defect inspection pattern for electron beam defect inspection according to an embodiment of the present disclosure is shown.

[0013] Figure 7 is a flowchart showing defect inspection according to an embodiment of the present disclosure.

[0014] Figure 8 is a flowchart showing a defect inspection operation and a device maintenance operation according to an embodiment of the present disclosure.

[0015] Figure 9A and Figure 9B A defect inspection system according to an embodiment of the present disclosure is shown. Detailed Description

[0016] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following describes specific embodiments or examples of components and arrangements to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the ranges or values disclosed, but may depend on the process conditions of the device and / or the desired characteristics. In addition, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. For simplicity and clarity, the various features may be drawn in arbitrary proportions. In the drawings, some layers / features may be omitted for simplicity.

[0017] In addition, spatially relative terms may be used herein, for example, "below", "beneath", "under", "above", "upper", etc., to easily describe the relationship of one element or feature shown in the figure with respect to another (some) element or feature. In addition to the orientations shown in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "consisting of" may mean "including" or "comprising". In addition, during subsequent manufacturing processes, there may be one or more additional operations among / between the described operations, and the order of operations may be changed. The materials, configurations, processes, and / or methods illustrated by one embodiment may be applied to other embodiments, and their detailed descriptions may be omitted.

[0018] The present disclosure relates to a method for inspecting pattern defects during manufacturing operations of semiconductor integrated circuits. In order to improve the yield of semiconductor devices during the semiconductor device manufacturing process, it is necessary to reduce or eliminate pattern defects that render one or more semiconductor devices formed on a semiconductor wafer inoperable. Pattern defects are caused by, for example, the following: film formation processes; lithography operations, including resist coating processes, exposure processes, and development processes (as resist pattern defects); etching operations; and planarization operations, including chemical mechanical polishing (CMP) processes.

[0019] Pattern defects can be detected by using an optical image of the pattern with an optical defect inspection tool. In such an optical defect inspection, an optical image of a portion of the pattern in a chip region is captured and compared with an optical image of a portion of the pattern in another chip region having the same design data. The light source (inspection light) for obtaining the optical image can be visible light (about 400 - 850 nm), ultraviolet light (UV) (about 280 - 400 nm), or deep UV (about 150 - 280 nm). In some embodiments, the wavelength of the inspection light (e.g., peak wavelength) is in the UV or DUV region and in the range of about 250 nm to about 330 nm. In other embodiments, the wavelength of the inspection light is in the range of about 255 nm to about 320 nm. The captured image is typically processed through image processing to identify the pattern or distinguish the pattern from the background image.

[0020] When the pattern size is reduced to below about 10 - 30 nm, although the optical inspection method is generally a high - throughput process, the resolution of the optical inspection method may be insufficient and may not be applicable to such fine patterns. In contrast, an inspection method using an electron beam (or ion beam) provides high resolution, but its throughput is 10 - 10000 times slower than the optical inspection method.

[0021] In the present disclosure, voltage contrast inspection (VCI) using local electron beam scanning is employed. In VCI, the difference in the induced surface voltage (charge) above the scanned region creates a difference in the secondary electron emission intensity, which in turn creates different image contrasts depending on the defect.

[0022] Figure 1A A process control module (PCM) according to an embodiment of the present disclosure is shown, and Figure 1B A layout of a defect inspection pattern in the PCM according to an embodiment of the present disclosure is shown. During the manufacturing operation of a semiconductor device, the PCM is used to monitor process quality, control the process (e.g., feedback process) and / or detect process problems (defects, etc.). In some embodiments, the PCM is disposed in a scribe lane between chips, within a chip, and / or replaces a chip region. In other embodiments, the semiconductor wafer only includes PCMs in a matrix, and thus the semiconductor wafer is a test wafer on which no pattern that is or will be part of an electronic device (e.g., a transistor) is formed.

[0023] In some embodiments, the PCM includes as Figure 1BThe defect inspection pattern 100 shown. In some embodiments, the defect inspection pattern includes a plurality of line patterns 10 (line-and-space patterns) arranged to have a spacing 20 therebetween. In some embodiments, the plurality of line patterns 10 correspond to the pattern to be inspected and are convex patterns formed on top of an underlying layer 30, as Figure 1C shown. In other embodiments, the plurality of line patterns 10 are embedded in the insulating layer 30, as Figure 1D shown. Although the drawings show straight lines with a constant width, the line patterns can include any of lines with varying widths, wavy lines, or zigzag lines.

[0024] In some embodiments, the plurality of line patterns 10 are made of a conductive material, e.g., an etched pattern of a conductive material (e.g., a metal material or a semiconductor material) or an embedded pattern of a conductive material. In some embodiments, the spacing pattern is formed by an exposed portion of the underlying layer. As Figure 1B - Figure 1D shown, the plurality of line patterns 10 are electrically isolated from each other by the spacing pattern 20. In the present disclosure, the phrase "the plurality of line patterns are electrically isolated from each other" means that the plurality of line patterns are designed to be electrically isolated from each other (e.g., on a photomask) in the absence of defects, particularly in the absence of bridging defects. In some embodiments, the spacing pattern 20 is connected to each other by bus bar patterns 25 at the top and bottom, as Figure 1B shown. In some embodiments, none of the plurality of line patterns 10 are connected to a lower conductive layer disposed below the plurality of line patterns 10, an upper conductive layer disposed above the plurality of line patterns 10, and a conductive pattern disposed at the same level as the plurality of line patterns 10. In other words, each of the plurality of line patterns 10 is electrically floating (e.g., not electrically connected to ground).

[0025] In some embodiments, a plurality of line patterns 10 are formed on or embedded in a bottom layer 30 disposed on a substrate 15 (e.g., a semiconductor wafer). The bottom layer 30 includes one or more dielectric layers, such as a silicon oxide (SiO2) layer, a silicon oxynitride (SiON) layer, a silicon nitride (SiN) layer, a silicon carbide (SiC) layer, a silicon oxycarbide (SiOC) layer, a silicon oxynitride carbide (SiOCN) layer, an aluminum oxide layer (AlO), a high-k (dielectric constant) material (e.g., hafnium oxide, zirconium oxide), or a low-k (dielectric constant) material layer. In some embodiments, one or more additional layers (e.g., dielectric layers) are disposed between the substrate 15 and the bottom layer 30. In some embodiments, the material of the bottom layer 30 is different from the material of the one or more additional layers. In some embodiments, the thickness of the bottom insulating layer 30 is in the range of about 20 nm to about 100 nm. In some embodiments, the materials for the line patterns 10 and the bottom layer 30 are selected such that the conductivity of the material for the line patterns 10 is higher than the conductivity of the bottom layer 30. In some embodiments, the conductivity of the material for the line patterns 10 is 100 to 10,000 times the conductivity of the bottom layer 30.

[0026] The substrate 15 can be made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a Group IV-IV compound semiconductor (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide), etc. In some embodiments, the substrate 15 is a glass or quartz substrate for a photomask or a flat panel display.

[0027] In some embodiments, the substrate 15 (e.g., a Si wafer) is a monitor or test wafer that will not be used to fabricate a semiconductor device as a final product. In other embodiments, the substrate 15 is a product wafer on which various semiconductor manufacturing operations have been or will be performed to fabricate a semiconductor device including transistors as a final product.

[0028] In some embodiments, the bottom layer 30 and / or the substrate 15 includes a bottom pattern, and in other embodiments, the bottom layer 30 and / or the substrate 15 do not have a pattern (flat surface). The bottom pattern on the bottom layer and / or the substrate can be one of the device patterns or can be a monitor pattern specifically prepared for defect inspection. The bottom pattern can be formed by one or more lithography and etching operations.

[0029] In some embodiments, the plurality of line patterns 10 includes one or more conductive layers, e.g., a semiconductor layer, including a crystalline semiconductor layer, a polysilicon layer, and an amorphous silicon layer; a metallization layer, including one or more selected from the group consisting of: W, Cu, Ti, Ag, Ta, Al, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr, or an alloy or compound thereof (e.g., TiN, TaN, TiO2, TiAl, TiAlC, TaAl, TaAlC, silicide, or any conductive material used in semiconductor device manufacturing operations).

[0030] In some embodiments, one or more conductive material layers for the plurality of line patterns 10 are formed by a physical vapor deposition (PVD) method including sputtering, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, an electroplating method, or any other suitable film formation method. In some embodiments, the thickness of the conductive material layer is in the range of about 20 nm to about 100 nm.

[0031] A photoresist pattern is formed over the conductive material layer by one or more lithography operations. The lithography operations include a resist coating process, an exposure process, and a development process. In some embodiments, the exposure process of the lithography operation includes UV lithography, deep UV (DUV) lithography, extreme ultraviolet (EUV) lithography, or electron beam lithography, or any other suitable operation. The conductive material layer is patterned into the plurality of line patterns 10 by using the resist pattern as an etch mask. In other embodiments, one or more hard mask layers are formed on the conductive material layer and the hard mask layer is patterned by using the resist pattern as an etch mask, and then the conductive material layer is patterned by using the patterned hard mask layer as an etch mask. In some embodiments, the hard mask pattern is removed, and in other embodiments, the hard mask pattern remains on the plurality of line patterns made of the conductive material.

[0032] Figure 2 and Figure 3A and Figure 3B An operation of detecting defects using an electron beam according to an embodiment of the present disclosure is shown. In some embodiments, the plurality of line patterns is referred to as a defect inspection pattern, as a set of patterns or a suite of patterns. In some embodiments, the number of the plurality of line patterns in a group is in the range of 2 to 100, and in other embodiments in the range of 10 to 50, depending on the design rules and / or process conditions of the semiconductor manufacturing operation, and / or the resolution of the inspection tool.

[0033] In some embodiments, the defect inspection is performed by an electron beam inspection device. In some embodiments, the electron beam only scans a selected portion of the defect inspection pattern, as Figure 2As shown. In some embodiments, when the entire length of the line pattern is A1, the scan width A2 is less than A1. In some embodiments, A2 is at least about 1%, about 2%, about 5%, or about 10% of A1, and at most about 5%, about 10%, about 20%, or about 50% of A1. In other embodiments, the scan is a single operation, and thus the scan width A2 is the same as the size of the electron beam spot. In some embodiments, alignment marks 19 indicating the scan width A2 are provided, as Figure 1B shown.

[0034] In some embodiments, the scan region 50 is located adjacent to the bus bar pattern 25. In some embodiments, the scan region 50 is spaced apart from the bus bar pattern 25, and thus the scan region 50 does not include the edges of the plurality of line patterns 10. In other embodiments, the scan region partially overlaps with the bus bar pattern 25, and thus the scan region 50 includes the edges of the plurality of line patterns 10.

[0035] As Figure 3A shown, when there are defects 12 or 14 in the defect inspection pattern, the charging state of the line pattern changes. For example, when the plurality of line patterns 10 includes a break defect 12 (a broken line pattern cut into two parts), the broken line pattern is charged with more electrons compared to a normal line pattern (without cutting), which results in a lower secondary electron emission intensity. On the other hand, when the plurality of line patterns 10 includes a bridging defect 14 (e.g., caused by resist scum) between two adjacent line patterns, the connected line pattern is charged with fewer electrons compared to a normal line pattern, which results in a higher secondary electron emission intensity. Therefore, when there are defects, the scanning electron microscope (SEM) image of the electron beam inspection tool has a different contrast (secondary electron signal intensity) from the remaining line patterns of the plurality of line patterns 10, as Figure 3B shown. Figure 3B The intensity of the secondary electrons is also shown. In some embodiments, the secondary electron signal intensity of each line pattern is compared with the average intensity of the plurality of line patterns. Thus, the line pattern (or two line patterns) including the defect can be found. In some embodiments, when the secondary electron signal intensity or contrast of the line pattern is lower than or higher than a threshold value, it is determined that there is a defect in the line pattern (or two line patterns). In some embodiments, the threshold value is ±5%, ±10%, ±15%, ±20%, or 30% of the average intensity of the secondary electrons from the plurality of line patterns, or any value therebetween.

[0036] In some embodiments, observation of the defect is performed. When a line pattern with a different contrast (secondary electron signal intensity) is found in the scan region 50, along the identified line pattern (e.g., as Figure 2Move the field of view of the SEM image downward (as shown) to find the defect. In some embodiments, the observation is performed starting from the scanning area 50. In some embodiments, the observation is automatically performed by using image analysis techniques.

[0037] In some embodiments, the position of the line pattern having the defect is obtained and stored in a memory for more careful inspection or observation. In some embodiments, the observation is performed by another observation tool (e.g., an SEM tool). The position is the coordinate of the line pattern, or the number of the line pattern counted from one end ( Figure 2 the left side or the left side in).

[0038] In some embodiments, the scanning of the electron beam over the scanning area A2 is a single scan. In other embodiments, the scanning of the electron beam over the scanning area A2 includes multiple scans. In some embodiments, multiple scans are performed at the same position, and in other embodiments, multiple scans are performed by changing the position along the Y direction within the scanning area A2.

[0039] When performing a single or multiple scans to obtain the accumulated secondary electrons for the local image, the pattern contrast of the two line patterns having the bridging (or scum) defect 14 may not have a sufficient contrast difference compared to the normal line pattern without the defect. In this case, the scanning of the electron beam is performed in a jumping manner, as Figure 4A shown. In some embodiments, the first scan is performed on the first, third,..., and the (2n - 1)th line patterns, and the second scan is performed on the second, fourth,..., and the 2nth line patterns (n = 1, 2,...). In some embodiments, the second scan is performed along the same direction or the opposite direction.

[0040] In some embodiments, after the first scan, the intensity (contrast) of the secondary electrons of the line pattern is obtained (and stored if necessary), and compared with each other to find one or more lines having different intensities. In other embodiments, after the first scan and the second scan, the intensity (contrast) of the secondary electrons of the line pattern is obtained, and compared with each other to find one or more lines having different intensities. In some embodiments, the second (or first) scan is not necessary for finding only the bridging defect, but the second (or first) scan can find the cutting (breaking) defect in the 2nth line pattern.

[0041] In other embodiments, as Figure 4B shown, the multiple line patterns include a first group (the first, third,..., and the (2n - 1)th line patterns) and a second group (the second, fourth,..., and the 2nth line patterns) arranged with an offset along the Y direction. The offset is adjusted such that the scanning area of the first group does not overlap with any line pattern of the second group.

[0042] In some embodiments, the scanning for each of the first group and the second group is performed one or more times. In some embodiments, after the scanning for the first group, the intensities (contrasts) of the secondary electrons of the line patterns in the first group are obtained (and stored if necessary) and compared with each other to find one or more lines having different intensities. In other embodiments, after the scanning for the first group and the scanning for the second group, the intensities (contrasts) of the secondary electrons of the line patterns in the first group and the second group are obtained and compared with each other to find one or more lines having different intensities. In some embodiments, the scanning for one of the first group and the second group is not necessary for finding only bridging defects, but the scanning for both groups can find cut (break) defects in any line pattern.

[0043] Figure 5A and Figure 5B shows a defect inspection pattern for electron beam defect inspection according to an embodiment of the present disclosure.

[0044] In some embodiments, as Figure 5A shown, a plurality of defect inspection patterns 100 are arranged in a matrix in one PCM region. Compared with the case of placing a large defect inspection pattern in one PCM, by arranging a plurality of defect inspection patterns 100, it is easier to find and observe defects.

[0045] In some embodiments, as Figure 5B shown, some of the defect inspection patterns 100 have different orientations from other defect inspection patterns 100. In other words, the extending directions of the plurality of line patterns in the defect inspection patterns are different between the defect inspection patterns. In some embodiments, some of the defect inspection patterns 100 are arranged to be rotated 90 degrees relative to other defect inspection patterns 100. In some embodiments, the rotation is 45 degrees or any other suitable angle.

[0046] Figure 6A and Figure 6B shows a defect inspection pattern for electron beam defect inspection according to an embodiment of the present disclosure.

[0047] In some embodiments, the PCM includes a plurality of defect inspection patterns 100 having different sizes. In some embodiments, as Figure 6A shown, the pitch of the plurality of line patterns 10 is different between the plurality of defect inspection patterns 100, 101, and 102. In some embodiments, the pattern pitch in the defect inspection pattern 101 is smaller than the pattern pitch in the defect inspection pattern 100, and in other embodiments, the pattern pitch in the defect inspection pattern 102 is larger than the pattern pitch in the defect inspection pattern 100, as Figure 6A shown. In some embodiments, as Figure 6BAs shown, between the multiple defect inspection patterns 100, 103, and 105, the line widths of the multiple line patterns 10 are different. In some embodiments, the line width in the defect inspection pattern 103 is less than the line width in the defect inspection pattern 100, and in other embodiments, the line width in the defect inspection pattern 105 is greater than the line width in the defect inspection pattern 100, as Figure 6B shown. In some embodiments, the pitch of the multiple line patterns in the defect inspection patterns 100, 103, and 105 is the same, and in other embodiments, the pitch is different, similar to Figure 6A . By adopting various sizes in the defect inspection patterns, the size of the defect can be estimated.

[0048] Figure 7 is a flowchart showing a defect inspection operation according to an embodiment of the present disclosure. In some embodiments, at S101, one or more defect inspection patterns 100 are formed over the insulating layer 30, and each defect inspection pattern 100 includes multiple wire patterns 10, for example, as Figure 1C shown. In some embodiments, the insulating layer 30 is disposed over a semiconductor wafer or substrate 15. In some embodiments, the defect inspection pattern 100 is formed on an insulating substrate, such as a glass or quartz substrate for a photomask or a flat panel display. In other embodiments, the multiple wire patterns 10 are embedded patterns formed in the insulating layer 30 by, for example, a CMP process, for example, as Figure 1D shown. In some embodiments, the wafer or substrate 15 is a test or monitoring wafer not used for manufacturing an electronic device as a final product. In other embodiments, the defect inspection pattern 100 is formed on a PCM region over a wafer or substrate used for manufacturing an electronic device as a final product. In some embodiments, after the patterning operation, a cleaning operation is performed to remove the insulating material from the multiple wire patterns.

[0049] In S102, the wafer or substrate 15 having one or more defect inspection patterns 100 is loaded into an electron beam inspection tool. Then, as described above, each defect inspection pattern 100 is partially or locally scanned using an electron beam.

[0050] In S103, the inspection tool searches for one or more line patterns having secondary electron signals different from other line patterns. When one or more line patterns having different secondary electron signals are found, at S104, the found (one or more) line patterns are searched to locate and observe the defects. In some embodiments, the search for and observation of the defects are performed fully automatically by the inspection tool or another observation tool, and in other embodiments, part of the search for and observation of the defects is performed manually by an operator. When no line pattern having a different secondary electron signal is found at S103, at S105, the inspection tool moves to the next defect inspection pattern and scans the next defect inspection pattern. In some embodiments, the inspection tool sequentially scans a plurality of defect line patterns and obtains (and stores in a memory) defect information, and then the observation process is performed by the inspection tool or another observation tool.

[0051] Figure 8 is a flowchart showing defect inspection and apparatus maintenance operations according to embodiments of the present disclosure.

[0052] In some embodiments, at S201, a conductive layer is formed on the insulating layer by using a film forming apparatus. In some embodiments, the film forming apparatus is a PVD apparatus, a CVD apparatus, an ALD apparatus, or an electroplating apparatus, or any other apparatus suitable for forming a conductive film. In some embodiments, the insulating layer is a silicon oxide layer formed on a silicon wafer by thermal oxidation or a CVD method. In other embodiments, the insulating layer is directly formed on an insulating substrate. In some embodiments, the wafer or substrate is a test or monitoring wafer not used for manufacturing an electronic device as a final product. In other embodiments, the defect inspection pattern is formed on a PCM region on a wafer or substrate used for manufacturing an electronic device as a final product.

[0053] In some embodiments, the film forming apparatus for the conductive layer and the formed conductive layer are subjected to defect inspection and maintenance operations. In other embodiments, the film forming apparatus for the insulating layer and the insulating layer are also subjected to defect inspection and maintenance operations. The insulating layer subjected to defect inspection is any insulating layer used in semiconductor manufacturing operations, including but not limited to silicon oxynitride, silicon nitride, silicon carbide, silicon carbon oxide, silicon carbon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, ferroelectric materials, or low-k (dielectric constant) materials. In some embodiments, the insulating layer is formed by using a PVD apparatus, a CVD apparatus, or an ALD apparatus.

[0054] At S202, a photoresist pattern is formed over the conductive material layer by using a lithography apparatus. The lithography apparatus includes a resist coating apparatus, an exposure apparatus, and a developing apparatus. In some embodiments, the coating apparatus and the developing apparatus are integrated. In some embodiments, the exposure apparatus includes a UV lithography apparatus, a DUV lithography apparatus, an EUV lithography apparatus, or an electron beam apparatus.

[0055] By using the resist pattern as an etching mask, at S203, the conductive material layer is patterned into one or more defect inspection patterns by using an etching apparatus. In other embodiments, one or more hard mask layers are formed over the conductive material layer by using a film forming apparatus, and the hard mask layer is patterned by using the resist pattern as an etching mask in an etching apparatus, and then the conductive material layer is patterned by using the patterned hard mask layer as an etching mask in the same or another etching apparatus. In some embodiments, the hard mask pattern is removed, and in other embodiments, the hard mask pattern remains over the plurality of line patterns made of the conductive material. In some embodiments, one or more of the film forming apparatus, the lithography apparatus, and the etching apparatus are subjected to defect inspection and maintenance operations.

[0056] In other embodiments, the plurality of wire patterns 10 are embedded patterns in the insulating layer 30, as Figure 1D shown. In some embodiments, the insulating layer 30 is formed by using a film forming apparatus. Then, the insulating layer is patterned into a plurality of grooves separated from each other by using an etching apparatus. Further, one or more conductive layers are formed over the wafer or substrate by using a film forming apparatus. Then, a CMP operation is performed by using a CMP apparatus to form Figure 1D the structure shown. In other embodiments, the etching apparatus is used for an etch-back operation. One or more of the film forming apparatus, the lithography apparatus, the etching apparatus, and the CMP apparatus are subjected to defect inspection and maintenance operations.

[0057] In S204, the wafer or substrate having one or more defect inspection patterns is loaded into an electron beam inspection tool. Then, as described above, each defect inspection pattern is partially or locally scanned with an electron beam to find one or more defects. The defect inspection operation is similar to the defect inspection operation explained with respect to Figure 7 or any other embodiment described above.

[0058] In S205, it is determined whether no defects are found in all the defect inspection patterns, or whether the found defect(s) is / are within the standards. The standards include the total number of defects, the type of defect (layer or material), the size of the defect, and / or the location of the defect, or any other defect information that helps to determine whether any manufacturing apparatus needs a maintenance operation.

[0059] If no defects are found in the inspection pattern for all defects, or the defect(s) found are within the standard (at S205, "Yes"), then one or more of a film forming apparatus, a lithography apparatus, and an etching apparatus (and a CMP apparatus) are used to perform semiconductor manufacturing operations.

[0060] If the inspection result exceeds the standard (at S205, "No"), then at S207, a maintenance operation is performed on one or more of a film forming apparatus, a lithography apparatus, and an etching apparatus (and a CMP apparatus). The target apparatus for maintenance is determined based on the total number of defects, the type of defect (layer or material), the size of the defect, and / or the location of the defect.

[0061] The foregoing inspection and / or maintenance operations can be applied to photomask manufacturing operations and / or flat panel display manufacturing operations. In the case of a photomask, the conductive layer is a Cr-based material (Cr, CrN), a Mo / Si-based material (Mo / Si multilayer), a Ru-based material (Ru), a Ta-based material (TaB, TaBN), or any other conductive material for a photomask.

[0062] In some embodiments, a resist pattern of a plurality of line patterns is subjected to defect inspection. In this case, in some embodiments, the resist pattern is made conductive by adding conductive material particles.

[0063] In some embodiments, the plurality of line patterns in the defect inspection pattern are made of an insulating material different from the underlying layer. In this case, the underlying layer can be a conductive layer. In some embodiments, the conductive layer is electrically isolated or not grounded.

[0064] Figure 9A and Figure 9B FIG. shows a defect inspection system according to an embodiment of the present disclosure.

[0065] Figure 9A is a schematic diagram of a computer system that performs defect inspection and data processing according to one or more embodiments as described above. The foregoing processes, methods, and / or operations of the embodiments can be implemented using computer hardware and computer programs executed thereon. In Figure 9A FIG., a defect inspection tool 1000 using an electron beam is communicatively coupled to a computer system 900. The computer system 900 is equipped with a computer 901 (including a compact disc read-only memory (e.g., CD-ROM or DVD-ROM) drive 905 and a disk drive 906), a keyboard 902, a mouse 903, and a monitor 904. In some embodiments, the computer system 900 is part of the defect inspection tool 1000. In some embodiments, an observation tool 1100 is provided separately from the inspection tool 1000 and is communicatively coupled to the computer system 900.

[0066] Figure 9B It is a diagram showing the internal configuration of the computer system 900. In 9B, in addition to the optical disk drive 905 and the magnetic disk drive 906, the computer 901 is also equipped with one or more processors 911 (e.g., microprocessing unit (MPU)), ROM 912 (in which programs such as a startup program are stored), random access memory (RAM) 913 (which is connected to the MPU 911 and in which commands of application programs are temporarily stored and provides a temporary storage area), a hard disk 914 (in which application programs, system programs, and data are stored), and a bus 915 (which connects the MPU 911, ROM 912, etc.). Note that the computer 901 may include a network card (not shown) for providing a connection to a LAN.

[0067] The program for causing the computer system 900 to execute the functions of the defect inspection and analysis device in the foregoing embodiments can be stored in the optical disk 921 or the magnetic disk 922 (the optical disk 921 or the magnetic disk 922 is inserted into the optical disk drive 905 or the hard disk drive 906), and transmitted to the hard disk 914. Alternatively, the program can be transmitted to the computer 901 via a network (not shown) and stored in the hard disk 914. When executed, the program is loaded into the RAM 913. The program can be loaded from the optical disk 921 or the magnetic disk 922 or directly from the network.

[0068] The program does not necessarily have to include, for example, an operating system (OS) or a third-party program for causing the computer 901 to execute the functions of the defect inspection and analysis device in the foregoing embodiments. The program can only include a command part for calling appropriate functions (modules) in a controlled mode and obtaining the required results.

[0069] According to an embodiment of the present disclosure, only a part of the defect inspection pattern is scanned with an electron beam to find defects. Therefore, the inspection time using an electron beam-based inspection tool can be greatly reduced. In some embodiments, the inspection speed is about 30 to 50 times the inspection speed when scanning the entire area of the defect inspection pattern. In addition, compared with the voltage contrast inspection (VCI) that requires grounding the conductive pattern, the structure of the test or monitoring wafer is simpler in this embodiment. Further, the method according to the embodiment of the present disclosure increases the defect detection rate compared with the optical inspection of fine pitch patterns.

[0070] It will be understood that not all advantages must be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0071] According to one aspect of the present disclosure, in a method for inspecting pattern defects, a plurality of patterns are formed on a substrate. The plurality of patterns are electrically isolated from each other. A portion of the plurality of patterns is scanned with an electron beam to charge the plurality of patterns. The intensity of secondary electrons emitted from the scanned portion of the plurality of patterns is obtained. One or more patterns among the plurality of patterns that exhibit an intensity of secondary electrons different from that of other patterns among the plurality of patterns are searched for. In one or more of the foregoing and following embodiments, the plurality of patterns include line and space patterns having a plurality of line patterns spaced apart from each other. In one or more of the foregoing and following embodiments, the plurality of line patterns are conductive. In one or more of the foregoing and following embodiments, the substrate is insulating. In one or more of the foregoing and following embodiments, the plurality of line patterns are more conductive than the substrate. In one or more of the foregoing and following embodiments, the plurality of patterns include a defect as a broken line pattern, and during scanning of a portion of the plurality of patterns, the electron beam does not scan the defect. In one or more of the foregoing and following embodiments, the plurality of patterns include a defect as a bridge between adjacent line patterns, and during scanning of a portion of the plurality of patterns, the electron beam does not scan the defect. In one or more of the foregoing and following embodiments, when the overall length of each line pattern among the plurality of line patterns is A1, the length A2 in the direction extending along the plurality of line patterns of a portion of the plurality of patterns is in the range of 1% to 20% of A1. In one or more of the foregoing and following embodiments, when one pattern among the plurality of patterns that exhibits an intensity of secondary electrons different from that of other patterns among the plurality of patterns is found, the position of the one pattern among the plurality of patterns is obtained. In one or more of the foregoing and following embodiments, the one pattern at the obtained position among the plurality of patterns is observed along the direction of the plurality of line patterns to find a defect.

[0072] According to another aspect of the present disclosure, in a method for inspecting pattern defects, multiple sets of multiple patterns are formed over a bottom layer. The multiple patterns are electrically isolated from each other. A portion of the first set of multiple patterns is scanned with an electron beam to find defects. The intensity of secondary electrons emitted from the scanned portion of the first set of multiple patterns is obtained. One or more patterns in the first set of multiple patterns that exhibit different intensities of secondary electrons from other patterns in the first set of multiple patterns are searched for. When one pattern in the multiple patterns that exhibits different intensities of secondary electrons from other patterns in the multiple patterns is found, the position of the one pattern in the multiple patterns is obtained. A portion of the second set of multiple patterns is scanned with an electron beam to find defects. In one or more of the foregoing and following embodiments, the multiple patterns are conductive and the bottom layer is insulating. In one or more of the foregoing and following embodiments, the multiple patterns in each of the multiple sets include line and space patterns having a plurality of line patterns spaced apart from each other. In one or more of the foregoing and following embodiments, at least one of the pattern width, pattern pitch, or pattern direction of the multiple line patterns in the first set is different from the corresponding one of the pattern width, pattern pitch, or pattern direction of the multiple line patterns in the second set. In one or more of the foregoing and following embodiments, the electron beam scans only a portion of each pattern in the first set of multiple patterns. In one or more of the foregoing and following embodiments, the bottom layer is disposed over a semiconductor wafer, and the semiconductor wafer is a test wafer on which no pattern that is or will be part of a transistor is formed. In one or more of the foregoing and following embodiments, when the overall length of each line pattern in the multiple line patterns is A1, the length A2 in the direction extending along the multiple line patterns of a portion of the multiple patterns is in the range of 1% to 10% of A1.

[0073] According to another aspect of the present disclosure, in a method, a conductive layer is formed over an insulating layer by using a film forming device. A resist pattern is formed over the conductive layer by using a lithography device. The conductive layer is patterned into a plurality of conductive patterns by using an etching device. The plurality of conductive patterns are electrically isolated from each other. Pattern defects are searched for by the following operations. A part of the plurality of patterns is scanned with an electron beam to charge the plurality of conductive patterns. The intensity of secondary electrons emitted from the scanned part of the plurality of conductive patterns is obtained. One or more conductive patterns among the plurality of patterns showing different intensities of secondary electrons from other conductive patterns among the plurality of conductive patterns are searched for. When a defect is found, a maintenance operation is performed on at least one of the film forming device, the lithography device, and the etching device. In one or more of the foregoing and following embodiments, the defect is observed, and based on the observation, which one of the film forming device, the lithography device, and the etching device is to be subjected to the maintenance operation is determined. In one or more of the foregoing and following embodiments, when no defect is found, a semiconductor manufacturing operation using the film forming device, the lithography device, and the etching device is performed. In one or more of the foregoing and following embodiments, the conductive layer includes one or more layers of Ti, Ta, W, Co, Ni, Mo, Cu, Al, Ru, their alloys, and semiconductor materials.

[0074] According to another aspect of the present disclosure, a test device for detecting defects includes: a bottom layer disposed over a substrate; and a plurality of line patterns disposed over the bottom layer and electrically isolated from each other. The plurality of line patterns are more conductive than the bottom layer, and the plurality of line patterns include at least one of a defect as a broken line pattern or a defect as a bridge between adjacent line patterns. In one or more of the foregoing and following embodiments, the plurality of line patterns include a first set of line patterns and a second set of line patterns, and at least one of a pattern width, a pattern pitch, or a pattern direction is different between the first set and the second set. In one or more of the foregoing and following embodiments, the substrate and the bottom layer do not include patterns. In one or more of the foregoing and following embodiments, the plurality of line patterns include a first set of line patterns and a second set of line patterns, the line patterns in the first set and the line patterns in the second set are alternately arranged along a first direction, and the first set and the second set are offset from each other along a second direction intersecting the first direction.

[0075] The foregoing outlines the features of several embodiments or examples, so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and they can be variously changed, substituted, and altered without departing from the spirit and scope of the present disclosure.

[0076] Example 1. A method for inspecting pattern defects, the method comprising: forming a plurality of patterns on a bottom layer, the plurality of patterns being electrically isolated from each other; scanning a portion of the plurality of patterns with an electron beam to charge the plurality of patterns; obtaining intensities of secondary electrons emitted from the scanned portion of the plurality of patterns; and searching for one or more patterns among the plurality of patterns that exhibit intensities of secondary electrons different from those of other patterns among the plurality of patterns.

[0077] Example 2. The method according to Example 1, wherein the plurality of patterns include line and space patterns, and the line and space patterns have a plurality of line patterns arranged spaced apart from each other.

[0078] Example 3. The method according to Example 2, wherein the plurality of line patterns are conductive and the bottom layer is insulating.

[0079] Example 4. The method according to Example 2, wherein the plurality of line patterns are more conductive than the bottom layer.

[0080] Example 5. The method according to Example 2, wherein: the plurality of patterns include a defect, which is a broken line pattern, and during scanning of the portion of the plurality of patterns, the electron beam does not scan the defect.

[0081] Example 6. The method according to Example 2, wherein: the plurality of patterns include a defect, which is a bridging of adjacent line patterns, and during scanning of the portion of the plurality of patterns, the electron beam does not scan the defect.

[0082] Example 7. The method according to Example 2, wherein when the overall length of each line pattern among the plurality of line patterns is A1, the length A2 of the portion of the plurality of patterns extending in the direction of the plurality of line patterns is in the range of 1% to 20% of A1.

[0083] Example 8. The method according to Example 1, further comprising: when finding one pattern among the plurality of patterns that exhibits intensities of secondary electrons different from those of other patterns among the plurality of patterns, obtaining the position of the one pattern among the plurality of patterns.

[0084] Example 9. The method according to Example 8, further comprising: observing the one pattern with the obtained position among the plurality of patterns along the direction in which the plurality of line patterns extend to find a defect.

[0085] Example 10. A method for inspecting pattern defects, the method comprising: forming multiple sets of multiple patterns on a bottom layer, the multiple patterns being electrically isolated from each other; scanning a portion of the first set of multiple patterns with an electron beam to find a defect; obtaining an intensity of secondary electrons emitted from the scanned portion of the first set of multiple patterns; searching for one or more patterns among the multiple patterns in the first set that exhibit an intensity of secondary electrons different from that of other patterns in the first set of multiple patterns; when finding a pattern among the multiple patterns that exhibits an intensity of secondary electrons different from that of other patterns among the multiple patterns, obtaining a position of the one pattern among the multiple patterns; and scanning a portion of a second set of multiple patterns with the electron beam to find a defect.

[0086] Example 11. The method according to Example 10, wherein the multiple patterns are conductive and the bottom layer is insulating.

[0087] Example 12. The method according to Example 10, wherein the multiple patterns in each set of the multiple sets include line and space patterns, and the line and space patterns have multiple line patterns arranged spaced apart from each other.

[0088] Example 13. The method according to Example 12, wherein at least one of a pattern width, a pattern pitch, or a pattern direction of the multiple line patterns in the first set is different from a corresponding one of a pattern width, a pattern pitch, or a pattern direction of the multiple line patterns in the second set.

[0089] Example 14. The method according to Example 10, wherein the electron beam scans only a portion of each pattern among the multiple patterns in the first set.

[0090] Example 15. The method according to Example 10, wherein the bottom layer is disposed on a semiconductor wafer, and the semiconductor wafer is a test wafer on which no pattern that is or will be part of a transistor is formed.

[0091] Example 16. The method according to Example 12, wherein when an overall length of each line pattern among the multiple line patterns is A1, a length A2 of the portion of the multiple patterns extending in a direction of the multiple line patterns is in a range of 1% to 10% of A1.

[0092] Example 17. A test device for detecting defects, comprising: a bottom layer disposed on a substrate; multiple line patterns disposed on the bottom layer and electrically isolated from each other, wherein the multiple line patterns are more conductive than the bottom layer, and the multiple line patterns include at least one of a defect as a broken line pattern or a defect as a bridge between adjacent line patterns.

[0093] Example 18. The test device according to Example 17, wherein the plurality of line patterns includes a first set of line patterns and a second set of line patterns, and at least one of a pattern width, a pattern pitch, or a pattern orientation is different between the first set and the second set.

[0094] Example 19. The test device according to Example 17, wherein the substrate and the underlying layer do not include patterns.

[0095] Example 20. The test device according to Example 17, wherein: the plurality of line patterns includes a first set of line patterns and a second set of line patterns, the line patterns in the first set and the line patterns in the second set are alternately arranged along a first direction, and the first set and the second set are offset from each other along a second direction intersecting the first direction.

Claims

1. A method for inspecting pattern defects, the method comprising: forming a plurality of patterns on a substrate, the plurality of patterns being electrically isolated from each other; scanning a portion of the plurality of patterns with an electron beam to charge the plurality of patterns; obtaining the intensity of secondary electrons emitted from the scanned portion of the plurality of patterns; and searching for one or more patterns among the plurality of patterns that exhibit an intensity of secondary electrons different from that of other patterns among the plurality of patterns; wherein the plurality of patterns include line and space patterns, the line and space patterns having a plurality of line patterns spaced apart from each other, when the overall length of each line pattern among the plurality of line patterns is A1, the length A2 of the portion of the plurality of patterns along the direction in which the plurality of line patterns extend is in the range of 1% to 20% of A1, during the scanning of the portion of the plurality of patterns, the electron beam does not scan the defects of the plurality of patterns.

2. The method according to claim 1, wherein The plurality of line patterns are conductive, and the substrate is insulating.

3. The method according to claim 1, wherein The plurality of line patterns are more conductive than the substrate.

4. The method according to claim 1, wherein: the defect is a broken line pattern, and during the scanning of the portion of the plurality of patterns, the electron beam does not scan the defect.

5. The method according to claim 1, wherein: the defect is a bridging of adjacent line patterns, and during the scanning of the portion of the plurality of patterns, the electron beam does not scan the defect.

6. The method according to claim 1 further comprises: When one pattern among the plurality of patterns that exhibits an intensity of secondary electrons different from that of other patterns among the plurality of patterns is found, obtaining the position of the one pattern among the plurality of patterns.

7. The method according to claim 6, further comprising: Observing the one pattern at the obtained position among the plurality of patterns along the direction in which the plurality of line patterns extend to find the defect.

8. A method for inspecting pattern defects, the method comprising: forming multiple sets of a plurality of patterns on a substrate, the plurality of patterns in each set being electrically isolated from each other; scanning a portion of a first set of the plurality of patterns with an electron beam to find a defect; obtaining the intensity of secondary electrons emitted from the scanned portion of the first set of the plurality of patterns; searching for one or more patterns among the plurality of patterns in the first set that exhibit an intensity of secondary electrons different from that of other patterns among the plurality of patterns in the first set; when one pattern among the plurality of patterns that exhibits an intensity of secondary electrons different from that of other patterns among the plurality of patterns is found, obtaining the position of the one pattern among the plurality of patterns; and scanning a portion of a second set of the plurality of patterns with the electron beam to find a defect; wherein the plurality of patterns in each of the multiple sets include line and space patterns, the line and space patterns having a plurality of line patterns spaced apart from each other, when the overall length of each line pattern among the plurality of line patterns is A1, the length A2 of the portion of the plurality of patterns along the direction in which the plurality of line patterns extend is in the range of 1% to 20% of A1, during the scanning of the portion of the first set of the plurality of patterns, the electron beam does not scan the defect.

9. The method according to claim 8, wherein The plurality of patterns are conductive, and the substrate is insulating.

10. The method according to claim 8, wherein At least one of a pattern width, a pattern pitch, or a pattern direction of a plurality of line patterns in the first group is different from a corresponding one of a pattern width, a pattern pitch, or a pattern direction of a plurality of line patterns in the second group.

11. The method according to claim 8, wherein, The electron beam scans only a part of each of the plurality of patterns in the first group.

12. The method according to claim 8, wherein, The underlying layer is disposed over a semiconductor wafer, and the semiconductor wafer is a test wafer on which no pattern that is or will be part of a transistor is formed.

13. The method according to claim 8, wherein, A2 is in the range of 1% to 10% of A1.

14. A test device for detecting a defect, comprising: An underlying layer disposed over a substrate; A plurality of line patterns disposed over the underlying layer and electrically isolated from each other, wherein the plurality of line patterns are more conductive than the underlying layer, and the plurality of line patterns include at least one of a defect as a broken line pattern or a defect as a bridge between adjacent line patterns, wherein a part of the plurality of line patterns is a scanning part, and when an overall length of each line pattern in the plurality of line patterns is A1, a length A2 of the scanning part along a direction in which the plurality of line patterns extend is in the range of 1% to 20% of A1, and the scanning part does not include the defect.

15. The test device according to claim 14, wherein, The plurality of line patterns include a first group of line patterns and a second group of line patterns, and at least one of a pattern width, a pattern pitch, or a pattern direction is different between the first group and the second group.

16. The test device according to claim 14, wherein, The substrate and the underlying layer do not include a pattern.

17. The test device according to claim 14, wherein: The plurality of line patterns include a first group of line patterns and a second group of line patterns, the line patterns in the first group and the line patterns in the second group are alternately arranged along a first direction, and the first group and the second group are offset from each other along a second direction intersecting the first direction.

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