Interconnect layer and method of manufacturing the same

Abstract

The present disclosure relates to interconnect layers and methods for making the same. The present disclosure describes a method for planarizing a ruthenium metal layer in a conductive structure. The method includes forming a first conductive structure on a second conductive structure, wherein forming the first conductive structure includes forming an opening in a dielectric layer disposed on the second conductive structure, and depositing ruthenium metal in the opening to overfill the opening. Forming the first conductive structure includes doping ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

Description

Technical Field

[0001] The present disclosure relates to interconnect layers and methods of making the same. Background Art

[0002] Chemical mechanical polishing or planarization (CMP) is a process that uses a combination of chemical and mechanical forces to smooth and planarize a surface. CMP uses an abrasive chemical slurry in conjunction with a polishing pad and retaining ring. In semiconductor manufacturing, CMP is used to planarize and polish different types of materials (e.g., dielectrics, metals, and semiconductors) with crystalline, polycrystalline, or amorphous microstructures. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for manufacturing an interconnection layer is provided, comprising: forming a first interconnection layer on a substrate, wherein forming the first interconnection layer comprises: forming an opening in a dielectric layer disposed on the substrate; depositing a ruthenium metal lining in the opening; depositing copper metal on the ruthenium metal lining to fill the opening; polishing the copper metal; doping the ruthenium metal lining; and polishing the doped ruthenium metal lining to form a conductive structure in the first interconnection layer; and forming a second interconnection layer on the first interconnection layer.

[0004] According to another embodiment of the present disclosure, a method for manufacturing an interconnection layer is provided, comprising: forming a first conductive structure on a second conductive structure, wherein forming the first conductive structure comprises: forming an opening in a dielectric layer disposed on the second conductive structure; depositing ruthenium metal in the opening to overfill the opening; doping the ruthenium metal; and polishing the doped ruthenium metal to form the first conductive structure; and forming an interconnection layer on the first conductive structure.

[0005] According to another embodiment of the present disclosure, an interconnect layer is provided, comprising: a dielectric layer, the dielectric layer being located on a substrate; a conductive structure, the conductive structure being located in the dielectric layer, wherein the conductive structure comprises: a first conductive material; and a ruthenium liner, the ruthenium liner surrounding a sidewall and a bottom surface of the first conductive material, wherein a top surface of the ruthenium liner and a top surface of the first conductive material are coplanar; and wherein the dielectric layer comprises a dopant concentration equal to or greater than 1×10 12 Atom / cm 3 of dopants. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 is a cross-sectional view of a metallization layer opening according to some embodiments.

[0008] Figure 2 is a flow chart of a method describing various operations for forming conductive structures in an interconnect layer, according to some embodiments.

[0009] Figure 3-Figure 8 is a cross-sectional view of an intermediate structure during formation of a conductive structure in an interconnect layer according to some embodiments.

[0010] Fig. 9 is a cross-sectional view having a conductive structure thereon according to some embodiments.

[0011] Fig.10 is a flow chart of a method describing various operations for forming a conductive structure, according to some embodiments.

[0012] Figure 11-Figure 15 is a cross-sectional view of an intermediate structure during formation of a conductive structure according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be set between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] As used herein, the term "nominal" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to minor variations in manufacturing processes and / or tolerances.

[0016] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of a value interpreted by a person skilled in the relevant art(s) in accordance with the teachings herein.

[0017] Ruthenium metal can be used as a filling material for conductive structures in the middle of the line (MEOL) process and as a diffusion barrier / seed layer for copper interconnects in the back end of the line (BEOL) process. This is because ruthenium metal exhibits low bulk resistivity (e.g., about 7.7 μΩ·cm) and sufficient corrosion resistance to copper plating chemicals.

[0018] Integration of ruthenium in semiconductor manufacturing has its challenges. For example, chemically resistant ruthenium is difficult to planarize (e.g., exhibits low polishing rates) with existing chemical mechanical polishing (CMP) slurries (e.g., CMP slurries used for other metals (e.g., copper, aluminum, tungsten, cobalt, etc.) in semiconductor manufacturing). Therefore, other CMP slurries have been developed for ruthenium planarization processes. These other CMP slurries require strong oxidants (e.g., cerium ammonium nitrate ((NH 4 ) 2 Ce(NO 3 ) 6 ), sodium periodate (NaIO 4 ), potassium periodate (KIO 4 ), potassium permanganate (KMnO 4 )), and longer polishing times to remove the ruthenium metal layer. Long polishing times and strong oxidants can damage surrounding materials. For example, strong oxidants can cause copper electrocorrosion—e.g., an electrochemical process in which one metal (e.g., copper) preferentially corrodes when in electrical contact with another metal (e.g., ruthenium) in the presence of an electrolyte (e.g., CMP slurry). In addition, the pH of the slurry used for ruthenium polishing needs to be controlled between about 8.4 and about 10 to prevent ruthenium tetroxide (RuO 4 ) is formed, the ruthenium tetraoxide (RuO 4 ) is a toxic byproduct of the chemical reaction between ruthenium metal and CMP slurry.

[0019] To address the above shortcomings, embodiments described herein are directed to an ion implantation method configured to increase the polishing rate of ruthenium metal for a CMP slurry (e.g., the CMP slurry described above) and reduce or minimize the ruthenium polishing time. As described above, the reduced ruthenium polishing time is beneficial to the surrounding materials. In some embodiments, the implantation method includes an implant having an implantation energy between about 0.3 keV and about 50 keV and an incident angle between 0° and about 80°. In some embodiments, the dopant dose is between about 1×10 14 Dopant / cm 2 About 1×10 17 Dopant / cm 2 In some embodiments, the doped ruthenium layer is removed during a subsequent CMP process after the implantation process. According to some embodiments, the polishing rate achieved by the doped ruthenium layer is about 1.1 to about 1.7 times the polishing rate of the undoped ruthenium layer. This is because the dopant causes defects in the ruthenium metal. The doped ruthenium metal oxidizes faster during the ruthenium CMP process and is therefore polished faster. In some embodiments, the implantation process parameters that adjust the polishing rate of the ruthenium layer during the CMP process include the type of dopant, the dopant dose, the implantation energy, and the incident angle at which the dopant impacts the ruthenium metal surface.

[0020] According to some embodiments, Figure 1 1 is a partial cross-sectional view of a partially fabricated interconnect layer 100 formed on a substrate 110. At this stage of fabrication, the interconnect layer 100 includes openings 120, 130, and 140 formed within a low-k dielectric 150 disposed on the semiconductor substrate 110. In subsequent operations, the openings 120, 130, and 140 will be filled with one or more conductive layers (including a ruthenium layer) to form various conductive structures for the interconnect layer 100. In some embodiments, Figure 1 is a precursor structure (eg, a starting structure) for the embodiments described herein.

[0021] By way of example and not limitation, substrate 110 may be a partially fabricated wafer having one or more layers formed thereon. Figure 1The one or more layers not shown in the figure may include, for example, front end of line (FEOL) structures (e.g., active devices, passive devices, doped regions, epitaxial structures, etc.) and local or global interconnect layers (e.g., MEOL metallization layers, BEOL metallization layers, or combinations of the foregoing). Thus, interconnect layer 100 may be the first BEOL layer in a stack of BEOL metallization layers disposed on substrate 110, or any BEOL in a stack of BEOL metallization layers. When formed, interconnect layer 100 will be electrically coupled to underlying metallization layers (e.g., MEOL and / or BEOL metallization layers) or devices of substrate 110. For example, conductive structures formed in openings 120 and 130 may contact corresponding conductive structures of underlying metallization layers (e.g., MEOL or BEOL metallization layers) included in substrate 110. The foregoing layers and features (not shown in the figure) included in substrate 110 may be electrically coupled to underlying metallization layers (e.g., MEOL and / or BEOL metallization layers). Figure 1 ) are within the spirit and scope of the present disclosure.

[0022] According to some embodiments, openings 120, 130, and 140 are formed, for example, by patterning low-k dielectric 150 (e.g., by using sequential photolithography and etching operations). By way of example and not limitation, openings 120 and 130 may require a double patterning process, while opening 140 may require a single patterning process. In some embodiments, low-k dielectric 150 includes a carbon-rich silicon oxide layer with or without pores, and the dielectric constant of low-k dielectric 150 is between about 2 and about 3. In some embodiments, low-k dielectric 150 includes a stack of dielectric layers, such as a low-k dielectric or another dielectric: (i) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon carbide with nitrogen doping; (ii) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon carbide with oxygen doping; (iii) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon nitride; or (iv) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon oxide.

[0023] Figure 2 is a method for forming an interconnect layer (e.g., Figure 1 100). More specifically, method 200 includes an implantation process configured to improve the polishing rate of a ruthenium metal layer deposited during the formation of the conductive structure in the interconnect layer. Other manufacturing operations may be performed between the various operations of method 200 and are omitted for clarity and ease of description only. These various operations are within the spirit and scope of the present disclosure. In addition, not all operations are required to perform the disclosure provided herein. Some operations may be performed simultaneously or in parallel. Figure 2 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. Figure 1 , Figure 3-Figure 8 Method 200 is described.

[0024] In reference Figure 2 , method 200 begins with operation 210 and a process of depositing a ruthenium metal liner in an opening formed in a dielectric layer of an interconnect layer. For example, the opening of operation 210 may correspond to the opening in Figure 1 The openings 120, 130 and 140 are shown formed in the low-k dielectric 150 of the interconnect layer 100. By way of example and not limitation, Figure 3 The interconnect layer 100 is shown after operation 210 and depositing a ruthenium metal liner 300 in the openings 120, 130, and 140. In some embodiments, the ruthenium metal liner 300 is blanket deposited on the interconnect layer 100 to cover the low-k dielectric 150 in the example Figure 3 The exposed surfaces in the areas inside and outside the openings 120, 130 and 140 are shown. In some embodiments, a ruthenium carbonyl precursor chemical (e.g., triruthenium dodecacarbonyl (Ru)) is used at a temperature below about 200° C. (e.g., about 180° C.). 3 (CO) 12 )), a ruthenium metal liner 300 is deposited by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some embodiments, the ruthenium metal liner 300 is deposited with a suitable thickness to serve as a barrier layer / seed layer for copper metal. For example, the thickness of the ruthenium metal liner 300 can be about to about in the range between.

[0025] In reference Figure 2 When the method 200 continues with operation 220 and a process of depositing copper metal on the ruthenium metal liner (e.g., ruthenium metal liner 300) to fill the openings (e.g., openings 120, 130, and 140) of the interconnect layer (e.g., interconnect layer 100). In some embodiments, Figure 4 The interconnect layer 100 is shown after operation 220, in which copper metal 400 is deposited on the ruthenium metal liner 300 and substantially fills the Figure 3 The openings 120, 130 and 140 are shown. In some embodiments, the copper metal 400 is grown directly on the ruthenium metal liner 300 by a suitable method (e.g., by electroplating). According to some embodiments, as Figure 4 As shown, copper metal 400 extends over the top surface of low-k dielectric 150 and forms an overburden 410 that will be subsequently removed (eg, polished) by a copper CMP process.

[0026] In reference Figure 2, method 200 continues with operation 230 and the process of polishing copper metal 410 using a copper CMP process. Figure 4 , the copper CMP process 420 removes the copper capping layer 410 according to operation 230. In some embodiments, for the reasons described above, the copper CMP process 420 cannot remove the ruthenium metal liner 300 from the top surface of the low-k dielectric 150. For example, the copper CMP process 420 polishes the copper metal 400 at a higher rate than the ruthenium metal liner 300. Therefore, after the copper CMP process 420, the ruthenium metal liner 300 appears "raised" relative to the top surface of the copper metal 400, such as Figure 5 In some embodiments, if the copper CMP process 420 is allowed to proceed to remove the ruthenium metal liner 300, the copper CMP process 420 will cause excessive copper dishing, for example, the copper CMP process 420 will cause the top surface of the copper metal 400 to be further recessed compared to the surrounding materials (e.g., the ruthenium metal layer 300 and the low-k dielectric 150).

[0027] In reference Figure 2 When the method 200 is performed, operation 240 and a process of doping the ruthenium metal liner 300 using an implantation process. In some embodiments, unlike an undoped ruthenium metal liner, the doped ruthenium metal liner 300 can be easily oxidized and subsequently removed (e.g., polished) from the top surface of the low-k dielectric 150 by a ruthenium CMP process. In some embodiments, the implantation process induces defects in the ruthenium metal, which accelerates the ruthenium oxidation rate during the CMP process.

[0028] During the implantation process of operation 240, as Figure 6 As shown, the ionized dopant 600 is accelerated toward the substrate 110 and strikes the top surface of the interconnect layer 100 at an incident angle θ. In some embodiments, the incident angle θ measured from a direction perpendicular to the substrate 110 (e.g., from the z direction) ranges from about 0° to about 80°. For example, in Figure 6 ionized dopant 600A strikes the top surface of interconnect layer 100 at a normal angle (e.g., incident angle θ equal to 0°), while ionized dopant 600B strikes the top surface of interconnect layer 100 at an incident angle of about 45°. In some embodiments, a small incident angle (e.g., close to 0°) allows ionized dopant 600 to penetrate deeper into low-k dielectric 150 than, for example, ionized dopant striking the top surface of the interconnect layer at a large incident angle (e.g., close to 80°). For example, under the same implantation conditions with respect to dopant type and dopant energy, as shown in FIG. Figure 6As shown, the implantation depth D1 of the ionized dopant 600A may be greater than the implantation depth D2 of the ionized dopant 600B (eg, D1>D2). In some embodiments, in operation 240, the incident angle θ is fixed for the duration of the implantation process.

[0029] In some embodiments, the implantation depth within the low-k dielectric 150 may be greater than the implantation depth in the ruthenium metal liner 300 and the copper metal 410. This is because the low-k dielectric 150 has a lower density than the ruthenium metal liner 300 and the copper metal 410. For example, the low-k dielectric 150 may be porous. In addition, the implantation process of operation 240 may damage the low-k dielectric 150. In some embodiments, the parameters of the implantation process (e.g., the incident angle θ) may be used to control the implantation depth and mitigate the damage caused by the dopant to the low-k dielectric 150. For example, a grazing incident angle θ (e.g., closer to about 80°) may be used to reduce the implantation depth in the low-k dielectric that is easily damaged during the implantation process of operation 240.

[0030] In addition to the incident angle θ, the implant depth can also be controlled by the implant energy of the ionized dopant 600, which can range from about 0.3 keV to about 50 keV. In some embodiments, for a fixed incident angle θ and the same dopant species, a high implant energy (e.g., close to about 50 keV) can result in a greater implant depth than a low implant energy (e.g., close to about 30 KeV). In some embodiments, the implant depth can be adjusted by the incident angle θ, the implant energy of the ionized dopant, or a combination of the foregoing to mitigate implant damage to the low-k dielectric 150. This ensures that the ruthenium metal liner 300 is removed during the ruthenium CMP process without damaging the underlying low-k dielectric 150.

[0031] In some embodiments, the unpolished portion of the ruthenium metal liner 300, the copper metal 400, and the low-k dielectric 150 may include equal to or greater than about 1×10 12 Atom / cm 3 For example, after the ruthenium CMP process, about 1×10 12 Atom / cm 3 or higher dopant concentration. In some embodiments, Figure 6 The shaded top portion of the ruthenium interconnect layer 100 shown represents an exemplary doped region formed by the implantation process of operation 240. In some embodiments, the doped region has a tail distribution toward its bottom surface, which can be detected in the unpolished portion as described above. In other words, Figure 6The bottom surface of the doped region shown may not be sharp, but may include a thickness equal to or greater than about 1×10 12 Atom / cm 3 The tail of the residual dopant concentration.

[0032] In some embodiments, the implantation process of operation 240 further includes a step of implanting a 14 Dopant / cm 2 About 1×10 17 Dopant / cm 2 . In some embodiments, the ionized dopant 600 includes, but is not limited to, C, B, P, O, Si, Ar, Ge, As, Xe, or any suitable dopant. In some embodiments, some dopant species may not be detected by SIMS. For example, SIMS may not be able to determine the concentration of O, Xe, or Ar in the low-k dielectric 150. According to some embodiments, the ionized dopant causes defects in the ruthenium metal liner 300, which accelerates the oxidation of the ruthenium metal liner 300 when the ruthenium metal liner 300 is exposed to a ruthenium CMP slurry. In some embodiments, the doped ruthenium metal oxidizes at a higher rate than the undoped ruthenium metal. In some embodiments, the polishing rate achieved by the doped ruthenium metal liner is about 1.1 to about 1.7 times the polishing rate of the undoped ruthenium metal liner.

[0033] In some embodiments, the CMP polishing rate of the ruthenium metal liner is adjusted by the following implantation process parameters: for example, the dopant species used (e.g., the atomic mass of the dopant species), implantation energy, incident angle, and dopant dose. The aforementioned implantation process parameters can control defects or "damage" to the ruthenium metal liner 300 caused by the dopant, and thus control the oxidation rate of the ruthenium metal liner 300 during the subsequent CMP process.

[0034] In some embodiments, the process parameters for the implantation process described in operation 240 are selected as follows. Initially, a dopant species is selected. Based on the atomic mass of the dopant species, an implantation energy and an angle of incidence θ are selected to achieve a desired implantation depth. Considerations for implantation depth include, but are not limited to, the material of the low-k dielectric 150 and its tolerance to implantation damage and the thickness of the ruthenium liner 300 to be polished. By way of example and not limitation, the implantation energy and angle of incidence θ may be provided by an implantation simulator software that uses the atomic mass of the dopant species and the implantation depth as input parameters. Once the dopant species, implantation energy, and angle of incidence θ are determined, a dopant dose is selected based on the desired amount of dopant to be implanted into the ruthenium liner 300.

[0035] In some embodiments, heavier dopants (e.g., having higher atomic mass, such as Xe and As) require lower dopant doses to achieve comparable ruthenium polishing rates than lighter dopants (e.g., having lower atomic mass, such as C and Ar). In some embodiments, the implant depth achieved with the heavier dopants may be different than the implant depth achieved with the lighter dopants. In some embodiments, implant energies less than about 0.3 keV and implant depths less than about 1×10 14 Dopant / cm 2 The dopant dose of 1×10 Å does not substantially increase the polishing rate of the ruthenium liner 300. On the other hand, an implantation energy greater than about 50 keV and an implantation energy greater than about 1×10 17 Dopant / cm 2 The dopant dose of 0.1 Å may damage the low-k dielectric 150 .

[0036] In reference Figure 2 When the method 200 continues with operation 250, and a process of polishing the doped ruthenium metal liner 300 using a ruthenium CMP process to form a conductive structure in the interconnect layer 100. Figure 7 When the doped Ruthenium metal liner 300 is implanted at a depth D, the Ruthenium CMP process 700 planarizes and removes the doped Ruthenium metal liner 300 (e.g., the top shaded portion of the interconnect layer 100). In some embodiments, the Ruthenium CMP process 700 removes the copper metal 400 and the low-k dielectric 150 at a substantially similar polishing rate as the doped Ruthenium metal liner 300 to achieve a planarized top surface topography of the interconnect layer 100, such as Figure 8 In some embodiments, and in reference Figure 7 and Figure 8 , the height H1 of the interconnect layer 100 before the ruthenium CMP process 700 is greater than the height H2 of the interconnect layer 100 after the ruthenium CMP process 700 (e.g., H1>H2). By way of example and not limitation, the difference between the heights H1 and H2 may be equal to, greater than, or less than Figure 7 The injection depth D is shown.

[0037] According to some embodiments, after the ruthenium CMP process 700, one or more interconnect layers ( Figure 8 Method 200 may be repeated for any additional interconnect layers that include a ruthenium metal liner and are formed on interconnect layer 100 .

[0038] In some embodiments, the implantation process of operation 240 in method 200 is not limited to BEOL interconnect layers having a ruthenium metal liner, such as interconnect layer 100. For example, the implantation process of operation 240 in method 200 can be used whenever planarization of ruthenium metal is required in a semiconductor manufacturing process. In some embodiments, the implantation process of operation 240 can be used to polish / planarize MEOL linerless conductive structures filled with ruthenium metal, such as Fig. 9 An unlined conductive structure 900 is shown.

[0039] According to some embodiments, Fig. 9 9 is a cross-sectional view of a structure having a conductive structure 900 formed on a cobalt conductive structure 905. In some embodiments, the conductive structure 900 is filled with a ruthenium metal 910. In some embodiments, the conductive structure 900 is a linerless conductive structure or a barrierless conductive structure filled with a ruthenium metal 910. Fig. 9 As shown, the cobalt conductive structure 905 is formed on a merged source / drain epitaxial structure 915 grown on a fin structure 920, which in turn are disposed on a substrate 925. In some embodiments, the fin structure 920 and the bottom portion of the source / drain epitaxial layer 915 are surrounded by a first dielectric layer 930, while the upper portion of the source / drain epitaxial layer 915 and the cobalt conductive structure 905 are surrounded by a second dielectric layer 935. In some embodiments, the first dielectric layer 930 forms an isolation structure, such as a shallow trench isolation (STI).

[0040] The top and middle portions of the conductive structure 900 (e.g., above the cobalt conductive structure 905) are surrounded by an etch stop layer 940 and an interlayer dielectric (ILD) 945. In contrast, the bottom portion of the conductive structure 900 (e.g., below the top surface of the cobalt conductive structure 905) is embedded in the cobalt conductive structure 905. The bottom portion of the conductive structure 900 (e.g., within the cobalt conductive structure 905) may or may not have an "anchor" 950 that prevents the ruthenium metal 910 from being "pulled out" during a ruthenium planarization process (e.g., during a ruthenium CMP process). The anchor 950 also increases the surface area between the ruthenium metal 910 and the cobalt conductive structure 905 to reduce the contact resistance between the two structures. In some embodiments, a silicide layer 955 is interposed between the cobalt conductive structure 905 and the source / drain epitaxial structure 915 to reduce the resistance between the cobalt conductive structure 905 and the source / drain epitaxial structure 915.

[0041] Fig. 9The structures shown are exemplary, and various variations are within the spirit and scope of the present disclosure. For example, each fin structure 920 may have its own source / drain epitaxial structure, rather than a single merged source / drain epitaxial structure 915. In addition, additional or fewer conductive structures 900 may be formed on the cobalt conductive structure 905. Additional or fewer fin structures 920 may also be formed on the substrate 925. In addition, Fig. 9 Selective parts of the structure are shown, and other parts are not shown for simplicity. For example, Fig. 9 Not shown are liner layers, barrier layers, or adhesion layers for the cobalt structure 905. In addition, not shown are the gate structures, spacer structures, doped regions, and capping layers formed on the fin structure 920 adjacent to the source / drain epitaxial structure 915 and the fin structure 920 along the x-direction.

[0042] In some embodiments, cobalt structure 905 is a source / drain contact on which conductive structure 900 is formed without an intervening layer such as a barrier layer, a liner layer, or an adhesion layer. In some embodiments, conductive structure 900 forms a network of vertical contacts that electrically connects cobalt structure 905 to an upper interconnect layer, such as Figure 8 The interconnect layer 100 is shown. According to some embodiments, the Figure 2 A similar process is shown for polishing the conductive structure 900 as used in operations 240 and 250 of the method 200 .

[0043] Fig.10 is a flow chart of method 1000, which describes a method for Fig. 9 The operation of forming the conductive structure 900 in the ILD 945 shown in FIG. More specifically, similar to Figure 2 200, method 1000 includes an implantation process configured to increase the polishing rate of ruthenium metal 910 deposited during the formation of conductive structure 900. Other manufacturing operations may be performed between the various operations of method 1000, and these operations are omitted only for clarity and ease of description. These various operations are within the spirit and scope of the present disclosure. In addition, not all operations are required to perform the disclosure provided herein. Some operations may be performed simultaneously, or in parallel. Fig.10 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. Figures 11 to 15 To describe method 1000.

[0044] In some embodiments, Fig.11 Before forming the conductive structure 900 Fig. 9 The structure shown in , and Fig.12is after forming the contact opening 1100 in the ILD 945 but before depositing the ruthenium metal 910 Fig.11 By way of example and not limitation, the contact opening 1100 in the ILD 945 can be formed by sequential photolithography and etching operations. In some embodiments, Fig.12 It is for Fig.10 A precursor structure (eg, starting structure) for method 1000 is shown.

[0045] exist Fig.12 In the example of FIG. 1 , the contact opening 1100 is formed with an “anchor groove” 1110 . However, this is not restrictive, and the contact opening 1100 may be formed without the anchor groove 1110 . In some embodiments, the contact opening 1100 is selectively formed with the anchor groove 1110 .

[0046] In reference Fig.10 1 , method 1000 begins at operation 1010 and a process of depositing ruthenium metal (e.g., ruthenium metal 910) in a contact opening (e.g., contact opening 1100) formed in a dielectric layer (e.g., ILD 945). By way of example and not limitation, ruthenium metal 910 may be deposited using a method similar to that used to deposit ruthenium metal liner layer 300. For example, a ruthenium carbonyl precursor chemistry (e.g., Ru 3 (CO) 12 ), ruthenium metal 910 is deposited by a CVD process, an ALD process, or another suitable method at a temperature below about 200° C. (e.g., about 180° C.). In some embodiments, the deposited ruthenium metal has a thickness of about 20 nm, or a thickness sufficient to substantially fill the opening 1100 (including the anchor recess 1110).

[0047] In some embodiments, Fig.13 is after depositing ruthenium metal 910 according to operation 1010 Fig.12 1100 is an enlarged view of the contact opening 1100 shown in FIG. Fig.13 As shown, the ruthenium metal 910 fills the contact opening in the ILD 945 and forms a capping layer over the top surface of the ILD 945. The capping layer will be removed by a ruthenium CMP process, thereby forming a linerless contact 900. As described above, the ruthenium metal 910 is deposited directly on the cobalt structure 905 without an intermediate layer. In addition, the ruthenium metal 910 is in direct contact with the sidewall surface of the etch stop layer 940 and the ILD 945, which together form Fig.12 The sidewall surfaces of the opening 1100 are shown.

[0048] In reference Fig.10When , method 1000 continues with operation 1020 and a process of doping ruthenium metal 910 using an implantation process. According to some embodiments, operation 1020 of method 1000 is similar to Figure 2 Operation 240 of method 200 is shown. For example, the implantation process of operation 1020 and the implantation process of operation 240 share a common operating principle. For example, during the implantation process of operation 1020, the ionized dopant 600 is accelerated toward the substrate 925 (e.g., Fig.12 shown), and with Fig.13 The incident angle θ is shown to impact the top surface of the ruthenium metal 910 and the ILD 945. In some embodiments, the incident angle θ is measured from a direction perpendicular to the planar top surface of the ILD 945 (e.g., from the z direction). In some embodiments, the incident angle θ is in a range from about 0° to about 80°. For example, Fig.13 ionized dopant 600A in operation 1020 strikes the top surface of ILD 945 at a normal angle (e.g., incident angle θ equal to 0°), while ionized dopant 600B strikes the top surface of ILD 945 at an incident angle of about 45°. In some embodiments, the small incident angle (e.g., close to 0°) allows ionized dopant 600 to penetrate deeper into ruthenium metal 910 and ILD 945 than ionized dopant with a large incident angle (e.g., close to 80°). For example, under the same implantation conditions (e.g., implantation energy and dopant species), the implantation depth D3 of ionized dopant 600A is greater than the implantation depth D4 of ionized dopant 600B (e.g., D3>D4). In some embodiments, in operation 1020, the incident angle θ is fixed for the duration of the implantation process.

[0049] Similar to the implantation process discussed above with respect to operation 240, in the implantation process of operation 1020, the implantation depth may be controlled by the energy of the ionized dopant 600. In some embodiments, the implantation energy of the ionized dopant is in the range of about 0.3 keV to 50 keV. In some embodiments, for a fixed incident angle θ and for the same type of dopant, a high implantation energy (e.g., about 50 keV) may result in a greater implantation depth than a low implantation energy (e.g., about 30 keV). In some embodiments, the implantation depth is adjusted by the incident angle θ, the implantation energy of the ionized dopant, or a combination of the foregoing.

[0050] In some embodiments, the unpolished portion of the ruthenium metal 910 and the ILD 945 may include equal to or greater than about 1×10 12 Atom / cm 3 For example, in ILD 945, SIMS can detect a residual dopant concentration of about 1×10 12 Atom / cm 3 or higher dopant concentration. In some embodiments, Fig.13 The shaded top portions of the ruthenium metal 910 and the ILD 945 shown in 1020 represent exemplary doped regions in the ruthenium metal 910 and the ILD 945 achieved by the implantation process of operation 1020 .

[0051] In some embodiments, the implantation process of operation 1020 further includes a step of 14 Dopant / cm 2 About 1×10 17 Dopant / cm 2 . In some embodiments, the ionized dopant 600 includes, but is not limited to, C, B, P, O, Si, Ar, Ge, As, or Xe. According to some embodiments, the ionized dopant causes defects in the ruthenium metal 910, which accelerates the oxidation of the ruthenium metal 910 when the ruthenium metal 910 is exposed to the ruthenium CMP slurry. In some embodiments, when both the doped ruthenium metal and the undoped ruthenium metal are polished under similar CMP processing conditions, the doped ruthenium metal has a higher polishing rate than the undoped ruthenium metal. In some embodiments, the polishing rate of the doped ruthenium metal is about 1.1 to about 1.7 times the polishing rate of the undoped ruthenium metal.

[0052] As discussed above with respect to the implantation process of operation 240, the CMP polishing rate of the ruthenium metal may be adjusted by a combination of implantation process parameters (e.g., the type of dopant species (e.g., the atomic mass of the dopant species), implantation energy, incident angle, and dopant dose). The aforementioned implantation process parameters control defects or "damage" caused by the dopant to the ruthenium metal 910, and thus control the oxidation rate of the ruthenium metal 910 during the subsequent CMP process.

[0053] As described in operation 240, process parameters may be selected for the implantation process described in operation 1020. For example, the dopant species may be selected first, then the implantation energy and incident angle may be selected, and then the implantation dose may be selected.

[0054] In some embodiments, a heavier dopant requires a lower dopant dose than a lighter dopant to achieve a comparable ruthenium polishing rate. In some embodiments, the implant depth achieved with the heavier dopant is different from the implant depth achieved with the lighter dopant. In some embodiments, an implantation energy of less than about 0.3 keV and less than about 1×10 14 Dopant / cm 2 The dopant dose of 1×10 Å does not substantially increase the polishing rate of the ruthenium liner 300. On the other hand, an implantation energy greater than about 50 keV and an implantation energy greater than about 1×10 17 Dopant / cm 2 A dopant dose of 0.1% or more may damage the ILD 945 .

[0055] In reference Fig.10 When , the method 1000 continues with operation 1030 and a process of polishing the doped ruthenium metal 910 using a ruthenium CMP process to form a conductive structure (eg, conductive structure 900). Fig.14 When the ruthenium CMP process 1400 planarizes and removes the doped ruthenium metal within the implant depth D, as well as the ruthenium metal capping layer above the ILD 945. In some embodiments, the ruthenium CMP process 1400 removes the ruthenium metal and the ILD 945 at substantially similar polishing rates to achieve the following: Fig.15 In some embodiments, and in reference to Fig.14 , the height H3 of the ILD 945 before the ruthenium CMP process 1400 is greater than the height H4 of the ILD 945 after the ruthenium CMP process 1400 (eg, H3>H4). By way of example and not limitation, the difference between H3 and H4 is substantially equal to Fig.14 The injection depth D is shown.

[0056] In some embodiments, the ruthenium CMP process 1400 is different from the ruthenium CMP process 250 due to differences between polishing materials.

[0057] According to some embodiments, after the ruthenium CMP process 1400, one or more interconnect layers (eg, such as Figure 8 Interconnect layer 100 is shown).

[0058] Various embodiments according to the present disclosure relate to a method for planarizing a ruthenium metal layer in a MEOL and BEOL conductive structure. In some embodiments, the ruthenium metal is implanted (doped) with a dopant species to increase its polishing rate during a subsequent ruthenium CMP process. In some embodiments, the implantation process includes an implantation energy between about 0.3 keV and about 50 keV and an implantation angle between 0° and about 80°. In some embodiments, the implantation dose range is between about 1×10 14 Dopant / cm 2 About 1×10 17 Dopant / cm 2 and includes a dopant selected from C, B, P, O, Si, Ar, Ge, As, or Xe. In some embodiments, the doped ruthenium layer is removed during a subsequent CMP process. In some embodiments, after the ruthenium CMP process, approximately 1×10 13 Atom / cm 3or higher residual dopant concentration. In some embodiments, during the ruthenium CMP process, the doped ruthenium metal layer oxidizes faster than the undoped ruthenium metal layer. In some embodiments, the polishing rate of the doped ruthenium metal layer is about 1.1 to about 1.7 times the polishing rate of the undoped ruthenium metal layer.

[0059] In some embodiments, a method includes: forming a first interconnect layer on a substrate, wherein forming the first interconnect layer includes: forming an opening in a dielectric layer disposed on the substrate, depositing a ruthenium metal liner in the opening, and depositing copper metal on the ruthenium metal liner to fill the opening. Forming the first interconnect layer also includes polishing the copper metal, doping the ruthenium metal liner, and polishing the doped ruthenium metal liner to form a conductive structure in the first interconnect layer. The method also includes forming a second interconnect layer on the first interconnect layer.

[0060] In some embodiments, a method includes: forming a first conductive structure on a second conductive structure, wherein forming the first conductive structure includes: forming an opening in a dielectric layer disposed on the second conductive structure, and depositing ruthenium metal in the opening to overfill the opening. Forming the first conductive structure also includes doping ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure. The method also includes forming an interconnect layer on the first conductive structure.

[0061] In some embodiments, an interconnect layer includes: a dielectric layer located on a substrate; a conductive structure located in the dielectric layer, wherein the conductive structure includes a first conductive material and a ruthenium liner surrounding a sidewall and a bottom surface of the first conductive material. In addition, the dielectric layer includes a dopant concentration of at least about 1×10 12 Atom / cm 3 of dopants.

[0062] It should be understood that the Detailed Description section, rather than the Abstract of the Disclosure, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all contemplated exemplary embodiments and thus, is not intended to limit the appended claims.

[0063] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the appended claims.

[0064] Example 1. A method for manufacturing an interconnection layer, comprising: forming a first interconnection layer on a substrate, wherein forming the first interconnection layer comprises: forming an opening in a dielectric layer disposed on the substrate; depositing a ruthenium metal lining in the opening; depositing copper metal on the ruthenium metal lining to fill the opening; polishing the copper metal; doping the ruthenium metal lining; and polishing the doped ruthenium metal lining to form a conductive structure in the first interconnection layer; and forming a second interconnection layer on the first interconnection layer.

[0065] Example 2. The method of Example 1, wherein depositing the ruthenium metal liner comprises depositing the ruthenium metal liner on a surface of the dielectric layer outside the opening.

[0066] Example 3. The method of Example 1, wherein doping the ruthenium metal liner comprises doping a portion of the copper metal and a portion of the dielectric layer.

[0067] Example 4. The method of Example 1, wherein polishing the doped ruthenium metal liner comprises polishing the copper metal, the dielectric layer, and the doped ruthenium metal liner at similar polishing rates.

[0068] Example 5. The method according to Example 1, wherein doping the ruthenium metal liner comprises: using carbon C, boron B, phosphorus P, oxygen O, silicon Si, argon Ar, germanium Ge, arsenic As or xenon Xe to dope the ruthenium metal liner.

[0069] Example 6. The method of Example 1, wherein doping the ruthenium metal liner comprises: doping the ruthenium metal liner using a doping process including an ion beam, wherein an incident angle of the ion beam is between 0° and 80°.

[0070] Example 7. The method of Example 1, wherein doping the ruthenium metal liner comprises doping the ruthenium metal liner using a doping process including a dopant having an ion energy between 0.3 keV and 20 keV.

[0071] Example 8. A method for manufacturing an interconnection layer, comprising: forming a first conductive structure on a second conductive structure, wherein forming the first conductive structure comprises: forming an opening in a dielectric layer disposed on the second conductive structure; depositing ruthenium metal in the opening to overfill the opening; doping the ruthenium metal; and polishing the doped ruthenium metal to form the first conductive structure; and forming an interconnection layer on the first conductive structure.

[0072] Example 9. The method according to Example 8, wherein doping the ruthenium metal includes: using carbon C, boron B, phosphorus P, oxygen O, silicon Si, argon Ar, germanium Ge, arsenic As or xenon Xe to dope the top portion of the ruthenium metal and the top portion of the dielectric layer.

[0073] Example 10. The method of Example 8, wherein doping the ruthenium metal comprises: doping a top portion of the ruthenium metal to form a top doped portion and a bottom undoped portion.

[0074] Example 11. The method according to Example 8, wherein doping the ruthenium metal comprises: exposing the ruthenium metal to a temperature between 1×10 14 Dopant / cm 2 Up to 1×10 17 Dopant / cm 2 between the dopant doses.

[0075] Example 12. The method of Example 8, wherein doping the ruthenium metal comprises increasing a polishing rate of the doped ruthenium metal by 1.1 to 1.7 times.

[0076] Example 13. The method of Example 8, wherein doping the ruthenium metal comprises: doping the ruthenium metal deposited on the dielectric layer outside the opening.

[0077] Example 14. The method of Example 8, wherein doping the ruthenium metal comprises: doping a top portion of the dielectric layer.

[0078] Example 15. The method of Example 8, wherein depositing the ruthenium metal comprises depositing the ruthenium metal on a surface of the dielectric layer outside the opening to form a capping layer.

[0079] Example 16. The method of Example 8, wherein polishing the doped ruthenium metal comprises polishing the doped ruthenium metal using a chemical mechanical planarization process.

[0080] Example 17. An interconnect layer, comprising: a dielectric layer, the dielectric layer being located on a substrate; a conductive structure, the conductive structure being located in the dielectric layer, wherein the conductive structure comprises: a first conductive material; and a ruthenium liner, the ruthenium liner surrounding a sidewall and a bottom surface of the first conductive material, wherein a top surface of the ruthenium liner and a top surface of the first conductive material are coplanar; and wherein the dielectric layer comprises a dopant concentration equal to or greater than 1×10 12 Atom / cm 3 of dopants.

[0081] Example 18. The interconnect layer of Example 17, wherein the first conductive material comprises copper.

[0082] Example 19. The interconnect layer of Example 17, wherein the first conductive material is different from the ruthenium liner.

[0083] Example 20. The interconnect layer according to Example 17, wherein the dopant includes carbon C, boron B, phosphorus P, oxygen O, silicon Si, argon Ar, germanium Ge, arsenic As or xenon Xe.

Claims

1. A method for manufacturing an interconnect layer, include: A first interconnect layer is formed on a substrate, wherein forming the first interconnect layer comprises: forming an opening in a dielectric layer disposed on the substrate; depositing a ruthenium metal liner in the opening; depositing copper metal on the ruthenium metal liner to fill the opening; polishing the copper metal; doping the ruthenium metal liner; and polishing the doped ruthenium metal liner to form a conductive structure in the first interconnect layer; and forming a second interconnect layer on the first interconnect layer; Wherein, doping the ruthenium metal liner includes: using carbon C, boron B, phosphorus P, oxygen O, silicon Si, argon Ar, germanium Ge, arsenic As or xenon Xe to dope the ruthenium metal liner.

2. The method according to claim 1, in, Depositing the ruthenium metal liner includes depositing the ruthenium metal liner on a surface of the dielectric layer outside the opening.

3. The method according to claim 1, in, Doping the ruthenium metal liner includes doping a portion of the copper metal and a portion of the dielectric layer.

4. The method according to claim 1, in, Polishing the doped ruthenium metal liner includes polishing the copper metal, the dielectric layer, and the doped ruthenium metal liner at similar polishing rates.

5. The method according to claim 1, in, Doping the ruthenium metal liner includes doping the ruthenium metal liner using a doping process including an ion beam, wherein the incident angle of the ion beam is between 0° and 80°.

6. The method according to claim 1, in, Doping the ruthenium metal liner includes doping the ruthenium metal liner using a doping process including a dopant having an ion energy between 0.3 keV and 20 keV.

7. A method for manufacturing an interconnect layer, include: Forming a first conductive structure on the second conductive structure, wherein forming the first conductive structure comprises: forming an opening in a dielectric layer disposed on the second conductive structure; depositing ruthenium metal in the opening to overfill the opening; doping the ruthenium metal; and polishing the doped ruthenium metal to form the first conductive structure; and forming an interconnect layer on the first conductive structure; Wherein, doping the ruthenium metal includes: using carbon C, boron B, phosphorus P, oxygen O, silicon Si, argon Ar, germanium Ge, arsenic As or xenon Xe to dope the top portion of the ruthenium metal and the top portion of the dielectric layer.

8. The method according to claim 7, in, Doping the ruthenium metal includes doping a top portion of the ruthenium metal to form a top doped portion and a bottom undoped portion.

9. The method according to claim 7, in, Doping the ruthenium metal includes: exposing the ruthenium metal to a temperature between 1×10 14 Dopant / cm 2 Up to 1×10 17 Dopant / cm 2 between the dopant doses.

10. The method according to claim 7, in, Doping the ruthenium metal includes: increasing the polishing rate of the doped ruthenium metal by 1.1 to 1.7 times.

11. The method according to claim 7, in, Doping the ruthenium metal includes doping the ruthenium metal deposited on the dielectric layer outside the opening.

12. The method according to claim 7, in, Doping the ruthenium metal includes doping a top portion of the dielectric layer.

13. The method according to claim 7, in, Depositing the ruthenium metal includes depositing the ruthenium metal on a surface of the dielectric layer outside the opening to form a capping layer.

14. The method according to claim 7, in, Polishing the doped ruthenium metal includes polishing the doped ruthenium metal using a chemical mechanical planarization process.

15. An interconnect layer, include: Dielectric layer, The dielectric layer is located on the substrate; A conductive structure, wherein the conductive structure is located in the dielectric layer, wherein the conductive structure comprises: a first conductive material; and a ruthenium liner surrounding sidewalls and a bottom surface of the first conductive material, wherein a top surface of the ruthenium liner and a top surface of the first conductive material are coplanar; and Wherein, the dielectric layer includes a dopant concentration equal to or greater than 1×10 12 Atom / cm 3 The dopant includes carbon C, boron B, phosphorus P, oxygen O, silicon Si, argon Ar, germanium Ge, arsenic As or xenon Xe.

16. The interconnect layer according to claim 15, in, The first conductive material includes copper.

17. The interconnect layer according to claim 15, in, The first conductive material is different from the ruthenium liner.

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