Method of manufacturing a semiconductor device and device thereof

Abstract

A method of manufacturing a semiconductor device and the device thereof, in a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed on a substrate. An isolation insulating layer is formed on the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed on a portion of the fin structure. A fin mask layer is formed on a sidewall of a source / drain region of the fin structure. The source / drain region of the fin structure is recessed. Epitaxial source / drain structures are formed on the recessed fin structure. In the recessing of the source / drain region of the fin structure, a plasma process using a combination of etching and deposition processes forms a recess having a rounded shape in a cross section along the second direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a Fin FET and a method of manufacturing the same. BACKGROUND

[0002] The present disclosure relates to semiconductor integrated circuits, and more particularly, to semiconductor devices having epitaxial source / drain (S / D) structures with apertures and methods of manufacturing the same. As the semiconductor industry has progressed into nanometer technology process nodes to pursue higher device densities, higher performance, and lower costs, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as fin field effect transistors (FinFETs) and the use of metal gate structures with high-k (dielectric constant) materials. Metal gate structures are often fabricated by using gate replacement techniques, and sources and drains are formed by using epitaxial growth methods. SUMMARY

[0003] According to an aspect of the present disclosure, a method of manufacturing a semiconductor device including a Fin FET includes forming a fin structure on a substrate, the fin structure extending in a first direction in a plan view. An isolation insulating layer is formed on the substrate so that a lower portion of the fin structure is embedded in the isolation insulating layer. An upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure is formed on a portion of the fin structure, the gate structure extending in a second direction crossing the first direction in the plan view. A fin mask layer is formed on sidewalls of the fin structure protruding from the isolation insulating layer and not covered by the gate structure, and on an upper surface of the isolation insulating layer. Source / drain regions of the fin structure are recessed. Epitaxial source / drain structures are formed on the recessed fin structure. In the recessing of the source / drain regions of the fin structure, a plasma process combining etching and deposition processes forms a recess having a rounded shape in a cross section along the second direction.

[0004] According to another aspect of the present disclosure, a method of manufacturing a semiconductor device including a Fin FET includes forming a plurality of fin structures on a substrate. The fin structures extend in a first direction and are arranged in a second direction crossing the first direction in a plan view. An isolation insulating layer is formed on the substrate so that lower portions of the fin structures are embedded in the isolation insulating layer, and upper portions of the fin structures are exposed from the isolation insulating layer. A fin mask layer is formed on sidewalls of source / drain regions of the fin structures protruding from the isolation insulating layer. The source / drain regions of the fin structures are recessed. Epitaxial source / drain structures are formed on each of the recessed fin structures to form a merged source / drain epitaxial layer. In the recessing of the source / drain regions, a plasma process combining etching and deposition processes forms a recess having a rounded shape in a cross section along the second direction.

[0005] According to one aspect of the present disclosure, a semiconductor device includes an isolation insulating layer, a plurality of fin structures, a source / drain epitaxial layer, and a dielectric layer. The isolation insulating layer is disposed on a substrate. The fin structures are disposed on the substrate and extend in a first direction in a plan view. A gate structure is disposed on portions of the fin structures and extends in a second direction that intersects the first direction. The dielectric layer is disposed on an upper surface of the isolation insulating layer. Wherein the fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source / drain epitaxial layer is formed on the recessed fin structures, and each of the interfaces between the source / drain epitaxial layer and each of the recessed fin structures has a rounded shape in a cross-section along the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure can best be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be emphasized that various features are not to scale and are given for purposes of illustration and explanation only. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] Figure 1 FIG. illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device according to embodiments of the present disclosure;

[0008] Figure 2 FIG. illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device according to embodiments of the present disclosure;

[0009] Figure 3 FIG. illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device according to embodiments of the present disclosure;

[0010] Figure 4 FIG. illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device according to embodiments of the present disclosure;

[0011] Figure 5A 、 Figure 5B and Figure 5C FIG. illustrates a view of one of various stages of a manufacturing operation for a semiconductor device according to embodiments of the present disclosure;

[0012] Figure 6 FIG. illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device according to embodiments of the present disclosure;

[0013] Figure 7A and Figure 7B FIG. illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device according to embodiments of the present disclosure;

[0014] Figure 8A and Figure 8B FIG. 2 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0015] Figure 9 FIG. 3 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0016] Figure 10 FIG. 4 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0017] Figure 11 FIG. 5 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0018] Figure 12 FIG. 6 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0019] Figure 13 FIG. 7 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0020] Figure 14 FIG. 8 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0021] Figure 15 FIG. 9 illustrates a cross-sectional view of one of various stages of a manufacturing operation for a semiconductor device, in accordance with embodiments of the present disclosure;

[0022] Figure 16 FIG. 10 illustrates a cross-sectional view of a semiconductor device, in accordance with embodiments of the present disclosure;

[0023] Figure 17 FIG. 11 illustrates a schematic view of an etching apparatus, in accordance with embodiments of the present disclosure.

[0024]

SYMBOL DESCRIPTION

[0025] 10: substrate

[0026] 10M: mesa shape

[0027] 15: mask layer

[0028] 15A: pad oxide layer

[0029] 15B: silicon nitride mask layer

[0030] 20: fin structure

[0031] 25: recess

[0032] 30: isolation insulating layer

[0033] 40: gate structure

[0034] 42: dielectric layer

[0035] 44: gate pattern

[0036] 46: cap insulating layer

[0037] 48: gate sidewall spacer

[0038] 50: fin mask layer

[0039] 55: sleeve portion

[0040] 60: epitaxial source / drain structure

[0041] 65: aperture

[0042] 65': aperture

[0043] 70: silicide layer

[0044] 80: insulating layer

[0045] 85: interlayer dielectric layer

[0046] 86: interlayer dielectric layer

[0047] 90: contact hole

[0048] 100: contact plug

[0049] 100A: contact plug

[0050] 100B: contact plug

[0051] 102: gate dielectric layer

[0052] 104: metal gate electrode

[0053] 110A: metal wiring

[0054] 110B: metal wiring

[0055] 1000: plasma etching apparatus

[0056] 1100: wafer table

[0057] 1200: counter electrode DETAILED DESCRIPTION

[0058] It should be understood that the following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of an element are not limited to the range or values ​​disclosed, but may depend on process conditions and / or the desired properties of the element. Furthermore, the formation of a first feature on or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed to be inserted into the first and second features such that the first and second features are not in direct contact. For simplicity and clarity, various features may be drawn at any scale. In the accompanying drawings, some layers / features may be omitted for simplicity.

[0059] Additionally, for simplicity, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the relationship between one element or feature as illustrated in the figures and another (additional) element or feature. These spatial relative terms are intended to cover different orientations of elements in use or operation, in addition to those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Furthermore, the term “made of” may mean “comprising” or “consisting of.” Additionally, in the following manufacturing processes, one or more additional operations may exist during / between the operations, and the order of the operations may change. In this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element from A, an element from B, and an element from C, unless otherwise described. In other embodiments, the same or similar materials, configurations, dimensions, processes and / or operations as those described in relation to one embodiment may be used, and their detailed description may be omitted.

[0060] The disclosed embodiments relate to semiconductor devices and methods of manufacturing thereof, specifically to the source / drain regions of field-effect transistors (FETs). Embodiments such as those disclosed herein are generally applicable not only to FinFETs but also to other FETs.

[0061] Figures 1 to 12 The illustration shows cross-sectional views of various stages for manufacturing a FinFET device according to embodiments of the present disclosure. It should be understood that... Figures 1 to 12Additional operations are provided before, during, and after the processes shown, and some of these operations can be replaced or eliminated to obtain additional embodiments of the method. The order of operations / processes is interchangeable.

[0062] FinFET fin structures can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fin structure, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the formation of patterns with, for example, smaller spacing than patterns obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrel can then be used to pattern the fin structure. Multi-patterning processes that combine photolithography and self-alignment processes typically result in the formation of a pair of fin structures.

[0063] In some embodiments, a masking layer 15 is formed on substrate 10 to fabricate a fin structure. The masking layer 15 is formed by, for example, thermal oxidation and / or chemical vapor deposition (CVD) processes. For instance, substrate 10 is a p-type silicon or germanium substrate with a surface area between approximately 1 × 10⁻⁶. 15 cm -3 To approximately 1×10 16 cm -3 The impurity concentration is between [value missing]. In other embodiments, the substrate is an n-type silicon or germanium substrate, having an impurity concentration between approximately 1 × 10 [value missing]. 15 cm -3 To approximately 1×10 16 cm -3 The concentration of impurities between them.

[0064] Alternatively, substrate 10 may comprise another elemental semiconductor, such as germanium; compound semiconductors, including group IV-IV compound semiconductors such as SiC and SiGe, group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, substrate 10 is a silicon layer of an SOI (silicon-on-insulator) substrate. When using an SOI substrate, the fin structure may protrude from the silicon layer of the SOI substrate or from the insulating layer of the SOI substrate. In the latter case, the silicon layer of the SOI substrate is used to form the fin structure. Amorphous substrates (such as amorphous Si or amorphous SiC) or insulating materials (such as silicon oxide) may also be used as substrate 10. Substrate 10 may comprise various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0065] In some embodiments, the mask layer 15 includes, for example, a liner oxide (e.g., silicon oxide) layer 15A and a silicon nitride mask layer 15B. The liner oxide layer 15A can be formed by using thermal oxidation or chemical vapor deposition (CVD) process. The silicon nitride mask layer 15B can be formed by physical vapor deposition (PVD) such as sputtering method, CVD, plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure CVD (LPCVD), high density plasma CVD (HDPCVD), atomic layer deposition (ALD), and / or other processes.

[0066] In some embodiments, the thickness of the liner oxide layer 15A is between about 2 nm to about 15 nm, and the thickness of the silicon nitride mask layer 15B is between about 2 nm to about 50 nm. A mask pattern is further formed on the mask layer. The mask pattern is, for example, a resist pattern formed by a lithography operation.

[0067] By using the mask pattern as an etch mask, a hard mask pattern 15 of the liner oxide layer and the silicon nitride mask layer is formed, as shown in Figure 1

[0068] Next, by using the hard mask pattern 15 as an etch mask, the substrate 10 is patterned into fin structures 20 by trench etching using a dry etching method and / or a wet etching method, as shown in Figure 2

[0069] In Figure 2 three fin structures 20 are provided on the substrate 10. However, the number of fin structures is not limited to three. The number can be as few as one or more than three. In some embodiments, the number of fin structures is between 5 to 1000, which are connected by source / drain epitaxial layers formed in subsequent operations. In other embodiments, the number of fin structures is between 5 to 100, which are connected by source / drain epitaxial layers formed in subsequent operations. In some embodiments, the number of fin structures is between 5 to 20, which are connected by source / drain epitaxial layers formed in subsequent operations. In addition, one or more dummy fin structures can be provided adjacent to two sides of the fin structures 20 to improve pattern fidelity in the patterning process.

[0070] The fin structures 20 can be made of the same material as the substrate 10, and can be continuously extended from the substrate 10. In this embodiment, the fin structures are made of Si. The silicon layer of the fin structures 20 can be intrinsic, or suitably doped with n-type impurities or p-type impurities.

[0071] ​​In some embodiments, the width Wl of the fin structure 20 is between about 5 nm to about 40 nm, and in other embodiments, between about 7 nm to about 12 nm. In some embodiments, the space SI between two fin structures is between about 10 nm to about 50 nm. In some embodiments, the height (in the Z direction) of the fin structure 20 is between about 100 nm to about 300 nm, and in other embodiments, between about 50 nm to 100 nm.

[0072] The lower portion of the fin structure 20 under the gate structure 40 (see Figure 5A ) can be referred to as a well region, and the upper portion of the fin structure 20 can be referred to as a channel region. Under the gate structure 40, the well region is embedded in the isolation insulating layer 30 (see Figure 5A ), and the channel region protrudes from the isolation insulating layer 30. The lower portion of the channel region can also be embedded in the isolation insulating layer 30 to a depth of about 1 nm to about 5 nm.

[0073] The height of the well region is between about 60 nm to 100 nm in some embodiments, and the height of the channel region is between about 40 nm to 60 nm, and in other embodiments, between about 38 nm to about 55 nm.

[0074] After the fin structure 20 is formed, the substrate 10 is further etched in some embodiments to form a mesa shape 10M, as shown in Figure 3 In other embodiments, the mesa shape 10M is formed first, and then the fin structure 20 is formed. In certain embodiments, no mesa shape is formed.

[0075] After forming the fin structures 20 and the mesa shape 10M, an isolation insulating layer 30 is formed in spaces between the fin structures and / or spaces between one fin structure and another element formed on the substrate 10. The isolation insulating layer 30 can also be referred to as a "shallow-trench-isolation (STI)" layer. The insulating material used for the isolation insulating layer 30 can include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or low dielectric constant dielectric material. The isolation insulating layer is formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, a flowable dielectric material can be deposited instead of silicon oxide. The flowable dielectric material, as the name implies, can "flow" during deposition to fill gaps or spaces with high aspect ratios. Typically, various chemicals are added to a silicon-containing precursor to allow the deposited film to flow. In some embodiments, hydrogen bonds are added. Examples of flowable dielectric precursors, especially flowable silicon oxide precursors, include silicates, siloxanes, methylsilsesquioxane (MSQ), hydrosilsesquioxane (HSQ), MSQ / HSQ, perhydridosilazane (TCPS), perhydropolysilazane (PSZ), tetraethyl orthosilicate (TEOS), or silyl amines such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple operation process. After depositing the flowable film, the flowable film is cured and then annealed to remove the undesired element(s) to form silicon oxide. When the undesired element(s) are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed more than once. The flowable film can be doped with boron and / or phosphorus.

[0076] The insulating layer 30 is first formed in a thick layer so that the fin structures are embedded in the thick layer, and the thick layer is recessed so as to expose the upper portions of the fin structures 20, as shown in Figure 4 The height Hl of the fin structures from the upper surface of the isolation insulating layer 30 is in some embodiments between about 20 nm to about 100 nm, and in other embodiments between about 30 nm to about 50 nm. After recessing the isolation insulating layer 30, or before, a thermal process (e.g., an annealing process) can be performed to improve the quality of the isolation insulating layer 30. In certain embodiments, the thermal process is performed by using rapid thermal annealing (RTA) in an inert gas environment (such as N2, Ar, or He environment) at a temperature ranging from about 900 °C to about 1050 °C for about 1.5 seconds to about 10 seconds.

[0077] After forming the insulating layer 30, a gate structure 40 is formed on the fin structures 20, as shown in Figures 5A to 5C Figure 5A is an illustrative perspective view,​Figure 5B is an exemplary cross-sectional view along line a-a of Figure 5A Figure 5C is an exemplary cross-sectional view along line b-b of Figure 5A Figure 6 , Figure 7A , Figure 8A and Figures 9 to 12 is a cross-sectional view along line b-b of Figure 5A Figure 7B and Figure 8B is a cross-sectional view along line c-c of Figure 5A

[0078] As shown in Figure 5A , the gate structure 40 extends in the X direction, while the fin structure 20 extends in the Y direction.

[0079] To fabricate the gate structure 40, a dielectric layer and a polysilicon layer are formed on the isolation insulating layer 30 and the exposed fin structure 20, and then a patterning operation is performed to obtain a gate structure including a gate pattern 44 made of polysilicon and a dielectric layer 42. In some embodiments, the polysilicon layer is patterned by using a hard mask, and the hard mask remains on the gate pattern 44 as a cap insulating layer 46. The hard mask (cap insulating layer 46) includes one or more layers of insulating material. In some embodiments, the cap insulating layer 46 includes a silicon nitride layer formed on a silicon oxide layer. In other embodiments, the cap insulating layer 46 includes a silicon oxide layer formed on a silicon nitride layer. The insulating material for the cap insulating layer 46 can be formed by CVD, PVD, ALD, e-beam evaporation, or other suitable processes. In some embodiments, the dielectric layer 42 can include one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. In some embodiments, the thickness of the dielectric layer 42 is between about 2 nm and about 20 nm, and in other embodiments, between about 2 nm and about 10 nm. The height H2 of the gate structure is between about 50 nm and about 400 nm in some embodiments, and between about 100 nm and 200 nm in other embodiments.

[0080] In some embodiments, a gate replacement technique is employed. In this case, the gate pattern 44 and the dielectric layer 42 are dummy gate electrodes and dummy gate dielectric layers, respectively, which are subsequently removed. If a first gate technique is employed, the gate pattern 44 and the dielectric layer 42 are used as gate electrodes and gate dielectric layers.

[0081] ​​​​Additionally, gate sidewall spacers 48 are formed on the two sidewalls of the gate pattern. The sidewall spacers 48 comprise one or more layers of insulating material (such as SiO2, SiN, SiON, SiOCN, or SiCN), formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. Low-dielectric-constant dielectric materials may be used as sidewall spacers. The sidewall spacers 48 are formed by forming a blanket layer of insulating material with or without subsequent anisotropic etching. In one embodiment, the sidewall spacers are made of silicon nitride-based materials, such as SiN, SiON, SiOCN, or SiCN.

[0082] Next, as Figure 6 As shown, a fin masking layer 50 is formed on the fin structure 20. The fin masking layer 50 is made of a dielectric material including silicon nitride-based materials (such as SiN, SiON, SiOCN, or SiCN). In one embodiment, SiN is used as the fin masking layer 50. The fin masking layer 50 is formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. In some embodiments, the thickness of the fin masking layer 50 is between about 3 nm and about 30 nm.

[0083] In some embodiments, the fin mask layer 50 and the sidewall spacers 48 for the gate structure are formed separately. In other embodiments, the same blanket layer is used for both the fin mask layer 50 and the sidewall spacers 48.

[0084] After forming the fin masking layer 50, the upper portion of the fin structure 20 is recessed, and the portion of the fin masking layer 50 disposed between the side and top surfaces of the fin structure protruding from the insulating layer is removed by dry etching and / or wet etching operations. For example... Figure 7A and Figure 7B As shown, the upper portion of the fin structure 20 is recessed (etched) downward to a level equal to or below the level of the upper surface of the fin mask layer 50 on the upper surface of the insulating layer 30.

[0085] In some implementations, such as Figure 7AAs shown in the middle, the top of the recessed fin structure 20 (the bottom of the recess 25) has a U-shape, a semi-circular shape, or a bullet-nose shape (which can be collectively referred to as a rounded corner shape, or rounded comer shape), which is a cross-sectional view along the gate extension direction (X). In some embodiments, V-shaped and rectangular shapes are excluded from the rounded corner shape. In some embodiments, in the case of, for example, semi-circular and bullet-nose shapes, there is no flat or linear portion in the cross-sectional view along the X direction at the top of the recessed fin structure. In the case of the bullet-nose shape, two curves meet at the bottom of the recess to form a point. In other embodiments, in the case of, for example, U-shape, there is a small flat or linear portion, which has a length of between about 0.5 nm to about 2 nm. In some embodiments, the rounded corner shape is not a semi-circular shape with a constant outer diameter. In some embodiments, the curved or rounded portion (not the straight portion) does not have a constant outer diameter or curvature. In some embodiments, the maximum outer diameter of the rounded corner is between about 0.5 nm to about 2 nm in some embodiments.

[0086] Along the Y direction (which is the source-to-drain direction), the recess or the top of the recessed fin structure 20 also has a U-shape, which has a rounded corner and a flat or linear bottom portion. In some embodiments, the width LI of the flat or linear bottom portion is about 10% to about 90% of the maximum width L2 of the recess 25 in the Y direction. In other embodiments, LI is about 30% to 70% of L2. In some embodiments, LI is between about 2 nm to about 20 nm. In certain embodiments, there is no flat or linear portion, i.e., LI = 0.

[0087] In some embodiments, the depth Dl of the recess 25, measured from the topmost surface of the fin structure 20, is between about 5 nm and about 60 nm in some embodiments, and between about 10 nm and about 15 nm in other embodiments. In some embodiments, the depth of the recess 25 varies among the plurality of fin structures 20. In some embodiments, the variation in terms of the difference between the maximum depth and the minimum depth is between about 0.5 nm and about 2.5 nm. In some embodiments, the depth D2 of the recess 25, measured from the topmost surface of the isolation insulating layer 30 to the bottommost surface of the recess 25, is between about 10 nm and about 15 nm. In some embodiments, the depth D2 of the recess, measured from the topmost recess portion of the recess 25 (at the edge of the recessed portion), is between about 5 nm and 10 nm. In some embodiments, the ratio of Dl / D2 is between about 1.9 and about 1.14. If the ratio of Dl / D2 is greater than 1.9, it increases the difficulty in subsequent epitaxial growth processes. If the ratio of Dl / D2 is less than 1.14, the strain induced by the source / drain features decreases, resulting in low carrier mobility. In at least one embodiment, the range of Dl / D2 is illustrated with respect to a cross-sectional view along the direction of the fin structure or with respect to a cross-sectional view along the direction of the gate structure.

[0088] As shown in Figure 7B , in some embodiments, the recess penetrates laterally through the portion of the fin structure below the sidewall spacer 48. In other embodiments, the recess extends laterally under a portion of the dummy gate electrode 44.

[0089] In some embodiments, when another gate structure 40 is disposed on the fin structure 20, a portion of the fin structure 20 is recessed from one gate structure to another gate structure, as shown in Figure 7B . In other embodiments, one end of the recess 25 (e.g., the right end in Figure 7B ) is defined by the isolation insulating layer 30. Thus, the size of the recess at this end is defined in a self-aligned manner.

[0090] The fin structure 20 is recessed to form a rounded shape by using a pulsed bias etching operation using the plasma etching apparatus 1000 shown in Figure 17 . In some embodiments, the substrate 10 is placed on a wafer table 1100 of an etching chamber, and the substrate 10 and / or the wafer table 1100 is biased by, for example, a DC voltage. RF power is applied to a counter electrode 1200, which is disposed above the substrate in some embodiments. In other embodiments, the RF power is applied via a coil surrounding the etching chamber.

[0091] In some embodiments, the etching gas includes a halogen-containing gas, such as HBr. In some embodiments, the HBr is diluted by an inert gas, such as He and / or Ar. In some embodiments, the HBr is diluted by nitrogen (N2). In some embodiments, the ratio of HBr to diluent gas is between about 0.3 and about 0.7, and in other embodiments, the ratio is between about 0.4 and about 0.6. If the ratio is greater than 0.7, the etch rate is too fast to control, and if the ratio is less than 0.3, it increases the manufacturing time, resulting in increased cost.

[0092] In some embodiments, during the etching operation, the plasma chamber is maintained at a pressure between about 1 mTorr and about 100 mTorr by a pumping system. In other embodiments, the pressure during the etching operation is between about 3 mTorr and about 15 mTorr.

[0093] The bias voltage is between about 300 V and about 800 V in some embodiments, and between about 500 V and 600 V in other embodiments. In some embodiments, the input RF power is between about 300 W and about 800 W. The frequency of the RF is 13.56 MHz, 2.56 GHz, or any other suitable frequency used in the semiconductor industry.

[0094] In some embodiments, the bias voltage is a pulsed voltage with a duty cycle (on-to-off ratio) between about 10% and about 90%. In other embodiments, the duty cycle is between about 30% and about 70%. In some embodiments, the unit cycle (one "on" period and one "off" period) is between about 0.5 seconds and 10 seconds, and in the range of about 1 second and 5 seconds. In some embodiments, the pulsed bias etch is a repetition of an etching and deposition operation. During the "on" period, the fin structure is etched, and during the "off" period, the deposition rate of byproducts is greater than the etching rate. Thus, by adjusting the duty cycle, the RF power, and / or the bias voltage, it is possible to form a rounded shape as shown in Figure 7A FIG. 2B.

[0095] In some embodiments, the fin mask layer 50 is completely removed. In other embodiments, the fin mask layer 50 remains on the upper surface of the isolation insulating layer 30 by adjusting the etching conditions (e.g., over-etching time). In some embodiments, the thickness of the remaining fin mask layer 50 is between about 2 nm and about 10 nm.

[0096] Next, as shown in Figure 8A and Figure 8BAs shown in FIG. 1C, epitaxial source / drain structures 60 are formed on the recessed fin structures 20. The epitaxial source / drain structures 60 are made of one or more layers of semiconductor material having a different lattice constant than the fin structures 20 (channel region). When the fin structures are made of Si, the epitaxial source / drain structures 60 include SiP, SiC, or SiCP for n-channel Fin FETs, or SiGe or Ge for p-channel Fin FETs. The epitaxial source / drain structures 60 are epitaxially formed on the upper portions of the recessed fin structures. Due to the crystal orientation of the substrate formed as the fin structures 20 (e.g., (100) plane), the epitaxial source / drain structures 60 grow laterally and have a diamond-like shape.

[0097] The source / drain epitaxial layers 60 can be grown at a temperature of about 600 °C to 800 °C at a pressure of about 80 Torr to 150 Torr by using a Si-containing gas (such as SiH4, Si2H6, or SiCl2H2); a Ge-containing gas (such as GeH4, Ge2H6, or GeCl2H2); a C-containing gas (such as CH4or C2H6); and / or a dopant gas (such as PH3). The source / drain structures for n-channel FETs and the source / drain structures for p-channel FETs can be formed by separate epitaxial processes.

[0098] Due to the relatively small space between the fin structures and the fin mask layer 50 remaining on the upper surface of the isolation insulating layer (between the fin structures and the rounded shape of the recessed fin structures 20), the adjacent epitaxial source / drain structures formed on each of the first fin structures 20 are merged, such that a void or gap (air gap) 65 is formed by the merged second epitaxial source / drain structures 60 and the fin mask layer 50 on the upper surface of the isolation insulating layer 30, as shown in FIG. 1D. Figure 8A

[0099] When the fin mask layer is retained, the height H2 of the void 65 is larger due to the fin mask layer 50 on the upper surface of the isolation insulating layer 30 than in the case where no fin mask layer 50 is retained on the upper surface of the isolation insulating layer 30. In some embodiments, the height H2 of the void measured from the upper surface of the fin mask layer 50 is between about 10 nm to about 30 nm, and in other embodiments, between about 15 nm to about 25 nm. In addition, the isolation insulating layer 30 is protected during the fin etching due to the remaining fin mask layer 50. In some embodiments, the fin mask layer 50 is not retained.

[0100] After the epitaxial source / drain structures 60 are formed, a silicide layer 70 is formed on the epitaxial source / drain structures 60, as shown in FIG. 1E. Figure 9

[0101] ​​A metallic material (such as Ni, Ti, Ta, and / or W) is formed on the epitaxial source / drain structure 60, and an annealing operation is performed to form a silicide layer 70. In other embodiments, a silicide material (such as NiSi, TiSi, TaSi, and / or WSi) is formed on the epitaxial source / drain structure 60, and an annealing operation may be performed. The annealing operation is performed at a temperature of about 250°C to about 850°C. The metallic material or silicide material is formed by CVD or ALD. In some embodiments, the thickness of the silicide layer 70 is between about 4 nm and about 10 nm. The metallic material or silicide material formed on the insulating layer 30 is selectively removed before or after the annealing operation.

[0102] Next, as Figure 10 As shown, an insulating layer 80 serving as a contact etch stop layer is formed on the metal gate structure and source / drain structure 60, followed by the formation of an interlayer dielectric layer 85. The insulating layer 80 is one or more layers of insulating material. In one embodiment, the insulating layer 80 is made of silicon nitride formed by CVD. The material used for the interlayer dielectric layer 85 includes compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the interlayer dielectric layer 85.

[0103] Next, a metal gate structure is formed using a gate replacement technique. After forming the interlayer dielectric layer 85, a CMP operation is performed to expose the dummy gate electrode 44. Then, the dummy gate structure (dummy gate electrode 44 and dummy gate dielectric layer 42) is removed and replaced with a metal gate structure (metal gate electrode and gate dielectric layer).

[0104] like Figure 11 As shown, the dummy gate electrode 44 and the dummy gate dielectric layer 42 are removed by appropriate etching processes to form a gate opening. A metal gate structure including a gate dielectric layer 102 and a metal gate electrode 104 is formed in the gate opening.

[0105] In some embodiments, the gate dielectric layer 102 is formed on an interface layer (not shown) disposed on the channel layer of the fin structure 20. In some embodiments, the interface layer may comprise silicon oxide or germanium oxide having a thickness of 0.2 nm to 1.5 nm. In other embodiments, the thickness of the interface layer is between about 0.5 nm and about 1.0 nm.

[0106] The gate dielectric layer 102 includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (Hf02- Al203) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer is formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), or other suitable methods and / or combinations thereof. The thickness of the gate dielectric layer is in some embodiments in a range from about 1 nm to about 10 nm, and in other embodiments can be between about 2 nm and about 7 nm.

[0107] A metal gate electrode 104 is formed on the gate dielectric layer. The metal gate electrode 104 includes one or more layers of any suitable metallic material, such as aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAIN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0108] In some embodiments of the disclosure, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer and the metal gate electrode. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or multiple layers of two or more of such materials. For n-channel Fin FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as work function adjustment layers, and for p-channel Fin FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as work function adjustment layers.

[0109] After the appropriate materials for the metal gate structure are deposited, a planarization operation, such as CMP, is performed.

[0110] After the metal gate structure is formed, one or more interlayer dielectric layers are formed on the metal gate structure and the interlayer dielectric layer 85. As shown in FIG. 1C, these interlayer dielectric layers are collectively referred to as interlayer dielectric layers 86. Figure 12

[0111] ​By using a patterning operation including e-beam lithography, contact holes 90 are formed in the ILD layer 86 and the insulating layer 80 to expose the epitaxial source and drain structures 60 having the silicide layer 70, as shown in Figure 12

[0112] Next, the contact holes are filled with a conductive material, thereby forming contact plugs 100, as shown in Figure 13 The contact plugs 100 can include a single layer or multiple layers of any suitable metal, such as Co, W, Ti, Ta, Cu, Al, and / or Ni and / or nitrides thereof.

[0113] After the contact plugs are formed, additional CMOS processes are performed to form various features, such as additional ILD layers, contacts / vias, interconnect metal layers, and passivation layers, etc.

[0114] In some embodiments, the silicide layer 70 is formed after the contact holes 90 are opened. In this case, after the epitaxial source / drain structures 60 are formed as shown in Figure 8A and Figure 8B the metal gate structures, the insulating layer 80 (contact etch stop layer) and the ILD layer 86 are formed without forming the silicide layer. Next, contact holes are formed in the insulating layer 80 and the ILD layer 86 to expose the upper surfaces of the epitaxial source / drain structures 60, and then the silicide layer is formed on the upper surfaces of the epitaxial source / drain structures 60. After the silicide layer is formed, a conductive material is formed in the contact holes, thereby forming the contact plugs.

[0115] Figure 14 and Figure 15 Exemplary cross-sectional views illustrating various stages for fabricating a Fin FET device according to another embodiment of the disclosure are shown. The same or similar materials, configurations, dimensions, processes and / or operations described with respect to the foregoing embodiments can be employed in the following embodiments, and detailed descriptions thereof can be omitted.

[0116] During the recess etching of the fin mask layer 50 and the fin structures 20 described with respect to Figure 7A and Figure 7B some lower portions of the fin mask layer 50 disposed on the sidewalls of the fin structures 20 are left unetched, thereby forming sleeve portions 55, as shown in Figure 14 In some embodiments, the height H3 of the sleeve portions 55 is between about 1 nm and about 10 nm.

[0117] Next, similar to Figure 8A the epitaxial source / drain structures 60 are formed, thereby forming the voids 65', as shown in Figure 15 ​As shown in the figure. Due to the sleeve-shaped portion 55, in this embodiment, the height H4 of the pore 65' is greater than the height H2 in Figure 8A. In some embodiments, the height H4 is between about 20 nm and about 35 nm.

[0118] In this disclosure, because a pore is formed between the source / drain epitaxial layer and the isolation insulating layer (STI), the parasitic capacitance at the source / drain structure can be reduced. Furthermore, by retaining the fin masking layer (e.g., SiN) on the upper surface of the isolation insulating layer, the height (size) of the pore can be increased.

[0119] Figure 16 The figure shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. The same or similar materials, configurations, dimensions, processes, and / or operations as those described with respect to the foregoing embodiments may be used in the following embodiments, and their detailed descriptions may be omitted.

[0120] like Figure 16 As shown, a plurality of fin structures 20 (e.g., 5 to 20 (e.g., 9) fin structures 20) are provided on the substrate 10, and a merged source / drain epitaxial structure 60 is formed on the fin structures. Figure 16 The etch termination layer is omitted. As described above, the source / drain epitaxial layer 60 is grown in a rounded shape from a self-recessed fin structure. The rounded shape influences the growth of the source / drain epitaxial layer in such a way that the epitaxial layers are more likely to merge and form a merged epitaxial structure. Furthermore, compared to cases where the recessed fin structure has a V-shape or rectangular shape, the upper surface of the merged epitaxial layer tends to have a smoother surface. In some embodiments, the upper surface of the merged epitaxial layer has a non-uniform surface, and the peak-to-valley value of the upper surface of the merged epitaxial layer in the X direction is between about 5 nm and about 20 nm, and in other embodiments it is between about 7 nm and about 15 nm. The peak-to-valley value is measured between the portion above the second fin structure from the left and the portion above the second fin structure from the right.

[0121] In some implementations, such as Figure 16 As shown, the combined source / drain epitaxial layer 60 is electrically coupled to a circuit element via contact plug 100A and metal wiring 110A, and electrically coupled to different circuit elements via contact plug 100B and metal wiring 110B. In this case, in some embodiments, two or more gate electrodes are provided on multiple fin structures.

[0122] In the embodiments disclosed herein, it is possible to improve the properties of the source / drain epitaxial layer by forming rounded grooves in the groove etching of the source / drain regions of the fin structure.

[0123] It is to be understood that not necessarily all objects or advantages are discussed above, that some implementations or examples can be practiced without all of the objects or advantages discussed, and that other implementations or examples can provide different advantages.

[0124] According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device including a Fin FET, a fin structure is formed on a substrate. The fin structure extends in a first direction in a plan view. An isolation insulating layer is formed on the substrate such that a lower portion of the fin structure is embedded in the isolation insulating layer and an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure is formed on a portion of the fin structure. The gate structure extends in a second direction crossing the first direction in the plan view. A fin mask layer is formed on sidewalls of the fin structure protruding from the isolation insulating layer and not covered by the gate structure and on an upper surface of the isolation insulating layer. A source / drain region of the fin structure is recessed. Epitaxial source / drain structures are formed on the recessed fin structure. In the recessing of the source / drain region of the fin structure, a plasma process using a combination of etching and deposition processes forms a recess having a rounded shape in a cross section along the second direction. In one or more of the foregoing and following embodiments, the plasma process includes applying an RF power and applying a pulsed bias. In one or more of the foregoing and following embodiments, the pulsed bias includes a duty cycle between 10% and 90%. In one or more of the foregoing and following embodiments, the pulsed bias includes a turn-on voltage between 300 V and 800 V. In one or more of the foregoing and following embodiments, the RF voltage includes an input power between 300 W and 800 W. In one or more of the foregoing and following embodiments, the plasma process includes supplying HBr and He. In one or more of the foregoing and following embodiments, a ratio of HBr to He is between 0.3 and 0.7. In one or more of the foregoing and following embodiments, the plasma process is performed at a pressure between 1 mTorr and 100 mTorr. In one or more of the foregoing and following embodiments, in the cross section along the second direction, the rounded shape is one of a U-shape and a bullet shape. In one or more of the foregoing and following embodiments, in the cross section along the second direction, the rounded shape is not a semi-circular shape.

[0125] According to another aspect of the present disclosure, in a method of fabricating a semiconductor device including a FinFET, a plurality of fin structures is formed on a substrate. The plurality of fin structures extends in a first direction and is arranged in a second direction that crosses the first direction in a plan view. An isolation insulating layer is formed on the substrate such that lower portions of the plurality of fin structures are embedded in the isolation insulating layer and upper portions of the plurality of fin structures are exposed from the isolation insulating layer. A fin mask layer is formed on sidewalls of the plurality of fin structures that protrude from the isolation insulating layer at source / drain regions of the plurality of fin structures. The source / drain regions of the plurality of fin structures are recessed. Epitaxial source / drain structures are formed on each of the recessed fin structures to form a merged source / drain epitaxial layer. In recessing the source / drain regions, a plasma process using a combination of etching and deposition processes forms a recess having a rounded shape in a cross-section along the second direction. In one or more of the foregoing and following embodiments, a depth of the recess is between 5 nm and 20 nm. In one or more of the foregoing and following embodiments, the depths are not uniform. In one or more of the foregoing and following embodiments, a difference between a maximum depth and a minimum depth is between 0.5 nm and 2.5 nm. In one or more of the foregoing and following embodiments, in a cross-section along the first direction, the recess has a U-shape with a straight bottom. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is one of a U-shape and a bullet shape. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is not a semicircular shape. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is a semicircular shape. In one or more of the foregoing and following embodiments, a number of the plurality of fin structures coupled to the source / drain epitaxial layer is between five and twenty.

[0126] According to another aspect of this disclosure, in a method of fabricating a semiconductor device including a FinFET, a first fin structure and a second fin structure are formed on a substrate. The first and second fin structures extend in a first direction in a plan view. An isolation insulating layer is formed on the substrate such that lower portions of the first and second fin structures are embedded in the isolation insulating layer and upper portions of the first and second fin structures are exposed from the isolation insulating layer. A gate structure is formed on portions of the first and second fin structures, the gate structure extending in a second direction that intersects the first direction in the plan view. A fin mask layer is formed on sidewalls of the first and second fin structures that protrude from the isolation insulating layer and are not covered by the gate structure and on an upper surface of the isolation insulating layer. The upper portions of the first and second fin structures are recessed, thereby resulting in a recessed first fin structure and a recessed second fin structure. A first epitaxial source / drain structure is formed on the recessed first fin structure and a second epitaxial source / drain structure is formed on the recessed second fin structure, such that the first and second epitaxial source / drain structures merge to form an aperture between the merged first and second epitaxial source / drain structures and a remaining fin mask layer on the upper surface of the isolation insulating layer. In recessing the first and second fin structures, a plasma process using a combination of etching and deposition processes forms a recess having a rounded shape in cross-section along the second direction.

[0127] According to one aspect of the present disclosure, a semiconductor device includes an isolation insulating layer disposed on a substrate; a plurality of fin structures disposed on the substrate and extending in a first direction in a plan view; gate structures disposed on portions of the plurality of fin structures and extending in a second direction crossing the first direction; a merged source / drain epitaxial layer; and a dielectric layer disposed on an upper surface of the isolation insulating layer. The plurality of fin structures not covered by the gate structures are recessed below the upper surface of the isolation insulating layer, the merged source / drain epitaxial layer is formed on the recessed fin structures, and each of the interfaces between the merged source / drain epitaxial layer and each of the recessed fin structures has a rounded shape in a cross-section along the second direction. In one or more of the foregoing and following embodiments, an interface depth measured from the upper surface of the isolation insulating layer is between 5 nm to 20 nm. In one or more of the foregoing and following embodiments, the depths are non-uniform. In one or more of the foregoing and following embodiments, a difference between a maximum depth and a minimum depth is between 0.5 nm to 2.5 nm. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is one of a U-shape and a bullet shape. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is not a semi-circular shape. In one or more of the foregoing and following embodiments, in a cross-section along the first direction, the interface has a U-shape with a straight bottom. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is a semi-circular shape. In one or more of the foregoing and following embodiments, a curved portion of the rounded shape does not have a constant curvature. In one or more of the foregoing and following embodiments, a number of the plurality of fin structures coupled to the source / drain epitaxial layer is between five and twenty. In one or more of the foregoing and following embodiments, an upper surface of the merged source / drain epitaxial layer has a non-uniform surface. In one or more of the foregoing and following embodiments, a peak-to-valley value of the non-uniform upper surface of the merged epitaxial layer in the second direction is between 5 nm to 20 nm. In one or more of the foregoing and following embodiments, the semiconductor device further includes a first via plug contacting the merged source / drain epitaxial layer, and a second via plug contacting the merged source / drain epitaxial layer. The first via plug and the second via plug are electrically coupled to different circuit elements from each other. In one or more of the foregoing and following embodiments, two or more gate structures are disposed on the plurality of fin structures.

[0128] According to another aspect of the present disclosure, a semiconductor device includes an isolation insulating layer disposed on a substrate; a first fin structure and a second fin structure each disposed on the substrate and extending in a first direction in a plan view; a gate structure disposed on portions of the first and second fin structures and extending in a second direction crossing the first direction; a merged source / drain epitaxial layer; and a dielectric layer disposed on an upper surface of the isolation insulating layer. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer, the merged source / drain epitaxial layer is formed on the recessed fin structures, and each of the interfaces between the merged source / drain epitaxial layer and each of the recessed first and second fin structures has a rounded shape in a cross-section along the second direction. In one or more of the foregoing and following embodiments, in a cross-section along the first direction, the interface has a U-shape with a straight bottom. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is a semi-circular shape. In one or more of the foregoing and following embodiments, in a cross-section along the second direction, the rounded shape is not a semi-circular shape. In one or more of the foregoing and following embodiments, a curved portion of the rounded shape does not have a constant curvature.

[0129] According to another aspect of the present disclosure, a semiconductor device includes an isolation insulating layer disposed on a substrate; a fin structure disposed on the substrate and extending in a first direction in a plan view; a gate structure disposed on portions of the structure and extending in a second direction crossing the first direction; a source / drain epitaxial layer; and a dielectric layer disposed on an upper surface of the isolation insulating layer. The fin structure not covered by the gate structure is recessed below the upper surface of the isolation insulating layer, the source / drain epitaxial layer is formed on the recessed fin structure, and an interface between the source / drain epitaxial layer and the recessed fin structure has a rounded shape in a cross-section along the second direction.

[0130] The foregoing outlines features of several embodiments or examples so that a thorough understanding of the present disclosure can be attained. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor device including a fin field effect transistor, the method comprising: The method comprises: forming a fin structure on a substrate, the fin structure extending in a first direction in plan view; forming an isolation insulating layer on the substrate such that a lower portion of the fin structure is embedded in the isolation insulating layer and an upper portion of the fin structure is exposed from the isolation insulating layer; forming a gate structure on a portion of the fin structure, the gate structure extending in a second direction crossing the first direction in plan view; forming a fin mask layer on sidewalls of the fin structure protruding from the isolation insulating layer and an upper surface of the isolation insulating layer not covered by the gate structure; recessing a source / drain region of the fin structure; and forming an epitaxial source / drain structure on the recessed fin structure; wherein in recessing the source / drain region of the fin structure, a plasma process using a combination of etching and deposition processes forms a recess, wherein the recess has a rounded shape in a cross-section along the first direction and in a cross-section along the second direction, wherein a ratio of a recess depth measured from a topmost portion of the recess to a bottommost surface of the recess to a recess depth measured from a topmost surface of the isolation insulating layer to the bottommost surface of the recess is between 1.9 and 1.

14.

2. The method of claim 1, wherein, The plasma process includes applying an RF power and applying a pulsed bias.

3. The method of claim 2, wherein, The pulsed bias includes a duty cycle in a range between 10% and 90%.

4. The method of claim 2, wherein, The pulsed bias includes a turn-on voltage between 300V and 800V.

5. The method of claim 2, wherein, The pulsed bias includes an input power between 300W and 800W.

6. The method of claim 2, wherein, The plasma process includes supplying HBr and He.

7. The method of claim 6, wherein, A ratio of HBr to He is between 0.3 and 0.

7.

8. The method of claim 6, wherein, The plasma process is performed at a pressure between 1 mTorr and 100 mTorr.

9. The method of claim 1, wherein, In the cross-section along the first direction, the rounded shape is U-shaped.

10. The method of claim 9, wherein, The rounded shape has rounded corners and flat bottom portions.

11. A method of fabricating a semiconductor device comprising a fin field effect transistor, the method comprising: The method comprises: forming a plurality of fin structures on a substrate, the plurality of fin structures extending in a first direction and arranged in a second direction crossing the first direction in plan view; forming an isolation insulating layer on the substrate such that lower portions of the plurality of fin structures are embedded in the isolation insulating layer and upper portions of the plurality of fin structures are exposed from the isolation insulating layer; forming a fin mask layer on sidewalls of a plurality of source / drain regions of the plurality of fin structures protruding from the isolation insulating layer; recessing the plurality of source / drain regions of the plurality of fin structures; and forming an epitaxial source / drain structure on each of the recessed plurality of fin structures to form a merged source / drain epitaxial layer, In the recessing of the plurality of source / drain regions, a plasma process using a combination of etching and deposition processes forms a recess having a rounded shape in a cross-section along the first direction and in a cross-section along the second direction, wherein a ratio of a recess depth measured from a topmost portion of the recess to a bottom surface of the recess to a recess depth measured from a topmost surface of the isolation insulating layer to the bottom surface of the recess is between 1.9 and 1.

14.

12. The method of claim 11, wherein, A depth of the recess is in a range between 5 nm and 20 nm.

13. The method of claim 12, wherein, The depth of the recess is non-uniform.

14. The method of claim 13, wherein, A difference between a maximum depth and a minimum depth of the recess is between 0.5 nm and 2.5 nm.

15. The method of claim 11, wherein, In the cross-section along the first direction, the rounded shape is a U-shape having a straight bottom.

16. The method of claim 15, wherein, In the cross-section along the second direction, the rounded shape has rounded corners, the rounded shape being one of a U-shape and a bullet shape.

17. The method of claim 15, wherein, In the cross-section along the second direction, the rounded shape is not a semi-circular shape.

18. The method of claim 15, wherein, In the cross-section along the second direction, the rounded shape is a semi-circular shape.

19. The method of claim 11, wherein, A number of the plurality of fin structures coupled to the merged source / drain epitaxial layer is between five and twenty.

20. A semiconductor device, comprising: Comprising: an isolation insulating layer disposed on a substrate; a first fin structure and a second fin structure disposed on the substrate and extending in a first direction in a plan view; a gate structure disposed on portions of the first fin structure and the second fin structure and extending in a second direction crossing the first direction; a merged source / drain epitaxial layer; a dielectric layer disposed on an upper surface of the isolation insulating layer, wherein the first fin structure and the second fin structure not covered by the gate structure are recessed below the upper surface of the isolation insulating layer to form a recess, the merged source / drain epitaxial layer is formed on the recess of the recessed fin structures, and each of interfaces between the merged source / drain epitaxial layer and each of the recessed first fin structure and the second fin structure has a rounded shape in a cross-section along the second direction and in a cross-section along the first direction, wherein a ratio of a recess depth measured from a topmost portion of the recess to a bottom surface of the recess to a recess depth measured from a topmost surface of the isolation insulating layer to the bottom surface of the recess is between 1.9 and 1.14; and an aperture formed between the merged source / drain epitaxial layer and the upper surface of the isolation insulating layer.

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