Integrated circuit

Abstract

The present disclosure relates to an integrated circuit. An integrated circuit includes a pull-up circuit, an electrostatic discharge (ESD) primary protection circuit, and a pull-down circuit. The pull-up circuit is coupled between a pad and a first voltage terminal. The ESD primary protection circuit includes a first terminal coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal. The pull-down circuit has a first terminal coupled to the pad, the ESD primary protection circuit, and the pull-up circuit, and a second terminal coupled to the second voltage terminal. The pull-down circuit includes at least one first transistor of a first conduction type, and a first terminal of the at least one first transistor is coupled to the first terminal of the pull-down circuit. The breakdown voltage of the at least one first transistor is greater than the trigger voltage of the ESD primary protection circuit.

Description

Technical Field

[0001] The present disclosure generally relates to integrated circuits. Background Art

[0002] ESD events generate extremely high voltages and result in high current pulses of short duration, which can damage integrated circuit devices. For the ESD protection design of integrated circuit devices, the industry has implemented a two-stage ESD protection circuit, including, for example, an ESD primary protection circuit and a victim device. However, before the ESD primary protection circuit conducts, the victim device may be damaged due to the high fast turn-on voltage of the ESD primary protection circuit. Summary of the Invention

[0003] According to one embodiment of the present disclosure, there is provided an integrated circuit, including: a pull-up circuit coupled between a pad and a first voltage terminal; an electrostatic discharge (ESD) primary protection circuit including a first terminal coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal; and a pull-down circuit including a first terminal coupled to the pad, the ESD primary protection circuit, and the pull-up circuit, and a second terminal coupled to the second voltage terminal, wherein the pull-down circuit includes at least one first transistor of a first conductivity type, a first terminal of the at least one first transistor being coupled to the first terminal of the pull-down circuit; wherein a breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary protection circuit.

[0004] According to another embodiment of the present disclosure, there is provided an integrated circuit, including: a resistor structure coupled between a first voltage terminal and a pad; a first active region coupled to the pad and the resistor structure; a second active region coupled between the first active region and a second voltage terminal different from the first voltage terminal; a third active region of a first type coupled to the pad and the first active region; and a fourth active region of the first type coupled between the third active region and the second voltage terminal, wherein a width of the third active region is greater than a width of the fourth active region; wherein the first active region and the second active region are included in a structure serving as a first transistor, and the third active region and the fourth active region are included in a structure serving as a second transistor; wherein the second transistor is configured to release electrostatic charge injected from the pad when the first transistor is turned off.

[0005] According to another embodiment of the present disclosure, a method of operating an integrated circuit is provided, including: releasing electrostatic charge from a pad to a first voltage terminal through a first active region and a second active region, where the first active region is coupled to the pad and the second active region is coupled between the first active region and the first voltage terminal; wherein the first active region and the second active region have the same conduction type and different widths, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and releasing the electrostatic charge through an ESD primary protection circuit having a first terminal coupled to the first active region and a second terminal coupled to the first voltage terminal, wherein the trigger voltage of the ESD primary protection circuit is lower than the first breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a block diagram of a portion of an integrated circuit in accordance with some embodiments.

[0008] Figure 2A is in accordance with some embodiments with Figure 1 of the integrated circuit corresponding to an equivalent circuit of a portion of the integrated circuit.

[0009] Figure 2B is in accordance with some embodiments of Figure 2A in the integrated circuit of a portion of the layout in a plan view.

[0010] Figure 3A is in accordance with various embodiments with Figure 1 of the integrated circuit corresponding to an equivalent circuit of a portion of the integrated circuit.

[0011] Figure 3B is in accordance with some embodiments of Figure 3A in the integrated circuit of a portion of the layout in a plan view.

[0012] Figure 3C is in accordance with other embodiments of Figure 3A in the integrated circuit of a portion of the layout in a plan view.

[0013] Figure 4A is in accordance with some embodiments with Figure 1 of the integrated circuit corresponding to an equivalent circuit of a portion of the integrated circuit.

[0014] Figure 4B is a layout diagram in a plan view of a part of an integrated circuit according to some embodiments. Figure 4A in the integrated circuit of

[0015] Figure 5A is an equivalent circuit of a part of an integrated circuit corresponding to the integrated circuit of Figure 1 according to some embodiments.

[0016] Figure 5B is a layout diagram in a plan view of a part of an integrated circuit according to some embodiments. Figure 5A in the integrated circuit of

[0017] Figure 6 is a flowchart of a method of operating an integrated circuit according to some embodiments.

[0018] Figure 7 is a block diagram of a system for designing an integrated circuit layout design according to some embodiments of the present disclosure.

[0019] Figure 8 is a block diagram of an integrated circuit manufacturing system and an associated integrated circuit manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] The terms used in this specification generally have their ordinary meanings in the art and in the particular context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely illustrative and in no way limits the scope and meaning of the present disclosure or any exemplary term. Similarly, the present disclosure is not limited to the various embodiments given in this specification.

[0022] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] Now refer to Figure 1 . Figure 1 is a block diagram of a portion of an integrated circuit 100 according to various embodiments. For illustration, the integrated circuit 100 includes a pad 110, a pull-up circuit 120, a pull-down circuit 130, and an electrostatic discharge (ESD) primary protection circuit 140. The pad 110 is coupled to the terminals of the pull-up circuit 120, the pull-down circuit 130, and the ESD primary protection circuit 140. The other terminal of the pull-up circuit 120 is coupled to a voltage terminal configured to receive a power supply voltage VDDIO (also referred to as "voltage terminal VDDIO" in the following paragraphs). The terminal of the pull-down circuit 130 is coupled to the terminal of the pull-up circuit 120 and the ESD primary protection circuit 140, and the other terminal of the pull-down circuit 130 is coupled to a voltage terminal configured to receive a power supply voltage VSS (also referred to as "voltage terminal VSS" in the following paragraphs). The terminal of the ESD primary protection circuit 140 is coupled to the terminal of the pull-up circuit 120 and the pull-down circuit 130, and the other terminal of the ESD primary protection circuit 140 is coupled to the other terminal of the pull-down circuit 130 and the voltage terminal VSS. In some embodiments, the integrated circuit 100 utilizes an effective release path to provide ESD protection to bypass any ESD stress. For example, the integrated circuit 100 protects an internal circuit (not shown) from being damaged by undesired and unpredictable electrostatic discharge events in a human body model (HBM), a charged device model (CDM), and a machine model (MM). For purposes of illustration, Figure 1 the integrated circuit 100 shown. Various equivalent ESD protection circuits are within the scope of the present disclosure. For example, in some embodiments, a tracker circuit is coupled to the pull-up circuit 120 and / or the pull-down circuit 130 and is configured to control the pull-up circuit 120 and the pull-down circuit 130 in a normal operating mode.

[0024] In some embodiments, during an ESD event, for example, the pull-down circuit 130 clamps the voltage induced by the static charge in the ESD event, and when the ESD primary protection circuit 140 has not been turned on, a portion of the ESD current from the pad 110 is shunted through the pull-down circuit 130 to the voltage terminal VSS. As the ESD current increases, the voltage across the two terminals of the ESD primary protection circuit 140 increases and further reaches the trigger voltage, which is configured to turn on the ESD primary protection circuit 140. Thus, the ESD primary protection circuit 140 is turned on to release a portion of the ESD current from the pad 110 to the voltage terminal VSS.

[0025] Now refer to Figure 2A . Figure 2A is a portion of the equivalent circuit of the integrated circuit 200 corresponding to the integrated circuit 100 of Figure 1 according to some embodiments. The integrated circuit 200 includes a pad 210 and transistors 220 - 240. The pad 210 is configured relative to the pad 110 such as Figure 1 . The transistor 220 is configured relative to the pull-up circuit 120 such as Figure 1 . The transistor 230 is configured relative to the pull-down circuit 130 such as Figure 1 . The transistor 240 is configured relative to the ESD primary protection circuit 140 such as Figure 1 . In some embodiments, the transistor 230 is substantially the same as the transistor 240.

[0026] For illustration, in some embodiments, a terminal of the transistor 220 is coupled to the voltage terminal VDDIO, and the other terminal of the transistor 220 is coupled to the pad 210. A terminal of the transistor 230 is coupled to the pad 210, and the other terminal of the transistor 230 is coupled to the voltage terminal VSS. A terminal of the transistor 240 is coupled to the pad 210, and the other terminal of the transistor 240 is coupled to the voltage terminal VSS.

[0027] In some embodiments, the transistor 220 is a transistor of the first conduction type (i.e., P-type), and the transistors 230 and 240 are transistors of the second conduction type (i.e., N-type).

[0028] In some embodiments, the breakdown voltage of the transistor 230 is greater than the trigger voltage of the transistor 240 of the ESD primary protection circuit such as Figure 2A . In alternative embodiments, the absolute value of the breakdown voltage of the transistor 230 is N times the absolute value of the breakdown voltage of the transistor 220, where N is greater than about 2. Details of the configuration of the transistors 220 - 240 will be discussed in the following paragraphs.

[0029] Integrated circuit 200 is provided for illustrative purposes. Various implementations of integrated circuit 200 are within the contemplated scope of the present disclosure. For example, in some embodiments, integrated circuit 200 includes a plurality of P-type transistors coupled in parallel to function as transistor 220, and / or a plurality of N-type transistors coupled in parallel to function as transistor 230 and / or transistor 240.

[0030] Reference now Figure 2B . Figure 2B According to some embodiments Figure 2A Layout diagram in a plan view of a portion of an integrated circuit 200 in FIG. For illustration, the integrated circuit 200 includes a substrate P_sub, a well region NW of a second conductivity type (i.e., N-type), gates 221a-221c, 231a-231c, 241a-241c, active regions 222a, 222b, 232a, 232b, 242a, 242b, and conductive segments 251a-251g. In some embodiments, the gates 221a-221c and the active regions 222a, 222b are disposed in the well region NW. The gates 231a-231c, 241a-241c and the active regions 232a, 232b, 242a, and 242b are disposed on the substrate P_sub. Conductive segments 251a-251g are, for example, arranged over gates 221a-221c, 231a-231c, 241a-241c and active regions 222a, 222b, 232a, 232b, 242a, 242b.

[0031] For illustration, gates 221a-221c and conductive segments 251a-251b and 251c together correspond to transistor 220. Gates 231a-231c and conductive segments 251c, 251d, and 251e together correspond to transistor 230. Gates 241a-241c and conductive segments 251c, 251f, and 251g together correspond to transistor 240. In such an embodiment, transistors 220-240 share conductive segment 251c, which corresponds to transistor 230. Figure 2A Transistors 220 - 240 are shown coupled to pad 210 via conductive segment 251 c .

[0032] For further explanation Figure 2B, the conductive segment 251a corresponds to the source terminal of the transistor 220. The gate 221b and the conductive segment 251b together correspond to the gate terminal of the transistor 220. The conductive segment 251c corresponds to the drain terminal of the transistor 220. The conductive segment 251c also corresponds to the drain terminal of the transistor 230. The gate 231b and the conductive segment 251d together correspond to the gate terminal of the transistor 230. The conductive segment 251e corresponds to the source terminal of the transistor 230. The conductive segment 251c further corresponds to the drain terminal of the transistor 240. The gate 241b and the conductive segment 251f together correspond to the gate terminal of the transistor 240. The conductive segment 251g corresponds to the source terminal of the transistor 240.

[0033] In some embodiments, the gates 221a, 221c, 231a, 231c, 241a, and 241c are referred to as dummy gates, where in some embodiments, a "dummy" gate is referred to as a gate that is not electrically connected as a MOS device gate and has no function in the circuit.

[0034] The active region 222a is coupled to the voltage terminal VDDIO through the conductive segment 251a. The active region 222b is coupled to the active regions 232a and 242a through the conductive segment 251c. The active region 232b is coupled to the voltage terminal VSS through the conductive segment 251e. The active region 242b is coupled to the voltage terminal VSS through the conductive segment 251g.

[0035] Continuing to refer Figure 2B , for illustration, the width of the active region 232a is greater than the width of the active region 232b, and is also greater than the widths of the active regions 222a, 222b, and 242b. In some embodiments, the width of the active region 232a is substantially equal to the width of the active region 242a. In alternative embodiments, the width of the active region 232a is about 5 to about 6 times the widths of the active regions 232b, 222a, 222b, and 242b.

[0036] Utilizing Figure 2B the configuration, in some embodiments, the active region 232a is configured to form the transistor 230, and the conductive segment 251c corresponds to the drain terminal of the transistor 230 coupled to the pad 210. In such embodiments, compared to some methods, the transistor 230 (with the wider-width active region 232a coupled to the pad 210 to receive ESD current) has increased and greater drain ballasting to improve ESD performance. Thus, when an ESD event occurs, the transistor 230 of the pull-down circuit 130 as Figure 1 is capable of withstanding a larger ESD current.

[0037] In some methods, compared to Figure 2AThe pull-down circuit associated with transistor 230 therein includes a transistor having an active region coupled to a pad to receive ESD current, wherein the width of the active region is equal to the width of other normal active regions coupled to a power supply voltage (e.g., voltage terminals VDDIO and / or VSS). Thus, the aforementioned transistor has a typical breakdown voltage. In addition, the pull-down circuit is coupled to the ESD primary protection circuit associated with Figure 2A transistor 240 therein. However, in some methods, the trigger voltage of the ESD primary protection circuit is greater than the breakdown voltage of the transistor included in the pull-down circuit. Thus, when the voltage across the pull-down circuit and the ESD primary protection circuit (caused by an ESD event) increases and reaches the breakdown voltage of the transistor included in the pull-down circuit without reaching the trigger voltage of the ESD primary protection circuit, the transistor included in the pull-down circuit is damaged by the ESD current before the ESD primary protection circuit conducts to release the ESD current.

[0038] Compared with the above method, using the configuration discussed in the embodiment as above in Figure 2A - Figure 2B , the breakdown voltage of transistor 230 can be increased and is, for example, about 2 to 3 times the breakdown voltage in the above method.

[0039] For illustrative purposes, an Figure 2A - Figure 2B integrated circuit 200 is given. Various implementations of integrated circuit 200 are within the scope of the present disclosure. For example, in some embodiments, the width of active region 222b is equal to the width of active region 232a, while the width of active region 222a is equal to the width of active region 232b.

[0040] In some embodiments, the width of the active region of the transistor coupled to the pad is selected such that the breakdown voltage of the transistor increases and is greater than the trigger voltage of the ESD primary protection circuit. The optimal width of the active region is balanced by ESD performance, leakage current, and layout area.

[0041] Now refer to Figure 3A . Figure 3A is an equivalent circuit of a part of integrated circuit 300 corresponding to integrated circuit 100 according to various embodiments. Regarding Figure 1 the embodiments, elements identical to those in Figure 3A are designated with the same reference numerals for easy understanding. For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here, unless the cooperation relationship with the elements shown in Figure 2A needs to be introduced. Figure 3A is shown.

[0042] is associated with Figure 2ACompared with the integrated circuit 200, the integrated circuit 300 further includes transistors 220a - 220c, 230a - 230c, and 240a - 240b. Transistors 220a - 220b are configured relative to, for example, Figure 2A transistors 220 and are configured to function as Figure 1 the pull - up circuit 120. Transistor 230a is configured relative to, for example, Figure 2A transistors 230 and transistors 230a - 230c are configured to function as Figure 1 the pull - down circuit 130. Transistor 240a is configured relative to, for example, Figure 2A transistors 240 and transistors 240a - 240b are configured to function as Figure 1 the ESD primary protection circuit 140.

[0043] For illustration, transistors 220a - 220c are serially coupled between the voltage terminal VDDIO and the pad 210. Transistors 230b - 230c are serially coupled to the terminal of transistor 230a and the voltage terminal VSS, while the other terminal of transistor 230a is coupled to the pad 210. Transistor 240b is serially coupled to the terminal of transistor 240a and the voltage terminal VSS, while the other terminal of transistor 240a is coupled to the pad 210. The control terminal of transistor 240b is coupled to the voltage terminal 240b.

[0044] In some embodiments, transistors 220a - 220c are transistors of a first conduction type (i.e., P - type), and transistors 230a - 230c and 240a - 240b are transistors of a second conduction type (i.e., N - type).

[0045] In some embodiments, the overall breakdown voltage of transistors 230a - 230c is greater than the overall trigger voltage of transistors 240a - 240b. In other words, transistors 240a - 240b are turned on before transistors 230a - 230c are damaged.

[0046] In some embodiments, the breakdown voltage of transistor 230a is N times the breakdown voltage of transistors 230b - 230c, where N is greater than about 2. The absolute value of the breakdown voltage of transistor 230a is N times the absolute value of the breakdown voltage of each of transistors 220a - 220c. In alternative embodiments, the breakdown voltage of transistor 230a is substantially the same as the breakdown voltage of transistor 240a. Details of the configurations of transistors 220a - 220c, 230a - 230c, and 240a - 240b will be discussed in the following paragraphs.

[0047] For illustrative purposes, an integrated circuit 300 is given. Various embodiments of the integrated circuit 300 are within the scope of the present disclosure. For example, in some embodiments, the breakdown voltage of the transistor 230a is greater than the trigger voltage of the transistors 240a - 240b as a whole.

[0048] Now referring to Figure 3B . Figure 3B is a layout diagram in a plan view of a part of the integrated circuit 300 according to some embodiments. Regarding Figure 3A the embodiments, elements that are the same as those in Figure 3B are designated with the same reference numerals for easy understanding. For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here, unless it is necessary to introduce the cooperation relationship with the Figure 2B elements shown in Figure 3B .

[0049] Compared with the integrated circuit 200 of Figure 2B , the integrated circuit 300 further includes gates 221d - 221i, 231d - 231i, and 241d, active regions 222c - 222f, 232c - 232f, and 242c, and conductive segments 251h - 251r. In some embodiments, the gates 221d - 221i and the active regions 222c - 222f are disposed in the well region NW. The gates 231d - 231i, 241d and the active regions 232c - 232f, 242c are disposed on the substrate P_sub. The conductive segments 251h - 251r are arranged, for example, above the gates 221d - 221i, 231d - 231i, and 241d and the active regions 222c - 222f, 232c - 232f, and 242c.

[0050] For illustration, the gates 221d - 221f and the conductive segments 251i, 251l, 251k together correspond to the transistor 220b. The gates 221g - 221i and the conductive segments 251j, 251l, 251m together correspond to the transistor 220c. The gates 231d - 231f and the conductive segments 251n, 251p, 251q together correspond to the transistor 230b. The gates 231g - 231i and the conductive segments 251o, 251q, 251r together correspond to the transistor 230c. The gates 241c - 241d and the conductive segment 251f together correspond to the transistor 240b. In some embodiments, the gates 221d, 221f, 221g, 221i, 231a, 231c, 231d, 231f, 231g, 231i, and 241d are referred to as dummy gates.

[0051] For further illustration Figure 3B, the conductive segment 251k corresponds to the source terminal of transistor 220a and the drain terminal of transistor 220b. The gate 221e and the conductive segment 251i together correspond to the gate terminal of transistor 220b. The conductive segment 251l corresponds to the source terminal of transistor 220b and the drain terminal of transistor 220c. The gate 221h and the conductive segment 251j together correspond to the gate terminal of transistor 220c. The conductive segment 251m corresponds to the source terminal of transistor 220c. In such an embodiment, transistors 220a - 220b share the conductive segment 251k, which corresponds to transistors 220a - 220b coupled to each other through the conductive segment 251k. Transistors 220b - 220c share the conductive segment 251l, which corresponds to transistors 220b - 220c coupled to each other through the conductive segment 251l.

[0052] The conductive segment 251p corresponds to the drain terminal of transistor 230a and the source terminal of transistor 230b. The gate 231e and the conductive segment 251n together correspond to the gate terminal of transistor 230b. The conductive segment 251q corresponds to the drain terminal of transistor 230b and the source terminal of transistor 230c. The gate 231h and the conductive segment 251o together correspond to the gate terminal of transistor 230c. The conductive segment 251r corresponds to the source terminal of transistor 230c. In such an embodiment, transistors 230a - 230b share the conductive segment 251p, which corresponds to transistors 230a - 230b coupled to each other through the conductive segment 251p. Transistors 230b - 230c share the conductive segment 251q, which corresponds to transistors 230b - 230c coupled to each other through the conductive segment 251q.

[0053] The conductive segment 251h corresponds to the source of transistor 240b, and the gate 241c and the conductive segment 251h together correspond to the gate terminal of transistor 240b. In such an embodiment, transistors 240a - 240b share the active region 242b, which corresponds to transistors 240a - 240b coupled to each other.

[0054] The active region 222e is coupled to the voltage terminal VDDIO through the conductive segment 251m. The active region 232f is coupled to the voltage terminal VSS through the conductive segment 251r. The active region 242c is coupled to the voltage terminal VSS through the conductive segment 251h.

[0055] Continuing to refer to Figure 3B , for illustration, the width of the active region 232a is greater than the widths of the active regions 232b - 232f, and is also greater than the widths of the active regions 222c - 222e and 242c. In some embodiments, the width of the active region 232a is about 5 to about 6 times the widths of the active regions 232b - 232f, 222c - 222e, and 242c.

[0056] Using Figure 3A - Figure 3B the configuration of, integrated circuit 300 has multiple transistors as a pull - down circuit and the ESD primary protection circuit operates in a higher voltage domain (e.g., the voltage VDDIO is about 3.3 volts), as compared to integrated circuit 200 which has a single transistor as a pull - down circuit and the ESD primary protection circuit operates at a voltage VDDIO of about 1.8 volts.

[0057] For illustrative purposes, the configuration of Figure 3A - Figure 3B is given. Various embodiments of integrated circuit 300 are within the scope of this disclosure. For example, in some embodiments, the number of transistors included in one transistor used as a pull - down circuit is less than 3.

[0058] Now refer to Figure 3C . Figure 3C is a layout diagram in a plan view of a part of integrated circuit 300 according to some other embodiments. Regarding the embodiment of Figure 3A , elements identical to those in Figure 3C are designated with the same reference numerals for easy understanding. For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here, unless it is necessary to introduce the cooperation relationship with the elements shown in Figure 3B . Figure 3C

[0059] Compared with the integrated circuit 300 of Figure 3B , instead of having separate active regions, the transistors of integrated circuit 300’ (corresponding to the transistors 220a - 220c, 230a - 230c of Figure 3A ) include shared active regions. For illustration, transistors 220a - 220b share active region 222a, which corresponds to transistors 220a - 220b that are coupled to each other at the source region of transistor 220a and the drain region of transistor 220b. Transistors 220b - 220c share active region 222f, which corresponds to transistors 220b - 220c that are coupled to each other at the source region of transistor 220b and the drain region of transistor 220c. In addition, transistors 230a - 230b share active region 232b, which corresponds to transistors 230a - 230b that are coupled to each other at the source region of transistor 230a and the drain region of transistor 230b. Transistors 230b - 230c share active region 232d, which corresponds to transistors 230b - 230c that are coupled to each other at the source region of transistor 230b and the drain region of transistor 230c.

[0060] Using Figure 3C the configuration of, as compared to Figure 3B ​Compared with the integrated circuit 300, the integrated circuit 300' with a shared active region occupies a smaller area in the layout design.

[0061] Now refer to Figure 4A . Figure 4A is an equivalent circuit of a part of the integrated circuit 400 corresponding to the integrated circuit 100 according to some embodiments. Regarding Figure 1 the embodiments, elements identical to those in Figure 4A are designated with the same reference numerals for easy understanding. For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here, unless it is necessary to introduce the cooperation relationship with the elements shown in Figure 3A . Figure 4A the elements shown in

[0062] Compared with the integrated circuit 300 of Figure 3A , instead of having multiple transistors 220a - 220c corresponding to the pull-up circuit 120 of Figure 1 , the integrated circuit 400 includes a resistive element R coupled between the voltage terminal VDDIO and the pad 210. In some embodiments, the resistive element R is implemented by a resistor with a high resistance to provide ESD protection.

[0063] Now refer to Figure 4B . Figure 4B is a layout diagram in a plan view of a part of the integrated circuit 400 according to some embodiments of Figure 4A . Regarding Figure 4B the embodiments, elements identical to those in Figure 3B are designated with the same reference numerals for easy understanding. For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here, unless it is necessary to introduce the cooperation relationship with the elements shown in Figure 4A .

[0064] Compared with the integrated circuit 300 of Figure 3B , instead of having a structure corresponding to the transistors 220a - 220c of Figure 3A , the integrated circuit 400 includes a resistive structure RL corresponding to the pull-up circuit 120 of Figure 1 , and a well region DNW provided on the substrate P_sub. For illustration, the resistive structure is provided on the substrate P_sub, and is coupled to the voltage terminal VDDIO through the conductive segment 251m and to the active regions 232a and 242a through the conductive segment 251c. In addition, instead of being arranged on the substrate P_sub, the gates 231a, 231b, 231d, 231h and 231i and the active regions 232a - 232b, 232d and 232f are arranged in the well region DNW.

[0065] For illustrative purposes, the configuration of the integrated circuit 400 given in Figure 4A - Figure 4B is provided. Various embodiments of the integrated circuit 400 are within the scope of the present disclosure. For example, in some embodiments, the transistors 230a - 230c include separate active regions instead of having a shared active region as shown in Figure 4B .

[0066] Now refer to Figure 5A . Figure 5A is an equivalent circuit of a part of the integrated circuit 500 corresponding to the integrated circuit 100 in Figure 1 according to some embodiments. Regarding the embodiments in Figure 5A , elements identical to those in Figure 4A are designated with the same reference numerals for easy understanding. For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here, unless it is necessary to introduce the cooperation relationship with the elements shown in Figure 5A .

[0067] Compared with the integrated circuit 400 in Figure 4A , the integrated circuit 500 includes a transistor FOD corresponding to the ESD primary protection circuit 140 in Figure 1 , and a transistor 230d of the second conductivity type (i.e., N-type). For illustration, the terminals of the transistor FOD are coupled to the resistive element R and the pad 210, while the other terminal of the transistor FOD is coupled to the voltage terminal VSS and the terminal of the transistor 230d. The control terminal of the transistor FOD is coupled to the other terminal of the transistor FOD and the voltage terminal VSS. The transistor 230d is coupled in series to the transistor 230c and the voltage terminal VSS. In some embodiments, the transistors 230a - 230d together serve as the transistors of the pull-down circuit 130 corresponding to Figure 1 .

[0068] In some embodiments, the transistor FOD is implemented by a field oxide device to divert ESD charge at the pad 210. The transistor FOD is given for illustrative purposes. Various embodiments of the transistor FOD are within the scope of the present disclosure. For example, in some embodiments, the transistor FOD is a thick field oxide device with an adjustable threshold voltage.

[0069] Now refer to Figure 5B . Figure 5B is a layout diagram in a plan view of a part of the integrated circuit 500 in Figure 5A according to some embodiments. Regarding the embodiments in Figure 5B , those identical to the elements in Figure 3B and 4BElements identical to those in are designated with the same reference numerals for easy understanding. For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here, unless it is necessary to introduce the cooperation relationship with the Figure 5B elements shown.

[0070] Compared with Figure 4B the integrated circuit 400, the integrated circuit 500 includes separated active regions, gates 231j - 231l, 241d - 241m, active regions 232g - 232h and 242d - 242e, and conductive segments 251s as discussed in Figure 3B . For illustration, gates 231j - 231l and active regions 232g - 232h are disposed in the well region DNW. Gates 241d - 241h and active region 242d are disposed in the well region NW on the substrate P_sub. Gates 241i - 241m and active region 242e are disposed on the substrate P_sub. In some embodiments, conductive segment 251c is further disposed above gates 241 - 241h and active region 242d. Conductive segment 251r is further disposed above active region 232g. Conductive segment 251s is disposed above active regions 232h and 242e and gates 241i - 241m.

[0071] For illustration, gates 231j - 232h and conductive segments 251r, 251p, and 251s together correspond to transistor 230d. Specifically, gate 251p and conductive segment 251p correspond to the gate terminal of transistor 230d. Conductive segment 251r corresponds to the drain terminal of transistor 230d. Conductive segment 251s corresponds to the source terminal of transistor 230d and is coupled to the voltage terminal VSS. Gates 241d - 241m, conductive segments 251c and 251r, and substrate P_sub together correspond to transistor FOD. Specifically, conductive segment 251c corresponds to the first terminal of transistor FOD, which is coupled to pad 210. Conductive segment 251s corresponds to the second terminal of transistor FOD, which is coupled to the voltage terminal VSS and the source terminal of transistor 230d. Substrate P_sub corresponds to the third terminal of transistor FOD, which is coupled to the second terminal of transistor FOD and the voltage terminal VSS. In some embodiments, gates 241d - 241m are referred to as dummy gates.

[0072] Active region 232h is coupled to active region 242e through conductive segment 251s. Active region 242d is coupled to the resistor structure RL, active region 232a, and pad 210 through conductive segment 251c.

[0073] In some embodiments, the active region 242d is of a first conduction type (i.e., P-type), and the active region 242e is of a second conduction type (i.e., N-type). The configuration of the transistor FOD is given for illustrative purposes. Various embodiments of the transistor FOD are within the scope of the present disclosure. For example, in some embodiments, the active regions included in the transistor FOD have the same conduction type (i.e., N-type).

[0074] Continuing to refer Figure 5B , for illustration, the width of the active region 232a is greater than the width of the active regions 232g - 232h. In some embodiments, the width of the active region 232a is about 5 to about 6 times the width of the active regions 232g - 232h.

[0075] In some methods, the integrated circuit includes a transistor corresponding to the transistor 230a, but the transistor has active regions of equal width. As a result, the integrated circuit passes the human body model test at about 1.5 KV and fails at about 1.8 KV, and passes the charged device model test at 450 V and fails at 500 V. Compared with the above methods, using Figure 5A - 5B the configuration, the integrated circuit 500 provides good ESD protection for the internal circuits operating in a higher voltage domain. For example, in some embodiments of the present disclosure, the integrated circuit 500 passes the human body model test at about 2.5 KV and passes the charged device model test at about 700 V (i.e., the peak value of the current is about 6.7 A). In addition, by comparing the results of the transmission line pulse (TLP) test, the breakdown current increases from about 1.1 A as shown in some methods to about 3.2 A as shown in some embodiments of the present disclosure. In other words, compared with some methods, the integrated circuit 500 has a great improvement in the transmission line pulse test.

[0076] The configuration of Figure 5A - 5B is given for illustrative purposes. Various embodiments of the integrated circuit 500 are within the scope of the present disclosure. For example, in some embodiments, the number of transistors included in one transistor serving as a pull-down circuit is greater than 4.

[0077] Now refer to Figure 6 . Figure 6 is a flowchart of a method 600 for operating an integrated circuit 100, 200, 300, 400, or 500 according to some embodiments. It should be understood that additional operations may be provided before, during, and after the process shown in Figure 6 , and for other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchanged. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Method 600 includes the following reference Figure 2AThe described operations 610 - 620.

[0078] In operation 610, the electrostatic charge is released from the pad 210 to the voltage terminal VSS through the active regions 232a and 232b. In some embodiments, the active regions 232a and 232b have N - type conductivity, and the widths of the active regions 232a and 232b are different from each other. The active regions 232a and 232b are included in the N - type doped transistor 230 having a first breakdown voltage.

[0079] In some embodiments, the width of the active region 232a is about 5 to about 6 times the width of the active region 232b.

[0080] In some embodiments, referring Figure 3B , the electrostatic charge is released from the pad 210 to the voltage terminal VSS through the active regions 232c - 232f coupled between the active region 232b and the voltage terminal VSS. The active regions 232a - 232f have the same conductivity type. The width of the active region 232a is greater than the widths of the active regions 232b - 232f.

[0081] In some embodiments, the active regions 232c - 232f are included in the structures serving as transistors 230b - 230c, where each of the transistors 230b - 230c has a second breakdown voltage less than the first breakdown voltage.

[0082] In some embodiments, referring Figure 3B , the electrostatic charge is transferred from the pad 210 to the voltage terminal VDDIO through the active regions 222a - 222f coupled between the pad 210 and the voltage terminal VDDIO. The active regions 222a - 222f have P - type conductivity. In some embodiments, the width of the active region 232a is greater than the widths of the active regions 222a - 222f.

[0083] In operation 620, the electrostatic charge is released through an ESD primary protection circuit, which includes, for example, Figure 1 the ESD primary protection circuit 140 and Figure 2A the transistor 240. In some embodiments, the transistor 240 has a terminal coupled to the active region 232a and the voltage terminal VSS as shown. In some embodiments, the ESD primary protection circuit 140 has a trigger voltage lower than the first breakdown voltage (e.g., Figure 2A the breakdown voltage of the transistor 230).

[0084] In some embodiments, in operation 620, referring Figure 2B, the static charge is released through the active region 242a coupled to the pad 210 and the active region 242b coupled between the active region 242a and the voltage terminal VSS.

[0085] In some embodiments, the active regions 232a and 242a have a first width, and the active regions 232b and 242b have a second width that is less than the first width.

[0086] Now refer to Figure 7 . Figure 7 is a block diagram of an electronic design automation (EDA) system 700 for designing an integrated circuit layout design according to some embodiments of the present disclosure. The EDA system 700 is configured to implement Figure 6 disclosed in and incorporated with Figure 2A - 5B the method 600 further explained. In some embodiments, the EDA system 700 includes an APR system.

[0087] In some embodiments, the EDA system 700 is a general-purpose computing device, including a hardware processor 720 and a non-transitory computer-readable storage medium 760. Among other things, the storage medium 760 is encoded (i.e., stores) computer program code (instructions) 761, which is a set of executable instructions. Executing the instructions 761 by the hardware processor 720 (at least in part) represents an EDA tool that implements, for example, part or all of the method 600.

[0088] The processor 720 is electrically coupled to the computer-readable storage medium 760 through a bus 750. The processor 720 is also electrically coupled to an I / O interface 710 and a manufacturing tool 770 through the bus 750. A network interface 730 is also electrically connected to the processor 720 through the bus 750. The network interface 730 is connected to a network 740 so that the processor 720 and the computer-readable storage medium 760 can be connected to external components through the network 740. The processor 720 is configured to execute the computer program code 761 encoded in the computer-readable storage medium 760 so that the EDA system 700 can be used to execute part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 720 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0089] In one or more embodiments, the computer-readable storage medium 760 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 760 includes semiconductor or solid-state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), rigid disks, and / or optical disks. In one or more embodiments in which an optical disk is used, the computer-readable storage medium 760 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0090] In one or more embodiments, the storage medium 760 stores computer program code 761 that is configured to make the EDA system 700 (where such execution (at least in part) represents an EDA tool) available to perform part or all of the processes and / or methods. In one or more embodiments, the storage medium 760 also stores information that facilitates the performance of part or all of the processes and / or methods. In one or more embodiments, the storage medium 760 stores a library 762 of standard cells, including such standard cells as disclosed herein, e.g., cells including the transistors 220-240 discussed above with respect to Figure 2A the units discussed above with respect to

[0091] The EDA system 700 includes an I / O interface 710. The I / O interface 710 is coupled to an external circuit. In one or more embodiments, the I / O interface 710 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor direction keys for transmitting information and commands to the processor 720.

[0092] The EDA system 700 also includes a network interface 730 coupled to the processor 720. The network interface 730 allows the EDA system 700 to communicate with a network 740 to which one or more other computer systems are connected. The network interface 730 includes: a wireless network interface, e.g., Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, e.g., Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods are implemented in two or more systems 700.

[0093] The EDA system 700 also includes a fabrication tool 770 coupled to the processor 720. The fabrication tool 770 is configured to fabricate an integrated circuit according to a design file processed by the processor 720, e.g., Figure 1 the integrated circuit 100 shown above.

[0094] The EDA system 700 is configured to receive information through the I / O interface 710. The information received through the I / O interface 710 includes one or more of instructions, data, design rules, a standard cell library, and / or other parameters for processing by the processor 720. The information is transmitted to the processor 720 via the bus 750. The EDA system 700 is configured to receive UI-related information through the I / O interface 710. This information is stored in the computer-readable medium 760 as a user interface (UI) 763.

[0095] In some embodiments, part or all of the process and / or method is implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in of a software application. In some embodiments, at least one of the process and / or method is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by the EDA system 700. In some embodiments, tools such as those available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool are used to generate a layout diagram including standard cells.

[0096] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as, for example, an optical disc (e.g., DVD), a magnetic disk (e.g., hard disk), a semiconductor memory (e.g., ROM, RAM), a memory card, etc.

[0097] Figure 8 is a block diagram of an IC manufacturing system 800 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the IC manufacturing system 800 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0098] In Figure 8In the present invention, the IC manufacturing system 800 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to manufacturing IC devices 840, such as a design room 810, a mask room 820, and an IC manufacturer / fabricator ("fab") 830. The entities in the IC manufacturing system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 810, the mask room 820, and the IC manufacturer / fabricator 830 are owned by a single larger company. In some embodiments, two or more of the design room 810, the mask room 820, and the IC manufacturer / fabricator 830 coexist in a public facility and use public resources.

[0099] The design office (or design team) 810 generates an IC design layout 811. The IC design layout 811 includes a layout for an IC device 840 (e.g., Figure 2B , Figure 3B , Figure 4B and Figure 5B The various geometric patterns (e.g., Figure 2B , Figure 3B , Figure 4B and Figure 5B The IC layout design depicted). The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layers of the various components that make up the IC device 840 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 811 includes various IC features (e.g., active areas, gate electrodes, source and drain, conductive segments or vias for interlayer interconnection, and openings for pads) formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room 810 implements an appropriate design process to form the IC design layout diagram 811. The design process includes one or more of logical design, physical design, or layout and routing. The IC design layout diagram 811 is presented in one or more data files with geometric pattern information. For example, the IC design layout diagram 811 can be expressed in a GDSII file format or a DFII file format.

[0100] The mask chamber 820 includes data preparation 821 and mask fabrication 822. The mask chamber 820 uses the IC design layout 811 to fabricate one or more masks 823, which are used to fabricate the respective layers of the IC device 840 according to the IC design layout 811. The mask chamber 820 performs mask data preparation 821, in which the IC design layout 811 is converted into a representative data file ("RDF"). The mask data preparation 821 provides the RDF to the mask fabrication 822. The mask fabrication 822 includes a mask writer. The mask writer converts the RDF into an image on a substrate, e.g., a mask (reticle) 823 or a semiconductor wafer 833. The mask data preparation 821 processes the IC design layout 811 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer / fabricator 830. In Figure 8 it, the data preparation 821 and the mask fabrication 822 are shown as separate elements. In some embodiments, the data preparation 821 and the mask fabrication 822 may be collectively referred to as mask data preparation.

[0101] In some embodiments, the data preparation 821 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, e.g., image errors that may be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 811. In some embodiments, the data preparation 821 includes further resolution enhancement techniques (RET), e.g., off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0102] In some embodiments, the data preparation 821 includes a mask rule checker (MRC), which utilizes a set of mask creation rules to check the IC design layout 811 that has already been processed in the OPC. The set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margins to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 811 to compensate for the limitations during the mask fabrication 822, which may undo some of the modifications performed by the OPC to meet the mask creation rules.

[0103] In some embodiments, data preparation 821 includes lithography process check (LPC), which simulates the process to be implemented by the IC manufacturer / fabricator 830 to fabricate the IC device 840. The LPC simulates the process based on the IC design layout 811 to create a simulated fabricated device, e.g., the IC device 840. The process parameters in the LPC simulation can include parameters associated with the respective processes of the IC manufacturing cycle, parameters associated with the tools used for manufacturing the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination thereof. In some embodiments, after creating the simulated fabricated device through LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 811.

[0104] It should be understood that the above description of data preparation 821 has been simplified for clarity. In some embodiments, data preparation 821 includes additional features such as logic operation (LOP) to modify the IC design layout 811 according to the manufacturing rules. Additionally, the processing applied to the IC design layout 811 during data preparation 821 can be performed in various different orders.

[0105] After data preparation 821 and during mask manufacturing 822, a mask 823 or a set of masks 823 is manufactured based on the modified IC design layout 811. In some embodiments, mask manufacturing 822 includes performing one or more lithographic exposures based on the IC design layout 811. In some embodiments, based on the modified IC design layout 811, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on the mask (photomask or reticle) 823. The mask 823 can be formed by various techniques. In some embodiments, the mask 823 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) for exposing an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 823 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 823 is formed using phase-shift techniques. In the phase-shift mask (PSM) version of the mask 823, each feature in the pattern formed on the phase-shift mask is configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 822 are used in various processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in the semiconductor wafer 833, in an etching process to form various etched regions in the semiconductor wafer 833, and / or in other suitable processes.

[0106] IC manufacturer / fabricator 830 includes wafer fabrication 832. IC manufacturer / fabricator 830 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer / fabricator 830 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing facility can provide other services for the foundry enterprise.

[0107] IC manufacturer / fabricator 830 uses one or more masks 823 fabricated by mask chamber 820 to fabricate IC device 840. Thus, IC manufacturer / fabricator 830 uses IC design layout 811 at least indirectly to fabricate IC device 840. In some embodiments, semiconductor wafer 833 is fabricated by IC manufacturer / fabricator 830 using one or more masks 823 to form IC device 840. In some embodiments, IC fabrication includes performing one or more photolithography exposures at least indirectly based on IC design layout 811. Semiconductor wafer 833 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 833 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent fabrication steps).

[0108] As described above, the integrated circuit of the present disclosure provides an ESD protection circuit that implements a drain ballast transistor coupled to a pad. During an ESD strike at the pad, the drain ballast transistor is capable of withstanding and releasing the ESD current until the ESD primary protection circuit conducts to release the ESD current.

[0109] In some embodiments, an integrated circuit includes a pull-up circuit, an electrostatic discharge (ESD) primary protection circuit, and a pull-down circuit. The pull-up circuit is coupled between a pad and a first voltage terminal. The ESD primary protection circuit includes a first terminal coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal. The pull-down circuit has a first terminal coupled to the pad, the ESD primary protection circuit, and the pull-up circuit, and a second terminal coupled to the second voltage terminal. The pull-down circuit includes at least one first transistor of a first conductivity type, a first terminal of the at least one first transistor being coupled to the first terminal of the pull-down circuit. The breakdown voltage of the at least one first transistor is greater than the trigger voltage of the ESD primary protection circuit. In some embodiments, the pull-down circuit further includes a plurality of second transistors of the first conductivity type. The second terminal of the at least one first transistor is coupled in series with the plurality of second transistors. The breakdown voltage of the at least one first transistor is greater than the breakdown voltage of each of the plurality of second transistors. In some embodiments, the ESD primary protection circuit further includes a second transistor of the first conductivity type. The at least one first transistor is substantially the same as the second transistor. In some embodiments, the pull-up circuit includes at least one third transistor of a second conductivity type, coupled to the at least one first transistor, wherein the second conductivity type is different from the first conductivity type. The absolute value of the breakdown voltage of the at least one first transistor is N times the absolute value of the breakdown voltage of the at least one third transistor, wherein N is greater than about 2. In some embodiments, the at least one first transistor includes a plurality of first transistors, wherein a first one of the plurality of first transistors is coupled to the first terminal of the pull-down circuit. The ESD primary protection circuit further includes a plurality of second transistors of the first conductivity type, wherein a first one of the plurality of second transistors is coupled to the first terminal of the ESD primary protection circuit. The breakdown voltage of the first one of the plurality of first transistors and the breakdown voltage of the first one of the plurality of second transistors have substantially the same value. In some embodiments, the ESD primary protection circuit further includes a second transistor of the first conductivity type, coupled between the first terminal and the second terminal of the ESD primary protection circuit. The pull-up circuit includes a resistive element, coupled to the second transistor. The pull-down circuit further includes a plurality of third transistors of the first conductivity type, coupled between the at least one first transistor and the second voltage terminal. The breakdown voltage of the at least one first transistor and the breakdown voltage of the second transistor are greater than the breakdown voltage of each of the plurality of third transistors. In some embodiments, the at least one first transistor further includes a first-stage transistor and a plurality of second-stage transistors. The first-stage transistor has a first terminal coupled to the first terminal of the pull-down circuit, and a second terminal coupled in series with the plurality of second-stage transistors. The breakdown voltage of the first-stage transistor is N times the breakdown voltage of each of the plurality of second-stage transistors, wherein N is greater than 2.

[0110] An integrated circuit is also disclosed, which includes a resistive structure, a first active region, a second active region, a third active region, and a fourth active region. The resistive structure is coupled between a first voltage terminal and a pad. The first active region is coupled to the pad and the resistive structure. The second active region is coupled between the first active region and a second voltage terminal, which is different from the first voltage terminal. A third active region of a first type is coupled to the pad and the first active region. A fourth active region of the first type is coupled between the third active region and the second voltage terminal, wherein the width of the third active region is greater than the width of the fourth active region. The first active region and the second active region are included in a structure serving as a first transistor, and the third active region and the fourth active region are included in a structure serving as a second transistor. The second transistor is configured to release electrostatic charges injected from the pad when the first transistor is turned off. In some embodiments, the width of the fourth active region is about 5 times to about 6 times the width of the third active region. In some embodiments, the resistive structure includes: a well region of a first type, a fifth active region of a second type, and a sixth active region of the second type, where the second type is different from the first type, the fifth active region and the sixth active region have the same width and are disposed in the well region, wherein the fifth active region is coupled to the pad, the first active region, and the fourth active region, and the sixth active region is coupled between the fifth active region and the first voltage terminal. The fifth active region and the sixth active region are included in a structure serving as a third transistor. The first active region and the second active region are of the first type, and the first active region and the fourth active region have the same width, which is greater than the width of the fifth active region and the sixth active region. In some embodiments, the integrated circuit further includes a seventh active region of the first type and an eighth active region of the first type. The seventh active region of the first type is disposed adjacent to the second active region and coupled to the second voltage terminal, wherein the second active region and the seventh active region are included in a structure serving as a fourth transistor, and the width of the first active region is greater than the width of the seventh active region. The eighth active region of the first type and a ninth active region of the first type have the same width and are included in a structure serving as a fifth transistor, wherein the width of the fourth active region is greater than the width of the eighth active region and the ninth active region. The integrated circuit further includes: a plurality of third transistors coupled in series between the pad and the first voltage terminal; and a plurality of fifth transistors coupled in series between the second transistor and the second voltage terminal. In some embodiments, the integrated circuit further includes a plurality of fifth active regions of the first type and a plurality of sixth active regions of the first type. One of the plurality of fifth active regions is coupled to the second voltage terminal, and another of the plurality of fifth active regions and the third active region are included in a structure serving as a third transistor, wherein each of the plurality of fifth active regions has a width less than the width of the fourth active region.The sixth active region is coupled to the second voltage terminal, and the width of the first active region is greater than the width of the sixth active region, wherein the sixth active region and the second active region are included in a structure serving as a fourth transistor. The resistive structure includes a well region of a first type and a plurality of seventh active regions of a second type, different from the first type, disposed in the well region. One of the plurality of seventh active regions is coupled to the pad, the first active region, and the fourth active region, and another one of the plurality of seventh active regions is coupled to the first voltage terminal. The width of the plurality of seventh active regions is less than the width of the fourth active region. In some embodiments, the integrated circuit further includes a first well region of the first type and a second well region of the first type, and a fifth active region of the first type and a sixth active region of the first type. The fifth active region and the sixth active region are disposed in the second well region. The fifth active region and the sixth active region have the same width and are included in a structure serving as a third transistor, wherein the width of the fourth active region is greater than the width of the fifth active region and the sixth active region. The resistive structure includes a resistive layer coupled between the pad and the first voltage terminal. The first active region is of a second type different from the first type and is disposed in the first well region, the second active region is of the first type, and the third through sixth active regions are disposed in the second well region. The integrated circuit further includes a plurality of third transistors coupled between the second transistor and the second voltage terminal. In some embodiments, the number of the plurality of third transistors is equal to or greater than 3.

[0111] Also disclosed is a method, which includes the following operations: releasing electrostatic charges from a pad to a first voltage terminal through a first active region and a second active region, where the first active region is coupled to the pad and the second active region is coupled between the first active region and the first voltage terminal. The first active region and the second active region have the same conductivity type and different widths from each other, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and releasing electrostatic charges through an ESD primary protection circuit, which has a first terminal coupled to the first active region and a second terminal coupled to the first voltage terminal, where the trigger voltage of the ESD primary protection circuit is lower than the first breakdown voltage. In some embodiments, the width of the first active region is about 5 to about 6 times the width of the second active region. In some embodiments, the method further includes the following operation: releasing electrostatic charges from the pad to the first terminal through a plurality of third active regions, where the plurality of third active regions are coupled between the second active region and the first voltage terminal. The first active region, the second active region, and the plurality of third active regions have a first conductivity type. The plurality of third active regions are included in a structure serving as a plurality of second transistors, and each of the plurality of second transistors has a second breakdown voltage less than the first breakdown voltage. In some embodiments, the width of the first active region is greater than the widths of the second active region and the plurality of third active regions. In some embodiments, the method further includes the following operation: releasing electrostatic charges from the pad to a second voltage terminal through a plurality of fourth active regions, where the plurality of fourth active regions are coupled between the pad and the second voltage terminal. The plurality of fourth active regions have a second conductivity type different from the first conductivity type. The width of the first active region is greater than the widths of the plurality of fourth active regions. In some embodiments, the operation of releasing static charges through the ESD primary protection circuit includes: releasing electrostatic charges through a third active region and a fourth active region, where the third active region is coupled to the pad and the first active region, and the fourth active region is coupled between the third active region and the first voltage terminal. The first active region and the third active region have a first width, and the second active region and the fourth active region have a second width less than the first width.

[0112] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0113] Example 1 is an integrated circuit, comprising: a pull-up circuit coupled between a pad and a first voltage terminal; an electrostatic discharge (ESD) primary protection circuit including a first terminal coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal; and a pull-down circuit including a first terminal coupled to the pad, the ESD primary protection circuit, and the pull-up circuit, and a second terminal coupled to the second voltage terminal, wherein the pull-down circuit includes at least one first transistor of a first conduction type, a first terminal of the at least one first transistor being coupled to the first terminal of the pull-down circuit; wherein a breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary protection circuit.

[0114] Example 2 is the integrated circuit according to Example 1, wherein the pull-down circuit further includes: a plurality of second transistors of the first conduction type; wherein the second terminal of the at least one first transistor is coupled in series with the plurality of second transistors; wherein the breakdown voltage of the at least one first transistor is greater than the breakdown voltage of each of the plurality of second transistors.

[0115] Example 3 is the integrated circuit according to Example 1, wherein the ESD primary protection circuit further includes: a second transistor of the first conduction type; wherein the at least one first transistor is substantially the same as the second transistor.

[0116] Example 4 is the integrated circuit according to Example 3, wherein the pull-up circuit includes: at least one third transistor of a second conduction type, coupled to the at least one first transistor, wherein the second conduction type is different from the first conduction type; wherein an absolute value of the breakdown voltage of the at least one first transistor is N times an absolute value of the breakdown voltage of the at least one third transistor, wherein N is greater than about 2.

[0117] Example 5 is the integrated circuit according to Example 1, wherein the at least one first transistor includes: a plurality of first transistors, wherein a first one of the plurality of first transistors is coupled to the first terminal of the pull-down circuit; wherein the ESD primary protection circuit further includes a plurality of second transistors of the first conduction type, wherein a first one of the plurality of second transistors is coupled to the first terminal of the ESD primary protection circuit; wherein the breakdown voltage of the first one of the plurality of first transistors and the breakdown voltage of the first one of the plurality of second transistors have substantially the same value.

[0118] Example 6 is the integrated circuit described in Example 1, wherein the ESD primary protection circuit further includes: a second transistor of the first conduction type, coupled between a first terminal and a second terminal of the ESD primary protection circuit; wherein the pull-up circuit includes a resistive element, coupled to the second transistor; wherein the pull-down circuit further includes a plurality of third transistors of the first conduction type, coupled between the at least one first transistor and the second voltage terminal; wherein the breakdown voltage of the at least one first transistor and the breakdown voltage of the second transistor are greater than the breakdown voltage of each of the plurality of third transistors.

[0119] Example 7 is the integrated circuit described in Example 1, wherein the at least one first transistor further includes: a first-stage transistor and a plurality of second-stage transistors; wherein the first-stage transistor has: a first terminal, coupled to a first terminal of the pull-down circuit; and a second terminal, serially coupled to the plurality of second-stage transistors; wherein the breakdown voltage of the first-stage transistor is N times the breakdown voltage of each of the plurality of second-stage transistors, wherein N is greater than 2.

[0120] Example 8 is an integrated circuit, including: a resistive structure, coupled between a first voltage terminal and a pad; a first active region, coupled to the pad and the resistive structure; a second active region, coupled between the first active region and a second voltage terminal, the second voltage terminal being different from the first voltage terminal; a third active region of a first type, coupled to the pad and the first active region; and a fourth active region of the first type, coupled between the third active region and the second voltage terminal, wherein the width of the third active region is greater than the width of the fourth active region; wherein the first active region and the second active region are included in a structure serving as a first transistor, and the third active region and the fourth active region are included in a structure serving as a second transistor; wherein the second transistor is configured to release electrostatic charge injected from the pad when the first transistor is turned off.

[0121] Example 9 is the integrated circuit described in Example 8, wherein the width of the third active region is about 5 times to about 6 times the width of the fourth active region.

[0122] Example 10 is the integrated circuit described in Example 8, wherein the resistive structure includes: the well region of the first type; and the fifth active region of the second type and the sixth active region of the second type, the second type being different from the first type, the fifth active region and the sixth active region having the same width and being disposed in the well region, wherein the fifth active region is coupled to the pad, the first active region, and the third active region, and the sixth active region is coupled between the fifth active region and the first voltage terminal; wherein the fifth active region and the sixth active region are included in the structure serving as the third transistor; wherein the first active region and the second active region have the first type, and the first active region and the third active region have the same width, which is greater than the width of the fifth active region and the sixth active region.

[0123] Example 11 is the integrated circuit described in Example 10, further including: the seventh active region of the first type, disposed adjacent to the second active region and coupled to the second voltage terminal, wherein the second active region and the seventh active region are included in the structure serving as the fourth transistor, and the width of the first active region is greater than the width of the seventh active region; and the eighth active region of the first type and the ninth active region of the first type, the eighth active region and the ninth active region having the same width and being included in the structure serving as the fifth transistor, wherein the width of the third active region is greater than the width of the eighth active region and the ninth active region; wherein the integrated circuit further includes: a plurality of the third transistors, serially coupled between the pad and the first voltage terminal; and a plurality of the fifth transistors, serially coupled between the second transistor and the second voltage terminal.

[0124] Example 12 is the integrated circuit described in Example 8, further comprising: a plurality of fifth active regions of the first type, wherein one of the plurality of fifth active regions is coupled to the second voltage terminal, and another of the plurality of fifth active regions and the fourth active region are included in a structure serving as a third transistor, wherein each of the plurality of fifth active regions has a width smaller than that of the third active region; and a sixth active region of the first type, wherein the sixth active region is coupled to the second voltage terminal, and the width of the first active region is greater than the width of the sixth active region, wherein the sixth active region and the second active region are included in a structure serving as a fourth transistor; wherein the resistance structure comprises: a well region of the first type; a plurality of seventh active regions of a second type, disposed in the well region, the second type being different from the first type, wherein one of the plurality of seventh active regions is coupled to the pad, the first active region, and the third active region, and another of the plurality of seventh active regions is coupled to the first voltage terminal; wherein the width of the plurality of seventh active regions is smaller than the width of the third active region.

[0125] Example 13 is the integrated circuit described in Example 8, further comprising: a first well region of the first type and a second well region of the first type; and a fifth active region of the first type and a sixth active region of the first type, the fifth active region and the sixth active region being disposed in the second well region, wherein the fifth active region and the sixth active region have the same width and are included in a structure serving as a third transistor, wherein the width of the third active region is greater than the width of the fifth active region and the sixth active region; wherein the resistance structure comprises a resistance layer coupled between the pad and the first voltage terminal; wherein the first active region has a second type different from the first type, and the first active region is disposed in the first well region, the second active region is of the first type, and the third active region to the sixth active region are disposed in the second well region; wherein the integrated circuit further comprises: a plurality of the third transistors, coupled between the second transistor and the second voltage terminal.

[0126] Example 14 is the integrated circuit described in Example 13, wherein the number of the plurality of third transistors is equal to or greater than 3.

[0127] Example 15 is a method of operating an integrated circuit, including: releasing electrostatic charge from a pad to a first voltage terminal through a first active region and a second active region, where the first active region is coupled to the pad and the second active region is coupled between the first active region and the first voltage terminal; wherein, the first active region and the second active region have the same conduction type and different widths from each other, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and releasing the electrostatic charge through an ESD primary protection circuit, the ESD primary protection circuit having a first terminal coupled to the first active region and a second terminal coupled to the first voltage terminal, wherein the trigger voltage of the ESD primary protection circuit is lower than the first breakdown voltage.

[0128] Example 16 is the method of Example 15, wherein the width of the first active region is about 5 times to about 6 times the width of the second active region.

[0129] Example 17 is the method of Example 15, further including: releasing the electrostatic charge from the pad to the first terminal through a plurality of third active regions, the plurality of third active regions being coupled between the second active region and the first voltage terminal; wherein, the first active region, the second active region, and the plurality of third active regions have a first conduction type; wherein, the plurality of third active regions are included in a structure serving as a plurality of second transistors, each of the plurality of second transistors having a second breakdown voltage less than the first breakdown voltage.

[0130] Example 18 is the method of Example 17, wherein the width of the first active region is greater than the widths of the second active region and the plurality of third active regions.

[0131] Example 19 is the method of Example 17, further including: releasing electrostatic charge from the pad to a second voltage terminal through a plurality of fourth active regions, the plurality of fourth active regions being coupled between the pad and the second voltage terminal; wherein, the plurality of fourth active regions have a second conduction type different from the first conduction type; wherein, the width of the first active region is greater than the widths of the plurality of fourth active regions.

[0132] Example 20 is the method described in Example 15, wherein releasing the static charge through the ESD primary protection circuit includes: releasing the static charge through a third active region and a fourth active region, the third active region being coupled to the pad and the first active region, and the fourth active region being coupled between the third active region and the first voltage terminal; wherein the first active region and the third active region have a first width, and the second active region and the fourth active region have a second width smaller than the first width.

Claims

1. An integrated circuit, comprising: A pull-up circuit coupled between a pad and a first voltage terminal; An electrostatic discharge (ESD) primary protection circuit including a first terminal coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal; And A pull-down circuit including a first terminal coupled to the pad, the ESD primary protection circuit, and the pull-up circuit, and a second terminal coupled to the second voltage terminal, wherein the pull-down circuit includes at least one first transistor of a first conduction type, and a first terminal of the at least one first transistor is coupled to the first terminal of the pull-down circuit; Wherein a breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary protection circuit; Wherein, in operation, when the ESD primary protection circuit and the pull-down circuit are configured to discharge an ESD current flowing from the pad to the second voltage terminal, the pull-up circuit is configured to operate using a first supply voltage received from the first voltage terminal.

2. The integrated circuit according to claim 1, wherein, The pull-down circuit further includes: A plurality of second transistors of the first conduction type; Wherein a second terminal of the at least one first transistor is coupled in series with the plurality of second transistors; Wherein a breakdown voltage of the at least one first transistor is greater than a breakdown voltage of each of the plurality of second transistors.

3. The integrated circuit according to claim 1, wherein The ESD primary protection circuit further includes: A second transistor of the first conduction type; Wherein the at least one first transistor is the same as the second transistor.

4. The integrated circuit according to claim 3, wherein, The pull-up circuit includes: At least one third transistor of a second conduction type coupled to the at least one first transistor, wherein the second conduction type is different from the first conduction type; Wherein an absolute value of a breakdown voltage of the at least one first transistor is N times an absolute value of a breakdown voltage of the at least one third transistor, where N is greater than 2.

5. The integrated circuit according to claim 1, wherein The at least one first transistor includes: A plurality of first transistors, wherein a first transistor of the plurality of first transistors is coupled to the first terminal of the pull-down circuit; Wherein the ESD primary protection circuit further includes a plurality of second transistors of the first conduction type, wherein a first transistor of the plurality of second transistors is coupled to the first terminal of the ESD primary protection circuit; Wherein a breakdown voltage of the first transistor of the plurality of first transistors and a breakdown voltage of the first transistor of the plurality of second transistors have the same value.

6. The integrated circuit according to claim 1, wherein, The ESD primary protection circuit further includes: A second transistor of the first conduction type coupled between the first terminal and the second terminal of the ESD primary protection circuit; Wherein the pull-up circuit includes a resistive element coupled to the second transistor; Wherein the pull-down circuit further includes a plurality of third transistors of the first conduction type coupled between the at least one first transistor and the second voltage terminal; Among them, the breakdown voltage of the at least one first transistor and the breakdown voltage of the second transistor are greater than the breakdown voltage of each of the plurality of third transistors.

7. The integrated circuit according to claim 1, wherein, The at least one first transistor further includes: a first-stage transistor and a plurality of second-stage transistors; Among them, the first-stage transistor has: a first terminal coupled to the first terminal of the pull-down circuit; and a second terminal serially coupled to the plurality of second-stage transistors; Among them, the breakdown voltage of the first-stage transistor is N times the breakdown voltage of each of the plurality of second-stage transistors, where N is greater than 2.

8. An integrated circuit, comprising: a resistive structure coupled between a first voltage terminal and a pad; a first active region coupled to the pad and the resistive structure; a second active region coupled between the first active region and a second voltage terminal, the second voltage terminal being different from the first voltage terminal; a third active region of a first type coupled to the pad and the first active region; and a fourth active region of the first type coupled between the third active region and the second voltage terminal, wherein the width of the third active region is greater than the width of the fourth active region; Among them, the first active region and the second active region are included in a structure serving as a first transistor, and the third active region and the fourth active region are included in a structure serving as a second transistor; Among them, in operation, the resistive structure is configured to operate using a first supply voltage received from the first voltage terminal, and the second transistor is configured to release electrostatic charge injected from the pad when the first transistor is turned off.

9. The integrated circuit according to claim 8, wherein, The width of the third active region is 5 to 6 times the width of the fourth active region.

10. The integrated circuit according to claim 8, wherein, The resistive structure includes: a well region of the first type; and a fifth active region of a second type and a sixth active region of the second type, the second type being different from the first type, the fifth active region and the sixth active region having the same width and being disposed in the well region, wherein the fifth active region is coupled to the pad, the first active region, and the third active region, and the sixth active region is coupled between the fifth active region and the first voltage terminal; Among them, the fifth active region and the sixth active region are included in a structure serving as a third transistor; Among them, the first active region and the second active region have the first type, and the first active region and the third active region have the same width, which is greater than the width of the fifth active region and the sixth active region.

11. The integrated circuit according to claim 10, further comprising: a seventh active region of the first type disposed adjacent to the second active region and coupled to the second voltage terminal, wherein the second active region and the seventh active region are included in a structure serving as a fourth transistor, and the width of the first active region is greater than the width of the seventh active region; and The eighth active region of the first type and the ninth active region of the first type, the eighth active region and the ninth active region having the same width and being included in a structure serving as a fifth transistor, wherein the width of the third active region is greater than the widths of the eighth active region and the ninth active region; Wherein, the integrated circuit further includes: A plurality of the third transistors, serially coupled between the pad and the first voltage terminal; and A plurality of the fifth transistors, serially coupled between the second transistor and the second voltage terminal.

12. The integrated circuit according to claim 8, further including: A plurality of fifth active regions of the first type, wherein one of the plurality of fifth active regions is coupled to the second voltage terminal, and another one of the plurality of fifth active regions and the fourth active region are included in a structure serving as a third transistor, wherein each of the plurality of fifth active regions has a width less than the width of the third active region; and A sixth active region of the first type, wherein the sixth active region is coupled to the second voltage terminal, and the width of the first active region is greater than the width of the sixth active region, wherein the sixth active region and the second active region are included in a structure serving as a fourth transistor; Wherein, the resistance structure includes: A well region of the first type; A plurality of seventh active regions of a second type, disposed in the well region, the second type being different from the first type, wherein one of the plurality of seventh active regions is coupled to the pad, the first active region, and the third active region, and another one of the plurality of seventh active regions is coupled to the first voltage terminal; Wherein, the widths of the plurality of seventh active regions are less than the width of the third active region.

13. The integrated circuit according to claim 8, further including: A first well region of the first type and a second well region of the first type; And A fifth active region of the first type and a sixth active region of the first type, the fifth active region and the sixth active region being disposed in the second well region, wherein the fifth active region and the sixth active region have the same width and are included in a structure serving as a third transistor, wherein the width of the third active region is greater than the widths of the fifth active region and the sixth active region; Wherein, the resistance structure includes a resistance layer coupled between the pad and the first voltage terminal; Wherein, the first active region has a second type different from the first type, and the first active region is disposed in the first well region, the second active region is of the first type, and the third active region to the sixth active region are disposed in the second well region; Wherein, the integrated circuit further includes: A plurality of the third transistors, coupled between the second transistor and the second voltage terminal.

14. The integrated circuit according to claim 13, wherein, The number of the multiple third transistors is equal to or greater than 3.

15. A method of operating an integrated circuit, comprising: releasing electrostatic charge from a pad to a first voltage terminal through a first active region and a second active region, the first active region being coupled to the pad, and the second active region being coupled between the first active region and the first voltage terminal; wherein the first active region and the second active region have the same conduction type and different widths from each other, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and releasing the electrostatic charge through an ESD primary protection circuit having a first terminal coupled to the first active region and a second terminal coupled to the first voltage terminal, wherein a trigger voltage of the ESD primary protection circuit is lower than the first breakdown voltage.

16. The method according to claim 15, wherein, The width of the first active region is 5 to 6 times the width of the second active region.

17. The method according to claim 15, further comprising: releasing the electrostatic charge from the pad to the first terminal through a plurality of third active regions, the plurality of third active regions being coupled between the second active region and the first voltage terminal; wherein the first active region, the second active region, and the plurality of third active regions have a first conduction type; wherein the plurality of third active regions are included in a structure serving as a plurality of second transistors, each of the plurality of second transistors having a second breakdown voltage less than the first breakdown voltage.

18. The method according to claim 17, wherein, The width of the first active region is greater than the widths of the second active region and the plurality of third active regions.

19. The method according to claim 17, further comprising: releasing electrostatic charge from the pad to a second voltage terminal through a plurality of fourth active regions, the plurality of fourth active regions being coupled between the pad and the second voltage terminal; wherein the plurality of fourth active regions have a second conduction type different from the first conduction type; wherein the width of the first active region is greater than the widths of the plurality of fourth active regions.

20. The method according to claim 15, wherein Releasing the electrostatic charge through the ESD primary protection circuit includes: releasing the electrostatic charge through a third active region and a fourth active region, the third active region being coupled to the pad and the first active region, and the fourth active region being coupled between the third active region and the first voltage terminal; wherein the first active region and the third active region have a first width, and the second active region and the fourth active region have a second width less than the first width.

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