Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a substrate; a first gate structure, a second gate structure, and a third gate structure; and a first source / drain region. The first gate structure, the second gate structure, and the third gate structure are located above the substrate and arranged along a first direction. The first gate structure, the second gate structure, and the third gate structure extend in a second direction different from the first direction, and the second gate structure is located between the first gate structure and the third gate structure. The first source / drain region is located between the first gate structure and the third gate structure, and is located at one end of the second gate structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Integrated circuits (ICs) are typically designed to implement a variety of devices, including, for example, transistors, resistors, capacitors, etc. These devices are typically designed to form circuits using connections of conductive traces. Increasingly dense ICs have yielded benefits in terms of speed, functionality, and cost, but have also led to increasingly difficult design and manufacturing problems. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a substrate; a first gate structure, a second gate structure, and a third gate structure, wherein the first gate structure, the second gate structure, and the third gate structure are located above the substrate and arranged along a first direction, wherein the first gate structure, the second gate structure, and the third gate structure extend in a second direction different from the first direction, and the second gate structure is located between the first gate structure and the third gate structure; and a first source / drain region, wherein the first source / drain region is located between the first gate structure and the third gate structure and at one end of the second gate structure.

[0004] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first semiconductor fin and a second semiconductor fin; a first gate structure, the first gate structure spanning the first semiconductor fin and the second semiconductor fin; a second gate structure, the second gate structure spanning the second semiconductor fin and spaced apart from the first semiconductor fin; and a first epitaxial structure and a second epitaxial structure, the first epitaxial structure and the second epitaxial structure being located above the first semiconductor fin and on opposite sides of the first gate structure, wherein the first epitaxial structure and the second epitaxial structure have different lengths.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming an active region above a substrate; forming a gate structure above the substrate and across the active region, wherein the gate structure has a substantially constant spacing; removing a portion of at least one of the gate structures to expose a portion of the active region; and forming a first epitaxial structure on at least the exposed portion of the active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] FIG. 1A to FIG. 6D Methods in various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure are shown.

[0008] Fig. 7A is a top view of a semiconductor device at various stages in accordance with some embodiments.

[0009] Figure 7B It is along Fig. 7A A cross-sectional view taken along line BB.

[0010] Figure 7C It is along Fig. 7A Cross-sectional view taken along line CC.

[0011] Fig.7D It is along Fig. 7A A cross-sectional view taken along line DD.

[0012] Figure 8 is a flow chart of a method for forming a semiconductor device according to some embodiments of the present disclosure.

[0013] Fig. 9 is a top view of a semiconductor device at various stages in accordance with some embodiments.

[0014] Fig.10 is a layout diagram of an integrated circuit according to some embodiments of the present disclosure.

[0015] Fig.11 is a layout diagram of an integrated circuit according to some embodiments of the present disclosure.

[0016] Fig.12 is a layout diagram of an integrated circuit according to some embodiments of the present disclosure.

[0017] Fig.13 is a layout diagram of an integrated circuit according to some embodiments of the present disclosure.

[0018] Fig.14 is a layout diagram of an integrated circuit according to some embodiments of the present disclosure.

[0019] Fig.15 is a flowchart of a method for generating an IC layout diagram according to some embodiments of the present disclosure.

[0020] Fig.16is a block diagram of an IC device design system according to some embodiments of the present disclosure.

[0021] Fig.17 is a block diagram of an IC manufacturing system 1700 and an IC manufacturing flow associated therewith, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0024] As used herein, "about," "approximately," or "substantially" generally means within 20%, within 10%, or within 5% of a given value or range. The values ​​given herein are approximate, which means that the term "about," "approximately," "approximately," or "substantially" can be inferred in the absence of explicit statement.

[0025] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. In general, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, smaller spacing than would otherwise be obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are then used to pattern the fins.

[0026] Some embodiments of the present disclosure relate to semiconductor devices with cut gate structures. Cut gate structures (including removal of dummy gates) improve utilization of wiring resources. Removal of dummy gates also reduces power consumption and parasitic capacitance of semiconductor devices. Below, these embodiments are discussed in the context of forming a FinFET transistor with multiple fins on a bulk semiconductor substrate.

[0027] FIG. 1A to FIG. 6D A method in various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure is shown.Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. Figure 1A is a top view of a method for manufacturing a semiconductor device in various stages according to some embodiments, Figure 1B It is along Figure 1A A cross-sectional view taken along line BB of Figure 1C It is along Figure 1A A cross-sectional view taken along line CC of Figure 1D It is along Figure 1A A cross-sectional view taken along line DD of FIG. 1 is provided. The substrate 110 includes a first semiconductor fin 112 and a second semiconductor fin 114 protruding from a top surface of the substrate 110. In some embodiments, the first semiconductor fin 112 and the second semiconductor fin 114 include silicon. It should be noted that Figures 1A-1D The numbers of the first semiconductor fins 112 and the second semiconductor fins 114 in FIG. 1 are illustrative and should not limit the scope of protection claimed in the present disclosure.

[0028] In some embodiments, substrate 110 may be a semiconductor material and may include, for example, a gradient layer or a buried oxide. In some embodiments, substrate 110 includes bulk silicon (e.g., p-type, n-type, or a combination thereof) that may be undoped or doped. Other materials suitable for semiconductor device formation may be used. Other materials (e.g., germanium, quartz, sapphire, and glass) may alternatively be used for substrate 110. Alternatively, silicon substrate 110 may be an active layer of a semiconductor on insulator (SOI) substrate or a multilayer structure (e.g., a silicon germanium layer formed on a bulk silicon layer).

[0029] The first semiconductor fin 112 and the second semiconductor fin 114 can be formed, for example, by patterning and etching the substrate 110 using photolithography techniques. In some embodiments, a layer of photoresist material (not shown) is deposited over the substrate 110. The layer of photoresist material is irradiated (exposed) according to the desired pattern (in this case, the first semiconductor fin 112 and the second semiconductor fin 114) and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material from subsequent process steps (e.g., etching). It should be noted that other masks (e.g., oxide or silicon nitride masks) can also be used for the etching process.

[0030] In some other embodiments, the first semiconductor fin 112 and the second semiconductor fin 114 may be grown epitaxially. For example, an exposed portion of an underlying material (e.g., an exposed portion of the substrate 110) may be used in an epitaxial process to form the first semiconductor fin 112 and the second semiconductor fin 114. A mask may be used to control the shape of the first semiconductor fin 112 and the second semiconductor fin 114 during the epitaxial growth process.

[0031] A plurality of isolation structures 120, such as shallow trench isolation (STI), are formed in the substrate 110 to separate the devices. The formation of the isolation structures 120 may include etching trenches in the substrate 110 and filling the trenches with an insulator material such as silicon oxide, silicon nitride, or silicon oxide. The filled trenches may have a multi-layer structure, such as a thermal oxide liner layer filling the trenches with silicon nitride. In some embodiments, the isolation structure 120 can be created using the following process sequence: growing a liner oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning the STI opening using a photoresist and a mask, etching trenches in the substrate 110 (to form semiconductor fins 112 and 114), optionally growing a thermal oxide trench liner to improve the channel interface, filling the trenches with oxide, removing excess oxide using chemical mechanical planarization (CMP), and recessing the thermal oxide trench liner and oxide to form the isolation structure 120 so that top portions of the semiconductor fins 112 and 114 protrude from the top surface of the isolation structure 120.

[0032] Figure 2A is a top view of a method for manufacturing a semiconductor device in various stages according to some embodiments, Figure 2B It is along Figure 2A A cross-sectional view taken along line BB of Figure 2C It is along Figure 2A A cross-sectional view taken along line CC of Figure 2D It is along Figure 2A The interface layer 130 is conformally formed to cover the semiconductor fins 112 and 114. For clarity, the interface layer 130 is shown in FIG. Figure 2B-2D is shown in Figure 2A In some embodiments, the interface layer 130 may include silicon dioxide, silicon nitride, a high-k dielectric material, or other suitable materials. In various examples, the interface layer 130 may be deposited by a thermal oxidation process, an ALD process, a CVD process, a negative pressure CVD (SACVD) process, a flowable CVD process, a PVD process, or other suitable processes. For example, the interface layer 130 may be used to prevent subsequent processes (e.g., subsequent formation of a gate structure) from causing damage to the semiconductor fins 112 and 114.

[0033] Subsequently, gate stacks 140a, 140b, 140c, 140d, and 140e are formed over the interface layer 130. Each of the gate stacks 140a-140e includes a gate structure 142a (or 142b or 142c or 142d or 142e), a liner layer 144 formed over the gate structure 142a (or 142b or 142c or 142d or 142e), and a hard mask layer 146 formed over the liner layer 144. In some embodiments, a gate layer (not shown) may be formed over the interface layer 130, and the liner layer 144 and the hard mask layer 146 may be formed over the gate layer. Then, the gate layer is patterned using the liner layer 144 and the hard mask layer 146 as masks to form the gate structures 142a-142e. In this way, the gate structures 142a, 142b, 142c, 142d, 142e, the liner layer 144 and the hard mask layer 146 are referred to as dummy gate stacks 140a, 140b, 140c, 140d and 140e. In some embodiments, the gate structures 142a-142e can be made of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe) or other suitable materials. The liner layer 144 can be made of silicon dioxide or other suitable materials, and the hard mask layer 146 can be made of silicon nitride or other suitable materials. If the gate-first technology is adopted, the gate structures 142a-142e and the interface layer 130 are used as gate electrodes and gate dielectric layers.

[0034] exist Figure 2AIn the embodiment, the gate stacks 140a-140e have substantially the same pitch. That is, the pitch P1 between the gate stack 140a and the gate stack 140b is substantially the same as the pitch P2 between the gate stack 140b and the gate stack 140c, the pitch P2 between the gate stack 140b and the gate stack 140c is substantially the same as the pitch P3 between the gate stack 140c and the gate stack 140d, and the pitch P3 between the gate stack 140c and the gate stack 140d is substantially the same as the pitch P4 between the gate stack 140d and the gate stack 140e. In some embodiments, the pitch P1 may be in the range of about 20 nm to about 100 nm.

[0035] Figure 3A is a top view of a method for manufacturing a semiconductor device in various stages according to some embodiments, Figure 3B It is along Figure 3A A cross-sectional view taken along line BB of Figure 3C It is along Figure 3A A cross-sectional view taken along line CC of Figure 3D It is along Figure 3A A cross-sectional view taken along line DD of FIG. 1 is shown with at least a portion of gate stacks 140 a - 140 e removed. For example, Figures 3A-3D , the gate stack 140c is removed (see Figure 2A ), so that portions of the semiconductor fins 112 and 114d originally covered by the gate stack 140c are exposed. In some embodiments, a mask layer is formed over the gate stacks 140a-140e, and the mask layer is patterned to expose the gate stack 140c. The mask layer can be formed of a photoresist or a hard mask (e.g., a silicon nitride layer). Subsequently, the exposed gate stack 140c is removed by, for example, an etching process.

[0036] Figure 4A is a top view of a method for manufacturing a semiconductor device in various stages according to some embodiments, Figure 4B It is along Figure 4A A cross-sectional view taken along line BB of Figure 4C It is along Figure 4A A cross-sectional view taken along line CC of Figure 4D It is along Figure 4A DD. Portions of the interface layer 130 not covered by the gate stacks 140a, 140b, 140d, and 140e are removed to expose portions of the semiconductor fins 112 and 114. Then, a spacer structure 150 is formed at least on opposite sides of the gate stack 140 and the interface layer 130. The spacer structure 150 may include a sealing spacer and a main spacer (not shown). The spacer structure 150 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiCx O y N z Or a combination thereof. The sealing spacer is formed on the sidewalls of the gate stack 140, and the main spacer is formed on the sealing spacer. The spacer structure 150 can be formed using a deposition method, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), negative pressure chemical vapor deposition (SACVD), etc. The formation of the spacer structure 150 may include a blanket formed spacer layer, and then an etching operation is performed to remove the horizontal portion of the spacer layer. The remaining vertical portion of the spacer layer forms the spacer structure 150.

[0037] Figure 5A is a top view of a method for fabricating a semiconductor device in various stages according to some embodiments. Figure 5B It is along Figure 5A A cross-sectional view taken along line BB of Figure 5C It is along Figure 5A A cross-sectional view taken along line CC of Figure 5D It is along Figure 5A DD is a cross-sectional view taken along line DD. Recesses 102 are formed in portions of semiconductor fins 112 and 114 that are not covered by gate stacks 140a, 140b, 140d and 140e and spacer structure 150, respectively. Gate stacks 140a, 140b, 140d and 140e and spacer structure 150 are used as etching masks in forming the recesses. The etching process includes a dry etching process, a wet etching process, or a combination thereof. Epitaxial structures 160a-160e and 165a-165e are then formed in the recesses by, for example, performing a selective growth process. Epitaxial structures 160a-160e are formed in semiconductor fins 112, and epitaxial structures 165a-165e are formed in semiconductor fins 114.

[0038] The epitaxial structures 160a-160e and 165a-165e are formed by epitaxially growing semiconductor materials. The semiconductor materials include: single element semiconductor materials, such as germanium (Ge) or silicon (Si); compound semiconductor materials, such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs); or semiconductor alloys, such as silicon germanium (SiGe) or gallium arsenide phosphide (GaAsP). The epitaxial structures 160a-160e and 165a-165e can be as follows: Figure 5DAs shown, the epitaxial structures 160a-160e and 165a-165e are separated from each other or merged together. In some embodiments, the epitaxial structures 160a-160e and 165a-165e are source / drain epitaxial structures. In some embodiments, where an N-type device is required, the epitaxial structures 160a-160e (or 165a-165e) may include epitaxially grown silicon phosphorus (SiP) or silicon carbon (SiC). In some embodiments, where a P-type device is required, the epitaxial structures 165a-165e (or 160a-160e) may include epitaxially grown silicon germanium (SiGe). The epitaxial structures 160a-160e and 165a-165e formed above the semiconductor fins 112 and 114 have different conductivity types and can be formed in different processes. The epitaxial process includes CVD deposition technology (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy and / or other suitable processes. In some embodiments, the formation of epitaxial structures 160a-160e and 165a-165e is omitted.

[0039] exist Fig. 6A , epitaxial structures 160a and 165a are formed on one side of gate stack 140a, epitaxial structures 160b and 165b are formed on the other side of gate stack 140a and between gate stacks 140a and 140b, epitaxial structures 160c and 165c are formed between gate stacks 140b and 140d, epitaxial structures 160d and 165d are formed on one side of gate stack 140e and between gate stacks 140d and 140e, and epitaxial structures 160e and 165e are formed on the other side of gate stack 140e. Each of epitaxial structures 160b, 160d, 165b, and 165d may have a length L1, and a length L2 of each of epitaxial structures 160c and 165c may be greater than the length L1.

[0040] Epitaxial structures 160a-160e and 165a-165e can be referred to as source / drain regions of corresponding transistors. Epitaxial structures 160a and 160b and gate structure 142a form transistor T1, epitaxial structures 160b and 160c and gate structure 142b form transistor T2, epitaxial structures 160c and 160d and gate structure 142d form transistor T3, epitaxial structures 160d and 160e and gate structure 142e form transistor T4, epitaxial structures 165a and 165b and gate structure 142a form transistor T5, epitaxial structures 165b and 165c and gate structure 142b form transistor T6, epitaxial structures 165c and 165d and gate structure 142d form transistor T7, and epitaxial structures 165d and 165e and gate structure 142e form transistor T8.

[0041] Epitaxial structure 160b may be the source of transistor T2, and epitaxial structure 160c may be the drain of transistor T2. Epitaxial structure 160d may be the source of transistor T3, and epitaxial structure 160c may be the drain of transistor T3. That is, transistors T2 and T3 share the same drain (i.e., epitaxial structure 160c). In addition, epitaxial structure 165b may be the source of transistor T6, and epitaxial structure 165c may be the drain of transistor T6. Epitaxial structure 165d may be the source of transistor T7, and epitaxial structure 165c may be the drain of transistor T7. That is, transistors T6 and T7 share the same drain (i.e., epitaxial structure 165c).

[0042] The gate structures 142a and 142b have a pitch P1, the gate structures 142d and 142e have a pitch P4 substantially the same as the pitch P1, and the gate structures 142b and 142d have a pitch P5 greater than the pitch P1. For example, the pitch P5 of the gate structures 142b and 142d is substantially twice the pitch P1 of the gate structures 142a and 142b.

[0043] Subsequently, an interlayer dielectric (ILD) 170 is formed over the epitaxial structures 160a-160e and 165a-165e, the gate stacks 140a, 140b, 140d and 140e, the spacer structure 150 and the isolation structure 120. The ILD 170 may be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering or other suitable methods. In some embodiments, the ILD 170 includes silicon oxide. In some other embodiments, the ILD 170 may include silicon oxynitride, silicon nitride or a low-k material. In some embodiments, a contact etch stop layer (CESL) is conformally formed over the epitaxial structures 160a-160e and 165a-165e, the gate stacks 140a, 140b, 140d and 140e, the spacer structure 150 and the isolation structure 120 in advance, and the ILD 170 is formed over the CESL. Then, a planarization process, such as a chemical mechanical planarization (CMP) process, is performed to planarize the ILD 170 to expose the gate electrodes 142 a , 142 b , 142 d , and 142 e .

[0044] Fig. 6A is a top view of a method for fabricating a semiconductor device in various stages according to some embodiments. Figure 6B It is along Fig. 6A A cross-sectional view taken along line BB of Figure 6C It is along Fig. 6A A cross-sectional view taken along line CC of Fig.6D It is along Fig. 6ADD. A plurality of source / drain openings 177 are formed in ILD 170, wherein the source / drain openings 177 expose some epitaxial structures (e.g., epitaxial structures 160b, 160d, 165b, and 165d in this case). Subsequently, a conductive material is filled in the openings 177, and excess portions of the conductive material are removed to form contacts 190 and 195. Contacts 190 and 195 may be made of tungsten, aluminum, copper, or other suitable materials.

[0045] Contact 190 is formed over epitaxial structures 160b and 165b so that epitaxial structure 160b is electrically connected to epitaxial structure 165b through contact 190. Contact 195 is formed over epitaxial structures 160d and 165d so that epitaxial structure 160d is electrically connected to epitaxial structure 165d through contact 195. It should be noted that the positions of contacts 190 and 195 are not limited to Fig. 6A The position of the contact portion is determined based on different circuit designs.

[0046] exist Figure 2A In the embodiment, gate stack 140c is a dummy gate stack, which is not a functional gate in the semiconductor device. If gate stack 140c is not removed, additional conductive traces will be formed above gate stack 140c to connect the drains of transistors T2 and T3 (see Figure 5A ). In addition, another through hole may be connected to the gate structure 142c to ground the gate structure 142c. Fig. 6A In the embodiment of the present invention, the gate stack 140c is removed and the drains of transistors T2 and T3 (i.e., the epitaxial structure 160c) are directly connected. With this configuration, additional conductive traces and vias are omitted, effectively saving metal wiring resources in a compact layout structure. In addition, in the absence of a grounded dummy gate, the parasitic capacitance between gate structures 142b and 142d is reduced, and the power consumption of the dummy gate grounding is reduced. For example, when one or more N-type and P-type dummy gates are removed, the speed of the semiconductor device in some embodiments increases by approximately 1.61%, and in some embodiments, approximately 1.7% of power is saved. When one or more N-type dummy gates are removed, the speed of the semiconductor device in some embodiments increases by approximately 0.32%, and in some embodiments, approximately 6.55% of power is saved.

[0047] In some embodiments, a replacement gate (RPG) process scheme is used. In the RPG process scheme, a dummy polysilicon gate (in this case, for example, gate electrodes 142a, 142b, 142d, 142e (see Figures 6A-6D )) is pre-formed and subsequently replaced by a metal gate. Fig. 7A is a top view of a semiconductor device at different stages according to some embodiments, Figure 7B It is along Fig. 7A A cross-sectional view taken along line BB of Figure 7C It is along Fig. 7A A cross-sectional view taken along line CC of Fig.7D It is along Fig. 7A In some embodiments, the gate structures 142a, 142b, 142d and 142e are removed to form openings 152, wherein the spacer structure 150 serves as their sidewalls. In some other embodiments, the interface layer 130 is also removed (see Figure 6B and 6C ). Alternatively, in some embodiments, the gate structures 142a, 142b, 142d, and 142e are removed, while the interface layer 130 remains. The gate structures 142a, 142b, 142d, and 142e (and the interface layer 130) may be removed by dry etching, wet etching, or a combination of dry etching and wet etching.

[0048] A plurality of gate structures 180 are then formed in the openings 152. The gate structures 180 crossover the semiconductor fins 112 and / or 114. The gate structures 180 may be referred to as functional gate structures. In some embodiments, each of the gate structures 180 includes a gate dielectric layer 182 and a gate electrode 184 located above the gate dielectric layer 182.

[0049] The gate dielectric layer 182 is conformally formed in the opening 152. The gate dielectric layer 182 is located above the semiconductor fins 112 and / or 114. The gate dielectric layer 182 can be a high-k dielectric layer having a dielectric constant (k) higher than the dielectric constant of SiO2 (i.e., k>3.9). The gate dielectric layer 182 can include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, or other suitable materials. The gate dielectric layer 182 is deposited by a suitable technique, such as ALD, CVD, PVD, thermal oxidation, a combination thereof, or other suitable techniques.

[0050] The gate electrode 184 may include (one or more) work function metal layers 185, (one or more) capping layers, (one or more) filling layers 186, and / or other suitable layers required in the metal gate stack. The work function metal layer 185 may include n-type and / or p-type work function metals. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The work function metal layer 185 may have multiple layers. (One or more) work function metal layers 185 may be deposited by CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, the gate electrode 184 is a p-type metal gate including a p-type work function metal layer. In some embodiments, the capping layer in the gate electrode 184 may include a refractory metal and its nitride (e.g., TiN, TaN, W2N, TiSiN, TaSiN). The capping layer may be deposited by PVD, CVD, metal organic chemical vapor deposition (MOCVD), ALD, etc. In some embodiments, the fill metal 186 may include tungsten (W) or other suitable conductive materials. The fill metal 186 may be deposited by ALD, PVD, CVD, or other suitable processes.

[0051] Figure 8 is a flow chart of a method M for forming a semiconductor device according to some embodiments of the present disclosure. Although method M is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or the actions may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0052] At block S12 , semiconductor fins are formed in the substrate. Figures 1A-1D Top views and cross-sectional views of some embodiments corresponding to the actions in block S12 are shown. At block S14, a gate electrode is formed over the substrate and across the semiconductor fin, wherein the gate electrode has a constant pitch. Figures 2A-2D Top views and cross-sectional views of some embodiments corresponding to the actions in block S14 are shown. At block S16, at least a portion of one of the gate electrodes is removed to expose a portion of the semiconductor fin. Figures 3A-3DTop views and cross-sectional views of some embodiments corresponding to the actions in block S16 are shown. At block S18, an epitaxial structure is formed over the semiconductor fins and between the gate structures. Figures 4A-4D Top views and cross-sectional views of some embodiments corresponding to the actions in block S18 are shown.

[0053] Fig. 9 is a top view of a semiconductor device 200 at various stages in accordance with some embodiments. Fig. 9 and Fig. 6A The differences between semiconductor devices involve the configuration of the gate structure. Fig. 9 In the embodiment, the semiconductor device 200 includes a plurality of gate structures and a plurality of epitaxial structures. The OD portion corresponds to the epitaxial structure, and the G portion corresponds to the gate structure. The gate structures are arranged along the x direction, and the spacings of adjacent gate structures are different. For example, adjacent gate structures 242a and 242b have a spacing P21, adjacent gate structures 242b and 242c have a spacing P22, adjacent gate structures 242c and 242d have a spacing P23, adjacent gate structures 242d and 242e have a spacing P24, adjacent gate structures 242f and 242g have a spacing P25, adjacent gate structures 242g and 242h have a spacing P26, and adjacent gate structures 242h and 242i have a spacing P27. The spacing P21 (or P25 or P26 or P27) is substantially twice the spacing P22 (or P23), and the spacing P24 is substantially three times the spacing P22 (or P23). That is, each pitch between adjacent gate structures is n times the pitch P22 (or P23), where n is a positive integer. In addition, the gate structures have substantially the same width.

[0054] The epitaxial structure extends along the x direction, and the length of the epitaxial structure may be different. For example, epitaxial structures 260a and 260b are located on the opposite side of the gate structure 242b, and the epitaxial structures 260a and 260b and the gate structure 242b form a transistor T21. The length L21 of the epitaxial structure 260a is different from the length L22 of the epitaxial structure 260b. For example, the length L21 is substantially twice the length L22. In addition, epitaxial structures 260b and 260c are located on the opposite side of the gate structure 242c, and the epitaxial structures 260b and 260c and the gate structure 242c form a transistor T22. The length L22 of the epitaxial structure 260b is substantially the same as the length L23 of the epitaxial structure 260c. In addition, epitaxial structures 260c and 260d are located on the opposite side of the gate structure 242d, and the epitaxial structures 260c and 260d and the gate structure 242d form a transistor T23. The length L23 of epitaxial structure 260c is different from the length L24 of epitaxial structure 260d. For example, length L24 is substantially three times the length L23. That is, each length of the epitaxial structure is m times the length L22 (or L23), where m is a positive integer. Fig. 9 Other relevant structural details of the semiconductor device 200 are Figures 6A-6D (or Figures 7A-7D ) are the same or similar to the semiconductor devices in the present invention. Therefore, the description of this aspect will not be repeated hereinafter.

[0055] Fig. 6A (or Fig. 7A or Fig. 9 ) can be applied to various integrated circuits / circuit units to increase wiring flexibility. Fig.10 300 is a layout diagram of an integrated circuit 300 according to some embodiments of the present disclosure. The integrated circuit 300 is an SDFQ (or SDFSNQ) circuit. The layout diagram of the integrated circuit 300 includes multiple active regions, multiple gate structures, and multiple conductive features. The OD portion corresponds to the active region (e.g., epitaxial structure), the G portion corresponds to the gate structure, the MP portion corresponds to the conductive feature, and the label 302 corresponds to the cell boundary of the integrated circuit 300. The conductive feature is formed above the gate structure. The active region extends along the x direction and the gate structure extends along the y direction.

[0056] Part of the gate structure is removed. For example, a portion of the gate structure 342a is removed to form gate structures 342aa and 342ab extending and arranged along the y direction. Epitaxial structures 360a and 360b and gate structure 342b form transistor T31. Epitaxial structure 360a is inserted between gate structures 342aa and 342ab. That is, epitaxial structure 360a is located between the ends of gate structures 342aa and 342ab, and gate structure 342aa, epitaxial structure 360a and gate structure 342ab are arranged in sequence along the y direction. In addition, the length L31 of epitaxial structure 360a is substantially twice the length L32 of epitaxial structure 360b.

[0057] Epitaxial structures 360j and 360k are located on opposite sides of gate structure 342ab. Epitaxial structures 360j and 360k have substantially the same length, which is substantially the same as the length L32 of epitaxial structure 360b. Epitaxial structure 360j (or 360k) and epitaxial structure 360a are arranged along the y direction. Edge 361a of epitaxial structure 360a is substantially aligned with edge 361j of epitaxial structure 360j.

[0058] In addition, Fig.10 , a portion of the gate structure 342e is removed. Fig.10 The gate structures in have a constant / uniform spacing. For example, gate structures 342c and 342d have a spacing P31, gate structures 342d and 342f have a spacing P32 that is substantially twice the spacing P31, and gate structures 342f and 342g have a spacing P33 that is substantially the same as the spacing P31. Epitaxial structures 360c and 360d and gate structure 342d form transistor T32, and epitaxial structures 360d and 360e and gate structure 342f form transistor T33. That is, transistors T32 and T33 share a common source / drain (i.e., epitaxial structure 360d in this case). Epitaxial structure 360d is located at one end 343e of gate structure 342e and between gate structures 342d and 342f. The length L34 of the epitaxial structure 360d is substantially twice the length L33 of the epitaxial structure 360c, and the length L34 of the epitaxial structure 360d is substantially twice the length L35 of the epitaxial structure 360e. In addition, the length L34 is greater than the spacing between the gate structures 342d and 342e (or the spacing between the gate structures 342e and 342f), which is substantially the same as the spacing P31 between the gate structures 342c and 342d. In addition, the end 343e of the gate structure 342e is located directly above the isolation structure.

[0059] In addition, Fig.10, a portion of the gate structure 342f is removed. The gate structures 342e and 342f have a spacing P34 that is substantially twice the spacing P31. The epitaxial structures 360f and 360g and the gate structure 342e form a transistor T34, and the epitaxial structures 360g and 360h and the gate structure 342g form a transistor T35. In other words, transistors T34 and T35 share a common source / drain (i.e., epitaxial structure 360g in this case). The epitaxial structure 360g is located at one end of the gate structure 342f and between the gate structures 342e and 342g. The length L37 of the epitaxial structure 360g is substantially twice the length L36 of the epitaxial structure 360f, and the length L37 of the epitaxial structure 360g is substantially twice the length L38 of the epitaxial structure 360h. Furthermore, epitaxial structure 360i is located between gate structures 342f and 342g, and epitaxial structures 360g and 360i are arranged along the y direction. Length L39 of epitaxial structure 360i is less than length L37 of epitaxial structure 360g, for example, substantially half of length L37 of epitaxial structure 360g. Fig.10 Other relevant structural details of the integrated circuit 300 are Figures 6A-6D (or Figures 7A-7D ) are the same or similar to the semiconductor devices in the drawings, so the description of this aspect will not be repeated below.

[0060] Fig.11 400 is a layout diagram of an integrated circuit 400 according to some embodiments of the present disclosure. The integrated circuit 400 is a MB2SDFQ circuit. The layout diagram of the integrated circuit 400 includes multiple active regions, multiple gate structures, and multiple conductive features. The OD portion corresponds to the active region (e.g., epitaxial structure), the G portion corresponds to the gate structure, the MP portion corresponds to the conductive feature, and the label 402 corresponds to the cell boundary of the integrated circuit 400. The active region extends along the x-direction, and the gate structure extends along the y-direction.

[0061] Portions of the gate structure are removed. For example, a portion of the gate structure 442c is removed. Fig.11The gate structures in have a constant / uniform spacing. For example, gate structures 442a and 442b have a spacing P41, gate structures 342b and 342d have a spacing P42 that is substantially twice the spacing P41, and gate structures 442d and 442e have a spacing P43 that is substantially the same as the spacing P41. Epitaxial structures 460a and 460b and gate structure 442b form transistor T41, and epitaxial structures 460b and 460c and gate structure 442d form transistor T42. In other words, transistors T41 and T42 share a common source / drain (i.e., epitaxial structure 460b in this case). Epitaxial structure 460b is located at one end of gate structure 442c and between gate structures 442b and 442d. The length L42 of the epitaxial structure 460b is substantially twice the length L41 of the epitaxial structure 460a, and the length L42 of the epitaxial structure 460b is substantially twice the length L43 of the epitaxial structure 460c.

[0062] In addition, Fig.11 , a portion of the gate structure 442b is removed, and an epitaxial structure 460d is formed at one end of the gate structure 442b. The epitaxial structures 460d and 460e and the gate structure 442c form a transistor T43, and the length of the epitaxial structure 460d is substantially twice the length of the epitaxial structure 460e. In addition, a portion of the gate structure 442g is removed, and an epitaxial structure 460f is formed at one end of the gate structure 442g and between the gate structures 442f and 442h. A portion of the gate structure 442h is removed, and an epitaxial structure 460g is formed at one end of the gate structure 442h and between the gate structures 442g and 442i. Fig.11 Other relevant structural details of the integrated circuit 400 are Figures 6A-6D (or Figures 7A-7D ) are the same or similar to the semiconductor devices in the drawings, so the description of this aspect will not be repeated below.

[0063] Fig.12 5 is a layout diagram of an integrated circuit 500 according to some embodiments of the present disclosure. The integrated circuit 500 is a MB2SRLSDFQD1 circuit. The layout diagram of the integrated circuit 500 includes a plurality of active regions, a plurality of gate structures, and a plurality of conductive features. The OD portion corresponds to the active region (e.g., an epitaxial structure), the G portion corresponds to the gate structure, the MP portion corresponds to the conductive feature, and the label 502 corresponds to the cell boundary of the integrated circuit 500. The active region extends along the x-direction, and the gate structure extends along the y-direction.

[0064] Portions of the gate structure are removed. For example, a portion of the gate structure 542c is removed. Fig.12The gate structures in have a constant / uniform spacing. For example, gate structures 542a and 542b have a spacing P51, gate structures 542b and 542d have a spacing P52 that is substantially twice the spacing P51, and gate structures 542d and 542e have a spacing P53 that is substantially the same as the spacing P51. Epitaxial structures 560a and 560b and gate structure 542b form transistor T51, and epitaxial structures 560b and 560c and gate structure 542d form transistor T52. In other words, transistors T51 and T52 share a common source / drain (i.e., epitaxial structure 560b in this case). Epitaxial structure 560b is located at one end of gate structure 542c and between gate structures 542b and 542d. The length L52 of the epitaxial structure 560b is substantially twice the length L51 of the epitaxial structure 560a, and the length L52 of the epitaxial structure 560b is substantially twice the length L53 of the epitaxial structure 560c.

[0065] In addition, Fig.12 , a portion of the gate structure 542b is removed, and an epitaxial structure 560d is formed at one end of the gate structure 542b. The epitaxial structures 560d and 560e and the gate structure 542c form a transistor T53, and the length of the epitaxial structure 560d is substantially twice that of the epitaxial structure 560e. In addition, a portion of the gate structure 542g is removed, and an epitaxial structure 560f is formed at one end of the gate structure 542g and between the gate structures 542f and 542h. A portion of the gate structure 542h is removed, and an epitaxial structure 560g is formed at one end of the gate structure 542h and between the gate structures 542g and 542i. Fig.12 Other relevant structural details of the integrated circuit 500 are Figures 6A-6D (or Figures 7A-7D ) are the same or similar to the semiconductor devices in the drawings, so the description of this aspect will not be repeated below.

[0066] Fig.13 600 is a layout diagram of an integrated circuit 600 according to some embodiments of the present disclosure. The integrated circuit 600 is an SDFQD1 circuit. The layout diagram of the integrated circuit 600 includes multiple active regions, multiple gate structures, and multiple conductive features. The OD portion corresponds to the active region (e.g., epitaxial structure), the G portion corresponds to the gate structure, the MP portion corresponds to the conductive feature, and the label 602 corresponds to the cell boundary of the integrated circuit 600. The active region extends along the x direction, and the gate structure extends along the y direction.

[0067] Portions of the gate structure are removed. For example, a portion of the gate structure 642c is removed. Fig.13The gate structures in have a constant / uniform spacing. For example, gate structures 642a and 642b have a spacing P61, gate structures 642b and 642d have a spacing P62 that is substantially twice the spacing P61, and gate structures 642d and 642e have a spacing P63 that is substantially the same as the spacing P61. Epitaxial structures 660a and 660b and gate structure 642b form transistor T61, and epitaxial structures 660b and 660c and gate structure 642d form transistor T62. In other words, transistors T61 and T62 share a common source / drain (i.e., epitaxial structure 660b in this case). Epitaxial structure 660b is located at one end of gate structure 642c and between gate structures 642b and 642d. The length L62 of the epitaxial structure 660b is substantially twice the length L61 of the epitaxial structure 660a, and the length L62 of the epitaxial structure 660b is substantially twice the length L63 of the epitaxial structure 660c.

[0068] In addition, Fig.13 In the embodiment, a portion of the gate structure 642d is removed, and an epitaxial structure 660d is formed at one end of the gate structure 642d. The epitaxial structures 660d and 660e and the gate structure 642c form a transistor T63, and the length of the epitaxial structure 660d is substantially twice that of the epitaxial structure 660e. Fig.13 Other relevant structural details of the integrated circuit 600 are Figures 6A-6D (or Figures 7A-7D ) are the same or similar to the semiconductor devices in the drawings, so the description of this aspect will not be repeated below.

[0069] Fig.14 700 is a layout diagram of an integrated circuit 700 according to some embodiments of the present disclosure. The integrated circuit 700 is a SDFSNQD1 circuit. The layout diagram of the integrated circuit 700 includes multiple active regions, multiple gate structures, and multiple conductive features. The OD portion corresponds to the active region (e.g., epitaxial structure), the G portion corresponds to the gate structure, the MP portion corresponds to the conductive feature, and the label 702 corresponds to the cell boundary of the integrated circuit 700. The active region extends along the x direction, and the gate structure extends along the y direction.

[0070] Portions of the gate structure are removed. For example, a portion of the gate structure 742c is removed. Fig.14The gate structures in have a constant / uniform spacing. For example, gate structures 742a and 742b have a spacing P71, gate structures 742b and 742d have a spacing P72 that is substantially twice the spacing P71, and gate structures 742d and 742e have a spacing P73 that is substantially the same as the spacing P71. Epitaxial structures 760a and 760b and gate structure 742b form transistor T71, and epitaxial structures 760b and 760c and gate structure 742d form transistor T72. In other words, transistors T71 and T72 share a common source / drain (i.e., epitaxial structure 760b in this case). Epitaxial structure 760b is located at one end of gate structure 742c and between gate structures 742b and 742d. The length L72 of the epitaxial structure 760b is substantially twice the length L71 of the epitaxial structure 760a, and the length L72 of the epitaxial structure 760b is substantially twice the length L73 of the epitaxial structure 760c. In addition, a portion of the gate structure 742e is also removed.

[0071] In addition, Fig.14 In the embodiment, a portion of the gate structure 742g is removed, and an epitaxial structure 760d is formed at one end of the gate structure 742g. The epitaxial structures 760d and 760e and the gate structure 742f form a transistor T73, and the length of the epitaxial structure 760d is substantially twice that of the epitaxial structure 760e. Fig.14 Other relevant structural details of the integrated circuit 700 are Figures 6A-6D (or Figures 7A-7D ) are the same or similar to the semiconductor devices in the drawings, so the description of this aspect will not be repeated below.

[0072] Fig.15 is a flowchart of a method 1500 for generating an IC layout diagram according to some embodiments of the present disclosure. In some embodiments, generating an IC layout diagram includes generating the above-mentioned IC layout diagram based on the generated IC layout diagram. Figure 9-14 Discuss one of layout diagrams 200, 300, 400, 500, 600, or 700. In some embodiments, generating an IC layout diagram is part of operating an IC manufacturing system as part of manufacturing IC devices (eg, memory circuits, logic devices, processing devices, signal processing circuits, etc.).

[0073] In some embodiments, part or all of method 1500 is performed by a processor of a computer. In some embodiments, part or all of method 1500 is performed by the following Fig.16 The processor 1602 of the IC device design system 1600 discussed above is executed. Some or all of the operations of the method 1500 can be implemented as a design studio (e.g., as described below for Fig.17 This is performed as part of a design program performed in the design studio 1720 discussed above.

[0074] In some embodiments, the operations of method 1500 are as follows: Fig.15 In some embodiments, the operations of method 1500 are performed simultaneously and / or in a sequential order. Fig.15 In some embodiments, one or more operations of method 1500 are performed before, between, during, and / or after one or more operations of method 1500 are performed.

[0075] In operation 1510, a first active region and a second active region are arranged on a substrate, wherein the first active region and the second active region have different lengths. Arranging the first active region and the second active region includes arranging the first active region and the second active region as described above for Figures 5A-7D The epitaxial structures 160c and 160b discussed above correspond to the active regions. In various embodiments, arranging the active regions includes: arranging Figures 5A-7D The epitaxial structures 165c and 165b discussed above are arranged Fig. 9 The epitaxial structures 260a and 260b discussed above are arranged Fig.10 The epitaxial structures 360a and 360b discussed above are arranged Fig.11 The epitaxial structures 460b and 460c discussed above are arranged Fig.12 The epitaxial structures 560b and 560c discussed above are arranged Fig.13 The epitaxial structures 660b and 660c discussed above; and the arrangement of Fig.14 Epitaxial structures 760b and 760c are discussed.

[0076] At operation 1520, a first gate structure, a second gate structure, and a third gate structure are arranged above the first active region and the second active region, wherein the first active region is located between the first gate structure and the second gate structure, and the second active region is located between the second gate structure and the third gate structure. Arranging the first gate structure, the second gate structure, and the third gate structure includes arranging the gate structure corresponding to the gate structure above. Figures 5A-7D The first gate structure, the second gate structure and the third gate structure corresponding to the gate structures 142b, 142d and 142e discussed above. In various embodiments, arranging the first gate structure, the second gate structure and the third gate structure includes: arranging the above-mentioned Fig. 9 The gate structures 242a, 242b and 242c discussed above are arranged Fig. 9 The gate structures 242e, 242d and 242c discussed above are arranged Fig.10 The gate structures 342d, 342f and 342g discussed above are arranged Fig.11 The gate structures 442b, 442d and 442e discussed above are arranged Fig.12The gate structures 542b, 542d and 542e discussed above are arranged Fig.13 The gate structures 642b, 642d and 642e discussed above; and the arrangement of Fig.14 Gate structures 742b, 742d and 742e are discussed.

[0077] At operation 1530, in some embodiments, an IC layout diagram is generated. The IC layout diagram includes a first gate structure, a second gate structure, a source / drain region, and a body region arranged as discussed above with respect to operations 1510-1520. In some embodiments, generating the IC layout diagram includes storing the IC layout diagram in a storage device. In various embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile, computer-readable memory or a cell library (e.g., a database) and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile, computer-readable memory or a cell library (e.g., a database) and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile, computer-readable memory or a cell library (e.g., a database) via a storage device. Fig.16 The network 1614 of the IC device design system 1600 discussed stores IC layout drawings.

[0078] At operation 1540, in some embodiments, at least one of the one or more semiconductor masks or at least one component in the semiconductor device layer is manufactured based on the IC layout diagram. Fig.17 The manufacture of at least one component in one or more semiconductor masks or layers of a semiconductor device is discussed.

[0079] At operation 1550, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing the one or more manufacturing operations includes performing one or more photolithography exposures based on the IC layout diagram. Fig.17 Discussion One or more manufacturing operations, such as one or more photolithography exposures, are performed based on the IC layout.

[0080] By executing part or all of the operations of method 1500, for example, Figures 1A-7D and Figure 9-14 IC layouts and corresponding semiconductor devices (various embodiments of which include cut gate structures) are discussed, thereby improving metal wiring resources of the semiconductor device.

[0081] Fig.16 is a block diagram of an IC device design system 1600 according to some embodiments of the present disclosure. According to some embodiments, as described above with respect to Fig.15 One or more operations of the discussed method 1500 may be implemented using the IC device design system 1600 .

[0082] In some embodiments, IC device design system 1600 is a computing device including hardware processor 1602 and non-transitory computer-readable storage medium 1604. Non-transitory computer-readable storage medium 1604 is encoded with or stores computer program code (i.e., a set of executable instructions 1606), among other things. Execution of instructions 1606 by hardware processor 1602 represents (at least in part) an IC device design system that implements the above-described IC device design system for the present invention. Fig.15 Part or all of method 1500 (the process and / or method described below).

[0083] The processor 1602 is electrically coupled to the non-transitory computer-readable storage medium 1604 via a bus 1608. The processor 1602 is also electrically coupled to an I / O interface 1610 via the bus 1608. The network interface 1612 is also electrically connected to the processor 1602 via the bus 1608. The network interface 1612 is connected to a network 1614, so that the processor 1602 and the non-transitory computer-readable storage medium 1604 can be connected to external elements via the network 1614. The processor 1602 is configured to execute instructions 1606 encoded in the non-transitory computer-readable storage medium 1604 so that the IC device design system 1600 can be used to perform some or all of the processes and / or methods. In one or more embodiments, the processor 1602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific IC (ASIC), and / or a suitable processing unit.

[0084] In one or more embodiments, the non-transitory computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the non-transitory computer-readable storage medium 1604 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the non-transitory computer-readable storage medium 1604 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0085] In one or more embodiments, the non-transitory computer-readable storage medium 1604 stores instructions 1606 configured to enable the IC device design system 1600 to perform some or all of the processes and / or methods. In one or more embodiments, the non-transitory computer-readable storage medium 1604 also stores information that facilitates the execution of some or all of the processes and / or methods. In various embodiments, the non-transitory computer-readable storage medium 1604 stores one or a combination of at least one IC layout design drawing 1620 or at least one design specification 1622, each of which is directed to the IC device design system 1600. Figures 1A-7D Discuss with 9-14.

[0086] IC device design system 1600 includes an I / O interface 1610. I / O interface 1610 is coupled to an external circuit. In various embodiments, I / O interface 1610 includes one or a combination of a keyboard, a key, a mouse, a trackball, a trackpad, a display, a touch screen, and / or a cursor direction key for transmitting information and commands to and / or from processor 1602.

[0087] The IC device design system 1600 also includes a network interface 1612 coupled to the processor 1602. The network interface 1612 allows the IC device design system 1600 to communicate with a network 1614 to which one or more other computer systems are connected. The network interface 1612 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 1600.

[0088] The IC device design system 1600 is configured to receive information through the I / O interface 1610. The information received through the I / O interface 1610 includes one or a combination of the following items: at least one design rule instruction, at least one set of criteria, at least one design rule, at least one DRM, and / or other parameters processed by the processor 1602. The information is transmitted to the processor 1602 via the bus 1608. The IC device design system 1600 is configured to send and / or receive information related to the user interface through the I / O interface 1610.

[0089] In some embodiments, part or all of the process and / or method is implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in for a software application. In some embodiments, at least one of the process and / or method is implemented as a software application that is part of an EDA tool. In some embodiments, the IC layout diagram is created using a VIRTUOSO such as that available from CADENCE DESIGN SYSTEMS. or another suitable layout generation tool.

[0090] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs, memory cards), etc.

[0091] Through can be used to achieve Fig.15 The IC device design system 1600 and the non-transitory computer-readable storage medium (eg, the non-transitory computer-readable storage medium 1604) enable the above method 1500 and the one or more operations of the method 1500. Fig.15 The benefits of the discussion were realized.

[0092] Fig.17 1 is a block diagram of an IC manufacturing system 1700 and an IC manufacturing process associated therewith according to some embodiments of the present disclosure. In some embodiments, based on a layout design, at least one of the following items is manufactured using the IC manufacturing system 1700: (A) one or more semiconductor masks or (B) at least one component in a semiconductor IC layer.

[0093] exist Fig.17 In the present invention, the IC manufacturing system 1700 includes entities such as a design room 1720, a mask room 1730, and an IC manufacturer / fabricator ("fab") 1750, etc., which interact in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 1760. The entities in the system 1700 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1720, the mask room 1730, and the IC manufacturer / fabricator 1750 are owned by a single larger company. In some embodiments, two or more of the design room 1720, the mask room 1730, and the IC manufacturer / fabricator 1750 coexist in a public facility and use public resources.

[0094] Design studio (or design team) 1720 based on Fig.15 Method 1500 and the above for Figures 1A-7D and Figure 9-14The discussion generates an IC design layout (or design) 1722. The IC design layout 1722 includes various geometric patterns that correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components of the integrated circuit device 1760 to be manufactured. The various layers are combined to form various characteristics. For example, a portion of the IC design layout 1722 includes various IC features, such as active areas, gate electrodes, sources and drains, metal lines or vias for interconnecting between layers, and openings for bonding pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design studio 1720 implements a process including Fig.15 Method 1500 and the above for Figures 1A-7D 9-14 to form an IC design layout diagram 1722. The design program includes one or more logical designs, physical designs, or locations and wiring. The IC design layout diagram 1722 is presented in one or more data files with information of geometric patterns. For example, the IC design layout diagram 1722 can be represented in a GDSII file format or a DFII file format.

[0095] The mask chamber 1730 includes data preparation 1732 and mask manufacturing 1744. The mask chamber 1730 uses the IC design layout drawing 1722 to manufacture one or more masks 1745 for manufacturing various layers of the IC device 1760 according to the IC design layout drawing 1722. The mask chamber 1730 performs mask data preparation 1732, wherein the IC design layout drawing 1722 is converted into a representative data file ("RDF"). The mask data preparation 1732 provides the RDF to the mask manufacturing 1744. The mask manufacturing 1744 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1745 or a semiconductor wafer 1753. The design layout drawing 1722 is manipulated by the mask data preparation 1732 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer / fabricator 1750. In Fig.17 , mask data preparation 1732 and mask manufacturing 1744 are shown as separate elements. In some embodiments, mask data preparation 1732 and mask manufacturing 1744 are collectively referred to as mask data preparation.

[0096] In some embodiments, mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1722. In some embodiments, mask data preparation 1732 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT), which treat OPC as an inverse imaging problem, are also used.

[0097] In some embodiments, mask data preparation 1732 includes a mask rule checker (MRC) that checks an IC design layout 1722 processed in OPC, which contains certain geometric and / or connection constraints to ensure a set of mask creation standard rules with sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1722 to compensate for the constraints during mask fabrication 1744, which may undo some of the modifications performed by the OPC to satisfy the mask creation standard rules.

[0098] In some embodiments, mask data preparation 1732 includes a lithography process check (LPC) that simulates a process that will be implemented by the IC manufacturer / fabricator 1750 to manufacture the IC device 1760. The LPC simulates this process based on the IC design layout diagram 1722 to create a simulated manufactured device, such as the IC device 1760. The process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after the simulated manufactured device is created by the LPC, if the shape of the simulated device is insufficient to meet the design rules, the OPC and / or MRC are repeated to further improve the IC design layout diagram 1722.

[0099] It should be understood that the above description of mask data preparation 1732 is simplified for the purpose of clarity. In some embodiments, data preparation 1732 includes additional features such as logic operations (LOPs) to modify IC design layout 1722 according to manufacturing rules. In addition, the processes applied to IC design layout 1722 during data preparation 1732 can be performed in a variety of different orders.

[0100] After mask data preparation 1732 and during mask manufacturing 1744, a mask 1745 or a set of masks 1745 are manufactured based on the modified IC design layout 1722. In some embodiments, mask manufacturing 1744 includes performing one or more photolithography exposures based on the IC design layout 1722. In some embodiments, based on the modified IC design layout 1722, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (photomask or reticle) 1745. Mask 1745 can be formed with various techniques. In some embodiments, mask 1745 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 1745 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated in the opaque area of ​​the binary mask. In another example, a mask 1745 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1745, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by the mask manufacturing 1744 are used for various processes. For example, such mask(s) are used to: form various doped regions in the semiconductor wafer 1753 in an ion implantation process; form various etched regions in the semiconductor wafer 1753 in an etching process; and / or other suitable processes.

[0101] IC manufacturer / fabricator 1750 includes wafer fabrication 1752. IC manufacturer / fabricator 1750 is an integrated circuit manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturer / fabricator 1750 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front-end of line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing for interconnection and packaging of IC products (back-end of line (BEOL) manufacturing), and a third manufacturing facility may provide other services for the foundry.

[0102] IC manufacturer / fabricator 1750 uses (one or more) masks 1745 manufactured by mask chamber 1730 to manufacture IC device 1760. Therefore, IC manufacturer / fabricator 1750 at least indirectly uses IC design layout 1722 to manufacture IC device 1760. In some embodiments, semiconductor wafer 1753 is manufactured by IC manufacturer / fabricator 1750 using (one or more) masks 1745 to form IC device 1760. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 1722 at least indirectly. Semiconductor wafer 1753 includes a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1753 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0103] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it is to be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and specific advantages are not required for all embodiments. One advantage is that since the dummy gate is removed, additional conductive traces and / or vias above the dummy gate can be omitted, and metal wiring resources in a compact layout structure can be effectively saved. Another advantage is that since the dummy gate is removed, the power consumption of the dummy gate grounding is reduced. In addition, removing the dummy gate also reduces the parasitic capacitance between the gate structures.

[0104] According to some embodiments, a semiconductor device includes a substrate, a first gate structure, a second gate structure, a third gate structure, and a first source / drain region. The first gate structure, the second gate structure, and the third gate structure are located above the substrate and arranged along a first direction. The first gate structure, the second gate structure, and the third gate structure extend along a second direction different from the first direction, and the second gate structure is located between the first gate structure and the third gate structure. The first source / drain region is located between the first gate structure and the third gate structure, and the first source / drain region is located at one end of the second gate structure.

[0105] According to some embodiments, a semiconductor device includes a first semiconductor fin, a second semiconductor fin, a first gate structure, a second gate structure, a first epitaxial structure, and a second epitaxial structure. The first gate structure spans the first semiconductor fin and the second semiconductor fin. The second gate structure spans the second semiconductor fin and is spaced apart from the first semiconductor fin. The first epitaxial structure and the second epitaxial structure are located above the first semiconductor fin and on opposite sides of the first gate structure. The first epitaxial structure and the second epitaxial structure have different lengths.

[0106] According to some embodiments, a method for manufacturing a semiconductor device includes forming an active region above a substrate. A gate structure is formed above the substrate and across the active region. The gate structures have a substantially constant spacing. A portion of at least one of the gate structures is removed to expose a portion of the active region. A first epitaxial structure is formed at least on the exposed portion of the active region.

[0107] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0108] Example 1. A semiconductor device, comprising: a substrate; a first gate structure, a second gate structure, and a third gate structure, wherein the first gate structure, the second gate structure, and the third gate structure are located above the substrate and arranged along a first direction, wherein the first gate structure, the second gate structure, and the third gate structure extend in a second direction different from the first direction, and the second gate structure is located between the first gate structure and the third gate structure; and a first source / drain region, wherein the first source / drain region is located between the first gate structure and the third gate structure and at one end of the second gate structure.

[0109] Example 2. The semiconductor device of Example 1, wherein the first gate structure and the second gate structure have a first pitch, and the second gate structure and the third gate structure have a second pitch that is substantially the same as the first pitch.

[0110] Example 3. The semiconductor device of Example 1, wherein the first source / drain region has a length in the first direction, and the length of the first source / drain region is greater than a spacing between the first gate structure and the second gate structure.

[0111] Example 4. The semiconductor device according to Example 1 further includes an isolation structure located above the substrate and adjacent to the first source / drain region, wherein the end of the second gate structure is located directly above the isolation structure.

[0112] Example 5. The semiconductor device of Example 1 further includes a second source / drain region located between the first gate structure and the second gate structure.

[0113] Example 6. The semiconductor device of Example 5, wherein a length of the second source / drain region is less than a length of the first source / drain region.

[0114] Example 7. The semiconductor device of Example 5, wherein a length of the second source / drain region is substantially half a length of the first source / drain region.

[0115] Example 8. The semiconductor device of Example 5, wherein the first source / drain region and the second source / drain region are arranged along the second direction.

[0116] Example 9. A semiconductor device, comprising: a first semiconductor fin and a second semiconductor fin; a first gate structure, the first gate structure spanning the first semiconductor fin and the second semiconductor fin; a second gate structure, the second gate structure spanning the second semiconductor fin and spaced apart from the first semiconductor fin; and a first epitaxial structure and a second epitaxial structure, the first epitaxial structure and the second epitaxial structure being located above the first semiconductor fin and on opposite sides of the first gate structure, wherein the first epitaxial structure and the second epitaxial structure have different lengths.

[0117] Example 10. The semiconductor device of Example 9, wherein the first epitaxial structure is located at one end of the second gate structure, and a length of the first epitaxial structure is greater than a length of the second epitaxial structure.

[0118] Example 11. The semiconductor device of Example 10, wherein a length of the first epitaxial structure is substantially twice a length of the second epitaxial structure.

[0119] Example 12. The semiconductor device of Example 9 further includes a third epitaxial structure and a fourth epitaxial structure, wherein the third epitaxial structure and the fourth epitaxial structure are located above the second semiconductor fin and on opposite sides of the second gate structure.

[0120] Example 13. The semiconductor device of Example 12, wherein the third epitaxial structure and the fourth epitaxial structure have substantially the same length.

[0121] Example 14. The semiconductor device of Example 12, wherein the second epitaxial structure and the third epitaxial structure have substantially the same length.

[0122] Example 15. The semiconductor device of Example 12, wherein an edge of the first epitaxial structure is substantially aligned with an edge of the fourth epitaxial structure.

[0123] Example 16. The semiconductor device of Example 15, wherein the third epitaxial structure is located between the first gate structure and the second gate structure.

[0124] Example 17. A method for manufacturing a semiconductor device, comprising: forming an active region above a substrate; forming gate structures above the substrate and across the active region, wherein the gate structures have a substantially constant spacing; removing a portion of at least one of the gate structures to expose a portion of the active region; and forming a first epitaxial structure on at least the exposed portion of the active region.

[0125] Example 18. The method of Example 17, wherein the first epitaxial structure is formed between two of the gate structures.

[0126] Example 19. The method according to Example 17 further includes: forming a second epitaxial structure above the active area and between two adjacent gate structures in the gate structure, wherein the first epitaxial structure is formed so that a first length of the first epitaxial structure is greater than a second length of the second epitaxial structure.

[0127] Example 20. A method according to Example 19, wherein the first length is n times the second length, and n is a positive integer.

Claims

1. A semiconductor device, comprising: substrate; a first gate structure, a second gate structure, and a third gate structure, wherein the first gate structure, the second gate structure, and the third gate structure are located above the substrate and arranged along a first direction, wherein the first gate structure, the second gate structure, and the third gate structure extend in a second direction different from the first direction, and the second gate structure is located between the first gate structure and the third gate structure; and A first source / drain region extends from the first gate structure to the third gate structure, wherein the first source / drain region is located at one end of the second gate structure and is separated from the second gate structure.

2. The semiconductor device according to claim 1, wherein The first gate structure and the second gate structure have a first pitch, and the second gate structure and the third gate structure have a second pitch that is the same as the first pitch.

3. The semiconductor device according to claim 1, wherein The first source / drain region has a length in the first direction, and the length of the first source / drain region is greater than a distance between the first gate structure and the second gate structure.

4. The semiconductor device according to claim 1, further comprising an isolation structure located above the substrate and adjacent to the first source / drain region, wherein: The end of the second gate structure is located directly above the isolation structure. 5 . The semiconductor device of claim 1 , further comprising a second source / drain region located between the first gate structure and the second gate structure.

6. The semiconductor device according to claim 5, wherein: The length of the second source / drain region is shorter than the length of the first source / drain region.

7. The semiconductor device according to claim 5, wherein: The length of the second source / drain region is half the length of the first source / drain region.

8. The semiconductor device according to claim 5, wherein: The first source / drain region and the second source / drain region are arranged along the second direction.

9. A semiconductor device comprising: a first semiconductor fin and a second semiconductor fin; a first gate structure, the first gate structure spanning the first semiconductor fin and the second semiconductor fin and extending from a first end to a second end in a first direction; a second gate structure that spans the second semiconductor fin and is spaced apart from the first semiconductor fin and extends from a third end to a fourth end in the first direction, wherein the first end of the first gate structure and the third end of the second gate structure are not aligned; and A first epitaxial structure and a second epitaxial structure, wherein the first epitaxial structure and the second epitaxial structure are located above the first semiconductor fin and on opposite sides of the first gate structure, wherein the first epitaxial structure and the second epitaxial structure have different lengths.

10. The semiconductor device according to claim 9, wherein The first epitaxial structure is located at the third end of the second gate structure, and a length of the first epitaxial structure is greater than a length of the second epitaxial structure.

11. The semiconductor device according to claim 10, wherein: The length of the first epitaxial structure is twice the length of the second epitaxial structure. 12 . The semiconductor device of claim 9 , further comprising a third epitaxial structure and a fourth epitaxial structure, the third epitaxial structure and the fourth epitaxial structure being located above the second semiconductor fin and on opposite sides of the second gate structure.

13. The semiconductor device according to claim 12, wherein: The third epitaxial structure and the fourth epitaxial structure have the same length.

14. The semiconductor device according to claim 12, wherein: The second epitaxial structure and the third epitaxial structure have the same length.

15. The semiconductor device according to claim 12, wherein: An edge of the first epitaxial structure is aligned with an edge of the fourth epitaxial structure.

16. The semiconductor device according to claim 15, wherein: The third epitaxial structure is located between the first gate structure and the second gate structure.

17. A method for manufacturing a semiconductor device, comprising: forming an active region above the substrate; forming a first gate structure, a second gate structure, and a third gate structure over the substrate and across the active region, wherein the first gate structure, the second gate structure, and the third gate structure have a constant spacing; removing a portion of the second gate structure between the first gate structure and the third gate structure to expose a portion of the active region; and A first epitaxial structure is formed on at least the exposed portion of the active region.

18. The method according to claim 17, wherein: The first epitaxial structure is formed between the first gate structure and the third gate structure.

19. The method according to claim 17, further comprising: A second epitaxial structure is formed over the active region and between the first gate structure and the second gate structure, wherein the first epitaxial structure is formed such that a first length of the first epitaxial structure is greater than a second length of the second epitaxial structure.

20. The method according to claim 19, wherein: The first length is n times the second length, and n is a positive integer.

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