Semiconductor structure and method for forming the same

Abstract

The present disclosure describes a method for reducing RC delay in a device operating at radio frequency or a device that would benefit from RC delay reduction. The method includes forming a transistor structure having a source / drain region and a gate structure on a substrate; depositing a first dielectric layer on the substrate to embed the transistor structure; forming a source / drain contact on the source / drain region of the transistor structure within the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; forming a metal line in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching the second dielectric layer between the metal lines and the first dielectric layer between the source / drain contacts through the opening; depositing a third dielectric layer in the first and second dielectric layers and above the transistor structure to form an air gap. Embodiments of the present application provide semiconductor structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Active devices (e.g., transistors) in both logic and memory chips are electrically connected to each other and to other areas of the chip through metal wiring. The wires in the metal wiring are separated from each other by non-conductive (e.g., electrically insulating) dielectric layers. In both logic and memory chips, the role of metal wiring is to transmit signals from one area of ​​the chip to another. Improving the speed of signal transmission while minimizing signal loss is critical to device scaling. Summary of the invention

[0003] In some embodiments, a structure includes: a substrate on which a first transistor and a second transistor are formed, wherein the first transistor and the second transistor have equal heights and each of the first transistor and the second transistor includes a source / drain region and a gate structure; a local interconnect layer including a source / drain contact and a gate contact connected to the source / drain region and the gate structure of the first transistor and the second transistor, respectively, wherein the source / drain contact is taller than the gate structure of the first transistor and the second transistor; a first interconnect layer located on the local interconnect layer, including metal lines connected to the source / drain contacts and the gate contacts of the local interconnect layer; and an air gap extending into the local interconnect layer and the first interconnect layer.

[0004] In some embodiments, a structure includes: a substrate having a transistor structure formed thereon, the transistor structure including a source / drain region and a gate structure; a local interconnect layer including a source / drain contact connected to the source / drain region of the transistor structure; a first interconnect layer disposed on the local interconnect layer, the first interconnect layer including a metal line connected to the source / drain contact of the local interconnect layer; and an air gap located within the first interconnect layer, wherein the air gap is located above the transistor structure and extends between adjacent metal lines of the first interconnect layer.

[0005] In some embodiments, a method includes: forming a transistor structure on a substrate, wherein the transistor structure includes a source / drain region and a gate structure disposed in the substrate; depositing a first dielectric layer on the substrate to embed the transistor structure; forming a source / drain contact located on the source / drain region of the transistor structure within the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; forming a metal line in the second dielectric layer to connect to the source / drain contact; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching the second dielectric layer between the metal lines and the first dielectric layer between the source / drain contacts through the opening to form an extended opening; and depositing a third dielectric layer to seal the extended opening and form an air gap in the first dielectric layer and the second dielectric layer and above the transistor structure.

[0006] Embodiments of the present application provide for reducing RC delay in a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1A to 3 is a cross-sectional view of a local contact having a reduced height and an air gap formed over a transistor structure in accordance with some embodiments.

[0009] Figure 4 and Figure 5 is a flow chart of a method for forming a local contact with a reduced height and air gap on a transistor structure, according to some embodiments.

[0010] Figure 6 is a cross-sectional view of an intermediate structure during fabrication of an air gap over a transistor structure according to some embodiments.

[0011] Figure 7 is a top view of an intermediate structure during fabrication of an air gap over a transistor structure according to some embodiments.

[0012] Figures 8 to 10 is a cross-sectional view of an intermediate structure during fabrication of an air gap over a transistor structure, according to some embodiments.

[0013] Figures 11 to 16 is a cross-sectional view of a local contact with a reduced height and an air gap formed over a transistor structure in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The manufacture and use of illustrative embodiments are discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be implemented in a variety of specific forms. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first component is formed on the second component, and may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which additional components are formed between the first component and the second component, so that the first and second components are not in direct contact. Of course, the description will specifically explain whether the components are in direct contact with each other. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is only for the purpose of simplicity and does not itself specify the relationship between the various embodiments and / or the structures discussed.

[0015] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly.

[0016] As used herein, the term "nominal" refers to the desired or target value for a characteristic or parameter of a component or process operation, as set during the design phase of a product or process, as well as values ​​above and / or below the desired value. The range of values ​​is usually due to minor variations in the manufacturing process or tolerances.

[0017] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0018] As used herein, the term "vertical" refers to nominally perpendicular to the surface of a substrate.

[0019] The speed at which signals propagate in logic and memory lines is determined by the product of resistance and capacitance, commonly referred to as “RC delay.” Reducing both resistance and capacitance is desirable to achieve fast signal propagation within a chip. Devices operating at radio frequencies (RF), such as RF switches and low-noise amplifiers (LNAs), are particularly susceptible to RC delays, which are exacerbated by device scaling. For example, RF switching devices may exhibit poor RC performance due to the effects of back-end (BE) resistance and capacitance. This is because parasitic capacitance in the BE results in poor isolation during operation, while wire resistance results in higher insertion loss (e.g., input / output signal loss) and slower operating speeds.

[0020] Embodiments described herein are directed to a method for reducing RC delay in RF devices or other devices that would benefit from the reduction in RC delay. In some embodiments, the method includes forming a local interconnect with a reduced height, and introducing an air gap between the contacts of the local interconnect and the BE metallization layer (also referred to herein as an "interconnect layer") to address the RC delay. The embodiments described herein can be implemented globally (e.g., applied to all areas of the chip) or selectively (e.g., applied to selective areas of the chip). As an example and not limitation, the air gap formed at the transistor level (e.g., between the contacts of the local interconnect) occupies about 30% to about 70% of the available volume, and the air gap formed above the transistor level (e.g., within the first metallization layer in the BE) occupies about 40% to about 90% of the available volume. Note that the above ranges are not limiting, and values ​​outside these ranges are within the spirit and scope of the present disclosure. In some embodiments, air gaps are formed at the transistor level, above the transistor level, in these two locations, and / or other applicable locations. In other embodiments, the source / drain contact is higher than the height of the gate structure of the transistor. In some embodiments, the source / drain contacts are about 2.5 times the height of the transistor gate structure including any intermediate silicide layers. The additional height ratio of the source / drain contacts to the gate of the transistor is within the spirit and scope of the present disclosure. In some embodiments, the height of the gate contact is reduced to improve contact resistance. In some embodiments, the combination of the reduction in contact height in the local interconnect and the presence of an air gap achieves optimal RC delay reduction in the circuit.

[0021] According to some embodiments, Figure 1A1 is a partial cross-sectional view of an exemplary transistor structure A formed in the first chip region A'. In some embodiments, the transistor structure A is formed on a portion of the substrate 102. By way of example and not limitation, the transistor structure A may be a planar transistor structure or a non-planar transistor structure, such as a finFET formed on a fin structure of the substrate 102. By way of example and not limitation, the transistor structure A includes a channel region 100, a source / drain region 105, a gate structure 110, and spacers 115a and 115b. In some embodiments, as Figure 1A and Figure 1B As shown in the exemplary layout diagram of chip regions A' and A", spacers 115a and 115b from transistor structure A and gate structure 110 extend in a second chip region A" on a dielectric layer 102' disposed on substrate 102. In some embodiments, gate structure 110 also includes a gate electrode 110a and a gate dielectric stack 110b. Additional transistor structures such as transistor structure A may be formed in other regions of the chip. For simplicity, Figure 1A Additional transistor structures are not shown in the figure. By way of example and not limitation, transistor structure A may be part of an RF circuit, such as an RF switching circuit or an LNA circuit. Alternatively, transistor structure A may be part of a DC circuit that may be affected by RC delay.

[0022] According to some embodiments, if the gate structure 110 includes polysilicon, a silicide layer 120 is formed on each of the source / drain region 105 and the gate structure 110 to reduce the contact resistance between the source / drain contact 125 of the first chip region A' and the source / drain region 105, and between the gate contact 130 of the second chip region A" and the gate structure 110. The source / drain contact 125 of the first chip region A' and the gate contact 130 of the second chip region A" form a network of contact structures, collectively referred to herein as local interconnects.

[0023] In some embodiments, if the gate electrode 110a includes polysilicon, the silicide layer 120 formed on the gate structure 110 is in direct contact with the gate electrode 110a. In some embodiments, if the gate electrode 110a includes a metal stack, the silicide layer 120 is omitted, and the gate dielectric stack 110b includes a high-k dielectric material, for example, a dielectric material having a dielectric constant (k value) greater than about 3.9.

[0024] In some embodiments, local interconnect contacts, such as source / drain contacts 125 and gate contacts 130, are shortened [e.g., reduced in height (e.g., in the z direction)] to reduce contact resistance (e.g., to reduce the resistance component of the RC delay). For example, heights H1 and H3 of the respective source / drain contacts 125 and gate contacts 130 have been shortened relative to their original heights. According to some embodiments, height H1 of source / drain contact 125 is greater than height H2 and is equal to or less than approximately 2.5 times (e.g., 1 Figure 1A As shown, heights H1 and H3 of the source / drain contacts 125 and the gate contact 130 are measured from the bottom surface of the contacts to the top surface of the contacts, respectively.

[0025] Since the source / drain contacts 125 and the gate contacts 130 are shorter at this time, the first metallization layer 135 is formed closer to the transistor structure A. This in turn increases the parasitic capacitance formed between the metal line 135a and the gate structure 110, which affects the RC delay of the circuit. In some embodiments, to compensate for the subsequent increase in parasitic capacitance, an air gap 140 is formed above the gate structure 110 of the transistor structure A within the first chip area A' by an interlayer dielectric (ILD) 145 and an intermetallic dielectric (IMD) 150. In some embodiments, an ILD 145 is formed around the local interconnect (e.g., the source / drain contacts 125 and the gate contacts 130) and the gate structure 110 of the transistor structure A as a means of electrical isolation. Separately, an IMD 150 is formed between the metal lines 135a of the first metallization layer 135 as a means of electrical isolation. Due to the formation process of the air gap 140 and the deposition characteristics of the IMD150, the air gap 140 can extend to the IMD150 of the second metal layer 155, and the second metal layer 155 includes a metal line 155a and a metal vertical interconnect access line ("via") 155b. Metallization layers such as the first and second metallization layers 135 and 155 are also collectively referred to herein as global interconnects, global interconnect layers, or interconnect layers. In some embodiments, the air gap 140 does not extend into the second chip area A". Therefore, there is no overlap between the air gap 140 and the gate contact 130.

[0026] By way of example and not limitation, Figure 1B It is above relative to Figure 1A Layout diagram of the chip areas A' and A" in question. Figure 1B The layout diagram shows Figure 1A ​In some embodiments, Figure 1A The cross-sectional view of the chip region A' shown corresponds to the cross-sectional view along Figure 1B The cross section is taken from line CD. Therefore, Figure 1A The cross-sectional view of the chip region A" shown corresponds to the cross-sectional view along Figure 1B The cross section is taken by line EF. Figure 1B As shown and discussed above, the air gap 140 indicated by the dashed line is formed in the first chip region A′ and does not extend into the second chip region A′. As a result, there is no overlap between the air gap 140 and the gate contact 130 .

[0027] like Figure 1A As shown, the inner surface of the air gap 140 is lined with a liner 140a. In some embodiments, the liner 140a includes, for example, silicon nitride (Si 3 N 4 ) one or more dielectric layers; silicon nitride (Si 3 N4); a stack of silicon carbide (SiC); Si 3 N4 and SiC stack; ILD, Si 3 N 4 and IMD stacking parts; ILD, Si 3 N 4 , a stack of SiC and IMD; or any combination thereof.

[0028] In some embodiments, additional metallization layers, such as a third metallization layer 160 having metal lines 160a and vias 160b, are formed over the second metallization layer 155. As an example and not limitation, the metallization layers may be separated by an etch stop layer 165. Figure 1A As shown, a contact etch stop layer 170 may be formed on the gate structure 100 in the first and second chip regions A' and A", respectively. In addition, the contact etch stop layer 170 may extend on the silicide layer 120, which is disposed on the source / drain region 105 in the first chip region A' and on the dielectric layer 102' in the second chip region A". The etch stop layers (e.g., the etch stop layer 165 and the contact etch stop layer 170) facilitate the formation of local and global interconnects (e.g., the source / drain contacts 125, the gate contacts 130, the metal lines 135a, and the vias 155b / 160b). In some embodiments, the gate structure 100 may be formed on the gate structure 100. Figure 1A For simplicity, these additional etch stop layers are not shown in FIG. Figure 1A For ease of explanation, Figure 1ANot shown are additional layers such as barrier layers included in metal lines, vias, and contacts; work function layers in the gate electrode 110a; dielectric layers in the dielectric stack 110b; capping layers, or isolation structures.

[0029] In some embodiments, the air gap 140 in the ILD 145 occupies about 30% to about 70% of the available space between the source / drain contacts 125 and the transistor structure A. In addition, the air gap 140 in the first metallization layer 135 occupies about 40% to about 90% of the available space between the metal lines 135a of the first metallization layer 135. In some embodiments, the shape of the air gap 140 may be different from Figure 1A 140. For example, the bottom of the air gap 140 may extend toward the silicide layer 120 disposed on the source / drain region 105, or may occupy the entire space between the source / drain contact 125 and the contact etch stop layer 170. In some embodiments, the volume of the air gap 140 in the IMD 150 is greater than the volume of the air gap 140 in the ILD 145. In some embodiments, when used in combination with shorter S / D contacts 125 and gate contacts 130, occupying less than about 30% of the air gap in the ILD 145 and occupying less than about 40% of the air gap in the first metallization layer 135 may not sufficiently reduce the RC delay. On the other hand, in some embodiments, occupying more than about 70% of the air gap in the ILD 145 and occupying more than about 90% of the air gap in the first metallization layer 135 may impair the mechanical strength of the ILD 145 and the first metallization layer 135.

[0030] According to some embodiments, and in order to further reduce parasitic capacitance and RC delay, as Figure 2 As shown, the air gap 140 can extend to the second metallization layer 155 and the third metallization layer 160 (e.g., along the z-direction). In some embodiments, extending the air gap 140 into the second metallization 155 further reduces parasitic capacitance and RC delay compared to an air gap extending only into the first metallization layer 135. In some embodiments, extending the air gap 140 into the third metallization layer 160 can further reduce parasitic capacitance and RC delay compared to, for example, an air gap extending only into the second metallization layer 155. In some embodiments, as discussed later, all portions of the air gap 140 can be formed in one or more operations. In other embodiments, the air gap 140 may not be formed in the ILD 145. For example, as shown in FIG. Figure 3 As shown, the air gap 140 may be selectively formed in the first metallization layer 135 and partially extend to the second metallization layer 155. Therefore, the air gap 140 may be selectively formed at different locations to suppress the formation of parasitic capacitance.

[0031] Figure 4 and 5is used to form the above Figure 1A Flowchart of a method 400 for fabricating a local interconnect with reduced height and air gap according to an embodiment shown. Variations of method 400 may be used to form Figure 2 and Figure 3 The air gap of the illustrated embodiment. Additional manufacturing operations may be performed between the various operations of method 400 and may be omitted for purposes of clarity and ease of description only. These additional manufacturing operations are within the spirit and scope of the present disclosure. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in parallel. Figure 4 and Figure 5 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. For purposes of illustration, reference will be made to Figures 6 to 10 The illustrated embodiment describes a method 400. The drawings provided for describing the method 400 are for illustrative purposes only and are not drawn to scale. Some structures, films, or geometric shapes may be intentionally exaggerated for illustrative purposes.

[0032] refer to Figure 4 The method 400 begins with operation 410 and forming a transistor structure on a substrate (eg, Figure 6 The transistor structure A) shown in FIG. 1 and FIG. 2 is a semiconductor substrate 102. Figure 6 The transistor A shown is substantially similar. By way of example and not limitation, semiconductor substrate 102 may be a bulk semiconductor wafer (e.g., crystalline silicon), a semiconductor on insulator (SOI) wafer, or a semiconductor fin structure formed on a bulk semiconductor wafer or SOI wafer. In some embodiments, if transistor structure A is formed on a fin structure, the fin structures will have a plurality of fins along the fin structure. Figure 1A and Figure 6 The length in the x direction and along Figure 1A and Figure 6The width in the Y direction in . In some embodiments, the channel region 100 may be part of the semiconductor substrate 102 or part of the semiconductor fin structure formed on or from the semiconductor substrate 102. The source / drain region 105 includes one or more epitaxial layers (e.g., an epitaxially grown silicon-germanium layer, or an epitaxially grown silicon layer doped with carbon and phosphorus or carbon and arsenic) formed in a recessed portion of the semiconductor substrate 102 or on a recessed portion of the semiconductor fin structure. In some embodiments, the source / drain region 105 is simply a doped region of the semiconductor substrate 102. In some embodiments, the silicide layer 120 is a product of a silicidation process between the deposited metal and the underlying silicon atoms (if present). If silicon atoms are not present, silicide will not be formed. For example, if the gate electrode 100a is a metal stack including a metal work function layer and a metal filler, the silicide layer 120 is not formed on the gate structure 110. However, silicide formation is essential for the source / drain region 105. The gate electrode 110a may include doped polysilicon or an optional metal layer. When the gate electrode 110a is metal, the gate dielectric stack 110b includes a high-k dielectric material to achieve optimal performance. The metal layer includes one or more work function layers and a metal fill material.

[0033] Reference Figure 4 and Figure 6 The method 400 continues with operation 415 and a process of depositing a contact etch stop layer 170 on the gate structure 110 of the transistor structure A in the first and second chip regions A' and A", respectively. Since the contact etch stop layer 170 facilitates the formation of local interconnects, blanket deposition can be performed on the regions of the chip where local interconnects (e.g., source / drain and gate contacts) are to be formed. By way of example and not limitation, the contact etch stop layer 170 includes a nitride, such as Si, that provides good etch selectivity relative to surrounding materials (e.g., ILD 145). 3 N 4 and any other suitable material.

[0034] Reference Figure 4 The method 400 continues with operation 420 and depositing the ILD 145 on the contact etch stop layer 170 as shown in FIG. Figure 6 The process of embedding transistor structure A is shown. As described above, ILD145 electrically isolates the gate structure 110 of transistor structure A from the subsequently formed local interconnect (e.g., source / drain contact 125). As an example and not limitation, ILD145 can be a silicon-based dielectric (e.g., silicon oxide) doped with carbon and containing nitrogen, hydrogen, or any other suitable dielectric material. ILD145 can be deposited by any suitable deposition method, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), flowable CVD, etc.

[0035] Reference Figure 4 and Figure 6 The method 400 continues with operation 425 and the process of forming source / drain contacts 125 in the first chip region A' and forming gate contacts 130 at a desired height in the second chip region A". As previously described with respect to Figure 1A As discussed, the heights H1 and H3 of the respective source / drain contacts 125 and gate contacts 130 are adjusted so that the height H1 of the source / drain contact 125 is greater than the height H2 and is equal to or less than about 2.5 times (eg, 1.5 times) the height H2.

[0036] There are many ways to achieve the above height ratio. As an example and not a limitation, one method includes: depositing a thick ILD145 (e.g., thicker than the desired heights H1 and H3); forming a contact opening in ILD145 using photolithography and etching operations; filling the contact opening with a conductive material; and flattening ILD145 in an appropriate amount to achieve the desired ratio of H1 and H3. For example, the flattening of ILD145 can be achieved by a chemical mechanical polishing (CMP) process. If the CMP process introduces undesirable thickness variations on the chip, an alternative method includes depositing ILD145 to a thickness closer to the desired heights H1 and H3, so that the CMP process removes a smaller amount of ILD material during polishing. The above method is exemplary and not restrictive. Alternative methods are possible and are within the spirit and scope of the present disclosure.

[0037] ​Note that the etching chemistry used to form the contact openings for the respective source / drain contacts 125 and the gate contact 130 is configured to exhibit low selectivity to the contact etch stop layer 170 (e.g., silicon nitride) compared to the ILD 145 (e.g., silicon oxide). This is beneficial because it helps to form contacts with different heights. For example, the source / drain contact openings and the gate contact openings are formed simultaneously. However, since the gate contact openings are shorter than the source / drain contact openings, the gate contact openings will be formed first. While the source / drain contact openings continue to be etched by the etching chemistry, the etching of the gate contact openings is significantly slowed down because the etching chemistry cannot etch through the contact etch stop layer 170. When the source / drain and gate openings are formed, the etching chemistry can be switched to another chemistry that is selectively directed to the contact etch stop layer 170 at this time, so that the etching stop layer can be removed and the underlying layers (e.g., the gate electrode 110a and the source / drain region 105) can be exposed. The thickness of the contact etch stop layer 170 can be adjusted based on the amount of additional time required to form the source / drain contact openings. In some embodiments, depending on the integration scheme, a silicide layer 120 may be formed on the source / drain regions 105 after forming the source / drain openings.

[0038] Reference Figure 4 The method 400 continues with operation 430 and the process of forming a first metallization layer on the ILD 145. Figure 1A , a first metallization layer 135 may be formed, for example, by depositing an etch stop layer 165 on the polished ILD 145; then depositing an IMD 150 on the etch stop layer 165; etching openings in the IMD 150 and the etch stop layer 165 to expose the underlying local interconnects; depositing one or more conductive materials to fill the openings and form lines 135a; and Figure 1A As shown, excess deposited material is polished away over IMD 150 such that a top surface of line 135 a is coplanar with a top surface of IMD 150 .

[0039] Like the contact etch stop layer 170, the etch stop layer 165 may also include a nitride, such as Si 3 N 4. Like ILD145, additional IMD150 can be a similar silicon oxide-based dielectric, such as carbon-doped silicon oxide containing hydrogen or nitrogen. In some embodiments, IMD150 can be a porous material, such as silicon oxide having pores. According to some embodiments, the conductive material used to fill line 135a is different from the conductive material used to fill source / drain contacts 125 and gate contact 130. As an example and not limitation, line 135a can be filled with copper, while source / drain contacts 125 and gate contact 130 can be filled with cobalt or tungsten. In addition, line 135a can be larger (e.g., wider) than source / drain contacts 125 and gate contact 130.

[0040] Reference Figure 5 , the method 400 continues with operation 435 and the process of forming an opening in the first metallization layer 135 to expose the ILD 145 above the transistor structure A. In some embodiments, the opening formed in operation 435 is used to form Figure 1A As described above, the opening of operation 435 is formed in the first chip region A' and does not extend to the second chip region A". As an example and not limitation, the opening can be formed by depositing a photoresist on the IMD 150, patterning the photoresist, and etching the IMD 150 of the first metallization layer 135 through the opening in the photoresist. After the opening is formed in the first metallization layer 135, the photoresist can be removed, for example, by a wet etching process. The resulting structure is Figure 6 , where an opening 600 is formed in the IMD 150 of the first metallization layer 135 to expose the ILD 145 . In some embodiments, the opening 600 is partially formed in the ILD 145 .

[0041] According to some embodiments, the sidewall angle θ of the opening 600 may be about 90°, greater than about 90° (e.g., 110°), or less than about 90° (e.g., 80°). In some embodiments, the sidewall angle θ is about 90°±20°. However, these angles are not limiting, and the opening 600 may be formed to have an angle greater than 110° or less than about 80°. As an example and not a limitation, the opening 600 may have substantially vertical sidewalls, wherein the top opening 600t is substantially equal to the bottom opening 600b (e.g., 600t=600b); the opening 600 may have a positive tapered profile, wherein the top opening 600t is wider than the bottom opening 600b (e.g., 600t>600b); or the opening 600 may have a negative tapered profile, wherein the top opening 600t is narrower than the bottom opening 600b (e.g., 600t<600b). The profile of the opening 600 determines, to a certain extent, the shape of the air gap formed in operation 450. In some embodiments, the top opening 600t is about 25% to about 30% of the distance 605 between adjacent wires 135a. However, these percentages are not limiting, and a wider or narrower top opening 600t may be formed.

[0042] Note that additional openings such as opening 600 may be formed in the first metallization layer 135 at other locations of the chip over other transistor structures. By way of example and not limitation, Figure 7 yes Figure 6 An exemplary top view of transistor structure A in FIG. Figure 7 Shows Figure 6 Selective parts of , other parts are omitted only for the sake of clarity. Figure 1A and Figure 1B For example, Figure 6 The cross-sectional view of the chip region A' shown in FIG. Figure 7 The cross section is taken from the CD line. Therefore, Figure 6 The cross-sectional view of the chip region A" shown corresponds to the cross-sectional view along Figure 7 The cross section is taken by line EF. Figure 7 As shown and as described above, the opening 600 indicated by the dashed line is formed in the first chip region A′ and does not extend into the second chip region A″. As a result, there is no overlap between the opening 600 and the gate contact 130 . Figure 7 The top view of is illustrative and not restrictive. Figure 6 Different arrangements of the elements are possible and are within the spirit and scope of the present disclosure. In some embodiments, the size of the opening 600 along the y-direction can define the lateral size of the air gap in that direction.

[0043] Reference Figure 5The method 400 continues with operation 440 and the process of removing a portion of the ILD 145 and a portion of the IMD 150 in the first metallization layer 135 through the opening 600 to form an extended opening (eg, an extended opening), as shown in FIG. Figure 8 The extended opening 800 is shown. In some embodiments, in addition to Figure 8 In addition to the xz plane shown, the extended opening 800 also extends along the y direction. In some embodiments, the etching process used to form the extended opening 800 includes a dry etching chemistry, a wet etching chemistry, or a combination thereof. According to some embodiments, the etching chemistry is isotropic or a combination of isotropic and anisotropic, which has a high selectivity to silicon oxide-based materials (e.g., IMD150 and ILD145) and a low selectivity to the etch stop layer 165 and the contact etch stop layer 170 (e.g., silicon nitride or nitride material). In addition, the etching chemistry is configured to exhibit low selectivity to the materials used in the line 135a and the source / drain contact 125. In some embodiments, due to the isotropy of the etching process, the extended opening 800 may form a curved or rounded inner surface (e.g., a convex or concave surface), a straight inner surface, or a combination thereof. For the same reason, the extended opening 800 may be formed with sharp corners, rounded corners, or a combination thereof. Therefore, the shape of the extended opening 800 may deviate from Figure 8 Shape shown.

[0044] By way of example and not limitation, the dry etch chemistry may be based on a fluorocarbon chemistry and may include tetrafluoromethane (CF 4 ), octafluoropropane (C 3 F 8 ), octafluorocyclobutane (C 4 F 8 ), fluoroform (CHF 3 ), nitrogen trifluoride (NF 3 ), sulfur trifluoride (SF 3 ) or a combination thereof. The dry etch chemistry may also include a buffer gas such as argon (Ar) or helium (He). The selectivity of the dry etch chemistry may be fine-tuned by adding hydrogen or oxygen to the gas mixture.

[0045] By way of example and not limitation, the wet etch chemistry may include ammonium fluoride (NF 4 F), which is called buffered oxide etch (BOE) or buffered HF (BHF). Silicon oxide is an amorphous material that etches isotropically when exposed to BOE.

[0046] The etching process may be timed so that the size of the extended opening 800 may be controlled. In some embodiments, the extended opening 800 may extend to a region 805 between the contact etch stop layer 170 and the source / drain contacts 125, as described above.

[0047] Reference Figure 5 , method 400 continues with operation 445 and depositing a liner (eg, Figure 1A As an example and not limitation, Fig. 9 The liner 140a is shown deposited in the extended opening 800. In some embodiments, the liner 140a is also deposited outside the extended opening 800 (e.g., on the horizontal surface of the etch stop layer 165). However, if desired, Fig.10 As shown, the portion of the liner 140a located outside the extended opening 800 can be removed by an anisotropic etching operation. As described above, the liner 140a includes a stack or a single layer of dielectric layers. For example, the liner 140a includes, for example, silicon nitride (Si 3 N 4 ) one or more dielectric layers; silicon nitride (Si 3 N4); a stack of silicon carbide (SiC); Si 3 N4 and SiC stack; ILD, Si 3 N 4 and IMD stacking parts; ILD, Si 3 N 4 , SiC and IMD stack; or any combination thereof. As an example and not limitation, the thickness of the liner 140a is in the range of about 10 nm to about 50 nm. Fig.10 As shown, the liner 140a does not fill the extended opening 800, but covers the inner sidewalls (or inner sidewall surfaces) of the opening 800. Due to the deposition of the liner 140a, the top opening 800t of the extended opening 800 is reduced by the amount of the thickness of the liner 140a on the sidewalls of the upper etch stop layer 165. In some embodiments, and before the deposition of the liner 140a, the top opening 800t is substantially equal to Figure 6 The top opening 600 of the illustrated opening 600 is open 600 t , provided that the etching chemistry used to form the extended opening 800 does not attack the etch stop layer 165 .

[0048] In some embodiments, the liner 140a is deposited using a conformal deposition process [e.g., atomic layer deposition (ALD), plasma assisted ALD (PEALD), chemical vapor deposition (CVD), plasma assisted CVD (PECVD), or any deposition process capable of depositing a conformal layer with a combined thickness of about 10 nm to about 50 nm].

[0049] Reference Figure 5 The method 400 continues with operation 450 and forms a second metallization layer (eg, similar to Figure 1A The process of forming the second metallization layer 155 as shown in the figure to seal the extended opening 800 and form the air gap 140. Figure 1A , the second metallization layer 155 may be formed, for example, by depositing another etch stop layer 165 on the IMD 150 of the first metallization layer 135. Etching the IMD 150 and the etch stop layer 165 to expose the underlying metal line 135a and form a via and line opening; depositing one or more conductive materials to fill the via and line opening by, for example, a dual damascene process to form a via 155b and a metal line 155a; and then polishing away excess deposited material on the IMD 150 so that the top surface of the metal line 155a is coplanar with the top surface of the IMD 150, as shown in FIG. Figure 1A In some embodiments, an additional metallization layer (eg, a third metallization layer 160 ) may be formed on the second metallization layer 155 .

[0050] According to some embodiments, Figure 1A As shown, during the deposition of the IMD 150 of the second metallization layer 155, a pinch point or rounded top surface 140b is formed within the IMD 150. The pinch point or rounded top surface 140b can be attributed to an overhang formed by the IMD material during the early stages of the IMD deposition. In some embodiments, Figure 1A The pinch point or rounded top surface 140b is shown as Figure 2 and Figure 3 (and subsequently in Figures 11 to 16 In some embodiments, the pinch point or rounded top surface 140b does not extend to more than about 60% of the height of the adjacent metallization layer. Figure 1A In the embodiment, the height 140bh of the pinch point or rounded top surface 140b is less than about 60% of the height 155h of the second metallization layer 155 (eg, 140bh < 0.6155h). Fig.10 When the top opening 800t is shown, the IMD material can be prevented from being deposited in the extended opening 800. Therefore, the deposition rate of the top opening 800t and the IMD 150 is promoted. Figure 1A The formation of air gap 140 is shown.

[0051] By way of example and not limitation, top opening 800t may be adjusted by opening 600, and more specifically, by Figure 6In some embodiments, the sidewall angle θ can be adjusted based on the deposition rate. IMD150 helps to form the air gap 140. For example, a positive tapered profile in which the top opening 600t is wider than the bottom opening 600b (e.g., 600t>600b) may be suitable for a high deposition rate process. At the same time, a negative tapered profile in which the top opening 600t is narrower than the bottom opening 600b (e.g., 600t<600b) may be suitable for a lower deposition rate process. In addition, the negative tapered profile for the opening 600 means that the top opening 800t will be smaller and sealed faster during the deposition of IMD150. As an example and not limitation, as shown in Figure 5 As described in operation 435 of , the size and profile of the opening 600 may be adjusted through patterning and etching processes.

[0052] As described above, the size of the top opening 800t is related to the size of the top opening 600t. In addition, as described above, the top opening 600t may be, for example, Figure 6 The distance 605 between adjacent lines 135a shown is between about 25% and about 30%. In some embodiments, if the top opening 600t is less than about 25% of the distance 605, the etching chemistry used to form the extended opening 800 may not reach the ILD 145 or may require a longer etching time, which is undesirable. On the other hand, in some embodiments, if the top opening 600t is greater than about 30% of the distance 605, Figure 1A The formation of the air gap 140 shown in FIG. 1 may be challenging because the IMD material may be deposited on and fill the Figure 8 The extended opening 800 is shown.

[0053] Variations of method 400 may be used to form Figure 2 In some embodiments, to generate the air gap 140 Figure 2 The method can form the first and second metallization layers 135 and 155; form an opening 600 in the second metallization layer 155 extending to the first metallization layer 136 and the ILD 145; form an extended opening in the IMD 150 of the second and first metallization layers and the ILD 145; deposit a liner 140a; and form a third metallization layer 160. Formation Figure 2 Another way to show the air gap is to Figure 1A The air gap 140 is shown extending to the second metallization layer 155. For example, Figure 1AStarting from the air gap 140 shown, before forming the third metallization layer 160, an opening 600 is formed in the second metallization layer 155 to expose the air gap 140 in the first metallization layer 135, thereby forming an extended opening 800 in the second metallization layer 155; a pad 140a is deposited in the new extended opening 800; and then the third metallization layer 160 is formed to form Figure 2 The air gap 140 is shown. In some embodiments, Figure 1A The existing liner 104a in the air gap 140 protects the surrounding IMD 150 in the first metallization layer 135 and ILD 145 from being Figure 2 The additional etching is caused by the etching chemistry that forms the air gap 140 in the second metallization layer 155.

[0054] In some embodiments, a variation of method 400 may be used to form Figure 3 In some embodiments, the air gap 140 may be Figure 6 When the opening 600 as shown and described in operation 435 stops on the etch stop layer 165 above the ILD 145 (eg, when the opening 600 does not expose the ILD 145), the etch stop layer 165 is formed. Figure 3 If the opening 600 does not expose the ILD 145, the subsequent etching process used in operation 440 will not remove the ILD 145. The above modification. Operations 440, 445 and 450 will form Figure 3 An air gap 140 is shown.

[0055] The above-described variations of method 400 are not limiting, and other variations are possible. These alternative modifications of method 400 are within the spirit and scope of the present disclosure.

[0056] By way of example and not limitation, Figures 11 to 16 is an example of forming air gaps 140 on similar transistor structures A and B in the first chip region A' according to the operations of the above method 400 or a variation thereof. Fig.11 In FIG. 1 , transistor structures A and B have an air gap 140 extending through the second metallization layer 155 , the first metallization layer 135 , and the ILD 145 . Fig.12 In FIG. 1 , the air gap 140 in the first metallization layers 135 and 110 and the second metallization layer 155 is formed above both transistor structures A and B. Fig.13 In FIG. 1 , the air gap 140 is selectively formed above the transistor structure A, while the adjacent transistor structure B does not include an air gap thereover. Fig.14 In, with Fig.11 Similarly, air gaps 140 are formed on both transistor structures A and B; however, the wiring layout of the second metallization layer 155 and the third metallization layer 160 is different from Fig.11The wiring layout shown is different. Fig.15 In FIG. 1 , both transistor structures A and B have an air gap 140 passing through the third metallization layer 160 , the second metallization layer 155 , the first metallization layer 135 , and the ILD 145 . Finally, Fig.16 is a cross-sectional view of two chip regions K and R having similar transistor structures A and B. In some embodiments, the chip region K is substantially similar to the height H1 configuration of the source / drain contact 125 in the first chip region A' discussed above, for example, greater than the height H2 and equal to or less than about 2.5 times the height H2. In addition, an air gap 140 is formed above the transistor structure A. In contrast, in the chip region R, the height of the source / drain contact 125' is greater than about 2.5 times the height H2, and there is no air gap above the transistor structure B. As an example and not limitation, the transistor structure A within the chip region K is part of an RF circuit that is sensitive to RC delay, so the shorter source / drain contact 125 and the air gap 140 can reduce the RC delay. On the other hand, the structure B in the chip region R is part of a circuit that is less sensitive to RC delay. In some embodiments, the chip regions K and R may be separated by the isolation region 1600 or may be adjacent to each other in a separated manner by other regions of the chip. Fig.16 The example illustrates that method 400 may be applied to selected portions / areas of a chip to mitigate issues related to RC delays.

[0057] In addition to the above, Figures 1 to Figure 3 and Figures 11 to 16 Various arrangements of the embodiments described in are possible and are within the spirit and scope of the present disclosure.

[0058] Embodiments described herein are directed to a method for reducing RC delay in an RF device or other device that would benefit from the reduction in RC delay. In some embodiments, the method includes forming local interconnects, such as source / drain and gate contacts, with reduced heights, and introducing air gaps between the above contacts and the BE metallization layer to reduce parasitic capacitance. The embodiments described herein can be implemented globally (e.g., applied to all areas of the chip) or selectively (e.g., applied to selective areas of the chip). In some embodiments, the portion of the air gap formed between the local interconnects occupies about 30% to about 70% of the available volume, and the portion of the air gap formed above the transistor level (e.g., within the first metallization layer of the BE) occupies about 40% to about 90% of the available volume. In some embodiments, the air gap is formed at the transistor level (e.g., in the ILD of the local interconnect), above the transistor level (e.g., in the IMD of the metallization layer), or a combination thereof. In a further embodiment, the source / drain contact is taller than the height of the gate structure of the transistor, but not higher than about 2.5 times the height of the gate structure of the transistor including any intermediate silicide layer. In some embodiments, the height of the gate contact is reduced to improve the contact resistance, and the height of the gate contact is configured to be about 0.25 times to about 1.5 times the height of the gate structure of the transistor (including any intermediate silicide layer on the transistor structure). In some embodiments, the combination of reducing the height of the contact in the local interconnect and the presence of the air gap achieves a reduction in RC delay in the circuit as described herein.

[0059] In some embodiments, a structure includes a substrate having a first transistor and a second transistor formed thereon, wherein the first transistor and the second transistor have equal heights and each include a source / drain region and a gate structure. The structure also includes a local interconnect layer, the local interconnect layer including source / drain contacts and gate contacts connected to the source / drain regions and the gate structure of the first transistor and the second transistor, respectively, wherein the source / drain contacts are taller than the gate structures of the first transistor and the second transistor. The structure also includes a first interconnect layer on the local interconnect layer, wherein metal lines are connected to the source / drain contacts and the gate contacts of the local interconnect layer, and air gaps extending into the local interconnect layer and the first interconnect layer.

[0060] In some embodiments, a structure includes a substrate having a transistor structure formed thereon, wherein the transistor structure includes a source / drain region and a gate structure; a local interconnect layer, whose source / drain contacts are connected to the source / drain region of the transistor structure; a first interconnect layer is disposed on the local interconnect layer, wherein metal lines are connected to the source / drain contacts of the local interconnect layer; and an air gap in the first interconnect layer is located above the transistor structure and extends between adjacent metal lines of the first interconnect layer.

[0061] In some embodiments, a method includes forming a transistor structure on a substrate, wherein the transistor structure includes a source / drain region and a gate structure disposed in the substrate; depositing a first dielectric layer on the substrate to embed the transistor structure; forming a source / drain contact located on the source / drain region of the transistor structure within the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; forming a metal line in the second dielectric layer to connect to the source / drain contact; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching the second dielectric layer between the metal lines and the first dielectric layer between the source / drain contacts through the opening to form an extended opening; depositing a third dielectric layer to seal the extended opening and form an air gap in the first and second dielectric layers and above the transistor structure.

[0062] In some embodiments, a structure includes: a substrate on which a first transistor and a second transistor are formed, wherein the first transistor and the second transistor have equal heights, and each of the first transistor and the second transistor includes a source / drain region and a gate structure; a local interconnect layer including a source / drain contact and a gate contact connected to the source / drain region and the gate structure of the first transistor and the second transistor, respectively, wherein the source / drain contact is taller than the gate structure of the first transistor and the second transistor; a first interconnect layer located on the local interconnect layer, including a metal line connected to the source / drain contact and the gate contact of the local interconnect layer; and an air gap extending into the local interconnect layer and the first interconnect layer. In some embodiments, a second interconnect layer located on the first interconnect layer is further included, and the air gap extends into the second interconnect layer. In some embodiments, a second interconnect layer is further included on the first interconnect layer; and a third interconnect layer is located on the second interconnect layer, wherein the air gap extends into the second interconnect layer and the third interconnect layer. In some embodiments, the air gap occupies about 30% to about 70% of the area between the source / drain contacts above the first transistor and below the first interconnect layer. In some embodiments, the air gap occupies about 40% to 90% of the area between the metal lines of the first interconnect layer. In some embodiments, the air gap includes a liner covering the inner sidewall surface of the air gap within the local interconnect layer and the first interconnect layer. In some embodiments, the liner includes one or more dielectric layers, and the one or more dielectric layers include silicon nitride, silicon carbide, or a combination thereof. In some embodiments, the gate contact is between about 0.25 and about 1.5 times the height of the gate structure of the first transistor and the second transistor. In some embodiments, each of the source / drain contacts is shorter than about 2.5 times the height of the gate structure of the first transistor and the second transistor.

[0063] In some embodiments, a structure includes: a substrate having a transistor structure formed thereon, the transistor structure including source / drain regions and a gate structure; a local interconnect layer including a source / drain contact connected to the source / drain region of the transistor structure; a first interconnect layer disposed on the local interconnect layer, the first interconnect layer including a metal line connected to the source / drain contact of the local interconnect layer; and an air gap located within the first interconnect layer, wherein the air gap is located above the transistor structure and extends between adjacent metal lines of the first interconnect layer. In some embodiments, a second interconnect layer disposed on the first interconnect layer is further included, wherein a portion of the air gap extends from the first interconnect layer into the second interconnect layer. In some embodiments, the portion of the air gap extending from the first interconnect layer into the second interconnect layer occupies an area less than about 40% of the area between the metal lines of the second interconnect layer. In some embodiments, the portion of the air gap extending from the first interconnect layer to the second interconnect layer has a rounded top surface surrounded by a dielectric material of the second interconnect layer. In some embodiments, the height of the source / drain contact is between about 1.0 and about 2.5 times the height of the gate structure. In some embodiments, the air gap includes a liner covering an inner sidewall surface of the air gap within the first interconnect layer. In some embodiments, the liner layer does not extend into the second interconnect layer.

[0064] In some embodiments, a method includes: forming a transistor structure on a substrate, wherein the transistor structure includes a source / drain region and a gate structure disposed in the substrate; depositing a first dielectric layer on the substrate to embed the transistor structure; forming a source / drain contact located on the source / drain region of the transistor structure within the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; forming a metal line in the second dielectric layer to connect to the source / drain contact; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching the second dielectric layer between the metal lines and the first dielectric layer between the source / drain contacts through the opening to form an extended opening; and depositing a third dielectric layer to seal the extended opening and form an air gap in the first dielectric layer and the second dielectric layer and above the transistor structure. In some embodiments, forming the source / drain contact includes forming the source / drain contact at a height between about 1.0 and about 2.5 times the height of the gate structure. In some embodiments, after the etching, a liner is deposited to cover an inner surface of the extended opening. In some embodiments, a top of the opening is between about 25% and about 30% of a distance between the metal lines.

[0065] It should be understood that the "Detailed Description" section, rather than the "Abstract of the Abstract" section, is intended to be used to interpret the claims. As intended by the inventors, the Abstract of the Disclosure Section may set forth one or more but not all possible embodiments of the present disclosure and, therefore, is not intended to limit the dependent claims in any way.

[0066] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a substrate having a first transistor and a second transistor formed thereon, wherein the first transistor and the second transistor have equal heights, and each of the first transistor and the second transistor includes a source / drain region and a gate structure; a local interconnect layer, comprising source / drain contacts and gate contacts connected to the source / drain regions and the gate structures of the first and second transistors, respectively, wherein the source / drain contacts are higher than the gate structures of the first and second transistors; a first interconnect layer, located on the local interconnect layer, comprising metal lines connected to the source / drain contacts and the gate contacts of the local interconnect layer; an etch stop layer located on the first interconnect layer; and an air gap extending into the local interconnect layer and the first interconnect layer and through the etch stop layer; A liner layer covers the local interconnect layer and inner sidewall surfaces of the air gaps in the first interconnect layer, and the liner layer extends to the level of the top surface of the etch stop layer. 2 . The semiconductor structure of claim 1 , further comprising a second interconnect layer on the first interconnect layer, the air gap extending into the second interconnect layer.

3. The semiconductor structure according to claim 1, further comprising: a second interconnect layer, located on the first interconnect layer; as well as A third interconnect layer is located on the second interconnect layer, wherein the air gap extends into the second interconnect layer.

4. The semiconductor structure according to claim 1, wherein: The air gap occupies 30% to 70% of an area between the source / drain contacts above the first transistor and below the first interconnect layer.

5. The semiconductor structure according to claim 1, wherein: The air gap occupies 40% to 90% of a region between the metal lines of the first interconnect layer.

6. The semiconductor structure according to claim 1, wherein: The air gap has a circular top surface.

7. The semiconductor structure according to claim 1, wherein: The liner includes one or more dielectric layers including silicon nitride, silicon carbide, or a combination thereof.

8. The semiconductor structure according to claim 1, wherein: The gate contact is between 0.25 and 1.5 times the height of the gate structures of the first and second transistors.

9. The semiconductor structure according to claim 1, wherein: Each of the source / drain contacts is shorter than 2.5 times the height of the gate structures of the first and second transistors.

10. A semiconductor structure comprising: A substrate having a transistor structure formed thereon, the transistor structure comprising a source / drain region and a gate structure; a local interconnect layer including source / drain contacts connected to said source / drain regions of said transistor structure; a first interconnect layer disposed on the local interconnect layer, the first interconnect layer comprising metal lines connected to the source / drain contacts of the local interconnect layer; an etch stop layer, located on the first interconnect layer; an air gap within the first interconnect layer and through the etch stop layer, wherein the air gap is above the transistor structure and extends between adjacent metal lines in the first interconnect layer; as well as The liner layer covers the inner sidewall surface of the air gap, and the liner layer extends to the level of the top surface of the etching stop layer.

11. The semiconductor structure according to claim 10, further comprising a second interconnect layer disposed on the first interconnect layer, wherein: Portions of the air gap extend from the first interconnect layer into the second interconnect layer.

12. The semiconductor structure according to claim 11, wherein: The portion of the air gap extending from the first interconnect layer into the second interconnect layer occupies an area less than 40% of an area between the metal lines of the second interconnect layer.

13. The semiconductor structure according to claim 11, wherein: The portion of the air gap extending from the first interconnect layer to the second interconnect layer has a circular top surface surrounded by a dielectric material of the second interconnect layer.

14. The semiconductor structure according to claim 10, wherein: The source / drain contacts have a height between 1.0 and 2.5 times the height of the gate structure.

15. The semiconductor structure according to claim 10, wherein: An additional etch stop layer is disposed between the gate structure and the air gap.

16. The semiconductor structure according to claim 10, wherein: The liner includes one or more dielectric layers including silicon nitride, silicon carbide, or a combination thereof.

17. A method of forming a semiconductor structure, comprising: forming a transistor structure on a substrate, wherein the transistor structure includes a source / drain region and a gate structure disposed in the substrate; depositing a first dielectric layer on the substrate to embed the transistor structure; forming a source / drain contact in a first dielectric layer on the source / drain region of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer to connect to source / drain contacts; forming openings in the second dielectric layer between the metal lines to expose the first dielectric layer; etching the second dielectric layer between the metal lines and the first dielectric layer between the source / drain contacts through the opening to form an extended opening; as well as A third dielectric layer is deposited to seal the extended opening and form an air gap in the first and second dielectric layers and over the transistor structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: Forming the source / drain contacts includes forming the source / drain contacts at a height between 1.0 and 2.5 times the height of the gate structure.

19. The method of forming a semiconductor structure according to claim 17, wherein after the etching, a liner is deposited to cover an inner surface of the extended opening.

20. The method for forming a semiconductor structure according to claim 19, wherein: The top of the opening is between 25% and 30% of the distance between the metal lines.

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