Semiconductor structure and method for forming integrated circuit structure

Abstract

The present disclosure provides an embodiment of a semiconductor structure. The semiconductor structure includes: a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active area of ​​the substrate; a first source / drain component formed on the active area and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; a backside contact component inserted between the backside power rail and the first source / drain component, and electrically connecting the backside power rail to the first source / drain component. The backside contact component also includes a first silicide layer disposed on the back side of the substrate. Embodiments of the present invention also relate to a method for forming an integrated circuit structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming integrated circuit structures. Background Art

[0002] Integrated circuits have evolved into advanced technologies with smaller component sizes (e.g., 7nm, 5nm, and 3nm). In these advanced technologies, the gate pitch (spacing) continues to shrink, thus triggering a connection with the gate bridge problem. In addition, three-dimensional transistors with fin-type active regions are generally required to enhance device performance. Those three-dimensional field effect transistors (FETs) formed on fin-type active regions are also called FinFETs. FinFETs require narrow fin widths for short channel control, which results in smaller source / drain regions than planar FETs. This will reduce the alignment margin and cause problems with further reducing device pitch and increasing packaging density. As device size decreases, power lines are formed on the back side of the substrate. However, existing backside power rails still face various challenges, including wiring resistance, alignment margin, layout flexibility, and packaging density. Therefore, structures and methods for fin transistors and power rails are needed to address these problems to enhance circuit performance and reliability. Summary of the invention

[0003] According to one aspect of the present invention, there is provided a semiconductor structure, comprising: a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source / drain component formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact component inserted between the backside power rail and the first source / drain component and electrically connecting the backside power rail to the first source / drain component, wherein the backside contact component further comprises a first silicide layer disposed on the back side of the substrate.

[0004] According to another aspect of the present invention, there is provided a semiconductor structure, comprising: a substrate having a front side and a back side; a fin-shaped active region protruding from the front side of the substrate; a gate stack disposed on the fin-shaped active region; a source component and a drain component formed on the fin-shaped active region and interposed by the gate stack; a front contact component falling from the front side of the substrate onto the drain component; a back side power rail formed on the back side of the substrate; and a back side contact component interposed between the back side power rail and the source component, wherein the back side contact component electrically connects the back side power rail to the source component, wherein the back side contact component comprises a first silicide layer disposed on the back side and in direct contact with the source component, and the front contact component comprises a second silicide layer disposed on the front side and in direct contact with the drain component.

[0005] According to another aspect of the present invention, a method for forming an integrated circuit structure is provided, comprising: receiving a substrate having a front surface and a back surface; forming a shallow trench isolation feature in the front surface of the substrate to define a fin-shaped active area surrounded by the shallow trench isolation feature; forming a gate stack on the fin-shaped active area; forming a source feature and a drain feature on the fin-shaped active area, wherein the gate stack spans from the source feature to the drain feature; forming an interconnect structure located on the gate stack, the source feature, and the drain feature from the front surface, wherein the interconnect structure includes a front contact feature contacting the drain feature; thinning the substrate from the back surface so that the source feature is exposed with an exposed surface. Forming a backside contact feature that falls on the exposed surface of the source feature; and forming a backside power rail that falls on the backside contact feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a top view of a semiconductor structure constructed according to some embodiments.

[0008] Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F is a cross-sectional view of a semiconductor structure constructed according to some embodiments.

[0009] Figure 2 It is constructed according to various aspects of the present disclosure Figures 1A to 1F Flowchart of a method for fabricating a semiconductor structure.

[0010] Figure 3 , Figure 4 , Figure 5A , Fig. 6A , Figure 6C , Figure 7 , Figure 8 , Fig. 9 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 are cross-sectional views of a semiconductor structure at various stages of fabrication constructed in accordance with some embodiments.

[0011] Figure 5B and Figure 6Bis a top view of a semiconductor structure at various fabrication stages constructed in accordance with some embodiments.

[0012] Fig. 10A and Fig. 10B is a cross-sectional view of a gate stack of a semiconductor structure constructed in accordance with some embodiments. DETAILED DESCRIPTION

[0013] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0014] The present disclosure provides a semiconductor structure with a backside power line and a manufacturing method thereof. In particular, the semiconductor structure includes a backside contact component arranged on the back side of a substrate and inserted between an active area and a backside power rail. The backside contact component electrically connects the backside power rail to the active area, for example, connects the backside power rail to a source component of a transistor. The semiconductor structure also includes an interconnect structure formed on the front side of the substrate. The interconnect structure also includes a front contact component electrically connected to a field effect transistor, such as falling on a drain component of a transistor and connected to the drain component of the transistor. In the present embodiment, the front contact component and the backside contact component both include silicide to reduce contact resistance. The semiconductor structure thus formed includes a backside power rail on the back side and an interconnect structure on the front side to jointly route power lines, for example, the drain component is connected to a corresponding power line through the interconnect structure, and the source component is connected to a corresponding power line through the backside power rail.

[0015] Figure 1A is a top view of a semiconductor structure 100 constructed in accordance with some embodiments. Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F are cross-sectional views of a semiconductor structure 100 constructed according to some embodiments along dashed lines AA′, BB′, CC′, DD′, and EE′, respectively. The semiconductor structure 100 may include one or more standard cells 101, each of which has one or more field effect transistors.

[0016] The semiconductor structure 100 includes a substrate 10, an active region 106, and a shallow trench isolation (STI) component 104 that isolates the active regions from each other. In the present embodiment, the active region 106 is a fin-shaped active region extruded above the STI component 104. In some embodiments, the active region 106 may be a planar active region or an active region having a plurality of channels stacked vertically (also referred to as a full-all-around GAA structure). The semiconductor structure 100 also includes a source (or referred to as a source component) 108, a drain (or referred to as a drain component) 110, and a gate stack 112 disposed on the active region 106. The corresponding gate stack 112 is interposed between the source component 108 and the drain component 110 to form various field effect transistors (FETs). In the present embodiment, the active region 106 has an elongated shape oriented along a first direction (X direction), and the gate stack 112 has an elongated shape oriented along a second direction (Y direction) orthogonal to the first direction.

[0017] The semiconductor structure 100 also includes an interconnect structure 114 formed on the front side 102FS of the substrate 102. The interconnect structure 114 includes various contact features 116, via features, and metal lines to connect FETs and other devices to functional circuits. The interconnect structure 114 includes multiple metal layers, each metal layer having multiple metal lines and via features to vertically interconnect metal lines in adjacent metal layers to front contact features, such as metal lines 126 in the first metal layer and via features 128 connecting metal lines 126. In the present embodiment, the contact features 116 are also referred to as front contact features when formed on the front side of the substrate 102. In particular, a subset of the front contact features 116 falls on the drain feature 110.

[0018] The semiconductor structure 100 includes a backside power rail 118 and a backside contact feature 120 formed on the back side 102BS of the substrate 102. The backside contact feature 120 is interposed between the active region 106 and the backside power rail 118 and electrically connects the backside power rail 118 to the active region 106, for example, according to the present embodiment, connects the backside power line 118 to the source feature 108. Therefore, the backside power rail on the backside and the interconnect structure on the front side together facilitate the routing of the power lines, for example, connecting the drain feature to the corresponding power line through the interconnect structure and connecting the source feature to the corresponding power line through the backside power rail.

[0019] In the present embodiment, both the front contact feature 116 and the back contact feature 120 include silicide and bulk metal on the silicide to reduce contact resistance. The silicide includes titanium silicon (TiSi), nickel silicon (NiSi), tantalum silicon (TaSi), cobalt silicon (CoSi), or a combination thereof. In the present embodiment, a silicide layer 144 is formed on the drain feature 110 from the front side and is interposed between the drain feature 110 and the front contact feature 116; Figure 1BAs shown, the silicide layer 152 is formed on the source feature 108 from the back side and is interposed between the source feature 108 and the back side contact feature 120 .

[0020] The semiconductor structure 100 also includes a dielectric layer 122 composed of a first dielectric material and a backside interlayer dielectric (BILD) layer 124 of a second dielectric material formed on the back side of the substrate 102 to provide etching selectivity. For example, the first dielectric material includes silicon nitride, silicon carbonitride, SiOCN, silicon oxide, SiOC, or a combination thereof. The second dielectric material includes one of the above dielectric materials, but is selected to be different in composition from the first dielectric material to provide etching selectivity.

[0021] Figure 2 is a flow chart of a method 200 for fabricating a semiconductor structure 100 according to some embodiments. The method 200 includes various operations 202 to 232 to form Figures 1A to 1F In particular, the method 200 includes forming FETs (and other devices) and an interconnect structure 114 on the front side of a substrate 102, and forming a backside power rail 118 and a backside contact feature 120 on the back side of the substrate 102, wherein power lines are centrally routed through the backside power rail 118 on the back side of the substrate 102 and the interconnect structure 114 on the front side.

[0022] In particular, method 200 includes an operation 220 for thinning substrate 102 from the back side. Operation 220 may include a combination of grinding, chemical mechanical polishing (CMP) and etching (such as wet etching) to make the thinning process effective. In order to properly stop the thinning process, substrate 102 includes an embedded layer such as a silicon germanium layer or a doped silicon germanium layer to provide etching selectivity during the thinning process so that the thinning process of operation 220 can be properly stopped. In the present embodiment, substrate 102 is a silicon substrate. A silicon germanium layer is epitaxially grown on a silicon surface, and then a silicon layer is epitaxially grown on the doped silicon germanium surface. Silicon germanium is used as an etch stop layer during etching. In other embodiments, the etch stop layer may be other semiconductor materials different from silicon, such as a compound semiconductor material, a silicon layer doped with other elements to improve etching selectivity, or other semiconductor layers doped or undoped, such as silicon carbide.

[0023] Figures 3 to 18 3 is a top view or cross-sectional view of a semiconductor structure (or workpiece) 300 at various stages of fabrication. Semiconductor structure 300 is an example of semiconductor structure 100 or an alternative structure constructed according to some embodiments. Semiconductor structure 300 includes a field effect transistor (FET), an interconnect structure, and a backside power rail. Figures 1A to 18 The semiconductor structure 300 (also the semiconductor structure 100 ) and the method 200 for manufacturing the same are described together.

[0024] Reference Figure 2 and Figure 3 , the method 200 begins at box 202 by receiving a workpiece (or semiconductor structure) 300 having a semiconductor substrate 102. The semiconductor substrate 102 includes silicon. In some other embodiments, the substrate 102 includes germanium, silicon germanium, or other suitable semiconductor materials. The substrate 102 may alternatively be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable semiconductor compound, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. The semiconductor substrate 102 also includes various doped regions, such as n-wells and p-wells. In one embodiment, the semiconductor substrate 102 includes an epitaxial (or epi) semiconductor layer. In another embodiment, the semiconductor substrate 102 includes a buried dielectric material layer for isolation formed by a suitable technique, such as a technique known as separation by implantation of oxygen (SIMOX). In some embodiments, the substrate 102 may be a semiconductor on an insulator, such as silicon on insulator (SOI). In particular, the substrate 102 includes a semiconductor layer 102A used as an etch stop layer (ESL) for later manufacturing associated with the backside power rail. The semiconductor layer 102A is embedded in the semiconductor substrate 102, but includes a different semiconductor composition to provide etching selectivity during the backside process. For example, the semiconductor layer 102A is a silicon germanium (SixGey) layer, and the bulk substrate is a silicon substrate. The etching selectivity can be adjusted by the concentration of germanium in the silicon germanium layer 102A. The germanium concentration (atomic percentage) in the silicon germanium layer can be between 30% and 90%. The semiconductor layer 102A can be undoped or doped with appropriate dopants (such as boron, phosphorus, carbon, or a combination thereof) to further improve the etching selectivity. In one example, an etching solution of NH4OH, H2O2, and H2O can be used to selectively etch silicon germanium relative to silicon with significant etching selectivity.

[0025] The semiconductor layer 102A may be formed by epitaxial growth, for example, epitaxially growing a silicon germanium layer 102A on a silicon substrate, and then epitaxially growing a silicon layer 102B on the silicon germanium layer 102A. In some embodiments, the semiconductor layer 102A has a thickness between 10 nm and 20 nm, and the silicon layer 102B has a thickness between 70 nm and 100 nm.

[0026] Reference Figure 2 and Figure 4 The method 200 proceeds to operation 204 by forming isolation features, such as shallow trench isolation (STI) features, on the semiconductor substrate 102, thereby defining active regions 106 separated and isolated from each other by the isolation features. Figure 4In some of the following drawings, for simplicity, the embedded semiconductor layer 102A is not shown, but it should be understood that the semiconductor layer 102A exists as a part of the semiconductor substrate 102 .

[0027] In some embodiments, STI features 104 are formed by a process including etching to form trenches, filling the trenches with dielectric material, and polishing to remove excess dielectric material and planarize the top surface. One or more etching processes are performed on semiconductor substrate 102 through openings of a soft mask or a hard mask, which is formed by photolithographic patterning and etching. According to some embodiments, the formation of STI features 104 is further described below.

[0028] In this example, the hard mask is deposited on the substrate 102 and patterned by a photolithography process. The hard mask layer includes a dielectric such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride and / or a semiconductor carbide, and in an exemplary embodiment, the hard mask layer includes a silicon oxide film and a silicon nitride film. The hard mask layer can be formed by thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high density plasma CVD (HDP-CVD), other suitable deposition processes.

[0029] A photoresist layer (or resist) is formed on the hard mask layer. An exemplary resist layer includes a photosensitive material that changes the properties of the layer when exposed to light such as ultraviolet (UV) light, deep ultraviolet (DUV) light, or extreme ultraviolet (EUV) light. The property change can be used to selectively remove the exposed or unexposed portion of the resist layer in the development process. The process of forming a patterned resist layer is also referred to as a photolithography process (or photolithography patterning process). An exemplary photolithography process includes spin coating of a resist layer, soft baking of a resist layer, mask alignment, exposure, post-exposure baking, developing a resist layer, rinsing, and drying (e.g., hard baking). Alternatively, the photolithography process can be implemented, supplemented, or replaced by other methods such as maskless lithography, electron beam writing, and ion beam writing.

[0030] After the resist is patterned, an etching process is performed on the semiconductor structure 300 to open the hard mask layer, thereby transferring the pattern from the resist layer to the hard mask layer. The remaining resist layer can be removed after the hard mask layer is patterned. The etching process for patterning the hard mask layer can include wet etching, dry etching, or a combination thereof. The etching process can include multiple etching steps. For example, the silicon oxide film in the hard mask layer can be etched by a diluted hydrofluoric acid solution, and the silicon nitride film in the hard mask layer can be etched by a phosphoric acid solution.

[0031] Then, another etching process may be performed to etch portions of the substrate 102 that are not covered by the patterned hard mask layer to form trenches in the semiconductor substrate 102. The patterned hard mask layer is used as an etching mask during the etching process to pattern the substrate 102. The etching process may include any suitable etching technique, such as dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching (RIE)). In some embodiments, the etching process includes multiple etching steps with different etching chemistries, which are designed to etch the substrate to form trenches with specific trench profiles to improve device performance and pattern density. In some examples, the semiconductor material of the substrate may be etched by a dry etching process using a fluorine-based etchant. In particular, the etching process applied to the substrate is controlled so that the substrate 102 is partially etched.

[0032] One or more dielectric materials are filled in the trenches to form the STI features 104. Suitable filling dielectric materials include semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, fluorinated quartz glass (FSG), low-K dielectric materials, and / or combinations thereof. In various exemplary embodiments, the dielectric material is deposited using a HDP-CVD process, a sub-atmospheric pressure CVD (SACVD) process, a high aspect ratio process (HARP), a flowable CVD (FCVD), and / or a spin deposition process.

[0033] The deposition of the dielectric material may be followed by a chemical mechanical polishing / planarization (CMP) process to remove excess dielectric material and planarize the top surface of the semiconductor structure 300. The CMP process may use a hard mask layer as a polishing stop layer to prevent polishing of the semiconductor surface. The hard mask may be removed by a CMP process or alternatively by an etching process.

[0034] Reference Figure 5A and Figure 5B The method 200 may proceed to operation 206 by forming a fin structure having a plurality of fin-shaped active areas (or fin features) 106 . Figure 5A and Figure 5B 2 are a cross-sectional view and a top view of the semiconductor structure 300, respectively. Operation 206 includes recessing the STI component 104 so that the active area 106 protrudes from above the STI component 104, and is therefore referred to as a fin-shaped active area. The recessing process uses one or more etching steps (e.g., dry etching, wet etching, or a combination thereof) to selectively etch back the STI component 104. For example, when the STI component 104 is a silicon oxide component, hydrofluoric acid can be applied using a wet etching process to selectively etch the STI component. The exemplary fin-shaped active areas 106 are spaced apart from each other in the second direction (Y direction). The fin-shaped active area 106 has an elongated shape oriented along the first direction (X direction).

[0035] A doping process may be applied to the fin-shaped active region 106 to form various doped wells in the semiconductor substrate 102, such as an n-well and a p-well before the current stage or operation 206. The various doped wells may be formed by respective ion implantation or diffusion.

[0036] Reference Fig. 6A , Figure 6B and Figure 6C The method 200 proceeds to operation 208 by forming various gate stacks 107 on the fin-shaped active region 106 . Figure 6B It is a top view; Fig. 6A is a cross-sectional view along the dotted line AA′; Figure 6C is a cross-sectional view along the dotted line BB′ of the semiconductor structure 300. In this embodiment, Figure 6B As shown, the gate stack 107 includes exemplary gate stacks 107a, 107b, 107c and 107d. However, in subsequent manufacturing stages, the following Figures 7 to 19 It is along Figure 6B All cross-sectional views of the semiconductor structure 300 are shown along the dashed line BB′.

[0037] The gate stack 107 has an elongated shape and is oriented in the second direction (Y direction). Each gate stack 107 extends over a plurality of fin-shaped active regions 106. In particular, one gate stack 107 (such as gate stack 107a or 107d) is disposed on an end (or edge) of the fin-shaped active region 106, so that the gate stack is configured to reduce boundary effects, increase device uniformity, and improve overall device performance.

[0038] In the present embodiment, the gate stack 107 is a dummy gate stack, which will be replaced by a metal gate at a later manufacturing stage. The dummy gate stack 107 may include a gate dielectric layer and a gate electrode, respectively. The gate dielectric layer includes a dielectric material such as silicon oxide, and the gate electrode may include polysilicon. The formation of the gate stack 107 includes depositing a gate material (including polysilicon in this example); and patterning the gate material by a photolithography process and etching. A gate hard mask layer may be formed on the gate material layer and used as an etching mask during the formation of the gate stack. The gate hard mask layer may include any suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, other suitable materials and / or combinations thereof. In one embodiment, the gate hard mask includes a multilayer film, such as silicon oxide and silicon nitride. In some embodiments, the patterning process for forming the gate stack 107 includes: forming a patterned resist layer by a photolithography process; and forming a patterned resist layer by a photolithography process. The hard mask layer is etched using the patterned resist layer as an etch mask; the gate material is etched using the patterned hard mask as an etch mask to form a gate stack 107 .

[0039] One or more gate sidewall components (or gate spacers) 113 are formed on the sidewalls of the gate stack 107. The gate spacer 113 can be used to compensate for the subsequently formed source / drain components to design or modify the source / drain structure profile, and / or provide isolation between the gate electrode and the source / drain components. The gate spacer 113 may include any suitable dielectric material, such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, other suitable dielectric materials, and / or combinations thereof. The gate spacer 113 may have a multilayer film, such as a double-layer film (e.g., a silicon oxide film and a silicon nitride film) or a triple-layer film ((silicon oxide film; silicon nitride film; and silicon oxide film)). The formation of the gate spacer 113 includes deposition and anisotropic etching, such as dry etching.

[0040] Refer to the cross-sectional view Figure 7 , the method 200 proceeds to operation 210 by forming respective source features 108 and drain features 110 to respective fin FETs (FinFETs). The source features 108 and drain features 110 may include lightly doped drain (LDD) features and heavily doped source and drain (S / D). For example, each field effect transistor includes a source feature 108 and a drain feature 110 formed on a respective fin feature 106 and interposed by a gate stack. A channel is formed in the fin structure 106 in a portion below the gate stack and in a portion spanning between the source structure 108 and the drain structure 110.

[0041] The source / drain components 108 and 110 may have an elevated source / drain structure and may be formed by selective epitaxial growth to produce a strain effect with enhanced carrier mobility and device performance. The gate stack 107 and the gate spacer 113 constrain the source / drain components 108 and 110 to the source / drain region. In some embodiments, the source / drain components 108 and 110 are formed by one or more epitaxial growth or epitaxial processes, thereby growing Si components, SiGe components, SiC components and / or other suitable semiconductor components in a crystalline state on the fin component 106. Alternatively, before epitaxial growth, an etching process is used to recess the source / drain region. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy and / or other suitable processes. The epitaxial process may use a gas and / or liquid precursor that interacts with the composition of the fin component 106.

[0042] The source / drain features 108 and 110 may be in-situ doped by introducing doping substances during the epitaxial process, the doping substances including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. If the source / drain features are not doped in-situ, an implantation process is performed to introduce corresponding dopants into the source / drain features 108 and 110. In an exemplary embodiment, the source / drain features 108 and 110 in the nFET include: Si or SiC doped with phosphorus, and the source / drain features 108 and 110 in the pFET include SiGe or Ge doped with boron. In some other embodiments, the source / drain features 108 and 110 include more than one semiconductor material layer. For example, a silicon germanium layer is epitaxially grown on the substrate in the source / drain region, and a silicon layer is epitaxially grown on the silicon germanium layer. In another example, a plurality of thin film semiconductor (silicon germanium or silicon) layers with different dopant concentrations are epitaxially grown on the substrate in the source / drain region. One or more annealing processes may be performed thereafter to activate the source / drain features. Suitable annealing processes include rapid thermal annealing (RTA), laser annealing processes, other suitable annealing techniques, or combinations thereof.

[0043] Reference Figure 8 , the method 200 proceeds to operation 212, where an interlayer dielectric material (ILD) layer 130 (also referred to as a front ILD layer or FILD layer to distinguish from the BILD 124) is formed on the substrate 102 to cover the source / drain features 108 and 110 from the front side. The ILD 130 surrounds the gate stack 107 and the gate spacer 113, thereby allowing the gate stack 107 to be removed and a replacement gate to be formed in the formed cavity (also referred to as a gate trench). Therefore, in such an embodiment, the gate stack 107 is removed after the ILD layer 130 is formed. The ILD layer 130 may also be part of an interconnect structure 114 that electrically interconnects various devices of the semiconductor structure 300. In such an embodiment, the ILD layer 130 serves as an insulator to support and isolate the conductive traces. The ILD layer 130 may include any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other suitable dielectric materials, or combinations thereof. In some embodiments, the formation of the ILD layer 130 includes deposition and CMP to provide a planarized top surface.

[0044] Reference Fig. 9 , the method 200 proceeds to gate replacement operation 214. The dummy gate stack 107 is replaced by a gate stack 112 having a high-k dielectric material and a metal, and is therefore also referred to as a high-k metal gate.

[0045] The gate stack 112 is configured in the fin-shaped active area 106 to form various field effect transistors (FETs), and is therefore also referred to as FinFETs. In some examples, the field effect transistors include n-type transistors and p-type transistors. In other examples, those field effect transistors are configured to form one or more static random access memory (SRAM) cells, logic gate cells, or structures having both. Each SRAM cell includes two cross-coupled inverters configured for data storage. In addition, the gate stack 112 is configured to increase pattern uniformity and improve manufacturing quality. For example, as described above, the gate stack 112 includes edge gate stacks 112a and 112d, each of which extends from the fin structure 106 to the STI structure 104 along the Y direction and lands on the STI structure 104 and the fin structure 106.

[0046] like Fig. 9 As shown, the fin-shaped active area 106 extends from one end 138A to the other end 138B along the Y direction. The gate replacement process may include etching, deposition, and polishing. In the present example used for illustration, the exemplary dummy gate stacks 107a, 107b, 107c, and 107d are removed to form gate trenches. In some embodiments, the dummy gate stack 107 is removed by an etching process such as wet etching to selectively remove the gate stack 107. If more material is present, the etching process may include multiple etching steps to remove the dummy gate. Then, gate materials such as high-k dielectric materials and metals are deposited in the gate trenches to form a gate stack 112 such as exemplary gate stacks 112a, 112b, 112c, and 112d. A CMP process is further performed to polish and remove excess gate material from the semiconductor structure 300. Refer to the following Fig. 10A and Fig. 10B The structure and formation of the gate stack 112 is further described. Fig. 10A and Fig. 10B A cross-sectional view of an exemplary gate stack 112 is shown according to various embodiments.

[0047] The gate stack 112 (e.g., 112b) is formed on the substrate 102 and covers the channel region of the fin-shaped active region 106. The gate stack 112 is formed in the gate trench by a suitable process (e.g., a process including deposition and CMP). However, it is understood that the gate stack 112 may have other suitable gate structures and may be formed by other suitable processes.

[0048] The gate stack 112 includes a gate dielectric layer (or gate dielectric component) 132 and a gate electrode 134 disposed on the gate dielectric layer 132. In the present embodiment, the gate dielectric layer 132 includes a high-k dielectric material, and the gate electrode 134 includes a metal or a metal alloy. In some examples, the gate dielectric layer 132 and the gate electrode 134 may each include a plurality of sub-layers.

[0049] The high-k dielectric material may include a metal oxide, a metal nitride (e.g., LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON)), or other suitable dielectric materials. The gate electrode 134 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, or any suitable material. In some embodiments, different metal materials are used for nFET and pFET devices with respective work functions.

[0050] The gate dielectric layer 132 may further include an interface layer sandwiched between the high-k dielectric material layer and the fin-shaped active area. The interface layer may include silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials. The interface layer is deposited by a suitable method, such as ALD, CVD, ozone oxidation, etc. The high-k dielectric layer is deposited on the interface layer (if an interface layer exists) by a suitable technique, such as ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, and / or other suitable techniques. In some embodiments, in operation 208 of forming the gate stack 107, the gate dielectric layer 132 is formed on the fin-shaped active area 106. In this case, the shape of the gate dielectric layer 132 is as shown in FIG. Fig. 10A In some other embodiments, the gate dielectric layer 132 is formed in a last high-k process, where the gate dielectric layer 132 is deposited in the gate trench at operation 214. In this case, the gate dielectric layer 132 is U-shaped, such as Fig. 10B shown.

[0051] The gate electrode 134 may include a variety of conductive materials. In some embodiments, the gate electrode 134 includes a capping layer 134-1, a barrier layer 134-2, a work function metal layer 134-3, another barrier layer 134-4, and a fill metal layer 134-5. In a further embodiment, the capping layer 134-1 is formed by a suitable deposition technique such as ALD, and the capping layer 134-1 includes titanium nitride, tantalum nitride, or other suitable materials. The barrier layer 134-2 is formed by a suitable deposition technique such as ALD, and the barrier layer 134-2 includes titanium nitride, tantalum nitride, or other suitable materials. In some examples, there may be no barrier layer or only one of the barrier layers in the gate electrode.

[0052] The work function metal layer 134-3 includes a conductive layer of a metal or metal alloy having an appropriate work function, thereby enhancing the device performance of the corresponding FET. For pFET and nFET, the work function (WF) metal layer 134-3 is different, respectively referred to as n-type WF metal and p-type WF metal. The selection of WF metal depends on the FET to be formed on the active area. For example, the semiconductor structure 300 includes a first active area for nFET and another active area for pFET, and therefore, n-type WF metal and p-type WF metal are formed in corresponding gate stacks, respectively. In particular, the n-type WF metal is a metal having a first work function, so that the threshold voltage of the associated nFET is reduced. The n-type WF metal is close to the silicon conduction band energy (Ec) or a lower work function, making it easier for electrons to escape. For example, the n-type WF metal has a work function of about 4.2eV or less. The p-type WF metal is a metal having a second work function, so that the threshold voltage of the associated pFET is reduced. The p-type WF metal is close to the work function of the valence band energy (Ev) of the silicon atom or higher, and has a strong electron bonding energy to the nucleus. For example, the WF of the p-type work function metal is about 5.2eV or higher. In some embodiments, the n-type WF metal includes tantalum (Ta). In other embodiments, the n-type WF metal includes titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or a combination thereof. In other embodiments, the n-metal includes Ta, TiAl, TiAlN, tungsten nitride (WN), or a combination thereof. The n-type WF metal may include various metal-based films as stacks to optimize device performance and process compatibility. In some embodiments, the p-type WF metal includes titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-metal includes TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or a combination thereof. The p-type WF metal may include various metal-based films as stacks to optimize device performance and process compatibility. The work function metal is deposited by a suitable technique, such as PVD or ALD.

[0053] The barrier layer 134-4 is formed by a suitable deposition technique such as ALD and includes titanium nitride, tantalum nitride or other suitable materials. In various embodiments, the fill metal layer 134-5 is deposited by a suitable technique such as PVD or electroplating and includes aluminum, tungsten or other suitable metals.

[0054] Reference again Fig. 9 , the method 200 may also include an operation of forming a hard mask 136 on top of the gate stack 112 to protect the gate stack 112 from being lost during subsequent processes. The formation of the hard mask 136 includes: recessing the gate stack 112 by selective etching; depositing (such as CVD) a hard mask; and CMP according to this example. The hard mask 136 may include a suitable material different from the dielectric material of the ILD layer to form an etching selectivity during the etching process to form a contact opening. In some embodiments, the hard mask 136 includes silicon nitride. For example, the hard mask 136 of silicon nitride (SiN) is formed by using CVD including hexachlorodisilane (HCD or Si2Cl6), dichlorosilane (DCS or SiH2Cl2), bis (tert-butylamino) silane (BTBAS or C8H22N2Si) and disilane (DS or Si2H6).

[0055] Figures 11 to 13 is a cross-sectional view of a semiconductor structure 300 at various stages of fabrication constructed in accordance with some embodiments. The method 200 proceeds to operation 216 by forming an interconnect structure 114 to connect FETs and various other devices to form an integrated circuit, such as Figures 11 to 13 and Figures 1A to 1F As further shown, interconnect structure 114 is formed on the front side of the workpiece. Semiconductor structure 300 also includes power rails and other conductive features formed on the back side of the workpiece and functioning in conjunction with interconnect structure 114 to connect various devices into a functional integrated circuit.

[0056] The interconnect structure 114 includes metal lines in multiple metal layers to provide horizontal electrical wiring and contact / via features to provide vertical wiring. The various metal lines, contact features, and via features in the interconnect structure 114 are formed by appropriate techniques such as damascene processes. In particular, the interconnect structure 114 includes one or more contact features 116 that fall on transistors and / or other devices, such as drain features 110 of FETs. Operation 216 may include multiple steps to form the one or more contact features 116, as described in detail below.

[0057] like Fig.11As shown, another ILD layer 140 similar to the ILD layer 130 in composition and formation is formed on the workpiece. In some embodiments, the formation of the ILD layer 140 may include deposition and CMP. The ILD layer 140 is further patterned by photolithography and etching to form one or more contact holes (or openings) 142. A hard mask may be used to pattern the ILD layer 140. Fig.12 As shown, the etching process etches through the ILD layers 140 and 130 until one or more drain features 110 are exposed. In the various patterning processes described above in method 200, each patterning process can be implemented by double patterning or multiple patterning. In some embodiments, as Fig.12 As shown, a silicide layer 144 is formed on the drain feature 110 to reduce contact resistance. The silicide layer 144 includes silicon and a metal, such as titanium silicide, tantalum silicide, nickel silicide, or cobalt silicide. The silicide layer 144 can be formed by a process called a self-aligned silicide (or self-aligned silicide) process (including metal deposition), annealing to react the metal with the silicon, and etching to remove the unreacted metal.

[0058] like Fig.13 As shown, one or more contact features 116 are formed in one or more contact holes 142. The contact holes 142 are filled with one or more conductive materials, such as Ti, TiN, TaN, Co, W, Al, Cu, or a combination thereof. According to some examples, the formation of the contact features 116 includes deposition and CMP of one or more conductive materials. The deposition can be performed by a suitable deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), plating, CVD, or other suitable methods.

[0059] As described above, operation 216 also includes forming other conductive features of the interconnect structure 114, such as via features 128 that land on the contact features 116, via features 146 that land on the gate electrode 134, and metal lines 126 in the first metal layer, such as Fig.13 or Figure 1C In addition, Fig.13 Other detailed structures such as semiconductor layers 102A and 102B are shown.

[0060] The method 200 also includes other operations, such as operation 218 of performing various processes in the back end process, including: forming a passivation layer, forming a redistribution layer (RDL), forming a capacitor in the passivation layer, and forming a bonding pad ( Fig.13 Then, if Figures 14 to 19 As shown, the workpiece 300 is subjected to subsequent operations on the back side of the workpiece. Figures 14 to 19 is along the fin-shaped active region 106 (such as along Figure 6BBB′) but is a cross-sectional view of the semiconductor structure 300 at various different fabrication stages.

[0061] Reference Fig.14 , the method 200 proceeds to operation 220 to thin the semiconductor substrate of the workpiece 300 from the back side using an appropriate method (such as by polishing, etching, or a combination thereof) to expose the active area. In some embodiments, the polishing process may include a CMP process. In some embodiments, in order to improve the yield, the polishing process includes a grinding process with a higher polishing rate followed by a CMP process with a higher polishing quality. In the present embodiment, the semiconductor substrate 102 includes an embedded semiconductor layer 102A used as a stop layer (such as a polishing stop layer or an etching stop layer). When the embedded semiconductor layer 102A is used as a polishing stop layer, the CMP process will stop on the embedded semiconductor layer 102A. When the embedded semiconductor layer 102A is used as an etching stop layer, after the CMP process, an etching process will be further applied to recess the semiconductor substrate 102 until it stops on the embedded semiconductor layer 102A. In the present embodiment where the semiconductor substrate 102 is a silicon substrate and the embedded semiconductor layer 102A is a silicon germanium layer, the etching process includes applying an etchant to selectively remove silicon relative to silicon germanium. In a further embodiment, the etching process includes low temperature deep reactive ion etching (DRIE) with SF6 and O2 to selectively etch silicon relative to silicon germanium. Thereafter, another etching process is applied to remove the embedded semiconductor layer 102A. For example, a dry etching process can be used to selectively remove the embedded semiconductor layer 102A of SiGe using an etchant including HBr, O2, and N2. In another example, a wet etching process is performed using a solution of NH4OH, H2O2, and H2O to selectively remove the embedded semiconductor layer 102A of SiGe.

[0062] Reference Fig.15 , the method 200 proceeds to operation 222 by forming an isolation layer 122 on the back side of the workpiece 300. The isolation layer 122 is a dielectric material layer and may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, other suitable dielectric materials, or combinations thereof. The isolation layer 122 may be formed by a suitable deposition technique, such as CVD, ALD, flowable CVD (FCVD), and may be followed by a CMP process. In some embodiments, the isolation layer 122 includes a thickness between 10 nm and 30 nm.

[0063] refer to Fig.16, the method 200 proceeds to operation 224 to form one or more contact holes (or backside contact holes) 150 in the isolation layer 122 by a process including a photolithography process and etching. The method of forming the backside contact holes 150 is similar to the method of forming the frontside contact holes 142. In the present embodiment, the backside contact holes 150 are aligned with the source components 108, wherein the source components 108 are exposed within the corresponding backside contact holes 150. In particular, the photolithography process forms a patterned resist having an opening aligned with the source components 108. The etching process transfers the opening to the isolation layer 122 to expose the source components. In some embodiments, the etching process includes further etching of the semiconductor substrate 102, such as etching the bottom of the fin-shaped active area to expose the source component 108.

[0064] refer to Fig.17 , the method 200 proceeds to operation 226 to form one or more contact features (also referred to as backside contact features) 120 in the contact hole 150. In the present embodiment, a silicide layer 152 is formed on the source feature 108 to reduce the contact resistance. The silicide layer 152 includes silicon and a metal, such as titanium silicide, tantalum silicide, nickel silicide, or cobalt silicide. The silicide layer 152 is similar to the silicide layer 144 in terms of composition and formation. However, the silicide layer 152 is formed on the back side of the workpiece. In particular, the silicide layer 152 is formed on the bottom surface of the source feature 108, while the silicide layer 144 is formed on the top surface of the drain feature 110.

[0065] The contact hole 150 is filled with one or more conductive materials, such as Ti, TiN, TaN, Co, W, Al, Cu or a combination thereof. According to some examples, the formation of the backside contact component 120 includes deposition and CMP of one or more conductive materials. The deposition can be performed by a suitable deposition technique such as CVD, ALD, plating, CVD or other suitable methods. The formed backside contact component 120 has a thickness similar to that of the isolation layer 122, such as in the range of 10nm to 30nm.

[0066] refer to Fig.18 , the method 200 proceeds to operation 228 to form another dielectric layer or backside ILD (BILD) layer 124 that is similar in composition and formation to the ILD layer 130. In some embodiments, the formation of the BILD layer 124 may include deposition and CMP.

[0067] Still reference Fig.18 The method 200 proceeds to operation 230 to pattern the BILD layer 124 by photolithography and etching to form one or more trenches 154. A hard mask may be used to pattern the BILD layer 124. An etching process is applied to etch through the BILD layer 124 until the backside contact features 120 are exposed.

[0068] Reference Fig.19 , the method 200 proceeds to operation 232 to form one or more backside power rails (BPRs) 118 in the trenches 154 of the BILD layer 124. The BPRs 118 include one or more conductive materials, such as Ti, TiN, TaN, Co, W, Al, Cu, or a combination thereof. According to some embodiments, the formation of the BPRs 118 includes deposition and CMP of one or more conductive materials. The deposition may be performed by a suitable deposition technique, such as PVD, ALD, plating, CVD, other suitable methods, or a combination thereof. In particular, the BPRs 118 are designed and configured to be electrically connected to the FET, such as the source feature 108 of the FET in this embodiment, via the backside contact feature 120. Other manufacturing steps may be performed before, during, and after the operation of the method.

[0069] According to various embodiments, the present disclosure provides a semiconductor structure having a backside power line formed on the backside of a substrate and a method for manufacturing the same. The semiconductor structure thus formed includes a backside power rail on the backside and an interconnection structure on the front side to route the power line together, for example, a drain component is connected to a corresponding power line through the interconnection structure, and a source component is connected to a corresponding power line through the backside power rail. In particular, the semiconductor structure includes a backside contact component, which falls on the source component from the backside and electrically connects the backside power line to the source component; a front contact component falls on the drain component and is electrically connected to an upper conductive component (e.g., a metal line) of the interconnection structure. In addition, the front contact component and the backside contact component each include respective silicide layers to further reduce contact resistance. The disclosed structure reduces wiring resistance, increases alignment margin, increases layout flexibility, and improves packaging density. The disclosed structure provides greater flexibility for circuit design layout and provides a larger process window for IC manufacturing, thereby making the disclosed structure suitable for advanced technology nodes.

[0070] The disclosed structures can be used in various applications that incorporate FinFETs to enhance performance. For example, FinFETs with multi-fin devices can be used to form static random access memory (SRAM) cells. In other examples, the disclosed structures can be incorporated into various integrated circuits, such as logic circuits, dynamic random access memory (DRAM), flash memory, or imaging sensors.

[0071] In one example aspect, the present disclosure provides a semiconductor structure according to some embodiments. The semiconductor structure includes: a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source / drain component formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact component interposed between the backside power rail and the first source / drain component and electrically connecting the backside power rail to the first source / drain component.

[0072] In the above semiconductor structure, the backside contact feature further includes a first silicide layer disposed on the back side of the substrate.

[0073] In the above semiconductor structure, the first silicide layer of the backside contact feature directly contacts the bottom surface of the first source / drain feature.

[0074] In the above semiconductor structure, the backside contact feature further extends into the first source / drain feature with an increased contact area.

[0075] In the above-mentioned semiconductor structure, it also includes: a second source / drain component formed on the active area; and an interconnect structure formed on the gate stack and having a first source / drain component and a second source / drain component, wherein the interconnect structure also includes a front contact component directly contacting the second source / drain component.

[0076] In the above semiconductor structure, the front contact feature includes a second silicide layer directly contacting a top surface of the second source / drain feature.

[0077] In the above semiconductor structure, the second silicide layer of the front contact feature is disposed on the front side of the substrate and directly contacts the top surface of the second source / drain feature.

[0078] In the above semiconductor structure, a shallow trench isolation component adjacent to the active region is further included, wherein the active region is a fin-shaped active region extruded above the top surface of the shallow trench isolation component.

[0079] In the above semiconductor structure, it also includes: a first dielectric material layer, which is arranged on the fin-shaped active area from the back side; and a second dielectric material layer, which is arranged on the first dielectric material layer, wherein the back side contact component is embedded in the first dielectric material layer, and the back side power rail is embedded in the second dielectric material layer.

[0080] In the above semiconductor structure, the first dielectric material layer and the second dielectric material layer have different compositions.

[0081] In the above semiconductor structure, the first dielectric material layer directly contacts the shallow trench isolation feature.

[0082] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate having a front side and a back side; a fin-shaped active region protruding from the front side of the substrate; a gate stack disposed on the fin-shaped active region; a source component and a drain component formed on the fin-shaped active region and inserted by the gate stack; a front contact component falling from the front side of the substrate onto the drain component; a back side power rail formed on the back side of the substrate; and a back side contact component inserted between the back side power rail and the source component, wherein the back side contact component electrically connects the back side power rail to the source component.

[0083] In the above semiconductor structure, the backside contact feature includes a first silicide layer disposed on the backside and in direct contact with the source feature, and the front contact feature includes a second silicide layer disposed on the frontside and in direct contact with the drain feature.

[0084] In the above semiconductor structure, the first silicide layer directly contacts a bottom surface of the source feature; and the second silicide layer directly contacts a top surface of the drain feature.

[0085] In the above semiconductor structure, the backside contact feature further extends into the source feature; and the front contact feature further extends into the source feature.

[0086] In the above semiconductor structure, it also includes: a first dielectric material layer, which is arranged on the fin-shaped active area from the back side of the substrate; and a second dielectric material layer, which is arranged on the first dielectric material layer, wherein the back side contact component is embedded in the first dielectric material layer, the back side power rail is embedded in the second dielectric material layer, and the first dielectric material layer and the second dielectric material layer have different compositions.

[0087] In the above semiconductor structure, a shallow trench isolation component is further included adjacent to the fin-shaped active region, wherein the fin-shaped active region extrude above a top surface of the shallow trench isolation component.

[0088] Another aspect of the present disclosure relates to a method for forming an integrated circuit structure. The method includes: receiving a substrate having a front surface and a back surface; forming a shallow trench isolation feature in the front surface of the substrate to define a fin-shaped active area surrounded by the shallow trench isolation feature; forming a gate stack on the fin-shaped active area; forming a source feature and a drain feature on the fin-shaped active area, wherein the gate stack spans from the source feature to the drain feature; forming an interconnect structure located on the gate stack, the source feature, and the drain feature from the front surface, wherein the interconnect structure includes a front contact feature contacting the drain feature; thinning the substrate from the back surface so that the source feature is exposed with an exposed surface. Forming a backside contact feature that falls on the exposed surface of the source feature; and forming a backside power rail that falls on the backside contact feature.

[0089] In the above method, forming the backside contact feature includes forming a first silicide layer in direct contact with the source feature; and forming the interconnect structure includes forming a second silicide layer in direct contact with the drain feature.

[0090] In the above method, forming the backside contact component includes: depositing a dielectric layer of a first dielectric material on a substrate, including depositing on an exposed surface of a source component; patterning the dielectric layer to form a contact opening; forming a first silicide layer on the source component exposed in the contact opening; and filling a first conductive material in the contact opening to form a backside contact component.

[0091] In the above method, forming the backside contact component includes: depositing a backside interlayer dielectric layer of a second dielectric material on the dielectric layer, wherein the second dielectric material has a different composition from the first dielectric material; patterning the backside interlayer dielectric layer to form a groove to expose the backside contact component; and depositing a second conductive material in the groove to form a backside power rail.

[0092] In the above method, receiving the substrate includes forming a silicon germanium layer on a semiconductor surface; and epitaxially growing a silicon layer on the silicon germanium; and thinning the substrate includes: polishing the silicon layer; selectively etching the silicon layer; and selectively etching the silicon germanium layer.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; A shallow trench isolation component surrounding the active area; a first source / drain feature formed on the active region and disposed at an edge of the gate stack; a first dielectric material layer disposed on the active area from the back side and contacting the shallow trench isolation feature; a backside power rail formed on the backside of the substrate; as well as A backside contact feature is inserted between the backside power rail and the first source / drain feature and embedded in the first dielectric material layer, and electrically connects the backside power rail to the first source / drain feature, wherein the backside contact feature further includes a first silicide layer disposed on the back side of the substrate.

2. The semiconductor structure according to claim 1, wherein: The first silicide layer of the backside contact feature directly contacts a bottom surface of the first source / drain feature.

3. The semiconductor structure according to claim 1, wherein: The backside contact feature further extends into the first source / drain feature with an increased contact area.

4. The semiconductor structure according to claim 1, further comprising: a second source / drain feature formed on the active region; as well as An interconnect structure is formed on the gate stack and has the first source / drain feature and the second source / drain feature, wherein the interconnect structure further includes a front contact feature directly contacting the second source / drain feature.

5. The semiconductor structure according to claim 4, wherein: The front contact feature includes a second silicide layer in direct contact with a top surface of the second source / drain feature.

6. The semiconductor structure according to claim 5, wherein: The second silicide layer of the front contact feature is disposed on the front side of the substrate and directly contacts the top surface of the second source / drain feature.

7. The semiconductor structure according to claim 1, further comprising: A via feature is disposed on the front side of the substrate and is located on the gate stack.

8. The semiconductor structure according to claim 1, further comprising: A second dielectric material layer is disposed on the first dielectric material layer, wherein The backside power rail is embedded in the second dielectric material layer.

9. The semiconductor structure according to claim 8, wherein: The first dielectric material layer and the second dielectric material layer have different compositions.

10. The semiconductor structure according to claim 1, wherein: The first silicide layer includes silicon and metal.

11. A semiconductor structure comprising: a substrate having a front side and a back side; a fin-shaped active region protruding from the front side of the substrate; A shallow trench isolation component surrounding the fin-shaped active area; A gate stack is disposed on the fin-shaped active area; a source feature and a drain feature formed on the fin-shaped active region and interposed by the gate stack; a front contact feature dropped onto the drain feature from the front side of the substrate; A first dielectric material layer is disposed on the fin-shaped active area from the back side of the substrate and contacts the shallow trench isolation feature; a backside power rail formed on the backside of the substrate; as well as a backside contact feature interposed between the backside power rail and the source feature and embedded in the first dielectric material layer, wherein the backside contact feature electrically connects the backside power rail to the source feature, wherein The backside contact feature includes a first silicide layer disposed on the backside and in direct contact with the source feature, and The front contact feature includes a second silicide layer disposed on the front side and in direct contact with the drain feature.

12. The semiconductor structure according to claim 11, wherein The first silicide layer directly contacts a bottom surface of the source feature; and The second silicide layer directly contacts a top surface of the drain feature.

13. The semiconductor structure of claim 12, wherein The backside contact feature further extends into the source feature; and The front contact feature further extends into the drain feature.

14. The semiconductor structure according to claim 12, further comprising A second dielectric material layer is disposed on the first dielectric material layer, wherein The backside power rail is embedded in the second dielectric material layer, and The first dielectric material layer and the second dielectric material layer have different compositions.

15. The semiconductor structure of claim 11, further comprising: A via feature is disposed on the front side of the substrate and is located on the gate stack.

16. A method of forming an integrated circuit structure, comprising: receiving a substrate having a front surface and a back surface; forming a shallow trench isolation feature in the front surface of the substrate, thereby defining a fin-shaped active area surrounded by the shallow trench isolation feature; forming a gate stack on the fin-shaped active area; forming a source feature and a drain feature on the fin-shaped active region, wherein the gate stack spans from the source feature to the drain feature; forming an interconnect structure over the gate stack, the source feature, and the drain feature from the front surface, wherein the interconnect structure includes a front contact feature contacting the drain feature; thinning the substrate from the back surface so that the fin-shaped active area is exposed with an exposed surface; forming an isolation layer on the exposed surface; selectively etching through the isolation layer and the fin active region to expose a surface of the source feature; forming a backside contact feature on the exposed surface of the source feature; and A back side power rail is formed that lands on the back side contact feature.

17. The method according to claim 16, wherein: forming the backside contact feature includes forming a first silicide layer in direct contact with the source feature; and Forming the interconnect structure includes forming a second silicide layer in direct contact with the drain feature.

18. The method according to claim 16, wherein: Forming the backside contact component includes: forming a first silicide layer on the exposed surface of the source feature from the back surface; and The backside contact feature is formed on the first silicide layer.

19. The method according to claim 18, wherein: Forming the backside contact component includes: Depositing a backside interlayer dielectric layer on the isolation layer, wherein the backside interlayer dielectric layer and the isolation layer have different compositions; patterning the backside interlayer dielectric layer to form trenches to expose the backside contact features; and A second conductive material is deposited in the trench to form the backside power rail.

20. The method according to claim 16, wherein: The receiving the substrate includes forming a silicon germanium layer on a semiconductor surface; and epitaxially growing a silicon layer on the silicon germanium; as well as The thinning of the substrate includes: polishing the silicon layer; selectively etching the silicon layer; and selectively etching the silicon germanium layer.

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