Semiconductor structure and method for forming the same

Abstract

Embodiments of the present invention relate to semiconductor structures and methods for forming the same. In one embodiment, a semiconductor structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack located above the fin; an epitaxial source / drain region located in the fin adjacent to the gate stack; and a gate spacer disposed between the epitaxial source / drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbon nitride layers, each of the plurality of silicon oxycarbon nitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one aspect of the present invention, a semiconductor structure is provided, comprising: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack located above the fin; an epitaxial source / drain region located in the fin adjacent to the gate stack; and a gate spacer disposed between the epitaxial source / drain region and the gate stack, the gate spacer comprising a plurality of silicon oxycarbon nitride layers, each of the plurality of silicon oxycarbon nitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

[0005] According to another aspect of the present invention, another semiconductor structure is provided, comprising a semiconductor substrate, comprising a channel region; a gate stack, located above the channel region; an epitaxial source / drain region, adjacent to the channel region; and a gate spacer, disposed between the epitaxial source / drain region and the gate stack, the gate spacer comprising: a first protective layer, located above the semiconductor substrate; a first main layer, disposed above the first protective layer; a second main layer, disposed above the first main layer; and a second protective layer, disposed above the second main layer, wherein the second main layer has a smaller relative permittivity than each of the first protective layer, the first main layer, and the second protective layer, and wherein, for an etching process, the first protective layer has a smaller etching rate than each of the first main layer, the second main layer, and the second protective layer.

[0006] According to another aspect of the present invention, a method for forming a semiconductor structure is provided, comprising: forming a first gate stack located on a fin; distributing a first precursor to deposit a first oxycarbon nitride silicon layer and a second oxycarbon nitride silicon layer, the first oxycarbon nitride silicon layer being located on the sidewalls and top surfaces of the first gate stack and the fin, the second oxycarbon nitride silicon layer being located on the first oxycarbon nitride silicon layer, when depositing the first oxycarbon nitride silicon layer, distributing the first precursor at a first flow rate set, when depositing the second oxycarbon nitride silicon layer, distributing the first precursor at a second flow rate set, the first flow rate set being different from the second flow rate set; and distributing a second precursor to deposit a third oxycarbon nitride silicon layer and a fourth oxycarbon nitride silicon layer, the third oxycarbon nitride silicon layer being located on the second oxycarbon nitride silicon layer, the fourth oxycarbon nitride silicon layer being located on the third oxycarbon nitride silicon layer, when depositing the third oxycarbon nitride silicon layer, distributing the second precursor at a third flow rate set, when depositing the fourth oxycarbon nitride silicon layer, distributing the second precursor at a fourth flow rate set, the third flow rate set being different from the fourth flow rate set. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 shows an example of a FinFET in a three-dimensional view according to some embodiments;

[0009] Figure 2 and Figure 3 is a three-dimensional view of an intermediate stage in the fabrication of a FinFET according to some embodiments;

[0010] FIG. 4A to FIG. 15B is a cross-sectional view of another intermediate stage in the fabrication of a FinFET according to some embodiments;

[0011] Fig.16 Scatter plots of test data for n-type FinFET (NFET) devices and p-type FinFET (PFET) devices are shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] According to some embodiments, a transistor having a multilayer gate spacer is formed. The gate spacer layers each include a different composition of silicon oxycarbon nitride. Some gate spacer layers are formed by a composition of silicon oxycarbon nitride, which allows the gate spacer layer to have a high etch selectivity for a subsequent etching process used to form the transistor. Therefore, the loss of the gate spacer layer can be reduced, thereby reducing the relative permittivity of the gate spacer. Therefore, the parasitic capacitance of the resulting FinFET can be reduced.

[0015] Figure 1 An example of a simplified fin field effect transistor (FinFET) in a three-dimensional view according to some embodiments is shown. For clarity of illustration, some other features of the FinFET (as discussed below) are omitted. The FinFET shown can be electrically connected or connected in a manner to operate, for example, as one transistor or multiple transistors (such as two transistors).

[0016] The FinFET includes a fin 52 extending from a substrate 50. A shallow trench isolation (STI) region 56 is disposed above the substrate 50, and the fin 52 protrudes above and from adjacent STI regions 56. Although the STI regions 56 are described / illustrated as being separated from the substrate 50, the term "substrate" as used herein may be used to refer to only a semiconductor substrate, or to a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 52 refers to the portion extending between adjacent STI regions 56.

[0017] The gate dielectric 104 is along the sidewalls of the fin 52 and is located above the top surface of the fin 52, and the gate electrode 106 is located above the gate dielectric 104. The source / drain region 90 is disposed on the opposite side of the fin 52 relative to the gate dielectric 104 and the gate electrode 106. The gate spacer 78 separates the source / drain region 90 from the gate dielectric 104 and the gate electrode 106. An interlayer dielectric (ILD) layer 96 is disposed above the source / drain region 90 and the STI region 56. In embodiments where multiple transistors are formed, the source / drain region 90 can be shared between the respective transistors. In embodiments where one transistor is formed by multiple fins 52, adjacent source / drain regions 90 can be electrically connected, for example by coalescing the source / drain regions 90 using epitaxial growth, or by connecting the source / drain regions 90 to the same source / drain contact.

[0018] Figure 1 Several reference cross sections are also shown. Cross section AA is along the longitudinal axis of the fin 52 and along the direction of current flow, for example, between the source / drain regions 90 of the FinFET. Cross sections B / CB / C are perpendicular to cross section AA and extend through the source / drain regions 90 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0019] Some embodiments discussed herein are discussed in the context of forming a FinFET using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0020] Figures 2 to 15B are various views of intermediate stages in the fabrication of a FinFET according to some embodiments. Figure 2 and Figure 3 is a three-dimensional view. Figure 4A , Figure 5A Figure 6A Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , and 15A are along Figure 1 Reference section AA shows a cross-sectional view except for multiple fins / FinFETs. Figure 4B , Figure 5B , Figure 6B , Figure 6C , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , and 15B are along Figure 1 Reference cross sections B / CB / C in FIG. 1 show a cross-sectional view except for multiple fins / FinFETs.

[0021] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. For example, when forming a p-type device, the substrate 50 may be a strained material, such as silicon germanium (SiGe) having a germanium concentration in the range of about 0% to about 40%. x Ge 1-x , where x can be in the range of 0 to 1), thereby forming a FinFET with a p-type fully strained channel (PFSC) region.

[0022] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type FinFET. The region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type FinFET. The region 50N can be physically separated from the region 50P, and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can be set between the region 50N and the region 50P.

[0023] The fin 52 is formed to extend from the substrate 50. The fin 52 is a semiconductor strip. In some embodiments, the fin 52 can be formed in the substrate 50 by etching a groove in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. After formation, the fin 52 has a width W1, and the fins 52 in the same area 50N / 50P are spaced apart at a pitch P1. The width W1 can be in the range of about 3nm to about 30nm. The pitch P1 can be in the range of about 20nm to about 100nm.

[0024] The fins may be patterned by any suitable method. For example, the patterned fins may use one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns with smaller pitches than can be obtained using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0025] STI regions 56 are formed over substrate 50 and between adjacent fins 52. As an example of forming STI regions 56, an insulating material is formed over the intermediate structure. The insulating material may be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., deposition of a material based on chemical vapor deposition (CVD) in a remote plasma system, and post-curing to convert it into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material may be formed so that excess insulating material covers the fins 52. Some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as the filling material discussed above may be formed over the liner. A removal process is applied to the insulating material to remove excess insulating material over the fins 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the fin 52 so that after the planarization process is completed, the fin 52 is flush with the top surface of the insulating material. The insulating material is then recessed, wherein the remaining portion of the insulating material forms an STI region 56. The insulating material is recessed so that the upper portion of the fin 52 located in the region 50N and located in the region 50P protrudes from between adjacent STI regions 56. After the recess, the exposed portion of the fin 52 extends a height H1 above the top surface of the STI region 56. The height H1 may be greater than about 40 nm, for example in the range of about 50 nm to about 80 nm. The exposed portion of the fin 52 includes an area that will become the channel region of the resulting FinFET.

[0026] In addition, the top surface of STI region 56 may have a flat surface, a convex surface, a concave surface (such as a depression), or a combination thereof as shown. The top surface of STI region 56 may be formed into a flat, convex, and / or concave surface by appropriate etching. STI region 56 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., the material of the insulating material is etched faster than the material of the fin 52). For example, an acid such as dilute hydrofluoric acid (dHF) may be used to remove chemical oxides by a suitable etching process.

[0027] The above process is only one example of how the fin 52 is formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. In addition, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, after the insulating material of the STI region 56 is planarized with the fin 52, the fin 52 can be recessed, and a material different from the fin 52 can be epitaxially grown above the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material and an epitaxially grown material disposed above the recessed material. In another embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer. The heteroepitaxial structure may then be epitaxially grown in the trench using a material different from that of the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments where the homostructure and heterostructure are epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implants, although in situ doping and implant doping may be used together.

[0028] Still further, it may be advantageous to epitaxially grow a different material in region 50N (e.g., an NMOS region) than in region 50P (e.g., a PMOS region). In various embodiments, the upper portion of fin 52 may be formed of silicon germanium (SixGe1-x, where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0029] In addition, suitable wells (not shown) may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well may be formed in both region 50N and region 50P.

[0030] In an embodiment with different types of wells, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type dopant implant may be performed in region 50P, and the photoresist may be used as a mask to substantially prevent the n-type dopant from being implanted into region 50N, such as an NMOS region. The n-type dopant may be phosphorus, arsenic, antimony, etc., implanted into the region, at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0031] After the implantation of region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type dopant implant may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type dopant from being implanted into region 50P, such as a PMOS region. The p-type dopant may be boron, BF2, indium, etc., implanted into the region, at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0032] After implantation of regions 50N and 50P, an anneal may be performed to activate the implanted p-type and / or n-type dopants. In some embodiments, the grown material of the epitaxial fins may be doped in situ during growth, which may avoid implantation, although in situ and implant doping may be used together.

[0033] exist Figure 3In the embodiment of the present invention, a dummy gate dielectric 60 is formed over the fin 52, and a dummy gate 62 is formed over the dummy gate dielectric 60. The dummy gate dielectric 60 and the dummy gate 62 may be collectively referred to as a "dummy gate stack," wherein each dummy gate stack includes a dummy gate dielectric 60 and a dummy gate 62. The dummy gate stack extends along the sidewalls and top surface of the fin 52. Although only one dummy gate stack is shown, it should be understood that multiple dummy gate stacks may be formed simultaneously, and each fin 52 may have multiple dummy gate stacks formed thereon.

[0034] As an example of forming a pseudo gate dielectric 60 and a pseudo gate 62, a pseudo dielectric layer is formed on the fin 52. The pseudo dielectric layer may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A pseudo gate layer is formed above the pseudo dielectric layer, and a mask layer is formed above the pseudo gate layer. The pseudo gate layer may be deposited above the pseudo dielectric layer and then planarized, for example, by CMP. The mask layer may be deposited above the pseudo gate layer. The pseudo gate layer may be a conductive material or a non-conductive material, and may be selected from a group including amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The pseudo gate layer may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art for depositing conductive materials. The pseudo gate layer may be made of other materials having high etching selectivity to the etching of the isolation region. The mask layer may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer and a single mask layer are formed across region 50N and region 50P. It is noteworthy that, for illustrative purposes only, the dummy dielectric layer is shown to cover only the fin 52. In some embodiments, the dummy dielectric layer may be deposited so that the dummy dielectric layer covers the STI region 56, extending between the dummy gate layer and the STI region 56. Then, the mask layer is patterned using acceptable photolithography and etching techniques to form a mask 64. Then, the pattern of the mask 64 is transferred to the dummy gate layer by an acceptable etching technique to form a dummy gate 62. The pattern of the mask 64 is further transferred to the dummy dielectric layer to form a dummy gate dielectric 60. The dummy gate 62 covers each channel region 58 of the fin 52. The pattern of the mask 64 can be used to physically space each of the dummy gates 62 from an adjacent dummy gate. The dummy gate 62 may also have a length direction substantially perpendicular to the length direction of each fin 52.

[0035] exist Figure 4A and Figure 4BIn the embodiment, a lightly doped source / drain (LDD) region 70 is formed in the fin 52. The LDD region 70 can be formed by, for example, implantation. In embodiments with different device types, similar to the implantation discussed above, a mask such as a photoresist can be formed over the region 50N while exposing the region 50P, and a dopant of an appropriate type (e.g., p-type) can be implanted into the exposed fin 52 in the region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist can be formed over the region 50P while exposing the region 50N, and a dopant of an appropriate type (e.g., n-type) can be implanted into the exposed fin 52 in the region 50N. The mask can then be removed. The n-type dopant can be any of the n-type dopants previously discussed, and the p-type dopant can be any of the p-type dopants previously discussed. The lightly doped source / drain region can have a thickness of about 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implant damage, as well as to activate implanted dopants.

[0036] A plurality of gate spacer layers 72 are formed. Another spacer layer 74 is then formed over the gate spacer layers 72. Each of the spacer layer 74 and the gate spacer layer 72 is formed of a dielectric material such as silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, silicon, a metal oxide, etc., or a combination thereof, and may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. As discussed further below, some of the gate spacer layers 72 have a high etch selectivity to the dummy gate dielectric 60 and the spacer layer 74.

[0037] Figure 4C yes Figure 4A A detailed view of region 4C of FIG. 4A shows more detail of gate spacer layer 72 and is shown with reference to FIG. Figure 4A and Figure 4B Described at the same time. The gate spacer layer 72 includes a first protective layer 72A, a first main layer 72B, a second main layer 72C, and a second protective layer 72D. In some embodiments, each of the gate spacer layers 72A, 72B, 72C, and 72D is an oxycarbon nitride silicon layer having a different composition of silicon, oxygen, carbon, and nitrogen. In other words, each of the gate spacer layers 72 is a dielectric layer of a different composition including the same four elements. Forming the gate spacer layer 72 with different compositions of oxycarbon nitride silicon can allow the gate spacer layer 72 to avoid damage during subsequent etching processes, and also allow some gate spacer layers 72 to have a low k value. The gate spacer layer 72 can be formed to have a combined thickness of about to about within the range.

[0038] The first protective layer 72A is deposited on the sidewalls and top surfaces of the fin 52 and the dummy gate 62. In some embodiments, the first protective layer 72A is formed by silicon oxycarbon nitride, which has a composition of about 20 atomic percent (at.%) to about 40 at.%, about 20 at.% to about 50 at.% of silicon, less than about 20 at.% of carbon, and about 10 at.% to about 30 at.% of nitrogen. The first protective layer 72A can be deposited using a dielectric material precursor including a silicon source precursor (e.g., hexachlorodisilane (Si2Cl6, HCD)), an oxygen source precursor (e.g., dioxygen (O2)), a carbon source precursor (e.g., propylene (C3H6)), and a nitrogen source precursor (e.g., ammonia (NH3)). In some embodiments where deposition is performed by CVD, the composition of the first protective layer 72A can be controlled by controlling the flow rate of the source precursor during CVD. For example, the silicon source precursor may be dispensed at a rate in the range of about 100 sccm to about 1000 sccm, the oxygen source precursor may be dispensed at a rate in the range of about 500 sccm to about 8000 sccm, the carbon source precursor may be dispensed at a rate in the range of about 100 sccm to about 3000 sccm, and the nitrogen source precursor may be dispensed at a rate in the range of about 1000 sccm to about 5000 sccm. The first protective layer 72A may be deposited at a temperature in the range of about 550° C. to about 650° C. After deposition, the first protective layer 72A has a carbon source precursor at about 2.3 g / cm 3 To about 2.6g / cm 3 The first protective layer 72A has a density in the range of about 1000 Å, a refractive index (RI) in the range of about 1.65 to about 1.8, and a k value in the range of about 4.5 to about 6. The first protective layer 72A has a small thickness, for example, about to about The thickness is within the range of .

[0039] The first main layer 72B is deposited on the first protective layer 72A. In some embodiments, if the first main layer 72B is formed of silicon oxycarbon nitride, it has a composition of about 20 at.% to about 40 at.%, about 20 at.% to about 50 at.% oxygen, less than about 20 at.% carbon, and about 10 at.% to about 30 at.% nitrogen. The first main layer 72B can be deposited using a dielectric material precursor including a silicon source precursor (e.g., hexachlorodisilane (Si2Cl6, HCD)), an oxygen source precursor (e.g., dioxygen (O2)), a carbon source precursor (e.g., propylene (C3H6)), and a nitrogen source precursor (e.g., ammonia (NH3)). In some embodiments where deposition is performed by CVD, the composition of the first main layer 72B can be controlled by controlling the flow rate of the source precursor during CVD. For example, the silicon source precursor may be dispensed at a rate in the range of about 100 sccm to about 1000 sccm, the oxygen source precursor may be dispensed at a rate in the range of about 500 sccm to about 8000 sccm, the carbon source precursor may be dispensed at a rate in the range of about 100 sccm to about 3000 sccm, and the nitrogen source precursor may be dispensed at a rate in the range of about 1000 sccm to about 5000 sccm. The first main layer 72B may be deposited at a temperature in the range of about 550° C. to about 650° C. After deposition, the first main layer 72B has a carbon source precursor at about 2.3 g / cm 3 To about 2.6g / cm 3 The first main layer 72B has a density in the range of about 1000 Å to about 1000 Å, a refractive index (RI) in the range of about 1.65 to about 1.8, and a k value in the range of about 4.5 to about 6. The first main layer 72B has a large thickness, for example, about to about The thickness is within the range of .

[0040] The second main layer 72C is deposited on the first main layer 72B. In some embodiments, the second main layer 72C is formed by silicon oxycarbon nitride, which has a composition of about 20 at.% to about 40 at.% silicon, about 20 at.% to about 70 at.% oxygen, less than about 20 at.% carbon, and less than about 20 at.% nitrogen. The second main layer 72C can be deposited using a dielectric material precursor including a silicon source precursor (e.g., hexachlorodisilane (Si2Cl6, HCD)), an oxygen source precursor (e.g., dioxygen (O2)), and a carbon and nitrogen source precursor (e.g., triethylamine (N(C2H5)3). In an embodiment in which deposition is performed by CVD, the composition of the second main layer 72C can be controlled by controlling the flow rate of the source precursor during CVD. For example, the silicon source precursor can be dispensed at a rate in the range of about 100 sccm to about 1000 sccm, and the silicon source precursor can be dispensed at a rate in the range of about 500 sccm to about 8000 sccm. The oxygen source precursor may be dispensed at a rate in the range of about 100 sccm to about 200 sccm, and the carbon and nitrogen source precursor may be dispensed at a rate in the range of about 500 sccm to about 3000 sccm. The second main layer 72C may be deposited at a temperature in the range of about 550°C to about 650°C. In some embodiments, annealing is performed after the deposition of the second main layer 72C. The annealing process may be performed at a temperature in the range of about 600°C to about 750°C, at a duration in the range of about 30 minutes to about 180 minutes, and in an environment containing, for example, oxygen. After deposition, the second main layer 72C has a carbon and nitrogen source precursor at about 2 g / cm 3 To about 2.4g / cm 3 The second main layer 72C has a density in the range of about 1.50 to about 1.6, a refractive index (RI) in the range of about 1.55 to about 1.6, and a k value in the range of about 4 to about 5. The second main layer 72C has a large thickness, for example, about to about The thickness is within the range of .

[0041] The second protective layer 72D is deposited on the second main layer 72C. In some embodiments, the second protective layer 72D is formed of silicon oxycarbide having a composition of about 20 at.% to about 40 at.% silicon, about 20 at.% to about 40 at.% oxygen, about 20 at.% to about 40 at.% carbon, and less than about 20 at.% nitrogen. The second protective layer 72D may be deposited using a dielectric material precursor including a silicon source precursor (e.g., hexachlorodisilane (Si2Cl6, HCD)), an oxygen source precursor (e.g., dioxygen (O2)), and a carbon and nitrogen source precursor (e.g., triethylamine (N(C2H5)3)). In an embodiment where deposition is performed by CVD, the composition of the second protective layer 72D may be controlled by controlling the flow rate of the source precursors during CVD. For example, the silicon source precursor may be dispensed at a rate in a range of about 100 sccm to about 1000 sccm, the oxygen source precursor may be dispensed at a rate in a range of about 500 sccm to about 8000 sccm, and the carbon source precursor may be dispensed at a rate in a range of about 100 sccm to about 1000 sccm. The carbon-nitrogen source precursor is dispensed at a rate in the range of about 500 sccm to about 3000 sccm. The second protective layer 72D can be deposited at a temperature in the range of about 550°C to about 650°C. In some embodiments, annealing is performed after the deposition of the second protective layer 72D. The annealing process can be performed in a temperature range of about 600°C to about 750°C, in a duration range of about 30 minutes to about 180 minutes, and in an environment containing, for example, oxygen. In some embodiments, a single annealing process is performed on both the second protective layer 72D and the second main layer 72C. After deposition, the second protective layer 72D has a temperature of about 2 g / cm 3 To about 2.4g / cm 3 The second protective layer 72D has a density in the range of about 1000 Å, a refractive index (RI) in the range of about 1.65 to about 1.75, and a k value in the range of about 4.5 to about 6. The second protective layer 72D has a small thickness, for example, about to about The thickness is within the range of .

[0042] The gate spacer layer 72 has different compositions. Specifically, each of the gate spacer layers 72 has different concentrations of silicon, different concentrations of oxygen, different concentrations of carbon, and different concentrations of nitrogen. The first protective layer 72A and the second protective layer 72D may have greater concentrations (e.g., in at.%) of carbon and nitrogen than the first main layer 72B and the second main layer 72C. For example, the first protective layer 72A and the second protective layer 72D each have a carbon concentration greater than the carbon concentration of each of the first main layer 72B and the second main layer 72C by about 1.5 times to about 30 times. Similarly, the first protective layer 72A and the second protective layer 72D each have a nitrogen concentration greater than the nitrogen concentration of each of the first main layer 72B and the second main layer 72C by about 1.1 times to about 4 times. Forming the first protective layer 72A and the second protective layer 72D to be both carbon-rich and nitrogen-rich can allow the first protective layer 72A and the second protective layer 72D to have selectivity for subsequent etching processes. In some embodiments, the second protection layer 72D has a greater concentration (e.g., in at.%) of carbon than the first protection layer 72A, the first main layer 72B, and the second main layer 72C. As discussed below, forming the second protection layer 72D with additional carbon can be used for the source / drain recess process (see Figure 5A and Figure 5B ), allows the second protective layer 72D to have a high etch selectivity to the spacer layer 74 for an etching process that patterns the spacer layer 74 in a replacement gate process (see FIG. 1 ). Therefore, the amount of etching loss of the second protective layer 72D during the process can be reduced. In some embodiments, the first protective layer 72A has a greater concentration (e.g., in at.%) of nitrogen than the first main layer 72B, the second main layer 72C, and the second protective layer 72D. As discussed below, forming the first protective layer 72A with additional nitrogen can be beneficial for the replacement gate process (see FIG. 1 ). Fig. 10A and Fig. 10B) for an etching process to be used to remove the dummy gate dielectric 60, allowing the first protective layer 72A to have a high etching selectivity to the dummy gate dielectric 60. Therefore, the amount of etching loss of the first protective layer 72A during the process can be reduced. In some embodiments, the second main layer 72C has a greater concentration (e.g., in at.%) of oxygen than the first protective layer 72A, the first main layer 72B, and the second protective layer 72D. For example, the second main layer 72C has an oxygen concentration that is greater than about 1.2 times to about 3 times the oxygen concentration of each of the first protective layer 72A, the first main layer 72B, and the second protective layer 72D. As discussed below, forming the second main layer 72C with a large amount of oxygen can allow the formation of a gate spacer layer with a very low k value. For example, the second main layer 72C can have a relative permittivity that is less than the relative permittivity of each of the first protective layer 72A, the first main layer 72B, and the second protective layer 72D by about 10% to about 40%. Reducing etching loss and reducing the k value of the gate spacer layer 72 helps to reduce the resulting gate spacer 78 (see Figure 5A and Figure 5B ) to reduce the parasitic capacitance of the resulting FinFET. For certain applications, such as ring oscillators or static random access memory (SRAM) cells, reducing the parasitic capacitance of the resulting FinFET may be particularly advantageous. The gate spacer layer 72 may be formed to have different compositions by controlling its deposition parameters.

[0043] In some embodiments, the first protective layer 72A and the first main layer 72B are formed with the same source precursor and are formed by dispensing the source precursor at different flow rate sets. The flow rate of each source precursor can be selected in proportion to the desired composition of the deposited layer. Specifically, when depositing the first protective layer 72A, the oxygen source precursor can be dispensed at a smaller rate than when depositing the first main layer 72B, when depositing the first protective layer 72A, the carbon source precursor can be dispensed at a greater rate than when depositing the first main layer 72B, and when depositing the first protective layer 72A, the nitrogen source precursor can be dispensed at a greater rate than when depositing the first main layer 72B. For example, an oxygen source precursor may be dispensed at a rate greater than about 5% to about 70% when depositing the first main layer 72B than when depositing the first protective layer 72A, a carbon source precursor may be dispensed at a rate less than about 5% to about 70% when depositing the first protective layer 72A, and a nitrogen source precursor may be dispensed at a rate less than about 5% to about 70% when depositing the first protective layer 72A. In some embodiments, the first protective layer 72A and the first main layer 72B are deposited in the same deposition chamber without breaking the vacuum between the deposition of the first protective layer 72A and the deposition of the first main layer 72B. When the first protective layer 72A and the first main layer 72B are formed in the same chamber and using the same source precursor, the boundary between the first protective layer 72A and the first main layer 72B may not be an abrupt transition, but may be a gradient change from the material of the first protective layer 72A to the material of the first main layer 72B.

[0044] In some embodiments, the second main layer 72C and the second protective layer 72D are formed by the same source precursor and are formed by dispensing the source precursor at different flow rate sets. The flow rate of each source precursor can be selected in proportion to the desired composition of the deposited layer. Specifically, the oxygen source precursor can be dispensed at a greater rate when the second main layer 72C is deposited than when the second protective layer 72D is deposited, and the carbon-nitrogen source precursor can be dispensed at a smaller rate when the second main layer 72C is deposited than when the second protective layer 72D is deposited. For example, the oxygen source precursor can be dispensed at a rate of less than about 20% to about 90% when the second main layer 72C is deposited, and the carbon-nitrogen source precursor can be dispensed at a rate of greater than about 20% to about 90% when the second main layer 72C is deposited. In some embodiments, the second main layer 72C and the second protective layer 72D are deposited in the same deposition chamber without destroying the vacuum between the deposition of the second main layer 72C and the deposition of the second protective layer 72D.

[0045] After formation, some or all of the gate spacer layers 72 may have different thicknesses. In some embodiments, the first main layer 72B and the second main layer 72C are each about 1.5 to about 6 times thicker than each of the first protective layer 72A and the second protective layer 72D.

[0046] Different compositions of the gate spacer layer 72 may allow the gate spacer layer 72 to have different material properties. For example, the refractive index (RI) of the second protective layer 72D may be greater than the refractive index (RI) of the first protective layer 72A, which may be greater than the refractive index (RI) of the first main layer 72B, which may be greater than the refractive index (RI) of the second main layer 72C. Similarly, the density of the first protective layer 72A may be greater than the density of the first main layer 72B, which may be greater than the density of the second main layer 72C, which may be greater than the density of the second protective layer 72D. Finally, the k value of the second main layer 72C may be less than the k value of the second protective layer 72D, which may be less than the k value of the first main layer 72B, which may be less than the k value of the first protective layer 72A. Such material properties may be desirable for certain types of gate spacers 78 (see Figure 5A and Figure 5B ) may be advantageous. For example, while the first protective layer 72A and the second protective layer 72D have other advantageous properties, they also have a greater relative permittivity than the second main layer 72C and the second protective layer 72D. Reducing the relative permittivity of the second main layer 72C can help offset any increase in relative permittivity contributed by the first protective layer 72A and the second protective layer 72D.

[0047] Other methods may also be used to form the gate spacer layers 72. For example, some or all of the gate spacer layers 72 may be formed by ALD using the above-described precursors. In such an embodiment, the composition of the gate spacer layers 72 may be controlled by adjusting the number of ALD cycles or the cycle ratio of the ALD process for each of the gate spacer layers 72.

[0048] The spacer layer 74 is deposited on the second protective layer 72D. In some embodiments, the spacer layer 74 is formed by silicon nitride. The spacer layer 74 has a large thickness, for example, a thickness in the range of about 1 nm to about 10 nm. The spacer layer 74 may (or may not) have a thickness greater than the thickness of each of the gate spacer layers 72.

[0049] exist Figure 5A and Figure 5B , patterned source / drain recesses 76 . Figure 5C yes Figure 5A A detailed view of region 5C of FIG. 5A shows more detail of gate spacer 78 and is shown with reference to FIG. Figure 5A and Figure 5BDescribed simultaneously. The source / drain recess 76 is patterned through the spacer layer 74, through each of the gate spacer layers 72, and in the fin 52. The source / drain recess 76 extends through the LDD region 70 and may also penetrate the fin 52. The source / drain recess 76 may have a depth in the range of about 20 nm to about 80 nm. The source / drain recess 76 may be formed by an appropriate etching process. For example, the etching process may include wet etching and dry etching, thus including both isotropic and anisotropic components. In some embodiments, an anisotropic wet etching selective to the material of the spacer layer 74 may be implemented to first form an opening in the spacer layer 74. For example, when the spacer layer 74 is formed by silicon nitride, wet etching may be implemented with a phosphoric acid solution (H3PO4:H2O). The temperature of the phosphoric acid solution may be in the range of about 50°C to about 200°C. As described above, the second protective layer 72D has a composition including additional carbon. Wet etching can remove the material of the spacer layer 74 at a higher rate than the carbon-rich material of the second protective layer 72D. For example, for wet etching, the etching rate of the spacer layer 74 is about 1.1 times to about 2 times greater than the etching rate of the second protective layer 72D. In other words, the second protective layer 72D is used as an etching stop layer during wet etching. An isotropic dry etch can then be performed to extend the opening through each of the gate spacer layers 72 and form a source / drain recess 76 in the fin 52. For example, dry etching can be performed with an etching gas solution that simultaneously generates plasma including a mixture of tetrafluoromethane (CF4) and hydrogen (H2). Dry etching may damage the spacer layer 74 that protects the underlying gate spacer layer 72. The etching process forms a gate spacer 78, which includes the remaining portion of the gate spacer layer 72, and also forms a second spacer 80, which includes the remaining portion of the damaged spacer layer 74.

[0050] exist Fig. 6A and Figure 6B In the embodiment of the present invention, epitaxial source / drain regions 90 are formed in the source / drain recesses 76 to apply stress in each channel region 58 to improve performance. The epitaxial source / drain regions 90 are formed in the source / drain recesses 76 so that each dummy gate 62 is disposed between each adjacent pair of epitaxial source / drain regions 90. In some embodiments, the gate spacers 78 and the second spacers 80 are used to separate the epitaxial source / drain regions 90 and the dummy gates 62 by an appropriate lateral distance so that the epitaxial source / drain regions 90 do not short-circuit the gate of the resulting FinFET formed subsequently.

[0051] The epitaxial source / drain regions 90 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P (e.g., PMOS region) and epitaxially growing the epitaxial source / drain regions 90 in the region 50N. The epitaxial source / drain regions 90 may include any acceptable material, such as suitable for n-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 90 in the region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 90 in the region 50N may have surfaces elevated from corresponding surfaces of the fin 52 and may have facets.

[0052] The epitaxial source / drain regions 90 in the region 50P (e.g., PMOS region) can be formed by masking the region 50N (e.g., NMOS) and epitaxially growing the epitaxial source / drain regions 90 in the region 50P. The epitaxial source / drain regions 90 can include any acceptable material, such as suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 90 in the region 50P can include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 90 in the region 50P can also have surfaces elevated from the corresponding surfaces of the fin 52 and can have facets.

[0053] The epitaxial source / drain regions 90 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions followed by annealing. The source / drain regions may have a thickness of about 10 19 cm -3 and about 10 21 cm -3 The n-type and / or p-type dopants used for the source / drain regions may be any of the dopants discussed previously. In some embodiments, the epitaxial source / drain regions 90 may be doped in situ during growth.

[0054] As a result of the epitaxial process used to form epitaxial source / drain regions 90 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 90 of the same FinFET to merge, as shown by Figure 6B In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 90 remain separated, as shown by Figure 6C As shown. Figure 6B and 6CIn the illustrated embodiment, gate spacer 78 and second spacer 80 are formed to cover a portion of the sidewalls of fin 52 extending over STI region 56, thereby preventing epitaxial growth. In some other embodiments, the etch used to form source / drain recesses 76 can be adjusted to remove spacer material to allow epitaxial growth regions to extend to the surface of STI region 56.

[0055] The order of operations may be modified. In some embodiments, source / drain recesses 76 may be patterned separately in each of regions 50P and 50N. For example, both source / drain recesses 76 and epitaxial source / drain regions 90 may be formed in region 50N while masking region 50P, or both source / drain recesses 76 and epitaxial source / drain regions 90 may be formed in region 50P while masking region 50N. In some embodiments, a single spacer layer 74 is formed in both regions 50P and 50N, and a single spacer layer 74 is patterned in each of regions 50P and 50N. In some embodiments, spacer layers 74 are formed and patterned separately in each region 50P / 50N while masking the corresponding other region 50N / 50P.

[0056] exist Fig. 7A and Figure 7B In the embodiment of the present invention, the second spacer 80 is optionally removed. Figure 7C yes Fig. 7A A detailed view of region 7C of FIG. 7C shows more detail of gate spacer 78 and is shown with reference to FIG. Fig. 7A and Figure 7B Described at the same time. Removal can be performed by an appropriate etching process. In some embodiments, anisotropic wet etching is performed with a phosphoric acid solution (H3PO4:H2O) to remove the second spacer 80. As described above, for wet etching using phosphoric acid, the protective layer 72D has a high etching selectivity to the spacer layer 74, thereby protecting the other gate spacer layers 72A, 72B, and 72C during wet etching. After removal, a recess 92 can be formed between the sidewalls of the epitaxial source / drain region 90 and the gate spacer 78. In some embodiments, the wet etching removes only some portions of the second spacer 80, such as the portion disposed between the dummy gate 62 and the epitaxial source / drain region 90, and the remaining portion of the second spacer 80 can remain below the epitaxial source / drain region 90. In other words, after wet etching, the first portion of the gate spacer 78 (e.g., the portion on the top surface of the fin 52) is not provided with the second spacer 80, while the second portion of the gate spacer 78 (e.g., the portion on the sidewall of the fin 52 and the top surface of the STI region 56) is covered by the second spacer 80.

[0057] exist Fig. 8A and Figure 8BIn the embodiment of the present invention, a first ILD layer 96 is deposited over the intermediate structure. The first ILD layer 96 may be formed by a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0058] In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD layer 96 and the epitaxial source / drain regions 90, the mask 64, and the gate spacer 78. The CESL 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., and may be formed by a deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. The CESL 94 has an etch rate different from that of the materials of the first ILD layer 96 and the gate spacer 78. In some embodiments, the CESL 94 includes a dielectric material different from each layer of the gate spacer 78, and may have a higher relative permittivity than at least some layers of the gate spacer 78 (e.g., the second main layer 72C). For example, the CESL 94 may be formed by silicon nitride. The CESL 94 physically contacts the sidewalls of the gate spacer 78, and any remaining portion of the second spacer 80. When the recess 92 is formed, the CESL 94 may also be formed in the recess 92. Notably, the remaining portion of the second spacer 80 is disposed between the sidewalls of the CESL 94 and the gate spacer 78. The remaining portion of the second spacer 80 may therefore be referred to as a source / drain sidewall spacer.

[0059] exist Fig. 9A and Fig. 9B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD layer 96 flush with the top surface of the dummy gate 62 or the mask 64. The planarization process may also remove the mask 64 on the dummy gate 62 and the portion of the gate spacer 78 along the sidewall of the mask 64. After the planarization process, the top surfaces of the dummy gate 62, the gate spacer 78, and the first ILD layer 96 are flush. Therefore, the top surface of the dummy gate 62 is exposed through the first ILD layer 96. In some embodiments, the mask 64 may be retained, in which case the planarization process makes the top surface of the first ILD layer 96 flush with the top surface of the mask 64.

[0060] exist Fig. 10A and Fig. 10B In the process, the dummy gate 62 and the mask 64 (if present) are removed in one or more etching steps. Fig. 10C yes Fig. 10AA detailed view of region 10C of FIG. 10A shows more detail of gate spacer 78 and is shown with reference to FIG. Fig. 10A and Fig. 10B Described at the same time. Removal can form a replacement gate recess 100. Portions of the dummy gate dielectric 60 in the replacement gate recess 100 can also be removed. In some embodiments, only the dummy gate 62 is removed, while the dummy gate dielectric 60 remains and is exposed through the replacement gate recess 100. In some embodiments, the dummy gate dielectric 60 is removed from the replacement gate recess 100 in a first area of ​​the tube core (e.g., a central logic area) and remains in the replacement gate recess 100 in a second area of ​​the tube core (e.g., an input / output area). In some embodiments, the dummy gate 62 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 62 without etching the first ILD layer 96 or the gate spacer 78. Each recess 100 exposes and / or covers the channel region 58 of each fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 90. During removal, when etching the dummy gate 62, the dummy gate dielectric 60 can be used as an etch stop layer. Then, after removing the dummy gate 62, the dummy gate dielectric 60 may be optionally removed. In some embodiments, the gate dielectric 60 is removed by an anisotropic wet etching process. For example, wet etching may be performed using a dilute hydrofluoric acid (dHF) acid solution (HF:H2O). The temperature of the dilute hydrofluoric acid solution may be in the range of about 20°C to about 100°C. As described above, the first protective layer 72A has a composition including additional nitrogen. Wet etching may remove the material of the gate dielectric 60 at a higher rate than the nitrogen-rich material of the first protective layer 72A. For example, for wet etching, the etching rate of the gate dielectric 60 is about 1.1 times to about 2 times greater than the etching rate of the first protective layer 72A. In other words, the first protective layer 72A acts as a protective layer during wet etching.

[0061] exist Fig.11A and Fig. 11BIn the embodiment of the present invention, a metal gate 102 is formed in the replacement gate recess 100. The metal gate 102 includes a gate dielectric 104 and a gate electrode 106. The gate dielectric 104 is conformally deposited in the recess, for example, on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate spacer 78. The gate dielectric 104 may also be formed on the top surface of the first ILD layer 96. According to some embodiments, the gate dielectric 104 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric 104 includes a high-k dielectric material, and in these embodiments, the gate dielectric 104 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric 104 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In embodiments where a portion of the dummy gate dielectric 60 remains in the recess, the gate dielectric 104 includes the material of the dummy gate dielectric 60 (eg, SiO 2 ).

[0062] The gate electrodes 106 are deposited over the gate dielectric 104, respectively, and fill the remaining portions of the recesses. The gate electrodes 106 may include metal-containing materials, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 106 is shown, each gate electrode 106 may include any number of liner layers, any number of work function adjustment layers, and filling materials. After filling the gate electrodes 106, a planarization process such as CMP may be performed to remove excess portions of the materials of the gate dielectric 104 and the gate electrodes 106, which are located above the top surface of the first ILD layer 96. The remaining portions of the materials of the gate electrodes 106 and the gate dielectric 104 thus form a metal gate 102. The metal gate 102 may also be referred to as a "gate stack" or a "replacement gate stack" for the resulting FinFET. The metal gate 102 may extend along the sidewalls of the channel region 58 of the fin 52.

[0063] The formation of the gate dielectric 104 in the region 50N and the region 50P may occur simultaneously, such that the gate dielectric 104 in each region is formed from the same material, and the formation of the gate electrode 106 may occur simultaneously, such that the gate electrode 106 in each region is formed from the same material. In some embodiments, the gate dielectric 104 in each region may be formed by a different process, such that the gate dielectric 104 may be a different material, and / or the gate electrode 106 in each region may be formed by a different process, such that the gate electrode 106 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0064] exist Fig. 12A and Fig. 12B In the embodiment of the present invention, a contact opening 110 is formed through the first ILD layer 96 and the CESL 94, exposing the epitaxial source / drain region 90. The contact opening 110 can be formed using acceptable photolithography and etching techniques. Then, a silicide 112 is formed in the contact opening 110 on the portion of the epitaxial source / drain region 90 exposed by the contact opening 110. The silicide 112 can be formed by depositing a metal in the contact opening 110 and performing an anneal. The metal can be, for example, titanium or cobalt, which can form a silicide 112 of TiSi2 or CoSi2, respectively. The silicide 112 can have a thickness in the range of about 2 nm to about 10 nm.

[0065] exist Fig.13A and Fig. 13B , the lower source / drain contact 114 is formed in the contact opening 110 (see Fig. 12A and Fig. 12B ). A liner and a conductive material such as a diffusion barrier layer, an adhesion layer, etc. are formed in the contact opening 110 and are located on the silicide 112. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the first ILD layer 96. The remaining liner and conductive material form a lower source / drain contact 114 in the contact opening 110. The lower source / drain contact 114 is physically and electrically connected to the silicide 112. The lower source / drain contact 114 may have a height in the range of about 5 nm to about 15 nm.

[0066] exist Fig.14A and Fig. 14B In the embodiment, the second ILD layer 120 is deposited over the first ILD layer 96 and the lower source / drain contact 114. In some embodiments, the second ILD layer 120 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer 120 is formed by a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. According to some embodiments, before forming the second ILD layer 120, the metal gate 102 can be recessed so that the recess is formed directly above the metal gate 102 and between the opposite portions of the gate spacer 78. A gate mask 122 including one or more layers of dielectric materials such as silicon nitride, silicon oxynitride, etc. is filled in the recess, and then the excess portion of the dielectric material extending over the first ILD layer 96 is removed by a planarization process.

[0067] exist Fig.15A and Fig. 15BIn the embodiment of the present invention, an upper source / drain contact 124 and a gate contact 126 are formed through the second ILD layer 120. An opening for the upper source / drain contact 124 and the gate contact 126 is formed through the second ILD layer 120. The opening can be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be implemented to remove excess material from the surface of the second ILD layer 120. The remaining liner and conductive material form an upper source / drain contact 124 and a gate contact 126 in the opening. The upper source / drain contact 124 is physically and electrically connected to the lower source / drain contact 114, and the gate contact 126 is physically and electrically connected to the metal gate 102. The gate contact 126 may penetrate the gate mask 122 (if present). The upper source / drain contact 124 and the gate contact 126 may be formed in different processes, or may be formed in the same process. Each of the upper source / drain contact 124 and the gate contact 126 may be formed in different cross-sections, which may avoid short circuiting of the contacts.

[0068] Embodiments can achieve advantages. For forming source / drain recesses 76 (see Figure 5A and Figure 5B ) and replacement gate recess 100 (see Fig. 10A and Fig. 10B ), the gate spacer layer 72 formed with different compositions of silicon, oxygen, carbon, and nitrogen can allow the gate spacer layer 72 to have a high etching selectivity. Specifically, the first protective layer 72A and the second protective layer 72D protect the first main layer 72B and the second main layer 72C from etching, thereby reducing the etching loss of the gate spacer layer 72. Therefore, the loss of the gate spacer layer 72 can be reduced, thereby reducing the relative permittivity of the gate spacer 78. Therefore, the parasitic capacitance of the resulting FinFET can be reduced, which is particularly beneficial for certain applications such as ring oscillators or SRAM cells.

[0069] Fig.16 Scatter plots of test data for n-type FinFET (NFET) devices and p-type FinFET (PFET) devices are shown. Fig.16 Test data 202N, 202P for FinFETs without gate spacers of embodiments are shown, and test data 204N, 204P for FinFETs with gate spacers of embodiments are also shown. As shown, the gate spacers of embodiments allow the gate-to-channel capacitance (C gc ) and the gate-to-drain / source capacitance (Cgd ) are reduced. Embodiments may allow for a reduction in parasitic capacitance of up to 5%.

[0070] In one embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack located above the fin; an epitaxial source / drain region located in the fin adjacent to the gate stack; and a gate spacer disposed between the epitaxial source / drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbon nitride layers, each of the plurality of silicon oxycarbon nitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

[0071] In some embodiments of the structure, the plurality of silicon oxycarbon nitride layers include: a first dielectric layer, contacting the gate stack; a second dielectric layer, contacting the first dielectric layer, the second dielectric layer being 1.5 to 6 times thicker than the first dielectric layer; a third dielectric layer, contacting the second dielectric layer, the third dielectric layer being 1.5 to 6 times thicker than the first dielectric layer; a fourth dielectric layer, contacting the third dielectric layer, the third dielectric layer being 1.5 to 6 times thicker than the fourth dielectric layer, and the second dielectric layer being 1.5 to 6 times thicker than the fourth dielectric layer. In some embodiments of the structure, the first dielectric layer has a nitrogen concentration that is 1.1 to 4 times greater than the nitrogen concentration of the second dielectric layer, the third dielectric layer, and the fourth dielectric layer. In some embodiments of the structure, the third dielectric layer has an oxygen concentration that is 1.2 to 3 times greater than the oxygen concentration of the first dielectric layer, the second dielectric layer, and the fourth dielectric layer. In some embodiments of the structure, the fourth dielectric layer has a carbon concentration that is 1.5 to 30 times greater than the carbon concentration of the first dielectric layer, the second dielectric layer, and the third dielectric layer. In some embodiments of the structure, the third dielectric layer has a relative permittivity that is 10% to 40% less than the relative permittivity of the first dielectric layer, the second dielectric layer, and the fourth dielectric layer. In some embodiments, the structure further includes: an isolation region surrounding the fin, a gate spacer having a first portion and a second portion, the first portion being disposed on a top surface of the fin, and the second portion being disposed on a sidewall of the fin and a top surface of the isolation region; and a sidewall spacer disposed on the second portion of the gate spacer, the first portion of the gate spacer not being disposed with a sidewall spacer. In some embodiments, the structure further includes: a contact etch stop layer (CESL) disposed on the epitaxial source / drain region, the contact etch stop layer contacting a sidewall of the first portion of the gate spacer, and the sidewall spacer disposed between the contact etch stop layer and the second portion of the gate spacer.

[0072] In one embodiment, a structure includes: a semiconductor substrate including a channel region; a gate stack located above the channel region; an epitaxial source / drain region adjacent to the channel region; a gate spacer disposed between the epitaxial source / drain region and the gate stack, the gate spacer including: a first protective layer located above the semiconductor substrate; a first main layer disposed above the first protective layer; a second main layer disposed above the first main layer; and a second protective layer disposed above the second main layer, wherein the second main layer has a smaller relative permittivity than each of the first protective layer, the first main layer, and the second protective layer, and wherein, for an etching process, the first protective layer has a smaller etching rate than each of the first main layer, the second main layer, and the second protective layer.

[0073] In some embodiments of the structure, each of the first main layer and the second main layer has a thickness that is 1.5 to 6 times greater than the thickness of each of the first protective layer and the second protective layer. In some embodiments of the structure, each of the first protective layer, the first main layer, the second main layer, and the second protective layer includes a different composition of silicon oxycarbon nitride, and further includes: a contact etch stop layer (CESL) disposed above the epitaxial source / drain region and along the sidewalls of the gate spacer, the contact etch stop layer including silicon nitride.

[0074] In one embodiment, a method includes: forming a first gate stack located on a fin; dispensing a first precursor to deposit a first silicon oxycarbon nitride layer and a second silicon oxycarbon nitride layer, the first silicon oxycarbon nitride layer being located on sidewalls and a top surface of the first gate stack and the fin, the second silicon oxycarbon nitride layer being located on the first silicon oxycarbon nitride layer, dispensing the first precursor at a first flow rate set when depositing the first silicon oxycarbon nitride layer, dispensing the first precursor at a second flow rate set when depositing the second silicon oxycarbon nitride layer, the first flow rate set being different from the second flow rate set; and dispensing a second precursor to deposit a third silicon oxycarbon nitride layer and a fourth silicon oxycarbon nitride layer, the third silicon oxycarbon nitride layer being located on the second silicon oxycarbon nitride layer, the fourth silicon oxycarbon nitride layer being located on the third silicon oxycarbon nitride layer, dispensing the second precursor at a third flow rate set when depositing the third silicon oxycarbon nitride layer, and dispensing the second precursor at a fourth flow rate set when depositing the fourth silicon oxycarbon nitride layer, the third flow rate set being different from the fourth flow rate set.

[0075] In some embodiments of the method, the first precursor includes a silicon source precursor, an oxygen source precursor, a carbon source precursor, and a nitrogen source precursor, and the second precursor includes a silicon source precursor, an oxygen source precursor, and a carbon-nitrogen source precursor. In some embodiments of the method, the oxygen source precursor is dispensed at a first rate when depositing the first silicon oxycarbon nitride layer, and the oxygen source precursor is dispensed at a second rate when depositing the second silicon oxycarbon nitride layer, and the second rate is greater than the first rate by 5% to 70%, wherein the carbon source precursor is dispensed at a third rate when depositing the first silicon oxycarbon nitride layer, and the carbon source precursor is dispensed at a fourth rate when depositing the second silicon oxycarbon nitride layer, and the fourth rate is less than the third rate by 5% to 70%, and wherein the nitrogen source precursor is dispensed at a fifth rate when depositing the first silicon oxycarbon nitride layer, and the nitrogen source precursor is dispensed at a sixth rate when depositing the second silicon oxycarbon nitride layer, and the sixth rate is less than the fifth rate by 5% to 70%. In some embodiments of the method, the oxygen source precursor is dispensed at a first rate when depositing the third silicon oxycarbon nitride layer, and the oxygen source precursor is dispensed at a second rate when depositing the fourth silicon oxycarbon nitride layer, the second rate being 20% ​​to 90% less than the first rate, and wherein the carbon and nitrogen source precursor is dispensed at a third rate when depositing the third silicon oxycarbon nitride layer, and the carbon and nitrogen source precursor is dispensed at a fourth rate when depositing the fourth silicon oxycarbon nitride layer, the fourth rate being 20% ​​to 90% greater than the third rate. In some embodiments of the method, the silicon source precursor is hexachlorodisilane, the oxygen source precursor is dioxygen, the carbon source precursor is propylene, the nitrogen source precursor is ammonia, and the carbon and nitrogen source precursor is triethylamine. In some embodiments, the method further includes: annealing the third silicon oxycarbon nitride layer and the fourth silicon oxycarbon nitride layer in an oxygen-containing environment, the annealing being performed at a temperature range of 600° C. to 750° C. and for a duration range of 30 minutes to 180 minutes. In some embodiments of the method, each of the first silicon oxycarbon nitride layer and the fourth silicon oxycarbon nitride layer has a thickness that is less than the thickness of each of the second silicon oxycarbon nitride layer and the third silicon oxycarbon nitride layer. In some embodiments, the method further includes: depositing a sacrificial layer on the fourth silicon oxycarbon nitride layer; etching the sacrificial layer, the first silicon oxycarbon nitride layer, the second silicon oxycarbon nitride layer, the third silicon oxycarbon nitride layer, the fourth silicon oxycarbon nitride layer, and the first recess in the fin using a first etching process, for the first etching process, the etching rate of the sacrificial layer is greater than the etching rate of the fourth silicon oxycarbon nitride layer; growing epitaxial source / drain regions in the first recess; and after growing the epitaxial source / drain regions, removing the sacrificial layer. In some embodiments, the method further includes: removing the first gate stack using a second etching process to form a second recess, for the second etching process, the etching rate of the first gate stack is greater than the etching rate of the first silicon oxycarbon nitride layer; and forming a second gate stack in the second recess.

[0076] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: Semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack located above the fin; an epitaxial source / drain region in the fin adjacent to the gate stack; as well as a gate spacer disposed between the epitaxial source / drain region and the gate stack, the gate spacer comprising a plurality of silicon oxycarbon nitride layers, each of the plurality of silicon oxycarbon nitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen; Wherein, the plurality of silicon oxycarbon nitride layers include: a first dielectric layer contacting the gate stack; a second dielectric layer, contacting the first dielectric layer; a third dielectric layer contacting the second dielectric layer; and a fourth dielectric layer, contacting the third dielectric layer; The nitrogen concentration of the first dielectric layer is greater than the nitrogen concentrations of the second dielectric layer, the third dielectric layer and the fourth dielectric layer.

2. The semiconductor structure according to claim 1, wherein: The second dielectric layer is 1.5 to 6 times thicker than the first dielectric layer; the third dielectric layer is 1.5 to 6 times thicker than the first dielectric layer; and the third dielectric layer is 1.5 to 6 times thicker than the fourth dielectric layer, and the second dielectric layer is 1.5 to 6 times thicker than the fourth dielectric layer.

3. The semiconductor structure according to claim 2, wherein: The first dielectric layer has a nitrogen concentration that is 1.1 to 4 times greater than nitrogen concentrations of the second dielectric layer and the third dielectric layer.

4. The semiconductor structure according to claim 2, wherein: The third dielectric layer has an oxygen concentration that is 1.2 to 3 times greater than oxygen concentrations of the first dielectric layer, the second dielectric layer, and the fourth dielectric layer.

5. The semiconductor structure according to claim 2, wherein: The fourth dielectric layer has a carbon concentration that is 1.5 to 30 times greater than carbon concentrations of the second and third dielectric layers.

6. The semiconductor structure according to claim 2, wherein: The third dielectric layer has a relative permittivity that is 10% to 40% smaller than relative permittivity of the first dielectric layer, the second dielectric layer, and the fourth dielectric layer.

7. The semiconductor structure according to claim 1, further comprising: An isolation region surrounding the fin, the gate spacer having a first portion and a second portion, the first portion being disposed on a top surface of the fin, and the second portion being disposed on a sidewall of the fin and a top surface of the isolation region; as well as A sidewall spacer is located on the second portion of the gate spacer, and the first portion of the gate spacer is not provided with the sidewall spacer.

8. The semiconductor structure according to claim 7, further comprising: A contact etch stop layer is located on the epitaxial source / drain region, the contact etch stop layer contacts the side wall of the first portion of the gate spacer, and the sidewall spacer is disposed between the contact etch stop layer and the second portion of the gate spacer.

9. A semiconductor structure comprising: a semiconductor substrate including a channel region; A gate stack located above the channel region; an epitaxial source / drain region adjacent to the channel region; as well as A gate spacer is disposed between the epitaxial source / drain region and the gate stack, the gate spacer comprising: A first protective layer, located above the semiconductor substrate; A first main layer, disposed above the first protective layer; a second main layer disposed above the first main layer; and A second protective layer is disposed above the second main layer, wherein the second main layer has a smaller relative permittivity than each of the first protective layer, the first main layer, and the second protective layer, and wherein, for an etching process, the first protective layer has a smaller etching rate than each of the first main layer, the second main layer, and the second protective layer; The nitrogen concentration of the first protective layer is greater than the nitrogen concentrations of the first main layer, the second main layer and the second protective layer.

10. The semiconductor structure according to claim 9, wherein: Each of the first main layer and the second main layer has a thickness greater than that of each of the first protective layer and the second protective layer by 1.5 to 6 times.

11. The semiconductor structure according to claim 9, wherein: Each of the first protective layer, the first main layer, the second main layer, and the second protective layer includes a different composition of silicon oxycarbon nitride, and further includes: A contact etch stop layer is disposed above the epitaxial source / drain region and along the sidewall of the gate spacer, wherein the contact etch stop layer comprises silicon nitride.

12. A method of forming a semiconductor structure, comprising: forming a first gate stack on the fin; dispensing a first precursor to deposit a first silicon oxycarbon nitride layer and a second silicon oxycarbon nitride layer, the first silicon oxycarbon nitride layer being located on sidewalls and top surfaces of the first gate stack and the fin, the second silicon oxycarbon nitride layer being located on the first silicon oxycarbon nitride layer, dispensing the first precursor at a first flow rate set when depositing the first silicon oxycarbon nitride layer, and dispensing the first precursor at a second flow rate set when depositing the second silicon oxycarbon nitride layer, the first flow rate set being different from the second flow rate set; as well as A second precursor is dispensed to deposit a third silicon oxycarbon nitride layer and a fourth silicon oxycarbon nitride layer, the third silicon oxycarbon nitride layer being on the second silicon oxycarbon nitride layer, the fourth silicon oxycarbon nitride layer being on the third silicon oxycarbon nitride layer, the second precursor being dispensed at a third flow rate set when depositing the third silicon oxycarbon nitride layer, and the second precursor being dispensed at a fourth flow rate set when depositing the fourth silicon oxycarbon nitride layer, the third flow rate set being different from the fourth flow rate set.

13. The method according to claim 12, wherein: The first precursor includes a silicon source precursor, an oxygen source precursor, a carbon source precursor, and a nitrogen source precursor, and wherein the second precursor includes the silicon source precursor, the oxygen source precursor, and a carbon-nitrogen source precursor.

14. The method according to claim 13, wherein: The oxygen source precursor is dispensed at a first rate when depositing the first silicon oxycarbon nitride layer, and the oxygen source precursor is dispensed at a second rate when depositing the second silicon oxycarbon nitride layer, the second rate being 5% to 70% greater than the first rate, wherein the carbon source precursor is dispensed at a third rate when depositing the first silicon oxycarbon nitride layer, and the carbon source precursor is dispensed at a fourth rate when depositing the second silicon oxycarbon nitride layer, the fourth rate being 5% to 70% less than the third rate, and wherein the nitrogen source precursor is dispensed at a fifth rate when depositing the first silicon oxycarbon nitride layer, and the nitrogen source precursor is dispensed at a sixth rate when depositing the second silicon oxycarbon nitride layer, the sixth rate being 5% to 70% less than the fifth rate.

15. The method according to claim 13, wherein: The oxygen source precursor is dispensed at a first rate when depositing the third silicon oxycarbon nitride layer, and is dispensed at a second rate when depositing the fourth silicon oxycarbon nitride layer, the second rate being 20% ​​to 90% less than the first rate, and wherein the carbon-nitrogen source precursor is dispensed at a third rate when depositing the third silicon oxycarbon nitride layer, and is dispensed at a fourth rate when depositing the fourth silicon oxycarbon nitride layer, the fourth rate being 20% ​​to 90% greater than the third rate.

16. The method according to claim 13, wherein: The silicon source precursor is hexachlorodisilane, the oxygen source precursor is dioxygen, the carbon source precursor is propylene, the nitrogen source precursor is ammonia, and the carbon and nitrogen source precursor is triethylamine.

17. The method according to claim 12, further comprising: The third silicon oxycarbon nitride layer and the fourth silicon oxycarbon nitride layer are annealed in an oxygen-containing environment at a temperature ranging from 600° C. to 750° C. and for a duration ranging from 30 minutes to 180 minutes.

18. The method according to claim 12, wherein: Each of the first silicon oxycarbon nitride layer and the fourth silicon oxycarbon nitride layer has a thickness smaller than a thickness of each of the second silicon oxycarbon nitride layer and the third silicon oxycarbon nitride layer.

19. The method according to claim 12, further comprising: depositing a sacrificial layer on the fourth silicon oxycarbon nitride layer; Etching the sacrificial layer, the first silicon oxycarbon nitride layer, the second silicon oxycarbon nitride layer, the third silicon oxycarbon nitride layer, the fourth silicon oxycarbon nitride layer, and the first recess in the fin using a first etching process, wherein for the first etching process, an etching rate of the sacrificial layer is greater than an etching rate of the fourth silicon oxycarbon nitride layer; growing epitaxial source / drain regions in the first recess; and After growing the epitaxial source / drain regions, the sacrificial layer is removed.

20. The method according to claim 19, further comprising: Removing the first gate stack by a second etching process to form a second recess, wherein an etching rate of the first gate stack is greater than an etching rate of the first silicon oxycarbon nitride layer for the second etching process; as well as A second gate stack is formed in the second recess.

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