Semiconductor device and method for manufacturing the same

Abstract

Embodiments relate to semiconductor devices and methods for manufacturing the same. The semiconductor device comprises: a semiconductor portion, a first electrode disposed on the back surface of the semiconductor portion, a second electrode disposed on the surface of the semiconductor portion, and a control electrode, which is disposed inside a groove disposed in the semiconductor portion between the semiconductor portion and the second electrode, is electrically insulated from the semiconductor portion by a first insulating film, and is electrically insulated from the second electrode by a second insulating film. The control electrode comprises a third insulating film disposed at a position separated from the first insulating film and the second insulating film. The semiconductor portion comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type. The first layer extends between the first electrode and the second electrode. The second layer is disposed between the first layer and the second electrode. The third layer is selectively disposed between the second layer and the second electrode.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2019-238876 (filing date: December 27, 2019). This application includes all the contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] In a trench gate MOS transistor, a gate electrode provided in a gate trench may contain voids, which may deteriorate transistor characteristics. Summary of the invention

[0005] Embodiments provide a semiconductor device and a method for manufacturing the same that can suppress degradation of transistor characteristics caused by voids in a gate electrode.

[0006] A semiconductor device of an embodiment includes: a semiconductor portion, a first electrode provided on the back surface of the semiconductor portion, a second electrode provided on the surface of the semiconductor portion, and a control electrode, which is arranged inside a groove provided in the semiconductor portion between the semiconductor portion and the second electrode, is electrically insulated from the semiconductor portion by a first insulating film, and is electrically insulated from the second electrode by a second insulating film. The semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type. The control electrode is located between the first semiconductor layer and the second electrode. The second semiconductor layer is provided between the first semiconductor layer and the second electrode, and is opposite to the control electrode via the first insulating film. The third semiconductor layer is selectively provided between the second semiconductor layer and the second electrode, is provided at a position in contact with the first insulating film, and is electrically connected to the second electrode. The control electrode includes a third insulating film provided at a position separated from the first insulating film and the second insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic cross-sectional view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 (a)~ Figure 7 (b) is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0009] Figure 8 (a) to (c) are schematic cross-sectional views showing a manufacturing process of a modified example of the first embodiment.

[0010] Fig. 9 (a) and (b) are schematic cross-sectional views showing a semiconductor device according to a modification of the first embodiment.

[0011] Fig.10 It is a schematic cross-sectional view showing a semiconductor device according to a second embodiment.

[0012] Fig.11 (a)~ Fig.12 (c) is a schematic cross-sectional view showing the manufacturing process of the second embodiment.

[0013] Fig.13 (a) and (b) are schematic cross-sectional views showing a semiconductor device according to a modification of the second embodiment. DETAILED DESCRIPTION

[0014] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The same reference numerals are given to the same parts in the drawings and their detailed description is appropriately omitted, and the different parts will be described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. In addition, even when representing the same part, there is a case where the sizes and ratios of each other are represented differently according to the drawings.

[0015] Furthermore, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, the Z direction is sometimes described as the upper direction and the opposite direction is described as the lower direction.

[0016] (First Embodiment)

[0017] Figure 1 1 is a schematic cross-sectional view showing a semiconductor device 1 according to Embodiment 1. The semiconductor device 1 is, for example, a trench gate MOS transistor.

[0018] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor portion 10 , a first electrode (hereinafter referred to as a drain electrode 20 ), a second electrode (hereinafter referred to as a source electrode 30 ), a gate electrode 40 , and a field plate electrode (hereinafter referred to as a FP electrode 50 ).

[0019] The semiconductor portion 10 is, for example, silicon. The drain electrode 20 is provided on the back surface of the semiconductor portion 10. The source electrode 30 is provided on the front surface side of the semiconductor portion 10. The gate electrode 40 and the FP electrode 50 are located between the semiconductor portion 10 and the source electrode 30, and are arranged inside the gate trench GT provided in the semiconductor portion 10.

[0020] The FP electrode 50 is disposed at a position closer to the drain electrode 20 than the gate electrode 40. That is, the FP electrode 50 is provided at a position closer to the drain electrode 20 than the distance between the drain electrode 20 and the gate electrode 40.

[0021] In this example, the FP electrode 50 is located between the drain electrode 20 and the gate electrode 40. The FP electrode 50 is electrically connected to the source electrode 30 at a portion not shown, for example.

[0022] The gate electrode 40 is electrically insulated from the semiconductor portion 10 by a gate insulating film 43 . In addition, the gate electrode 40 is electrically insulated from the source electrode 30 by an interlayer insulating film 45 .

[0023] The FP electrode 50 is electrically insulated from the semiconductor portion 10 by the insulating film 53. In addition, the FP electrode 50 is electrically insulated from the gate electrode 40 by the insulating film 55 and the insulating film 57.

[0024] The gate electrode 40 is located, for example, between the interlayer insulating film 45 and the insulating film 53 , and between the interlayer insulating film 45 and the insulating film 55 .

[0025] The semiconductor portion 10 includes a first semiconductor layer (hereinafter, n-type drift layer 11 ), a second semiconductor layer (hereinafter, p-type diffusion layer 13 ), a third semiconductor layer (hereinafter, n-type source layer 15 ), a p-type contact layer 17 , and an n-type drain layer 19 .

[0026] The n-type drift layer 11 extends between the drain electrode 20 and the source electrode 30 . The gate electrode 40 is located between the n-type drift layer 11 and the source electrode 30 . In addition, the FP electrode 50 is located inside the n-type drift layer 11 .

[0027] The p-type diffusion layer 13 is provided between the n-type drift layer 11 and the source electrode 30. The p-type diffusion layer 13 is arranged to face the gate electrode 40 via the gate insulating film 43.

[0028] The n-type source layer 15 is selectively provided between the p-type diffusion layer 13 and the source electrode 30. The n-type source layer 15 is arranged at a position in contact with the gate insulating film 43. The n-type source layer 15 contains n-type impurities having a higher concentration than the n-type impurities of the n-type drift layer 11. The n-type source layer 15 is electrically connected to the source electrode 30.

[0029] The p-type contact layer 17 is selectively provided between the p-type diffusion layer 13 and the source electrode 30. The p-type contact layer 17 contains p-type impurities having a higher concentration than that of the p-type diffusion layer 13. The p-type contact layer 17 is electrically connected to the source electrode 30.

[0030] In this example, the source electrode 30 has an extension 30c reaching the p-type contact layer 17. The extension 30c contacts and electrically connects the n-type source layer 15 and the p-type contact layer 17. The source electrode 30 is electrically connected to the p-type diffusion layer 13 via the p-type contact layer 17.

[0031] The n-type drain layer 19 is provided between the n-type drift layer 11 and the drain electrode 20. The drain electrode 20 is in contact with and electrically connected to the n-type drift layer 11. The n-type drain layer 19 contains n-type impurities having a higher concentration than that of the n-type drift layer 11.

[0032] like Figure 1 As shown, the gate electrode 40 includes, for example, a void, a so-called aperture V G . Pore V G The inner surface of the insulating film 47 is covered. In addition, the insulating film 47 may also be filled with pores V G The insulating film 47 is provided at a position separated from the gate insulating film 43, the interlayer insulating film 45, the insulating film 53, and the insulating film 55. For example, the pore V G Located between the interlayer insulating film 45 and the insulating film 55 .

[0033] Next, refer to Figure 2 (a)~ Figure 7 (b) of the drawings illustrates a method for manufacturing the semiconductor device 1. Figure 2 (a)~ Figure 7 (b) is a schematic cross-sectional view sequentially showing the manufacturing process of the semiconductor device 1.

[0034] like Figure 2 As shown in (a), a gate trench GT is formed on the surface side of the semiconductor wafer 100. The gate trench GT is formed, for example, using anisotropic RIE (Reactive Ion Etching). The semiconductor wafer 100 is, for example, an n-type silicon wafer. The semiconductor wafer 100 includes n-type impurities at the same concentration as the n-type impurities of the n-type drift layer 11.

[0035] like Figure 2 As shown in (b) of FIG. 1 , an insulating film 53 is formed to cover the inside of the gate trench GT. The insulating film 53 is formed to leave a space SP1 inside the gate trench GT. The insulating film 53 is, for example, a silicon oxide film formed by thermally oxidizing the semiconductor wafer 100 .

[0036] like Figure 2As shown in (c) of FIG. 1 , a conductive film 103 is formed on the surface side of the semiconductor wafer 100. The conductive film 103 is formed to fill the space SP1 in the gate trench GT. The conductive film 103 is, for example, a polycrystalline silicon film having conductivity, and is formed using CVD (Chemical Vapor Deposition). The conductive film 103 contains, for example, phosphorus (P) as an n-type impurity.

[0037] like Figure 3 As shown in (a), the conductive film 103 is selectively removed, leaving the portion buried in the bottom of the gate trench GT. Thus, the FP electrode 50 is formed at the bottom of the gate trench GT. A space SP2 is formed inside the gate trench GT.

[0038] like Figure 3 As shown in (b) of FIG. 5 , an insulating film 57 is formed on the upper end of the FP electrode 50. The insulating film 57 is, for example, a silicon oxide film, and is formed by thermally oxidizing the FP electrode 50 via the space SP2.

[0039] like Figure 3 As shown in (c), an insulating film 55 is formed on the surface side of the semiconductor wafer 100. The insulating film 55 is formed to fill the space SP2 in the gate trench GT. The insulating film 55 is, for example, a silicate glass film containing boron (B) and phosphorus (P), a so-called BPSG film, and is formed using CVD.

[0040] like Figure 4 As shown in (a), the insulating film 55 and the insulating film 53 are selectively removed while leaving the portion that buries the inside of the gate trench GT. The insulating film 53 is removed in such a manner that its upper end is at a position higher than the upper end of the FP electrode 50 in the Z direction. A portion of the insulating film 55 remains on the insulating film 57 above the FP electrode 50. For example, the insulating film 53 and the insulating film 55 are removed by wet etching. A space SP3 is formed in the upper portion of the gate trench GT.

[0041] like Figure 4 As shown in (b), a gate insulating film 43 is formed to cover the exposed portion of the semiconductor wafer 100. The gate insulating film 43 is, for example, a silicon oxide film, and is formed by thermally oxidizing the semiconductor wafer 100. The gate insulating film 43 is formed to leave a space SP3 above the gate trench GT.

[0042] like Figure 4 As shown in (c) of FIG. 1 , a conductive film 105 is formed on the surface side of the semiconductor wafer 100. The conductive film 105 is formed to fill the space SP3 in the gate trench GT. The conductive film 105 is, for example, a polycrystalline silicon film including phosphorus (P) as an n-type impurity, and is formed using CVD. The gate insulating film 43 is located between the semiconductor wafer 100 and the conductive film 105.

[0043] The conductive film 105 includes a void V therein. G The conductive film 105 is formed, for example, under conditions such that the deposition rate at the opening of the space SP3 is faster than the deposition rate at the bottom of the space SP3. G The void V is formed at a position separated from the gate insulating film 43, the insulating film 53, and the insulating film 55, for example, at the center of the space SP3. G For example, it has a cross-sectional shape in which the length in the Z direction is longer than the width in the X direction.

[0044] like Figure 5 As shown in (a), the insulating film 107 is formed by thermally oxidizing the conductive film 105. The insulating film 107 is, for example, a silicon oxide film. The insulating film 107 is formed to cover the exposed surface of the conductive film 105. In this process, the pores V G The inner surface of is also oxidized to form an insulating film 47. The insulating film 47 is, for example, a silicon oxide film.

[0045] For example, oxygen, which is an oxidant, penetrates into the polysilicon film along the grain boundaries. When oxygen reaches the pores V G When the pore V G The silicon atoms on the inner surface are oxidized to form an insulating film 47 .

[0046] like Figure 5 As shown in (b) of FIG. 1 , the insulating film 107 is removed to expose the surface of the conductive film 105. The insulating film 107 is removed by, for example, wet etching.

[0047] like Figure 5 As shown in (c), the landfill space SP3 is reserved (refer to Figure 4 The conductive film 105 is selectively removed from the portion (b) of FIG. 1 . The conductive film 105 is removed by, for example, dry etching or wet etching. Thus, the gate electrode 40 is formed inside the gate trench GT.

[0048] like Figure 6 As shown in FIG. 1 ( a ), a p-type diffusion layer 13 and an n-type source layer 15 are formed on the surface side of a semiconductor wafer 100 .

[0049] The p-type diffusion layer 13 is formed by ion implanting, for example, boron (B) as a p-type impurity into the surface side of the semiconductor wafer 100, and then activating and diffusing the p-type impurity by heat treatment. At this time, the heat treatment time is controlled so that the interface between the n-type drift layer 11 and the p-type diffusion layer 13 is located at the same level as the lower surface of the gate electrode 40 or at a level higher than the lower surface of the gate electrode 40 in the Z direction.

[0050] The n-type source layer 15 is formed by, for example, ion-implanting phosphorus (P) as an n-type impurity into the surface side of the semiconductor wafer 100 and then activating the impurity by heat treatment.

[0051] like Figure 6 As shown in (b) of FIG. 1 , an interlayer insulating film 45 is formed on the surface side of the semiconductor wafer 100. The interlayer insulating film 45 is formed so as to cover the gate electrode 40 and the gate insulating film 43. The interlayer insulating film 45 is, for example, a silicon oxide film, and is formed using CVD.

[0052] Furthermore, a contact groove 45 c is formed by selectively removing the gate insulating film 43 and the interlayer insulating film 45 . The contact groove 45 c communicates with the n-type source layer 15 and extends along the gate electrode 40 , for example, in the Y direction.

[0053] like Figure 6 As shown in (c), the n-type source layer 15 is selectively removed through the contact groove 45c, exposing the p-type diffusion layer 13 at the bottom surface of the contact groove 45c. Thereafter, boron is ion-implanted as a p-type impurity through the contact groove 45c, and heat treatment is performed, thereby forming a p-type contact layer 17.

[0054] like Figure 7 As shown in (a), a source electrode 30 is formed on the surface side of the semiconductor wafer 100. The source electrode 30 is formed to cover the interlayer insulating film 45 and have an extension portion 30c extending inside the contact groove 45c. The source electrode 30 is, for example, a metal layer formed by sputtering and includes aluminum (Al).

[0055] like Figure 7 As shown in (b) , an n-type drain layer 19 and a drain electrode 20 are formed on the back surface side of the semiconductor wafer 100 , and the semiconductor device 1 is completed.

[0056] The n-type drain layer 19 is formed by thinning the semiconductor wafer 100 to a predetermined thickness by grinding or etching the back side of the semiconductor wafer 100, then implanting phosphorus (P) ions as n-type impurities into the back side and performing a heat treatment. The portion of the semiconductor wafer 100 between the p-type diffusion layer 13 and the n-type drain layer 19 becomes the n-type drift layer 11.

[0057] The drain electrode 20 is a metal layer including titanium (Ti), for example, and is formed on the back surface of the n-type drain layer 19 by sputtering.

[0058] In the manufacturing method of the embodiment, the conductive film 105 is thermally oxidized to form the pores V G The inner surface of the insulating film 47 is covered (refer to Figure 5 (a)). Therefore, for Figure 5The heat treatment in the manufacturing process after the step (a) can make the pores V G In addition, the insulating film 47 may be formed so that the pores V G That is, after the insulating film 47 is formed, the pore V G There is also a situation where there is no remaining space inside.

[0059] For example, when the insulating film 47 is not formed, the pore V G The silicon atoms exposed on the inner surface of the pores are detached by heat treatment and reattached to the pores V. G By repeating this action, sometimes the internal pores V of the gate electrode 40 G Move, for example, to the vicinity of the gate insulating film 43. As a result, the pore V G This causes changes in gate threshold voltage, channel resistance, etc., deteriorating transistor characteristics.

[0060] On the other hand, in the semiconductor device 1, the insulating film 47 is formed to suppress the void V G The silicon atoms at the inner surface of the pore V can be prevented from being separated. G That is, in the semiconductor device 1, the pore V G It is held at a position away from the gate insulating film 43 and does not affect the transistor characteristics.

[0061] Next, refer to Figure 8 (a) to (c) of the present invention describe a method for manufacturing the semiconductor device 1 according to a modified example of the first embodiment. Figure 8 (a) to (c) indicate the next Figure 4 (b) Schematic cross-sectional view of the manufacturing process.

[0062] like Figure 8 As shown in (a), a polysilicon layer 115 not doped with impurities is formed on the surface side of the semiconductor wafer 100. The polysilicon layer 115 is formed to fill the space SP3 above the gate trench GT. The polysilicon layer 115 includes a pore V in the portion filling the space SP3. G .

[0063] like Figure 8 As shown in (b), the polysilicon layer 115 is thermally oxidized to form an insulating film 107 covering the surface of the polysilicon layer 115. In this process, the insulating film 107 is formed to cover the pores V G An insulating film 47 is formed on the inner surface of the insulating film.

[0064] like Figure 8As shown in (c), after removing the insulating film 107, phosphorus (P) as an n-type impurity is diffused into the polysilicon layer 115. For example, phosphorus (P) is diffused into the polysilicon by performing a heat treatment in an atmosphere of an inert gas such as N2 including phosphine (PH3). In addition, phosphorus (P) may be ion-implanted into the polysilicon and diffused by heat treatment. Alternatively, a polysilicon layer containing phosphorus (P) may be formed on non-doped polysilicon, and phosphorus (P) may be diffused into the non-doped polysilicon by heat treatment. Thus, the polysilicon layer 115 has conductivity.

[0065] Next, the polysilicon layer 115 is removed while leaving the portion of the buried space SP3 (see Figure 5 (c)). Then, through Figure 6 (a)~ Figure 7 The semiconductor device 1 is completed through the manufacturing process shown in (b).

[0066] In this example, by covering the aperture V with the insulating film 47 G For example, in the process of diffusing n-type impurities into the polysilicon layer 115, the pores V G movement.

[0067] Fig. 9 (a) and (b) are schematic cross-sectional views showing semiconductor devices 2 and 3 according to modified examples of the first embodiment.

[0068] Fig. 9 The semiconductor device 2 shown in (a) includes a gate electrode 40 a (first control unit) and a gate electrode 40 b (second control unit). The gate electrodes 40 a and 40 b are arranged inside the gate trench GT together with the FP electrode 50 .

[0069] The gate electrodes 40a and 40b are respectively arranged to face the p-type diffusion layer 13 via the gate insulating film 43. The FP electrode 50 includes a main portion facing the n-type drift layer 11 via the insulating film 53 and an extension portion 50ex extending between the gate electrode 40a and the gate electrode 40b. The extension portion 50ex is electrically insulated from the gate electrodes 40a and 40b by the insulating film 59. The insulating film 59 is provided between the gate electrode 40a and the gate electrode 40b.

[0070] The gate electrodes 40a and 40b are electrically insulated from the source electrode 30 by the interlayer insulating film 45. The gate electrodes 40a and 40b are respectively located between the interlayer insulating film 45 and the insulating film 53. In addition, the gate electrodes 40a and 40b are respectively located between the gate insulating film 43 and the insulating film 59.

[0071] The source electrode 30 has a stacked structure including a bonding layer 33 and a contact layer 35. The bonding layer 33 is, for example, a metal layer containing aluminum (Al). The contact layer 35 is located between the bonding layer 33 and the interlayer insulating film 45. The contact layer 35 is, for example, a metal layer containing titanium (Ti).

[0072] The contact layer 35 has an extension portion 35c that reaches the p-type contact layer 17. The source electrode 30 is electrically connected to the n-type source layer 15 and the p-type contact layer 17 via the extension portion 35c.

[0073] In this example, the gate electrodes 40a and 40b also have a hole V G , pore V G The inner surface of the gate electrodes 40a and 40b is covered with an insulating film 47. In each of the gate electrodes 40a and 40b, the aperture V G The gap V is provided at a position separated from the gate insulating film 43, the interlayer insulating film 45, the insulating film 53, and the insulating film 59. G The insulating film 47 is located between the gate insulating film 43 and the insulating film 59 and between the interlayer insulating film 45 and the insulating film 53. The insulating film 47 suppresses the voids V caused by the heat treatment. G movement, preventing the degradation of transistor characteristics.

[0074] Fig. 9 The semiconductor device 3 shown in (b) has a gate trench GT and a field trench FT. The gate electrode 40 is arranged inside the gate trench GT. The gate electrode 40 is electrically insulated from the semiconductor portion 10 by a gate insulating film 43. In addition, the gate electrode 40 is electrically insulated from the source electrode 30 by an interlayer insulating film 45.

[0075] FP electrode 50 is arranged inside field trench FT and is electrically insulated from semiconductor portion 10 by insulating film 53. Gate electrode 40 is provided, for example, between adjacent FP electrodes 50 along the surface of semiconductor portion 10. FP electrode 50 is electrically connected to source electrode 30 at a portion not shown.

[0076] In this example, the gate electrode 40 also includes a void V G . Pore V G The inner surface of the hole V is covered by the insulating film 47. G The gap V is provided at a position separated from the gate insulating film 43 and the interlayer insulating film 45. G , it is stabilized against heat treatment by the insulating film 47 and is held at a position that does not affect the transistor characteristics.

[0077] (Second Embodiment)

[0078] Fig.102 is a schematic cross-sectional view showing a semiconductor device 4 according to the second embodiment. The semiconductor device 4 includes an FP electrode 50 and a gate electrode 60 provided inside the gate trench GT. The FP electrode 50 is provided closer to the drain electrode 20 than the distance between the drain electrode 20 and the gate electrode 60 .

[0079] In this example, the FP electrode 50 is disposed between the drain electrode 20 and the gate electrode 60. The FP electrode 50 is electrically insulated from the semiconductor portion 10 by the insulating film 53. The FP electrode 50 is electrically insulated from the gate electrode 60 by the insulating films 55 and 57.

[0080] The gate electrode 60 is located between the source electrode 30 and the FP electrode 50 and is electrically insulated from the source electrode 30 by the interlayer insulating film 45 . In addition, the gate electrode 60 is electrically insulated from the semiconductor portion 10 by the gate insulating film 63 .

[0081] like Fig.10 As shown, the semiconductor device 4 further includes an insulating film 65 located between the interlayer insulating film 45 and the gate electrode 60 . The insulating film 65 includes a protrusion 67 protruding toward the inside of the gate electrode 60 .

[0082] The protrusion 67 is, for example, located between the interlayer insulating film 45 and the insulating film 55, and extends toward the insulating film 55. The length of the protrusion 67 in the Z direction is, for example, shorter than the distance from the front end of the protrusion 67 to the lower end of the gate electrode 60. The insulating film 65 may also include, for example, the same material as the interlayer insulating film 45, and be provided integrally with the interlayer insulating film 45.

[0083] Next, refer to Fig.11 (a)~ Fig.12 (c) of the drawings illustrates a method for manufacturing the semiconductor device 4. Fig.11 (a)~ Fig.12 (c) means next Figure 4 (b) Schematic cross-sectional view of the manufacturing process.

[0084] like Fig.11 As shown in (a), a conductive film 123 is formed on the surface side of the semiconductor wafer 100. The conductive film 123 covers the inner surface of the space SP1 above the gate trench GT. The conductive film 123 is, for example, a polycrystalline silicon film including phosphorus (P) as an n-type impurity. The conductive film 123 is formed using CVD, for example.

[0085] like Fig.11 As shown in (b), as the conductive film 123 is formed thicker, the space SP3 becomes narrower.

[0086] like Fig.11As shown in (c), the conductive film 123 is formed thickly so that the space SP3 is blocked. As a result, the conductive film 123 is formed to have a seam SM inside it. The seam SM is formed by, for example, a portion of the conductive film 123 deposited on the inner walls on both sides of the space SP3 contacting each other.

[0087] In this example, the conductive film 123 does not include Figure 4 (c) shows the pore V G , and has a seam SM. Such a difference depends on, for example, the shape or size of the space SP3. For example, the opening width W of the space SP3 GT Than the bottom width W BT In the case of wide, no pores V are formed G , the conductive film 123 includes a seam SM.

[0088] like Fig.12 As shown in (a) of FIG. 1 , the portion filling the space SP3 is left, and the conductive film 123 is removed. The portion of the conductive film 123 filling the space SP3 becomes the gate electrode 60 .

[0089] like Fig.12 As shown in (b) of FIG. 6 , the gate electrode 60 is thermally oxidized to form an insulating film 65 . The insulating film 65 is, for example, a silicon oxide film, and is formed to cover the upper surface of the gate electrode 60 . The insulating film 65 has a protrusion 67 extending into the gate electrode 60 .

[0090] The protrusion 67 of the insulating film 65 is formed along the seam SM. The protrusion 67 is formed, for example, by oxidizing silicon atoms located in the seam SM with oxygen as an oxidizing agent.

[0091] like Fig.12 As shown in (c), p-type impurities and n-type impurities are ion-implanted into the surface side of the semiconductor wafer 100 and heat-treated, thereby forming a p-type diffusion layer 13 and an n-type source layer 15. Figure 6 (a)~ Figure 7 The manufacturing process shown in (b) completes the semiconductor device 4.

[0092] In this example, the width of the gate electrode 60 in the X direction is widened by the protrusion 67 of the insulating film 65 formed inside the gate electrode 60. Therefore, stress is applied to the p-type diffusion layer 13 and the n-type source layer 15 located between the gate electrodes 60 adjacent to each other in the X direction, and strain is generated in the semiconductor crystals constituting the p-type diffusion layer 13 and the n-type source layer 15. As a result, for example, the mobility of electrons in the p-type diffusion layer 13 increases. Thus, the resistance to the on-current flowing through the inversion channel induced at the interface between the p-type diffusion layer 13 and the gate insulating film 63 can be reduced.

[0093] Fig.13 (a) and (b) are schematic cross-sectional views showing semiconductor devices 5 and 6 according to modified examples of the second embodiment.

[0094] Fig.13 The semiconductor device 5 shown in (a) includes gate electrodes 60 a and 60 b. The gate electrodes 60 a and 60 b are arranged inside the gate trench GT together with the FP electrode 50 .

[0095] The gate electrodes 60a and 60b are respectively arranged to face the p-type diffusion layer 13 via the gate insulating film 63. The FP electrode 50 includes an extension portion 50ex extending between the gate electrode 60a and the gate electrode 60b. The extension portion 50ex is electrically insulated from the gate electrodes 60a and 60b by the insulating film 59.

[0096] The gate electrodes 60a and 60b are electrically insulated from the source electrode 30 by the interlayer insulating film 45. The source electrode 30 has a stacked structure including a bonding layer 33 and a contact layer 35. The contact layer 35 has an extension portion 35c that reaches the p-type contact layer 17. The source electrode 30 is electrically connected to the n-type source layer 15 and the p-type contact layer 17 via the extension portion 35c.

[0097] In this example as well, an insulating film 65 is provided between the interlayer insulating film 45 and the gate electrodes 60a and 60b, respectively. The insulating film 65 includes a protrusion 67 extending into each of the gate electrodes 60a and 60b.

[0098] The protrusion 67 is located between the interlayer insulating film 45 and the insulating film 53, and extends toward the insulating film 53. The length of the protrusion 67 along the extension direction is, for example, shorter than the distance from the front end of the protrusion 67 to the lower end of each of the gate electrodes 60a and 60b. The protrusion 67 can, for example, apply stress to the p-type diffusion layer 13 and the n-type source layer 15, and the resistance in the inversion channel induced at the interface between the p-type diffusion layer 13 and the gate insulating film 63 can be reduced.

[0099] Fig.13 The semiconductor device 6 shown in (b) has a gate trench GT and a field trench FT. The gate electrode 60 is arranged inside the gate trench GT and is electrically insulated from the semiconductor portion 10 by a gate insulating film 63. In addition, the gate electrode 60 is arranged between the semiconductor portion 10 and the source electrode 30 and is electrically insulated from the source electrode 30 by an interlayer insulating film 45.

[0100] The FP electrode 50 is arranged inside the field trench FT, and is electrically insulated from the semiconductor portion 10 by the insulating film 53. The FP electrode 50 is electrically connected to the source electrode 30 at a portion not shown, for example.

[0101] In this example as well, an insulating film 65 is provided between the interlayer insulating film 45 and the gate electrode 60. The insulating film 65 includes a protrusion 67 extending into the gate electrode 60. The length of the protrusion 67 in the Z direction is shorter than, for example, the distance from the front end of the protrusion 67 to the lower end of the gate electrode 60. Thus, stress is applied to the p-type diffusion layer 13 and the n-type source layer 15, and the resistance in the inversion channel induced at the interface between the p-type diffusion layer 13 and the gate insulating film 63 can be reduced.

[0102] The above-described embodiment is also effective for a structure in which the FP electrode 50 is not provided. For example, in the semiconductor devices 3 and 6, a structure in which the field trench FT is not provided and the FP electrode 50 is not disposed may be sufficient.

[0103] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: a semiconductor portion; a first electrode provided on the back surface of the semiconductor portion; a second electrode provided on the surface of the semiconductor portion; a control electrode arranged inside a trench provided in the semiconductor portion between the semiconductor portion and the second electrode; a first insulating film electrically insulating the control electrode from the semiconductor portion; and a second insulating film, which electrically insulates the control electrode from the second electrode, including a protrusion extending into the control electrode, the semiconductor portion including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type, the first semiconductor layer extending between the first electrode and the second electrode, the control electrode being located between the first semiconductor layer and the second electrode, the second semiconductor layer being arranged between the first semiconductor layer and the second electrode, opposite to the control electrode via the first insulating film, the third semiconductor layer being selectively arranged between the second semiconductor layer and the second electrode, configured at a position in contact with the first insulating film, and electrically connected to the second electrode, the length of the second insulating film along the extension direction of the protrusion being shorter than the distance from the front end of the protrusion to the lower end of the control electrode.

2. The semiconductor device according to claim 1, wherein It also includes: a third electrode, which is arranged inside the groove between the control electrode and the first electrode, is electrically insulated from the first semiconductor layer of the semiconductor part by a fourth insulating film, and is electrically insulated from the control electrode by a fifth insulating film, and the protrusion of the second insulating film is located between the second insulating film and the fifth insulating film, and extends toward the fifth insulating film.

3. The semiconductor device according to claim 1, wherein It also includes: a third electrode, which is arranged inside the groove together with the control electrode, the control electrode includes a first control part and a second control part arranged in a direction from the second semiconductor layer of the semiconductor part toward the control electrode, the third electrode has: a main part opposite to the first semiconductor layer of the semiconductor part across a fourth insulating film, and a part extending between the first control part and the second control part, the extended part of the third electrode is electrically insulated from the control electrode by a fifth insulating film arranged between the first control part and the second control part, the first control part and the second control part are respectively located between the second insulating film and the fourth insulating film, and the protrusion of the second insulating film is located between the first insulating film and the fifth insulating film, and extends toward the fourth insulating film.

Images