Analog-to-digital conversion device and related electronic sensor

Abstract

Analog-to-digital conversion device and associated electronic sensor are disclosed. The analog-to-digital conversion device (10) comprises: - an input terminal (12) for receiving an analog input signal (V in (z)); - an output terminal (14) for emitting a digital output signal (D out (z)); - a first successive approximation register analog-to-digital conversion module (24), referred to as first SAR ADC module (24), connected to the input terminal (12); - a first feedback module (30) associated to the first SAR ADC module (24); - a second successive approximation register analog-to-digital conversion module (38), referred to as second SAR ADC module (38), connected to the first SAR ADC module (24); - a second feedback module (44) associated to the second SAR ADC module (38); and - a multiplexing module (20) connected to the first and second SAR ADC modules (24) to deliver the digital output signal (D out (z)).

Description

[Technical Field]

[0001] The present invention relates to an analog-to-digital converter for converting analog input signals into digital output signals.

[0002] The present invention also relates to an electronic sensor including such an analog-to-digital conversion device. [Background Technology]

[0003] This invention relates to the field of analog-to-digital converters (ADCs), particularly in high-channel-density data acquisition systems. Such ADCs are commonly used in biomedical and instrumentation applications.

[0004] Also referred to as SAR ADC, the successive approximation register analog-to-digital converter (ADC) is popular in multiplexed systems due to its low latency and fast response, even for unresolved full-scale input steps, as illustrated in M. Pachchigar's article "Demystifying High-Performance Multiplexed Data-Acquisition Systems" in Analog Dialogue (2014). Successive approximation register ADCs are widely used in energy-saving applications due to their simplicity and power efficiency.

[0005] A successive approximation register analog-to-digital converter (ADC) typically includes: a digital-to-analog converter (DAC) with inputs and an output; a comparator with two inputs and an output, one input connected to the output of the DAC and the other adapted to receive a reference signal; and a SAR logic unit connected to the output of the comparator, adapted to control the DAC. The DAC typically contains a capacitor array.

[0006] US 2018 / 0183450A1 relates to an interleaved successive approximation register analog-to-digital converter (SAR ADC) with noise shaping, the SAR ADC having a first successive approximation register block, also referred to as a first SAR block, a second successive approximation register block, also referred to as a second SAR block, and noise shaping circuitry. The first and second SAR blocks alternately sample the input voltage to successively approximate the input voltage and observe a digital representation of the input voltage. The noise shaping circuitry alternately receives a first residual voltage from the first SAR block and a second residual voltage from the second SAR block, and outputs a noise-shaped signal to feed into the first and second SAR blocks. This successive approximation register ADC allows for increased processing speed because while one SAR block is in conversion mode, another SAR block samples the next input.

[0007] However, successive approximation register analog-to-digital converters suffer from significant comparator noise and the additional power required to drive large DAC capacitor arrays. Therefore, such successive approximation register analog-to-digital converters are rarely used in applications exceeding 10-12 bit resolution. [Summary of the Invention]

[0008] Therefore, the object of the present invention is to provide an improved analog-to-digital converter (ADC) comprising at least one successive approximation register ADC.

[0009] Therefore, the subject of this invention is an analog-to-digital converter (ADC) for converting analog input signals into digital output signals, the ADC comprising:

[0010] - Input terminal, used to receive analog input signals;

[0011] - Output terminals, used to output digital signals;

[0012] - A first successive approximation register analog-to-digital converter module, referred to as the first SAR ADC module, is connected to the input terminal via its input and configured to deliver a first digital signal via its output;

[0013] - A first feedback module is configured to receive a first residual signal from a first SAR ADC module, process the first residual signal and inject it back into the input of the first SAR ADC module;

[0014] - A second successive approximation register analog-to-digital converter module, referred to as the second SAR ADC module, is connected via its input to the first SAR ADC module to receive the first residual signal and is configured to deliver a second digital signal via its output;

[0015] - A second feedback module, configured to receive a second residual signal from a second SAR ADC module, process the second residual signal, and inject it back into the input of the second SAR ADC module; and

[0016] - A multiplexing module, connected to the output of the first SAR ADC module and the output of the second SAR ADC module, configured to deliver digital output signals at the output terminals.

[0017] Therefore, the analog-to-digital converter according to the present invention comprises two cascaded noise-shaping successive approximation register analog-to-digital converter stages, also referred to as NS-SAR ADC stages, namely a first NS-SAR ADC stage and a second NS-SAR ADC stage. Each NS-SAR ADC stage includes a SAR ADC module and a corresponding error feedback module, which performs noise shaping on the quantization noise of the SAR ADC module. The quantization noise of the first NS-SAR ADC stage, particularly the first SAR ADC module, is fed into the second NS-SAR ADC stage to form a multi-stage noise-shaping (MASH) SAR ADC.

[0018] Those skilled in the art will also note that noise shaping is performed using error feedback techniques, so that the analog-to-digital converter according to the invention no longer uses any operational transconductance amplifier (OTA). Therefore, it is effectively an OTA-free topology.

[0019] In an optional supplement, the multiplexing module can operate in a first operating mode where the delivered digital output signal is a first digital signal or in a second operating mode where the delivered digital output signal is a combination of a first digital signal and a second digital signal. Therefore, another advantage of the analog-to-digital converter according to the invention is its configurability, allowing it to be configured as a single-stage or multi-stage converter to support different bandwidths and resolutions.

[0020] In an optional supplement, each feedback module includes a corresponding second-order filter for filtering the residual signal before injecting it back into the input of the corresponding SAR ADC module. Therefore, another advantage of the analog-to-digital converter according to the invention is that it provides fourth-order noise shaping performance while remaining as stable as a second-order analog-to-digital converter.

[0021] According to other advantageous aspects of the invention, the analog-to-digital conversion device includes one or more of the following features, which may be taken individually or in any technically possible combination:

[0022] - The multiplexing module is configured to operate in a first operating mode in which the delivered digital output signal is a first digital signal or in a second operating mode in which the delivered digital output signal is a combination of a first digital signal and a second digital signal;

[0023] - The conversion device also includes a selection module for selecting an operating mode between a first operating mode and a second operating mode of the multiplexing module;

[0024] - The first feedback module includes a first filter for filtering the first residual signal before injecting it back into the input of the first SAR ADC module.

[0025] The first filter is preferably a second-order filter;

[0026] The first filter is still preferably a finite impulse response filter;

[0027] - The second feedback module includes a second filter for filtering the second residual signal before injecting it back into the input of the second SAR ADC module.

[0028] The second filter is preferably a second-order filter;

[0029] The second filter is still preferably a finite impulse response filter;

[0030] - The first SAR ADC module includes:

[0031] + First digital-to-analog converter, with input and output;

[0032] + A first comparator has two inputs and one output; one input is connected to the output of a first digital-to-analog converter, and the other input is adapted to receive a reference signal; and

[0033] + A first successive approximation register logic unit is connected to the output of a first comparator. The first successive approximation register logic unit is adapted to control a first digital-to-analog converter.

[0034] The input of the first digital-to-analog converter forms the input of the first SAR ADC module;

[0035] The output of the first comparator forms the output of the first SAR ADC module;

[0036] - The input of the second SAR ADC module is connected to the output of the first digital-to-analog converter;

[0037] - The second SAR ADC module includes:

[0038] +A second digital-to-analog converter, with input and output;

[0039] + A second comparator has two inputs and one output; one input is connected to the output of the second digital-to-analog converter, and the other input is adapted to receive a reference signal; and

[0040] + A second successive approximation register logic unit is connected to the output of the second comparator. The second successive approximation register logic unit is configured to control the second digital-to-analog converter.

[0041] The input of the second digital-to-analog converter forms the input of the second SAR ADC module;

[0042] The output of the second comparator forms the output of the second SAR ADC module;

[0043] - The multiplexing module includes a digital cancellation logic unit adapted to apply a first transfer function to a first digital signal and a second transfer function to a second digital signal in order to cancel the first residual signal.

[0044] The subject of this invention is also an electronic sensor that includes an analog-to-digital converter for converting an analog input signal into a digital output signal, as defined above. [Attached Image Description]

[0045] The invention will be better understood upon reading the following description, which is given by way of example only and with reference to the accompanying drawings, in which:

[0046] Figure 1 This is a schematic diagram of an electronic sensor including an analog-to-digital converter according to the present invention, the converter including a first NS-SAR ADC stage and a second NS-SAR ADC stage, the second NS-SAR ADC stage being cascaded to the first NS-SAR ADC stage to feed the quantization noise of the first NS-SAR ADC stage into the second NS-SAR ADC stage; the view is in the form of a block diagram also known as a linear model.

[0047] Figure 2 Is with Figure 1 A similar view is presented in the form of a time-domain behavior model;

[0048] Figure 3 It is a set of two curves, each representing the analog power spectral density of the digital output signal delivered by the analog-to-digital converter. The first curve corresponds to... Figure 1 The linear model, and the second curve corresponds to Figure 2 The temporal behavior model; and

[0049] Figure 4 It is a set of two pairs of curves, each pair representing the time-domain error signal for the second SAR ADC stage and the corresponding filtered error signal. The first pair of curves corresponds to... Figure 1 The linear model, and the second pair of curves corresponds to Figure 2 The temporal behavior model.

Detailed Implementation Methods

[0050] In the following description, NS stands for noise shaping; SAR stands for successive approximation register; and ADC stands for analog-to-digital converter or analog-to-digital conversion. Thus, NS-SAR ADC stands for noise-shaping successive approximation register analog-to-digital converter or conversion stage.

[0051] exist Figure 1 In the middle, the electronic sensor 8 includes a function for transmitting analog input signal Vin (z) is converted into a digital output signal D. out (z) Analog-to-digital converter 10. Electronic sensor 8 is suitable for use in a variety of applications, such as biomedical and / or instrumentation applications.

[0052] The analog-to-digital converter 10 is configured to convert the analog input signal V in (z) is converted into a digital output signal D. out (z), and includes a function for receiving analog input signal V in (z) input terminal 12 and for emitting digital output signal D out (z) output terminal 14.

[0053] The analog-to-digital converter 10 further includes: a first noise-shaping successive approximation register analog-to-digital converter stage 16, also referred to as a first NS-SAR ADC stage; a second noise-shaping successive approximation register analog-to-digital converter stage 18, also referred to as a second NS-SAR ADC stage, the second NS-SAR ADC stage 18 being cascaded to the first NS-SAR ADC stage 16; and a multiplexing module 20, which is connected to the outputs of the first NS-SAR ADC stage 16 and the second NS-SAR ADC stage 18 respectively. The multiplexing module 20 is configured to deliver a digital output signal D at output terminal 14 based on a first digital signal D1(z) from the first NS-SAR ADC stage 16 or additionally based on a second digital signal D2(z) from the second NS-SAR ADC stage 18. out (z).

[0054] Those skilled in the art will understand that the term "multiplexing" generally refers to the action of grouping information or signals from several channels onto a single channel. Multiplexing module 20 should therefore be understood as a module capable of grouping signals from several channels (i.e., signals from NS-SAR ADC stages 16, 18) together at output terminal 14. Multiplexing module 20 is configured to deliver the digital output signal D at output terminal 14. out (z), which is based on the first digital signal D1(z) from the first NS-SAR ADC level 16, and even further based on the second digital signal D2(z) from the second NS-SAR ADC level 18, that is, based on the combination of the first digital signal D1(z) and the second digital signal D2(z).

[0055] As an optional supplement, the multiplexing module 20 is configured to... out (z) is the first operating mode M1 of the first digital signal D1(z) or the delivered digital output signal D. out(z) is the operation under the second operating mode M2, which is a combination of the first digital signal D1(z) and the second digital signal D2(z).

[0056] According to this optional supplement, the conversion device 10 also includes a selection module 22, which is configured to select an operation mode between a first operation mode M1 and a second operation mode M2 ​​of the multiplexing module 20.

[0057] The first NS-SAR ADC stage 16 includes a first successive approximation register analog-to-digital converter module 24, referred to as the first SARADC module 24, also denoted as SAR_ADC1. The first SAR ADC module is connected to the input terminal 12 via its input 26 and is configured to deliver a first digital signal D1(z) via its output 28.

[0058] The first NS-SAR ADC stage 16 also includes a first feedback module 30, which is configured to receive a first residual signal E1(z) from the first SAR ADC module 24 via its input 32, process the signal and inject the signal back to the input 26 of the first SAR ADC module 24 via its output 34.

[0059] exist Figure 1 In the example, the first NS-SAR ADC stage 16 includes a first adder 36, which is connected on one hand to the input terminal 12 and the output 34 of the first feedback module 30, and on the other hand to the input 26 of the first SAR ADC module 24. The first adder 36 is configured to process the signal by the first feedback module 30, also represented as... Added to analog input signal V in (z), and sum the signals Input 26 is delivered to the first SAR ADC module 24.

[0060] The second NS-SAR ADC stage 18 includes a second successive approximation register analog-to-digital converter module 28, referred to as the second SARADC module 38, also denoted as SAR_ADC2. This second SAR ADC module is connected to the first SAR ADC module 24 via its input 40 to receive the first residual signal E1(z) and is configured to deliver the second digital signal D2(z) via its output 42.

[0061] The second NS-SAR ADC stage 18 also includes a second feedback module 44, which is configured to receive a second residual signal E2(z) from the second SAR ADC module 38 via its input 46, process the signal, and inject the signal back to the input 40 of the second SAR ADC module 38 via its output 48.

[0062] exist Figure 1 In the example, the second NS-SAR ADC stage 18 includes a second adder 50, which is connected on one hand to the output 48 of the first NS-SAR ADC stage 16 and the second feedback module 44, and on the other hand to the input 40 of the second SAR ADC module 38. The second adder 50 is configured to process the signal, also represented as... Add to the first residual signal E1(z), and sum the signals. Input 40 is delivered to the second SAR ADC module 38.

[0063] Multiplexing module 20 is configured to deliver digital output signal D based on the first digital signal D1(z) and the second digital signal D2(z). out (z). The multiplexing module 20 is connected to the output 28 of the first SAR ADC module 24 and the output 42 of the second SAR ADC module 38.

[0064] The multiplexing module 20 is preferably configured to deliver a first digital signal D1(z) or a combination of the first digital signal D1(z) and the second digital signal D2(z) as a digital output signal D at the output terminal 14. out (z).

[0065] The multiplexing module 20 includes a digital cancellation logic unit 52, also referred to as DCL, which is adapted to apply a first transfer function H1(z) to a first digital signal D1(z) and a second transfer function H2(z) to a second digital signal D2(z), such as... Figure 2 As shown. The digital cancellation logic unit 52 is adapted to cancel the first residual signal E1(z).

[0066] exist Figure 2 In the example, the first SAR ADC module 24 includes a first digital-to-analog converter 54, also referred to as C-DAC1, which has an input 56 and an output 58. The input 56 of the first digital-to-analog converter 54 forms the input 26 of the first SAR ADC module 24.

[0067] Those skilled in the art will observe that input 56, which forms the input of the first SAR ADC module 24 performing the analog-to-digital conversion function, is an input of the first digital-to-analog converter 54, but not its only input. Those skilled in the art will then understand that input 56 is an analog input corresponding to an additional input of the digital-to-analog converter 54, rather than a digital input intended to receive a digital signal for conversion to an analog signal, which is itself known to the SAR ADC module. The additional input 56 is configured to receive a reference voltage for normalizing the digital input. Figure 2In the example, the reference voltage corresponds to the signal delivered by the first adder 36 to the first SAR ADC module 24, i.e., the sum of the signals.

[0068] The first SAR ADC module 24 also includes a first comparator 60 having two inputs 62A and 62B, namely first input 62A and second input 62B, and an output 64. One input of the first comparator 60, such as the first input 62A, is connected to the output 58 of the first digital-to-analog converter 54, and the other input, such as the second input 62B, is adapted to receive a reference signal, such as a first reference voltage V. ref1 The output 64 of the first comparator 60 forms the output 28 of the first SAR ADC module 24.

[0069] The first SAR ADC module 24 also includes a first successive approximation register logic unit 66, also called the first SAR logic unit 66 and denoted as SAR1, connected to the output 64 of the first comparator 60. The first SAR logic unit 66 is adapted to control the first digital-to-analog converter 54.

[0070] The first feedback module 30 includes a first filter 68, which is used to filter the first residual signal E1(z) as the residual signal after the first filtering. The input 26 is filtered before being injected back into the first SAR ADC module 24.

[0071] exist Figure 2 In the example, the second SAR ADC module 38 includes a second digital-to-analog converter 70, also referred to as C-DAC2, which has an input 72 and an output 74. The input 72 of the second digital-to-analog converter 70 forms the input 40 of the second SAR ADC module 38.

[0072] Those skilled in the art will observe that input 72, which forms the input of the second SAR ADC module 58 performing the analog-to-digital conversion function, is an input of the second digital-to-analog converter 70, but not its only input. Those skilled in the art will then understand that input 72 is an analog input corresponding to an additional input of the digital-to-analog converter 70, rather than a digital input intended to receive a digital signal for conversion to an analog signal, which is itself known to the SAR ADC module. The additional input 72 is configured to receive a reference voltage for normalizing the digital input. Figure 2 In the example, the reference voltage corresponds to the signal delivered by the second adder 50 to the second SAR ADC module 38, i.e., the sum of the signals.

[0073] The second SAR ADC module 38 also includes a second comparator 76 having two inputs 78A and 78B, namely a first input 78A and a second input 78B, and an output 80. One input of the second comparator 76, such as the first input 78A, is connected to the output 74 of the second digital-to-analog converter 70, and the other input, such as the second input 78B, is adapted to receive a reference signal, such as a second reference voltage V. ref2 The output 80 of the second comparator 76 forms the output 42 of the second SAR ADC module 38.

[0074] The second SAR ADC module 38 also includes a second successive approximation register logic unit 82, also called the second SAR logic unit 82 and denoted as SAR2, connected to the output 80 of the second comparator 76. The second SAR logic unit 82 is adapted to control the second digital-to-analog converter 70.

[0075] The second feedback module 44 includes a second filter 84, which is used to filter the second residual signal E2(z) as the residual signal after the second filtering. The input 40 is filtered before being injected back into the second SAR ADC module 38.

[0076] The digital cancellation logic unit 52 is configured, for example, to apply a first transfer function H1(z) to a first digital signal D1(z) and a second transfer function H2(z) to a second digital signal D2(z) according to the following equation:

[0077] [Formula 1]

[0078] D out (z)=H1(z)·D1(z)+H2(z)·D2(z)

[0079] Among them, D out Indicates digital output signal,

[0080] H1 represents the first transfer function.

[0081] D1 represents the first digital signal.

[0082] H2 represents the second transfer function, and

[0083] D2 represents the second digital signal.

[0084] For example, verify the following equation using the first digital signal D1(z):

[0085] [Formula 2]

[0086] D1(z)=STF1(z)·V in (z)+NTF1(z)·E1(z)

[0087] Where D1 represents the first digital signal,

[0088] STF1 represents the first signal transfer function.

[0089] V in Indicates analog input signal,

[0090] NTF1 represents the first noise transfer function, and

[0091] E1 represents the first residual signal.

[0092] For example, verify the following equation using the second digital signal D2(z):

[0093] [Formula 3]

[0094] D2(z)=STF2(z)·E1(z)+NTF2(z)·E2(z)

[0095] Where D2 represents the second digital signal,

[0096] STF2 represents the second signal transfer function.

[0097] E1 represents the first residual signal.

[0098] NTF2 represents the second noise transfer function, and

[0099] E2 represents the second residual signal.

[0100] Based on equations (1), (2), and (3) above, the digital output signal D out (z) Verify the following equations written in a condensed form:

[0101] [Formula 4]

[0102] D out (z)=H1·[STF1·V in (z)+NTF1·E1(z)]+H2·[STF2·E1(z)+NTF2·E2(z)]

[0103] This results in the following equations written in a condensed form:

[0104] [Formula 5]

[0105] D out (z)=H1·STF1·V in (z)+[H1·NTF1+H2·STF2]·E1(z)+H2·NTF2·E2(z)

[0106] Therefore, based on equation (5), verify the following equation in order to eliminate the first residual signal E1(z):

[0107] [Formula 6]

[0108] H1(z)·NTF1(z)+H2(z)·STF2(z)=0

[0109] exist Figure 2 In the example, the first digital-to-analog converter 54, denoted as C-DAC1, includes a first capacitor array 86.

[0110] The first filter 68 is preferably a finite impulse response filter, also known as an FIR filter, and is accordingly denoted as FIR1.

[0111] The first filter 68 is preferably a second-order filter.

[0112] The first noise transfer function NTF1(z) is typically verified using the following equation:

[0113] [Formula 7]

[0114] NTF1(z)=1-H F1 (z)

[0115] Where NTF1 represents the first noise transfer function, and

[0116] H F1 This represents the transfer function of the first filter 68.

[0117] exist Figure 2 In the example, the first filter 68 is preferably a second-order FIR filter. According to this example, the first filter 68 includes a first gain unit 88 for applying a gain G1 to a first residual signal E1(z), a first first-stage delay unit 90 with a gain a1 connected to the output of the first gain unit 88, a first second-stage delay unit 92 with a gain a2 connected to the output of the first first-stage delay unit 90, and a third adder 94 connected to the two outputs of the first first-stage delay unit 90 and the first second-stage delay unit 92.

[0118] Based on this example, the transfer function of the first filter 68 verifies the following equation:

[0119] [Formula 8]

[0120] H F1 (z)=G1·(a1z -1 +a2z -2 )

[0121] The ideal first noise transfer function NTF1(z) for second-order noise shaping verifies the following equation, which requires G1 = 2, a1 = 1, and a2 = -0.5 as parameter values:

[0122] [Formula 9]

[0123] NTF1(z)=(1-z -1 ) 2

[0124] exist Figure 2 In the example, the second digital-to-analog converter 70, denoted as C-DAC2, includes a second capacitor array 96.

[0125] The second filter 84 is preferably a finite impulse response filter, also known as an FIR filter, and is accordingly denoted as FIR2.

[0126] The second filter 84 is preferably a second-order filter.

[0127] The second noise transfer function NTF2(z) is typically verified using the following equation:

[0128] [Formula 10]

[0129] NTF2(z)=1-H F2 (z)

[0130] Where NTF2 represents the second noise transfer function, and

[0131] H F2 This represents the transfer function of the second filter 84.

[0132] exist Figure 2 In the example, the second filter 84 is preferably a second-order FIR filter. According to this example, the second filter 84 includes a second gain unit 98 for applying gain G2 to the second residual signal E2(z), a second first-stage delay unit 100 with gain b1 connected to the output of the second gain unit 98, a second second-stage delay unit 102 with gain b2 connected to the output of the second first-stage delay unit 100, and a fourth adder 104 connected to the two outputs of the second first-stage delay unit 100 and the second second-stage delay unit 102.

[0133] Based on this example, the transfer function of the second filter 84 verifies the following equation:

[0134] [Formula 11]

[0135] H F2 (z)=G2·(b1z -1 +b2z -2 )

[0136] The ideal second noise transfer function NTF2(z) used for second-order noise shaping verifies the following equation, which requires G2 = 2, b1 = 1, and b2 = -0.5 as parameter values:

[0137] [Formula 12]

[0138] NTF2(z)=(1-z -1 ) 2

[0139] Assuming that the first signal transfer function STF1(z) and the second signal transfer function STF2(z) are ideal, the following equations were verified:

[0140] [Formula 13]

[0141] STF1(z)=STF2(z)=1

[0142] Furthermore, considering the first transfer function H1(z), the following equation was verified:

[0143] [Formula 14]

[0144] H1(z)=1

[0145] Then, equations (6) and (9) above produce the following equation:

[0146] [Formula 15]

[0147] H2(z)=-NTF1(z)=-(1-z -1 ) 2

[0148] Therefore, in this example, according to equations (5), (6) and (12) to (15), the digital output signal D out (z) Verify the following equation:

[0149] [Formula 16]

[0150] D out (z)=V in (z)-(1-z -1 ) 4 ·E2(z)

[0151] Thus, equation (16) above confirms that when each feedback module 30, 44 includes a corresponding second-order filter 68, 84 for filtering the corresponding residual signals E1(z), E2(z) before injecting them back into the input of the corresponding SAR ADC modules 24, 38, the analog-to-digital converter 10 according to the invention provides fourth-order noise shaping performance.

[0152] Therefore, compared with prior art analog-to-digital converters, the analog-to-digital converter 10 according to the present invention allows for improved results, as will be stated below. Figure 3 and Figure 4 Explanation.

[0153] Figure 3 There are two curves, 200 and 210, namely the first curve 200 and the second curve 210. Each curve 200 and 210 represents the digital output signal D delivered by the analog-to-digital converter 10. out The simulated power spectral density, the first curve 200 corresponds to Figure 1 The linear model, the second curve 210 corresponds to Figure 2 The temporal behavior model.

[0154] therefore, Figure 3 The power spectral densities of the linear and behavioral models of the present invention are shown, and similar results for the two implementations are demonstrated. The 80 dB / Dec slopes of curves 200 and 210 further demonstrate the fourth-order noise shaping performance of the analog-to-digital converter 10 according to the present invention.

[0155] Figure 4 It consists of two pairs of curves, 300 and 310, namely the first pair of 300 and the second pair of 310. Each pair of 300 and 310 represents the time-domain error signal and the corresponding filtering error signal of the second NS-SAR ADC stage 18. The first pair of 300 corresponds to... Figure 1 The linear model, the second pair of 310 corresponds to Figure 2 The temporal behavior model.

[0156] exist Figure 4 In China, according to Figure 1 The linear model, the first pair of 300 includes a third curve 300A representing the time-domain error signal and a fourth curve 300B representing the filtered error signal of the second NS-SAR ADC stage 18. Similarly, according to Figure 2 The time-domain behavior model, the second pair 310 includes a fifth curve 310A representing the time-domain error signal and a sixth curve 310B representing the filtered error signal of the second NS-SAR ADC stage 18.

[0157] therefore, Figure 4 The time-domain error signals of the second NS-SAR ADC stage 18 used in two implementations are compared. It also shows how filtering affects this error. It can be seen that it adds some noise to the analog-to-digital converter 10, but it is not significant and does not degrade the performance of the analog-to-digital converter 10.

[0158] Thus, compared with conventional noise-shaping successive approximation register analog-to-digital converters, the analog-to-digital converter 10 according to the present invention offers several advantages, as will be explained below.

[0159] First, according to the present invention, the analog-to-digital converter 10 obtains a higher noise shaping order by cascading NS-SAR ADC stages 16 and 18, which have the ability to lower noise shaping order and no stability problems.

[0160] Then, no additional circuitry is needed to extract the error signal from the first NS-SAR ADC stage 16 to feed it as the input to the second NS-SAR ADC stage 18. Therefore, the analog-to-digital converter 10 has a simpler architecture because, at the end of the conversion, the analog error signals E1(z), E2(z) are already present on the corresponding digital-to-analog converters 54, 70, such as on the corresponding capacitor arrays 86, 96. Furthermore, the analog error signal E1(z) of the first digital-to-analog converter 54, such as that on the first capacitor array 86, can be used as the input to the second NS-SAR ADC stage 18.

[0161] This also makes the analog-to-digital converter 10 according to the invention more accurate than a conventional MASH converter because it eliminates the analog-to-digital conversion of the corresponding outputs 28, 42 of the SAR ADC modules 24, 38 (i.e., the outputs of the quantizer), and also because it eliminates the subtraction step.

[0162] Furthermore, each NS-SAR ADC stage 16, 18 provides a digital signal with a specific resolution, namely a corresponding first digital signal D1(z) and a second digital signal D2(z), such that the analog-to-digital converter 10 allows, for example, to simultaneously provide two different resolutions at the output of the digital cancellation logic 52, namely a first resolution corresponding to a first operating mode M1 and a second resolution corresponding to a second operating mode M2, in which the delivered digital output signal D out (z) is the first digital signal D1(z), and in the second operating mode, it is the delivered digital output signal D. out (z) is a combination of the first digital signal D1(z) and the second digital signal D2(z).

[0163] The analog-to-digital converter 10 according to the invention also provides the flexibility to use combinations of different NS-SAR ADC stages 16, 18, and in particular to change the noise shaping order and resolution via a selection module 22, which can select the operating mode from a first operating mode M1 and a second operating mode M2 ​​of the multiplexer module 20. Therefore, the analog-to-digital converter provides a reconfigurable resolution architecture.

[0164] Furthermore, there are no restrictions on the type of feedback modules 30 and 44 in NS-SAR ADC stages 16 and 18 (such as loops, loop filters, or FIR filters).

[0165] Furthermore, noise shaping is performed using error feedback technology, and the analog-to-digital converter 10 according to the invention no longer uses an operational transconductance amplifier (OTA). In other words, the analog-to-digital converter 10 preferably provides an OTA-free topology.

Claims

1. A method for converting analog input signals (V) in (z) is converted into a digital output signal (D) out (z)) an analog-to-digital converter (10), the analog-to-digital converter comprising: - Input terminal (12), for receiving the analog input signal (V) in (z)); - Output terminal (14), used to output the digital output signal (D) out (z)); - A first successive approximation register analog-to-digital converter module (24), referred to as the first SAR ADC module (24), is connected to the input terminal (12) via its input (26) and configured to deliver a first digital signal (D1(z)) via its output (28); - A first feedback module (30) is configured to receive a first residual signal (E1(z)) from the first SAR ADC module (24), process the first residual signal and inject it back into the input (26) of the first SAR ADC module (24); - A second successive approximation register analog-to-digital converter module (38), referred to as the second SAR ADC module (38), is connected to the first SAR ADC module (24) via its input (40) to receive the first residual signal (E1(z)) and is configured to deliver a second digital signal (D2(z)) via its output (42); - A second feedback module (44) configured to receive a second residual signal (E2(z)) from the second SAR ADC module (38), process the second residual signal and inject it back into the input (40) of the second SAR ADC module (38); and - A multiplexing module (20) is connected to the output (28) of the first SAR ADC module (24) and the output (42) of the second SAR ADC module (38), the multiplexing module (20) being configured to deliver the digital output signal (D) at the output terminal (14). out (z)), and The first feedback module (30) includes a first filter (68) for filtering the first residual signal before injecting the first residual signal (E1(z)) back into the input (26) of the first SAR ADC module (24).

2. The conversion device (10) according to claim 1, wherein, The multiplexing module (20) is configured to process the delivered digital output signal (D) out (z) is the first operating mode (M1) of the first digital signal (D1(z)) or the delivered digital output signal (D out (z) is the operation under the second operating mode (M2) of the combination of the first digital signal (D1(z)) and the second digital signal (D2(z)).

3. The conversion device (10) according to claim 2, wherein, The conversion device (10) further includes a selection module (22) for selecting an operation mode from the first operation mode (M1) and the second operation mode (M2) of the multiplexing module (20).

4. The conversion device (10) according to claim 1, wherein, The first filter (68) is a second-order filter.

5. The conversion device (10) according to claim 1, wherein, The first filter (68) is a finite impulse response filter (FIR1).

6. The conversion device (10) according to claim 1, wherein, The second feedback module (44) includes a second filter (84) for filtering the second residual signal (E2(z)) before injecting it back into the input (40) of the second SAR ADC module (38).

7. The conversion device (10) according to claim 6, wherein, The second filter (84) is a second-order filter.

8. The conversion device (10) according to claim 6, wherein, The second filter (84) is a finite impulse response filter (FIR2).

9. The conversion device (10) according to claim 1, wherein, The first SAR ADC module (24) includes: - A first digital-to-analog converter (54) having an input (56) and an output (58); - A first comparator (60) has two inputs (62A, 62B) and one output (64). One input (62A) is connected to the output (58) of the first digital-to-analog converter (54), and the other input (62B) is adapted to receive a first reference signal (V). ref1 );as well as - A first successive approximation register logic unit (66) is connected to the output (64) of the first comparator (60), and the first successive approximation register logic unit (66) is adapted to control the first digital-to-analog converter (54); The input (56) of the first digital-to-analog converter (54) forms the input (26) of the first SAR ADC module (24); The output (64) of the first comparator (60) forms the output (28) of the first SAR ADC module (24).

10. The conversion device (10) according to claim 9, wherein, The input (40) of the second SARADC module (38) is connected to the output (58) of the first digital-to-analog converter (54).

11. The conversion device (10) according to claim 1, wherein, The second SAR ADC module (38) includes: - A second digital-to-analog converter (70) having an input (72) and an output (74); - A second comparator (76) has two inputs (78A, 78B) and one output (80). One input (78A) is connected to the output (74) of the second digital-to-analog converter (70), and the other input (78B) is adapted to receive a second reference signal (V). ref2 );as well as - A second successive approximation register logic unit (82) is connected to the output (80) of the second comparator (76), and the second successive approximation register logic unit (82) is configured to control the second digital-to-analog converter (70); The input (72) of the second digital-to-analog converter (70) forms the input (40) of the second SAR ADC module (38); The output (80) of the second comparator (76) forms the output (42) of the second SARADC module (38).

12. The conversion device (10) according to claim 1, wherein, The multiplexing module (20) includes a digital elimination logic unit (52) which is adapted to apply a first transfer function (H1(z)) to the first digital signal (D1(z)) and a second transfer function (H2(z)) to the second digital signal (D2(z)) in order to eliminate the first residual signal (E1(z)).

13. An electronic sensor (8), comprising a means for transmitting an analog input signal (V) in (z) is converted into a digital output signal (D) out (z)) analog-to-digital converter (10), wherein, The analog-to-digital converter (10) is as described in claim 1.

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